LTC1983-5_15 [Linear]
100mA Regulated Charge-Pump Inverters in ThinSOT;
| 型号： | LTC1983-5_15 |
| 厂家： | 
Linear |
| 描述： | 100mA Regulated Charge-Pump Inverters in ThinSOT |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1983-3/LTC1983-5
100mA Regulated
Charge-Pump Inverters
in ThinSOT
U
FEATURES
DESCRIPTIO
The LTC®1983-3 and LTC1983-5 are inverting charge
pump DC/DC converters that produce negative regulated
outputs. The parts require only three tiny external capaci-
tors and can provide up to 100mA of output current. The
devices can operate in open loop mode (creating a –VIN
supply) or regulated output mode depending on the input
supply voltage and the output current.
■
Fixed Output Voltages: –3V, –5V or Low Noise VIN
to –VIN Inverted Output
■
±4% Output Voltage Accuracy
■
Low Quiesient Current: 25µA
■
100mA Output Current Capability
■
2.3V to 5.5V Operating Voltage Range
■
Internal 900kHz Oscillator
“Zero Current” Shutdown
■
The LTC1983-3/LTC1983-5 have many useful features for
portableapplicationsincludingverylowquiescentcurrent
(25µA typical) and a zero current shutdown mode pro-
grammed through the SHDN pin.
■
Short-Circuit and Over-Temperature Protected
Low Profile (1mm) ThinSOTTM Package
■
U
APPLICATIO S
The LTC1983-3/LTC1983-5 are over-temperature and
short-circuit protected. The parts are available in a 6-pin
low profile (1mm) ThinSOT package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
–3V Generation in Single-Supply Systems
■
Portable Equipment
■
LCD Bias Supplies
GaAs FET Bias Supplies
■
U
TYPICAL APPLICATIO
–3V at 100mA DC/DC Converter
V vs I
OUT OUT
–3.3
–3.2
–3.1
–3.0
–2.9
–2.8
–2.7
V
V
= –3V
= UP TO 100mA
IN
3V TO 5.5V
OUT
OUT
V
V
OUT
LTC1983-3
IN
I
C
IN
10µF
C
OUT
10µF
GND
SHDN
OFF ON
V
= 5V
IN
–
+
C
C
1983-3 TA01
V
= 3.3V
IN
C
FLY
1µF
C
C
: TAIYO YUDEN LMK212BJ105
FLY
, C : TAIYO YUDEN JMK316BJ106ML
IN OUT
0
20
40
60
80
100
I
(mA)
OUT
1983 TA02
1983fa
1
LTC1983-3/LTC1983-5
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
VIN to GND................................................... –0.3V to 6V
SHDN Voltage .............................................. –0.3V to 6V
VOUT to GND (LTC1983-3) .................. 0.2V to VOUT Max
VOUT to GND (LTC1983-5) .................. 0.2V to VOUT Max
IOUT Max ............................................................. 125mA
Output Short-Circuit Duration.......................... Indefinite
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
NUMBER
TOP VIEW
LTC1983ES6-3
LTC1983ES6-5
V
1
2
3
6 SHDN
5 GND
CC
V
OUT
+
–
C
4 C
S6 PART
MARKING
S6 PACKAGE
6-LEAD PLASTIC SOT-23
TJMAX = 125°C, θJA = 256°C/W
LTPC
LTYB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, C
= 1µF, C
= 10µF unless otherwise noted.
A
IN
FLY
OUT
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Operating Voltage (Regulated Output Mode) (LTC1983-3)
●
3.0
5.0
5.5
5.5
V
V
(LTC1983-5)
V
V
Minimum Startup Voltage
2.3
V
IN
(LTC1983-3)
V
IN
V
IN
≥ 3.3V, I ≤ 25mA
OUT
●
●
–2.88
–2.88
–3
–3
–3.12
–3.12
V
V
OUT
≥ 5V, I
≤ 100mA
OUT
V
V
V
(LTC1983-5)
V
V
≥ 5V, V –5V ≥ I
• R
OUT
●
●
– 4.8
–5
25
–5.2
60
V
OUT
IN
IN
IN
OUT
Operating Current
≤ 5.5V, I
= 0µA, SHDN = V
µA
IN
IN
OUT
IN
Operating Current (Open-Loop Mode) (LTC1983-5)
V
IN
V
IN
= 3.3V
= 4.75V
2.5
4
mA
mA
V
Shutdown Current
SHDN = 0V, V ≤ 5.5V
●
0.1
60
11
1
µA
IN
IN
Output Ripple
3.3 ≤ V ≤ 5.5
mV
P-P
IN
Open-Loop Output Impedance (LTC1983-3): R
Open-Loop Output Impedance (LTC1983-5): R
V
IN
= 3.3V, V
= –3V
Ω
OUT
OUT
OUT
V
V
= 3.3V, I
≈50mA
11
8.5
Ω
Ω
IN
OUT
≈60mA
= 5V, I
IN
OUT
Oscillator Frequency
SHDN Input High
SHDN Input Low
(Non Burst Mode® Operation)
900
kHz
V
●
●
●
1.1
0.3
4
V
SHDN Input Current
V
= 5.5V
2.2
µA
SHDN
Burst Mode is a registered trademark of Linear Technology Corporation.
Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
1983fa
2
LTC1983-3/LTC1983-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Impedance vs
Input Voltage
Output Impedance
Efficiency vs I
(LTC1983-5)
vs I
(LTC1983-5)
OUT
OUT
90
80
70
60
50
40
30
20
10
0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
30
25
20
15
10
5
T
= 25°C
I
= 25mA
A
A
OUT
T
V
= 2.3V
IN
= 25°C
V
= 5V
IN
V
= 3.3V
V
IN
= 2.3V
IN
R
OUT
V
= 3.3V
IN
9.0
V
= 5V
IN
8.5
T
= 25°C
A
8.0
2.35
0
80
100
20
40
60
(mA)
3.35
5.35
0
20
40
I
60
(mA)
80
100
4.35
I
V
(V)
OUT
IN
OUT
1983 G01
1983 TA02
1983 G03
–3V
IN
vs I
Over Temperature
OUT
OUT
Efficiency vs I
–3V
vs I
Over Temperature
(V = 5V)
OUT
OUT
OUT
100
75
50
25
0
–2.1
–2.3
–2.5
–2.7
–2.9
–3.1
–3.3
–3.5
3.3
3.2
3.1
3.0
2.9
2.8
2.7
V
A
= –3V
V
IN
= 5V
OUT
= 25°C
T
V
= 3.3V
IN
120°C
80°C
V
IN
= 5V
–40°C 0°C
40°C
80°C
–40°C, 0°C, 40°C
0.1
1
100
0.01
10
80
OUTPUT CURRENT (mA)
120
0
40
60
80
100
120
0
20
40
60
100
20
I
(mA)
OUTPUT CURRENT (mA)
OUT
1983 GO4
1983 G05
1983 G06
Open-Loop Current
vs Temperature (LTC1983-5)
Open-Loop Input Current
vs V (LTC1983-5)
Burst Mode Current
vs Temperature (LTC1983-3)
IN
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
50
45
40
35
V
= 5V
V
IN
= 5V
T
= 25°C
IN
A
30
25
20
15
10
60
10
TEMPERATURE (°C)
110
2.3
3.3
3.3
(V)
4.3
4.8
10
60
–40
–40
110
2.8
V
TEMPERATURE (°C)
IN
1983 G07
1983 G09
1983 G08
1983fa
3
LTC1983-3/LTC1983-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Input Current
vs V (LTC1983-3)
R
(I
vs Temperature
= 10mA)
SHDN Pin Threshold Voltage
vs Temperature
OUT
OUT
IN
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
31.0
30.5
30.0
29.5
29.0
28.5
28.0
27.5
27.0
18
16
14
12
10
8
T
= 25°C
A
I
= 10mA
OUT
V
IN
= 3V
V
= 5V
IN
6
4
2
26.5
0
–50
0
50
100
150
3.1
5.1
5.5
–50
0
50
100
150
3.6
4.1
V
4.6
TEMPERATURE (°C)
(V)
TEMPERATURE (°C)
IN
1983 G12
1983 G10
1983 G11
SHDN Pin Input Current
vs Temperature
V
Start-Up into 100mA
OUT
R
OUT
vs C (V = 5V)
FLY IN
Resistive Load
1400
3.5
3.0
2.5
V
A
= 5V
IN
T
= 25°C
1200
1000
800
600
400
200
0
VOUT
1V
2.0
1.5
1.0
0.5
0
VIN
5V
50µs/DIV
1983 G15
0
50
TEMPERATURE (°C)
150
–50
100
0.1
(µF)
1
0.01
C
FLY
1983 G13
1983 G14
V
Load Step Reponse from
OUT
OUT
V
Ripple at 100mA Load
V
Ripple at 30mA Load
I
= 0 to I
= 100mA
OUT
OUT
OUT
VOUT
20mV
VOUT
20mV
VOUT
20mV
IOUT
100mA
1µs/DIV
1983 G16
2.5µs/DIV
1983 G17
100µs/DIV
1983 G18
1983fa
4
LTC1983-3/LTC1983-5
U
U
U
PI FU CTIO S
VIN (Pin 1): Charge Pump Input Voltage. May be between
2.3V and 5.5V. VIN should be bypassed with a ≥4.7µF low
ESR capacitor as close as possible to the pin for best
performance.
C–(Pin4):ChargePumpFlyingCapacitorNegativeTermi-
nal. This node is switched between GND and VOUT (It is
connected to GND during shutdown).
GND (Pin 5): Signal and Power Ground for the 6-Pin
SOT-23 package. This pin should be tied to a ground plane
for best performance.
VOUT (Pin 2): Regulated Output Voltage for the IC. VOUT
should be bypassed with a ≥4.7µF low ESR capacitor as
close as possible to the pin for best performance.
C+ (Pin 3): Charge Pump Flying Capacitor Positive Termi-
nal. This node is switched between VIN and GND (It is
connected to VCC during shutdown).
SHDN (Pin 6): Shutdown. Grounding this pin shuts down
the IC. Tie to VIN to enable. This pin should not be pulled
above the VIN voltage or below GND.
W
BLOCK DIAGRA
LTC1983-X
V
IN
C
IN
10µF
S1A
+
C
S2A
CLOCK1
CLOCK2
C
FLY
SHDN
1µF
CONTROL
LOGIC
V
REF
S1B
–
C
+
–
S2B
V
OUT
CHARGE PUMP
COMP1
C
OUT
1µA
10µF
1983 BD
1983fa
5
LTC1983-3/LTC1983-5
U
OPERATIO (Refer to Block Diagram)
The LTC1983-3/LTC1983-5 use a switched capacitor
charge pump to invert a positive input voltage to a regu-
lated –3V ±4% (LTC1983-3) or –5 ±4% (LTC1983-5)
output voltage. Regulation is achieved by sensing the
output voltage through an internal resistor divider and
enablingthechargepumpwhentheoutputvoltagedroops
above the upper trip point of COMP1. When the charge
pump is enabled, a 2-phase, nonoverlapping clock con-
trols the charge pump switches. Clock 1 closes the S1
switches which enables the flying capacitor to charge up
to the VIN voltage. Clock 2 closes the S2 switches that
invert the VIN voltage and connect the bottom plate of CFLY
to the output capacitor at VOUT. This sequence of charging
and discharging continues at a free-running frequency of
900kHz (typ) until the output voltage has been pumped
down to the lower trip point of COMP1 and the charge
pump is disabled. When the charge pump is disabled, the
LTC1983 draws only 25µA (typ) from VIN which provides
high efficiency at low load conditions.
For all ROUT values, check the corresponding curves in
the Typical Performance Characteristics section (Note:
CFLY = 1µF for all ROUT curves). The ROUT value will be
different for different flying caps, as shown in the follow-
ing equation:
Short-Circuit/Thermal Protection
During short-circuit conditions, the LTC1983 will draw
several hundred milliamps from VIN causing a rise in the
junction temperature. On-chip thermal shutdown cir-
cuitry disables the charge pump once the junction tem-
peratureexceeds≈155°C,andreenablesthechargepump
once the junction temperature falls back to ≈145°C. The
LTC1983 will cycle in and out of thermal shutdown
indefinitely without latchup or damage until the VOUT
short is removed.
In shutdown mode, all circuitry is turned off and the part
draws less than 1µA from the VIN supply. VOUT is also
disconnected from VIN and CFLY. The SHDN pin has a
threshold of approximately 0.7V. The part enters shut-
downwhenalowisappliedtotheSHDNpin.TheSHDNpin
should not be floated; it must be driven with a logic high
or low.
Capacitor Selection
For best performance, it is recommended that low ESR
capacitors be used for both CIN and COUT to reduce noise
and ripple. The CIN and COUT capacitors should be either
ceramic or tantalum and should be 4.7µF or greater.
Aluminum electrolytic are not recommended because of
theirhighequivalentseriesresistance(ESR).Ifthesource
impedanceisverylow, CIN maynotbeneeded. Increasing
the size of COUT to 10µF or greater will reduce output
voltage ripple. The flying capacitor and COUT should also
have low equivalent series inductance (ESL). The board
layoutiscriticalaswellforinductanceforthesamereason
(the suggested board layout should be used).
Open-Loop Operation
TheLTC1983-3/LTC1983-5invertingchargepumpsregu-
lateat–3V/–5Vrespectively,unlesstheinputvoltageistoo
low or the output current is too high. The equations for
output voltage regulation are as follows:
VIN –5.06V > IOUT • ROUT (LTC1983-5)
VIN –3.06V > IOUT • ROUT (LTC1983-3)
Aceramiccapacitorisrecommendedfortheflyingcapaci-
tor with a value in the range of 0.1µF to 4.7µF. Note that
a large value flying cap (>1µF) will increase output ripple
unless COUT is also increased. For very low load applica-
tions, C1 may be reduced to 0.01µF to 0.047µF. This will
reduce output ripple at the expense of efficiency and
maximum output current.
If this condition is not met, then the part will run in open
loop mode and act as a low output impedance inverter for
which the output voltage will be:
VOUT = –[VIN –(IOUT • ROUT)]
1983fa
6
LTC1983-3/LTC1983-5
U
OPERATIO (Refer to Block Diagram)
There are many aspects of the capacitors that must be
taken into account. First, the temperature stability of the
dielectric is a main concern. For ceramic capacitors, a
three character code specifies the temperature stability
(e.g. X7R, Y5V, etc.). The first two characters represent
the temperature range that the capacitor is specified and
the third represents the absolute tolerance that the ca-
pacitor is specified to over that temperature range. The
ceramiccapacitorusedfortheflyingandoutputcapaci-
tors should be X5R or better. Second, the voltage coef-
ficient of capacitance for the capacitor must be checked
and the actual value usually needs to be derated for the
operating voltage (the actual value has to be larger than
the value needed to take into account the loss of capaci-
tance due to voltage bias across the capacitor). Third, the
frequency characteristics need to be taken into account
because capacitance goes down as the frequency of
oscillation goes up. Typically, the manufacturers have
capacitance vs frequency curves for their products. This
curve must be referenced to be sure the capacitance will
not be too small for the application. Finally, the capacitor
ESR and ESL must be low for reasons mentioned in the
following section.
results in higher ripple due to higher output voltage dV/dt.
HighESRcapacitors(ESR>0.1Ω)ontheoutputpincause
high frequency voltage spikes on VOUT with every clock
cycle.
There are several ways to reduce the output voltage ripple.
A larger COUT capacitor (22µF or greater) will reduce both
the low and high frequency ripple due to the lower COUT
charging and discharging dV/dt and the lower ESR typi-
cally found with higher value (larger case size) capacitors.
A low ESR ceramic output capacitor will minimize the high
frequency ripple, but will not reduce the low frequency
rippleunlessahighcapacitancevalueischosen.Areason-
able compromise is to use a 10µF to 22µF tantalum
capacitor in parallel with a 1µF to 4.7µF ceramic capacitor
on VOUT to reduce both the low and high frequency ripple.
However, the best solution is to use 10µF to 22µF, X5R
ceramic capacitors which are available in 1206 package
sizes. An RC filter may also be used to reduce high
frequency voltage spikes (see Figure 1).
In low load or high VIN applications, smaller values for
CFLY may be used to reduce output ripple. A smaller flying
capacitor (0.01µF to 0.047µF) delivers less charge per
clock cycle to the output capacitor resulting in lower
output ripple. However, the smaller value flying caps also
reduce the maximum IOUT capability as well as efficiency.
Output Ripple
NormalLTC1983operationproducesvoltagerippleonthe
VOUT pin.OutputvoltagerippleisrequiredfortheLTC1983
to regulate. Low frequency ripple exists due to the hyster-
esisinthesensecomparatorandpropagationdelaysinthe
chargepumpenable/disablecircuits.Highfrequencyripple
is also present mainly due to ESR of the output capacitor.
Typical output ripple under maximum load is 60mVP-P
with a low ESR 10µF output capacitor. The magnitude of
the ripple voltage depends on several factors. High input
LTC1983-X
3.9Ω
V
OUT
V
OUT
10µF
TANTALUM
10µF
TANTALUM
LTC1983-X
V
V
OUT
OUT
voltage to negative output voltage differentials [(VIN
+
15µF
TANTALUM
1µF
CERAMIC
VOUT) >1V] increase the output ripple since more charge
isdeliveredtoCOUT perclockcycle.Alargeflyingcapacitor
(>1µF) also increases ripple for the same reason. Large
outputcurrentloadand/orasmalloutputcapacitor(<10µF)
1983 F01
Figure 1. Output Ripple Reduction Techniques
1983fa
7
LTC1983-3/LTC1983-5
U
OPERATIO (Refer to Block Diagram)
Inrush Currents
LTC1983-3
3.3V TO 5.5V
FROM MPU
SHDN
V
V
SHDN
IN
IN
During normal operation, VIN will experience current tran-
sientsintheseveralhundredmilliamprangewheneverthe
charge pump is enabled. During start-up, these inrush
currents may approach 1 to 2 amps. For this reason, it is
important to minimize the source resistance between the
input supply and the VIN pin. Too much source resistance
may result in regulation problems or even prevent start-
up. One way that this can be avoided (especially when the
source impedance can’t be lowered due to system con-
straints) is to use a large VIN capacitor with low ESR right
at the VIN pin. If ceramic capacitors are used, you may
need to add 1µF to 10µF tantalum capacitor in parallel to
limit input voltage transients. Input voltage transients will
occur if VIN is applied via a switch or a plug. One example
of this situation is in USB applications.
C
IN
10µF
TANTALUM
–3V ± 4%
GND
V
OUT
C
OUT
10µF
CERAMIC
+
–
C
C
C
FLY
1µF
CERAMIC
SHDN PIN WAVEFORMS:
LOW I MODE
V
LOAD ENABLE MODE
= 100µA TO 100mA)
Q
OUT
(I
(I
≤ 100µA)
OUT
OUT
(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
1983 F02
Figure 2. Ultralow Quiescent Current Regulated Supply
Ultralow Quiescent Current Regulated Supply
The LTC1983 must be out of shutdown for a minimum
durationof200µstoallowenoughtimetosensetheoutput
and keep it in regulation. A 1Hz, 2% duty cycle signal will
keep VOUT in regulation under no-load conditions. Even
thoughthetermno-loadisused,therewillalwaysbeboard
leakage current and leakage current drawn by anything
connected to VOUT. This is why it is necessary to wake the
part up every once in a while to verify regulation. As the
VOUT load current increases, the frequency with which the
part is taken out of shutdown must also be increased to
prevent VOUT from drooping below the – 2.88V (for the 3V
version) during the OFF phase (see Figure 3). A 100Hz, 2%
duty cycle signal on the SHDN pin ensures proper regula-
tion with load currents as high as 100µA. When load
current greater than 100µA is needed, the SHDN pin must
be forced high as in normal operation.
The LTC1983 contains an internal resistor divider (refer to
the Block Diagram) that draws only 1µA (typ for the 3V
version)fromVOUT duringnormaloperation. Duringshut-
down, the resistor divider is disconnected from the output
and the part draws only leakage current from the output.
During no-load conditions, applying a 1Hz to 100Hz, 2%
to 5% duty cycle signal to the SHDN pin ensures that the
circuit of Figure 2 comes out of shutdown frequently
enough to maintain regulation even under low-load condi-
tions. Since the part spends nearly all of its time in
shutdown, the no-load quiescent current is essentially
zero. However, the part will still be in operation during the
time the SHDN pin is high, so the current will not be zero
and can be calculated using the following equations to
determine the approximate maximum current: IIN(MAX)
=
[(Time out of shutdown) • (Burst Mode operation quies-
cent current) + (Normal operating IIN) • (Time output is
being charged before the LTC1983 enters Burst Mode
operation)]/(Period of SHDN signal). This number will be
highly dependent on the amount of board leakage current
and how many devices are connected to VOUT (each will
draw some leakage current) and must be calculated and
verified for each different board design.
Each time the LTC1983 comes out of shutdown, the part
delivers a minimum of one clock cycle worth of charge to
the output. Under high VIN (>4V) and/or low IOUT (<10µA)
conditions, thisbehaviormaycauseanetexcessofcharge
to be delivered to the output capacitor if a high frequency
signal is used on the SHDN pin (e.g., 50Hz to 100Hz).
Under such conditions, VOUT will slowly drift positive and
may even go out of regulation. To avoid this potential
1983fa
8
LTC1983-3/LTC1983-5
U
OPERATIO (Refer to Block Diagram)
1000
100
10
problem in the low IQ mode, it is necessary to switch the
part in and out of shutdown at the minimum allowable
frequency (refer to Figure 3) for a given output load.
SHDN ON PULSE WIDTH = 200µs
OUT
C
= 10µF
General Layout Considerations
Due to the high switching frequency and high transient
currentsproducedbytheLTC1983, carefulboardlayoutis
a must. A clean board layout using a ground plane and
short connections to all capacitors will improve perfor-
mance and ensure proper regulation under all conditions
(refer to Figures 4a and 4b). You will not get advertised
performance with careless layout.
1
1
10
100
1000
OUTPUT CURRENT (µA)
1983 F03b
Figure 3
V
IN
: 2.3V TO 5.5V
C
IN
1
2
3
V
V
C
SHDN
GND
6
IN
V
5
4
OUT
OUT
+
–
C
C
FLY
1983 F04a
C
OUT
Figure 4a. Recommended Component
Placement for a Single Layer Board
TOP LAYER
BOTTOM LAYER
C
1
2
3
V
SHDN
GND
6
5
4
IN
IN
V
OUT
V
OUT
C
OUT
+
–
C
C
C
FLY
1983 F04b
Figure 4b. Recommended Component
Placement for a Double Layer Board
1983fa
9
LTC1983-3/LTC1983-5
U
TYPICAL APPLICATIO S
2.5V to –2.5V DC/DC Converter
V
V
OUT
–2.5V
IN
V
V
OUT
IN
2.5V
4.7µF
CERAMIC
1µF
LTC1983-5
CERAMIC
GND
SHDN
OFF ON
–
+
C
C
1983 TA03
0.47µF
CERAMIC
100mA Inverting DC/DC Converter
V
V
OUT
–V
IN
V
V
OUT
IN
2.5V TO 5.5V
IN
10µF
CERAMIC
10µF
LTC1983-5
GND
SHDN
OFF ON
–
+
C
C
1983 TA04
1µF
CERAMIC
1983fa
10
LTC1983-3/LTC1983-5
U
PACKAGE DESCRIPTIO
S6 Package
6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1983fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1983-3/LTC1983-5
U
TYPICAL APPLICATIO
Combined Unregulated Doubler
and Regulated Inverter
V
IN
V
V
OUT
V
IN
OUT
C
IN
10µF
C
OUT1
LTC1983-3/
LTC1983-5
10µF
CERAMIC
CERAMIC
OFF ON
SHDN
GND
+
–
C
C
C
FLY
D1
1µF
CERAMIC
C
BOOST
1µF
D2
V
BOOST
C
OUT2
10µF
V
= 2V –2(V )
IN
BOOST
D
CERAMIC
1983 TA05
RELATED PARTS
PART NUMBER
LTC1261
DESCRIPTION
COMMENTS
Switched-Capacitor Regulated Voltage Inverter
Switched-Capacitor Regulated Voltage Inverter
Selectable Fixed Output Voltages
LTC1261L
Adjustable and Fixed Output Voltages, Up to 20mA I , MSOP
OUT
LTC1429
Clock-Synchronized Switched-Capacitor Voltage Inverter
Step-Up/Step-Down Switched-Capacitor DC/DC Converters
Micropower Regulated 5V Charge Pump DC/DC Converter
Micropower Regulated 5V Charge Pump DC/DC Converter
Synchronizable Up to 2MHz System Clock
LTC1514/LTC1515
LTC1516
V
2V to 10V, Adjustable or Fixed V , I
to 50mA
IN
OUT OUT
I
I
= 20mA (V ≥ 2V), I
= 50mA (V ≥ 3V)
OUT
OUT
IN
OUT IN
LTC1522
= 10mA (V ≥ 2.7V), I
= 20mA (V ≥ 3V)
OUT IN
IN
LTC1550L/LTC1551L Low Noise, Switched-Capacitor Regulated Voltage Inverters 900kHz Charge Pump, 1mV Ripple
P-P
LT1611
1.4MHz Inverting Mode Switching Regulator
Micropower, Switched-Capacitor Voltage Inverter
Doubler Charge Pumps with Low Noise LDO
Doubler Charge Pumps
–5V at 150mA from a 5V Input, 5-Lead ThinSOT
1.2V/1V to 15V; 350mA/100mA Current Limit
LT1617/LT1617-1
LTC1682/-3.3/-5
LTC1751/-3.3/-5
LTC1754/-3.3/-5
LTC1928-5
V
IN
MS8 and SO-8 Packages, I
= 80mA, Output Noise = 60µV
RMS
OUT
V
=5V at 100mA; V
=3.3V at 80mA; ADJ; MSOP Packages
OUT
OUT
Doubler Charge Pumps with Shutdown
Doubler Charge Pump with Low Noise LDO
Constant Frequency Doubler Charge Pump
ThinSOT Package; I = 13µA; I
= 50mA
Q
OUT
ThinSOT Output Noise = 60µV
; V
= 5V; V = 2.7V to 4V
RMS OUT IN
LTC3200
Low Noise, 5V Output or Adjustable
1983fa
LT/LWI 0606 REV A • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2002
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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