LTC2122_技术文档

DEMO MANUAL DC1974

LTC2123, LTC2122

14-Bit, 250Msps to 170Msps Dual

ADCs with JESD204B Outputs

DESCRIPTION

Demonstration circuit 1974 supports the LTC^®2123 14-bit

dual ADC family with JESD204B compliant CML outputs.

It was specially designed for applications that require

single-endedACcoupledinputs.TheDC1974supportsthe

LTC2123 and LTC2122 with sample rates from 250Msps

to 170Msps.

Refer to the data sheet for proper input networks for dif-

ferent input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo/DC1974

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

The specific ADC characteristics are listed in the DC1974

Variants section. The circuitry on the analog inputs is opti-

mizedforanaloginputfrequenciesfrom5MHzto400MHz.

DC1974 VARIANTS

RESOLUTION

MAXIMUM SAMPLE RATE

(Msps)

INPUT FREQUENCY

(MHz)

DC1974 VARIANTS

1974A-B

ADC PART NUMBER

LTC2123

(Bit)

14

250

170

5 to 400

1974A-C

LTC2122

14

PERFORMANCE SUMMARY ^{Specifications are at T}_A^{= 25°C}

PARAMETER

CONDITION

MIN

4

TYP

MAX

6

UNIT

ADC Supply Voltage

This Supply Must Provide Up to 700mA

V

Analog Input Range

1.35

10

0

1.5

250

V

PP

Sampling Frequency (Device Clock Frequency)

Device Clock Level (Single-Ended at J3)

Depending on ADC (1X CLK Mode)

MHz

V

Minimum Logic Levels (DEV + Tied to GND)

CLK

Maximum Logic Levels (DEV + Tied to GND)

3.6

V

CLK

Device Clock Level (Differential Signal Across J3 and J4) Minimum Logic Levels (DEV + Not Tied to GND,

0.2

1.1

V

CLK

1.2V Common Mode)

Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P,

SYNC_N, SYNC_P)

Differential Input Voltage

1.8

1.5

V

Common Mode Input Range

1.2

dc1974fa

1

DEMO MANUAL DC1974

QUICK START PROCEDURE

Demonstrationcircuit1974iseasytosetuptoevaluatethe

performance of the LTC2123 A/D converter family. Refer

to Figure 1 for proper measurement equipment setup and

follow the procedure below:

SETUP

TheDC1974evaluationsystemusesstandard,offtheshelf

FPGA evaluation boards for data capture and communi-

cation with the host computer. Follow the instructions in

Appendix A for the Xilinx KC705 based system. Verilog

codemaybedownloadedfromtherespectiveADClanding

page. www.linear.com/LTC2123

OPTIONAL FPGA

REFERENCE

CLOCK INPUT

OPTIONAL FPGA

REFERENCE

SIGNAL INPUT

4V TO 6V

THE DC1974 CONNECTS TO

KC705 VIA AN FMC CONNECTOR

CHANNEL 1

SINGLE-ENDED

ANALOG INPUT

CHANNEL 2

SINGLE-ENDED

ANALOG INPUT

dc1974 F01

JUMPERS SHOWN IN THEIR

DEFAULT POSITIONS

SINGLE-ENDED DEVICE

CLOCK INPUT

OPTIONAL SYS_REF

INPUT FOR ADC

(SUB CLASS 1 ONLY)

OPTIONAL SYS_REF

INPUT FOR FPGA

(SUB CLASS 1 ONLY)

Figure 1. DC1974 Setup

dc1974fa

2

DEMO MANUAL DC1974

HARDWARE SETUP

SMAs

TURRETS

J1: AINA – Analog input for channel A – Apply a signal to

J1 from a 50Ω driver. Filters are required for data sheet

performance.

V+: Positive supply voltage for the ADC and digital

logic – This voltage feeds a regulator that supplies the

propervoltagesfortheADCandbuffers.Thevoltagerange

for this turret is 4V to 6V. The supply should be able to

deliver 700mA of current.

J2: AINB – Analog input for channel B – Apply a signal to

J2 from a 50Ω driver. Filters are required for data sheet

performance.

SENSE: Optional reference voltage – This pin is connected

directly to the SENSE pin of the ADC. Connecting SENSE

to VDD selects the internal reference and a 0.66V input

range. The same input voltage range can be achieved

by applying an external 1.25V reference to SENSE. If no

external voltage is supplied this pin will be pulled up to

VDD through a 1k pull-up resistor.

J3: DEV – – Encode clock input for single-ended

CLK

clocks – By default the DC1974 is defined to accept a

single-ended clock signal on J3. It can be modified to ac-

cept a differential clock signal through J3 and J4. Some

component changes are required, see the encode clock

section for more information.

1.8V OUT: Optional 1.8V turret – This pin is connected

directly to the VDD pin of the ADC. It requires a supply that

candeliverupto500mA.Drivingthispinwillshutdownthe

on board regulator. It can also be a test point to measure

the voltage at the output of the regulators.

J4: DEV + – Encode clock input for differential sig-

CLK

nals – By default the DC1974 is defined to accept a

single-ended clock signal on J3. It can be modified to

accept a differential clock signal through J3 and J4. Some

component changes are required, see the encode clock

section for more information.

GND: Ground Connection – This demo board only has a

single ground plane. This turret should be tied to the GND

terminal of the power supply being used.

J5 and J6: ADC_SYS_REF – JESD204B Subclass 1 only –

When testing the ADC in subclass 1 operation a SYS_REF

input is required to synchronize the ADC and FPGA. Apply

a SYS_REF signal to this input from a SYS_REF driver

board. This input drives the SYS_REF of the ADC.

JUMPERS:

JP1EEPROM:EEPROMwriteprotect.Forfactoryuseonly.

Should be left in the enable (PROG) position.

J11 and J12: FPGA_SYS_REF – JESD204B Subclass 1

only – When testing the ADC in subclass 1 operation a

SYS_REF input is required to synchronize the ADC and

FPGA.ApplyaSYS_REFsignaltothisinputfromaSYS_REF

driver board. This input drives the SYS_REF of the FPGA.

JP2 SYNC: This jumper is provided to manually force the

SYNC~ signal of the ADC to a known value. By default,

the resistors connecting this jumper are removed. If R20

and R21 are installed the SYNC jumper can be used to

force SYNC~ high or low depending on the position of the

jumper. Position 0 is for low and 1 is for high.

J7 and J8: FPGA_GBT_REF – This is an optional reference

port for the FPGA. It is used for testing purposes only. In

the default configuration these SMAs are not used.

J9 and J10: FPGA_CLK – This is an optional clock input

port for the FPGA. It is used for testing purposes only. In

the default configuration these SMAs are not used.

dc1974fa

3

DEMO MANUAL DC1974

APPLYING POWER AND SIGNALS TO THE DC1974 DEMONSTRATION CIRCUIT

DC1974 requires up to 700mA. The DC1974 should not be

removed or connected to the Kintex 7 FPGA board while

power is applied.

If a Kintex 7 FPGA board is used to acquire data from

the DC1974, the Kintex 7 FPGA board must FIRST be

poweredBEFOREapplying4Vto6Vacrossthepinsmarked

“V+” and “GND” on the DC1974. For more information

about the Kintex 7 board, please see the demo manual at

www.xilinx.com.TheDC1974requiresatleast4Vforproper

operation. Regulators on the board produce the voltages

required for the ADC and the required logic devices. The

The DC2159 should also be connected to the Kintex 7

board and the supplied mini USB cable should be con-

nected to the DC2159. The Kintex 7 board should be

poweredonBEFOREtheminiUSBconnectorisconnected

to the DC2159. See Figure 5 in Appendix A.

ANALOG INPUT NETWORK

Apply the analog input signal of interest to the SMA con-

nectorontheDC1974boardmarkedJ1orJ2.Inthedefault

setup, the DC1974 has a single SMA input that is meant

to be driven with a 50Ω source. The DC1974 is populated

with an input network that has 50Ω characteristic imped-

ance over a wide frequency range. This can be modified

to produce different frequency responses as needed. Al-

though the input of the DC1974 is single-ended, there is a

transformer on the board that translates the single-ended

signal to a differential signal to drive the ADC.

In almost all cases, off board filters with good return loss

will be required on the analog input of the DC1974 to

produce data sheet SNR.

The off board filter should be located close to the input

of the demo board to avoid reflections from impedance

discontinuitiesatthedrivenendofalongtransmissionline.

Most filters do not present 50Ω outside the passband. In

some cases, 3dB to 10dB pads may be required to make

the filter look more like 50Ω to obtain low distortion.

ENCODE CLOCK

ApplyanencodeclocktotheSMAconnectorontheDC1974

marked J3. By default, the DC1974 is configured to have

a single-ended clock input. Although the clock input of

the DC1974 is single-ended, there is a transformer on

the board that translates the single-ended signal to a dif-

ferential signal to drive the ADC.

The DC1974 is designed to accept single-ended signals

by default. To modify the DC1974 to accept a differential

signal, remove C33, R44, R45 and R46. Populate R49,

R43, R48 and R47 with 0Ω resistors. Drive the demo

board with a differential signal on J3 and J4. These SMAs

are positioned 0.5" apart to accommodate LTC differential

clock boards.

For the best noise performance, the encode input must

be driven with a very low jitter signal generator source.

The amplitude should be as large as possible up to 2V

or 10dBm.

P-P

dc1974fa

4

DEMO MANUAL DC1974

SOFTWARE

The DC1974 is controlled by the PScope^™System Soft-

ware provided or downloaded from the Linear Technology

website at http://www.linear.com/software/. If a Kintex 7

FPGA board and DC2159 were provided, follow the demo

manual of these boards for proper setup.

Manual Configuration settings:

Bits: 14

Alignment: 16

Channs: 2

The Kintex 7 FPGA board will act as the data collection

board and the DC2159 is used to connect the FPGA to

the computer. These boards both are designed to work

seamlessly with PScope, Linear Technology’s data col-

lection software.

Bipolar: Unchecked

Positive-Edge Clk: Unchecked

If everything is hooked up properly, powered and a suit-

able encode clock is present, clicking the “Collect” button

should result in time and frequency plots displayed in

the PScope window. Additional information and help for

PScope is available in the KC705 guide and in the online

help available within the PScope program itself.

To start the data collection software and if “PScope.exe”

is installed (by default) at \Program Files\LTC\PScope\,

double click the PScope icon or bring up the run window

under the start menu and browse to the PScope directory

and select PScope.

NOTE: If a PRBS error occurs hit connect again. This

is a bug in the first version of the software.

If the DC1974 is properly connected to the Kintex 7 FPGA

boardandtheDC2159,PScopeshouldautomaticallydetect

the DC1974 and configure itself accordingly. If necessary

the procedure below explains how to manually configure

PScope.

SERIAL PROGRAMMING

PScope has the ability to program the DC1974 board

serially through the DC2159. There are several options

available for the LTC2123 family that are only available

through serial programming. PScope allows all of these

features to be tested.

Underthe“Configure”menu, go to “ADC Configuration...”

Check the “Config Manually” box and use the following

configuration options, shown in Figure 2:

These options are available by first clicking on the “Set

Demo Bd Options” icon on the PScope toolbar (Figure 3).

This will bring up the menu shown in Figure 4.

Figure 3: PScope Toolbar

Figure 2: ADC Configuration

dc1974fa

5

DEMO MANUAL DC1974

SOFTWARE

Nap Mode – Selects between normal operation and

nap mode.

n

Off (Default) – Entire ADC is powered and active.

n

On – The entire ADC is put into nap mode.

Channel B Power Down – Selects between normal opera-

tion and powering down channel B.

n

Off (Default) – Normal operation.

n

On – Channel B is powered down.

Channel A Power Down – Selects between normal opera-

tion and powering down channel B.

n

Off (Default) – Normal operation.

n

On – Channel A is powered down.

2x Clock – Selects between a sample rate equal to the

device clock, or device clock twice the sample rate.

n

Off (Default) – DEV

is equal to the sample rate.

CLK

n

On – DEV

is twice the sample rate.

CLK

Overflow – Enables or disables the overflow bit in the

output data.

n

Disabled (Default) – Over flow bit is disabled.

n

Enabled – Overflow bit is enabled.

Duty Cycle Stabilizer – Enables or disables Duty Cycle

Stabilizer.

n

Stabilizeroff(Default)–DutyCycleStabilizerDisabled.

n

Stabilizer on – Duty Cycle Stabilizer Enabled.

Figure 4: Demo Bd Configuration Options

Device ID – Sets the device ID defined in JESD204B 8.3.

Default is 00000000, but can be set to whatever the user

chooses.

This menu allows any of the options available for the

LTC2123 to be programmed serially. The LTC2123 family

has the following options:

Bank ID – Sets the bank ID defined in JESD204B 8.3. De-

fault is 0000, but can be set to whatever the user chooses.

Sleep Mode – Selects between normal operation and

sleep mode.

Frames per MultiFrame – Selects number of frames in

eachmultiframeasdefinedinJESD204B5.3.3.5. Theuser

selects the number of desired frames per multiframe and

PScope configures the ADC accordingly. Valid values for

number of frames per multiframe are 9 to 32.

n

Off (Default) – Entire ADC is powered and active.

n

On – The entire ADC is powered down.

dc1974fa

6

DEMO MANUAL DC1974

SOFTWARE

Lane Alignment Sequence – Enables or disables the lane

alignment sequence.

TX Sync – Enables or disables Transmitter induced syn-

chronization.

n

Enabled (Default) – Lane alignment sequence is

enabled.

Disabled (Default) – Transmitter induced synchro-

nization is disabled.

n

Disabled - Lane alignment sequence is disabled.

Enabled - Transmitter induced synchronization

is enabled.

Lane Alignment Monitor – Enables or disables the lane

monitor sequence.

Test Pattern – Selects the data presented at the output

of the ADC

n

Enabled(Default)–Lanealignmentmonitorsequence

is enabled.

Normal ADC Data (Default) – The data that is sampled

by the input of the ADC

n

Disabled – Lane alignment monitor sequence is

disabled.

K28.5 Pattern – A repeating SYNC comma.

K28.7 Pattern – 1111100000.

FrameAlignmentMonitor–EnablesordisablestheFrame

monitor sequence

D21.5 Pattern – 1010101010.

n

Enabled (Default) – Frame alignment monitor se-

quence is enabled.

PRBS15 Pattern – A Pseudorandom bit sequence pat-

tern described by 1 + x + x .

14

15

n

Disabled – Frame alignment monitor sequence is

disabled.

Lane Alignment Sequence – The lane alignment se-

quence is transmitted according to tables 3a to 3h from

the datasheet.

Reset Dividers (Subclass 1 or 2 Only) – Enables or dis-

ables SYSREF reset of dividers.

TestSamplesSequence–Thetestsamplesarerepeat-

edly transmitted according to tables 4a to 4b from the

datasheet.

n

Enabled(Default)–Subclass1–EnablestheSYSREF

reset of dividers. Subclass 2 – Enables SYNC~ reset

of dividers.

Modified RPAT Pattern – A modified RPAT pattern as

described in IEEE Std. 802.3-2008 Annex 48A.

n

Disabled – Subclass 1 – Disables the SYSREF reset

of dividers. Subclass 2 – Disables SYNC~ reset of

dividers.

CML Output Magnitude – Magnitude of the CML out-

put signals.

Scrambling – Enables or disables the scrambling of the

output data.

Value selections are:

10mA (250mV) Default

12mA (300mV)

n

Disabled (Default) – Scrambling is disabled.

n

Enabled – Scrambling is enabled.

14mA (350mV)

Alert Mode De-arm Length (Subclass 1 Only) – Selects

the de-arming length in multiframe periods to trigger the

alert in subclass 1. Valid values are 1 to 8.

16mA (400mV)

Once the desired settings are selected hit OK and PScope

will automatically update the register of the device on the

DC1974 demo board.

Alert Mode (Subclass 1 Only) – Enables or disables the

alert mode.

n

Disabled (Default) – Alert mode is disabled.

n

Enabled – Alert mode is enabled.

dc1974fa

7

DEMO MANUAL DC1974

APPENDIX A

XILINX KC705 BASED EVALUATION SYSTEM

4) Apply power, encode clock and analog input signals to

the DC1974 board.

ThedemonstrationsystemfortheLTC2123familyconsists

of the DC1974, a Xilinx KC705 FPGA evaluation board, a

DC2159USBcommunicationboardandahostPCrunning

the PScope software.

5) VerifythatPScopesoftwareisinstalled.ConnectDC2159

tothehostPCwithaUSB-minicable. Driverinstallation

will start automatically and PScope will recognize the

DC1974 when installation ﬁnishes.

Complete systems that ship from Linear Technology will

have the KC705 board configured to automatically load

the default subclass 0 FPGA image from the onboard

configuration EEPROM. The procedure for bringing up

the system is as follows:

NOTE: Power must be applied to the KC705 board when

the USB cable is connected or the driver installation will

not complete properly.

ALTERNATE FPGA CONFIGURATION

1) If the boards were obtained separately, assemble them

asshowninFigure5(FMCconnectorsarefragile, make

sure they are properly aligned before seating.)

KC705 boards not obtained from Linear Technology will

need to be configured via JTAG. FPGA images are located

in the PScope installation directory in the FPGA_images

folder. Connect a USB micro cable to the JTAG USB con-

nector on the KC705 board and use a Xilinx tool such as

Impact to load the Subclass 0, 2 lane bitfile. Once the

FPGA is configured, remove the USB cable and exit the

software. (The onboard JTAG adapter and the DC2159

USB communication board use the same USB controller

and they may interfere with one another.)

2) Connect power supply to the KC705 board and turn on

thepowerswitch.Iftheassembledsystemwasobtained

from Linear Technology, the subclass 0 image will load

automaticallyfromtheonboardconﬁgurationmemory.

3) Boards not obtained from Linear Technology will need

to be conﬁgured as described in the Alternate FPGA

Conﬁguration section.

dc1974fa

8

DEMO MANUAL DC1974

APPENDIX A

5. CONNECT

DC2159

TO PC

4. POWER-UP

DC1974, TURN ON

CLOCK AND

ANALOG INPUTS

1. ASSEMBLE BOARDS

2. POWER-UP

KC705

3. CONFIGURE

FPGA VIA JTAG

(IF NECESSARY),

THEN REMOVE

USB CABLE

dc1974 F05

Figure 5. KC705 Based Demonstration System

dc1974fa

9

DEMO MANUAL DC1974

PARTS LIST

ITEM QTY REFERENCE

PART DESCRIPTION

MANUFACTURER/PART #

Required Circuit Components

1

2

1

4

7

1

C1, C2

CAP., X5R, 1µF, 10V, 10%, 0402

CAP., TANT, 100µF, 10V, 10%, 6032

CAP., X7R, 47µF,10V, 10%, 1210

CAP., X5R, 2.2µF, 10V, 20%, 0603

CAP., X7R, 0.01µF, 16V, 10%, 0402

CAP., X5R, 10µF, 6.3V, 20%, 0805

AVX, 0402ZD105KAT2A

C3

AVX, TAJW107K010RNJ

3

C4

MURATA, GRM32ER71A476KE15L

AVX, 0603ZD225MAT2A

4

C5, C11, C25, C26

C6, C33-C35, C50-C52

C7

5

AVX, 0402YC103KAT2A

6

AVX, 08056D106MAT2A

7

22 C10, C12-C24, C27-C32, C41, C53 CAP., X5R, 0.1µF, 10V, 10%, 0402

AVX, 0402ZD104KAT2A

8

4

8

4

2

C37, C38, C39, C40

C42-C49

CAP., C0G, 47pF, 16V, 10%, 0402

CAP., X7R, 1000pF, 50V, 10%, 0402

TESTPOINT, TURRET, 0.094"

HEADER, HD1X3-079

AVX, 0402YA470KAT2A

9

AVX, 04025C102KAT2A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

E1, E2, E3, E4

JP1, JP2

MILL-MAX, 2501-2-00-80-00-00-07-0

SULLINS, NRPN031PAEN-RC

EF JOHNSON, 142-0701-851

SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR

VISHAY, CRCW12060000Z0EA

MURATA, BLM31PG330SN1L

OPT

10 J1-J6, J9-J12

CONN., SMA 50Ω, EDGE-LAUNCH

CONN., BGA 40X10

0

1

0

2

1

4

J7, J8 (OPT)

J13

L1

RES., CHIP, 0Ω, 1206

L2

IND., FERRITE BEAD, 33Ω, 1206

RES., 1206

L3

R1,R59

RES., CHIP, 3.01k, 1/16W, 1%, 0402

RES., CHIP, 10k, 1/16W, 1%, 0402

RES., CHIP, 182k, 1/16W, 1%, 0402

RES., CHIP, 1k, 1/16W, 1%, 0402

RES., CHIP, 24.9Ω, 1/16W, 1%, 0402

RES., CHIP, 0Ω, 1/16W, 0402

VISHAY, CRCW04023K01FKED

VISHAY, CRCW040210K0FKED

VISHAY, CRCW0402182KFKED

NIC, NRC04F1001TRF

R2

R4

R5, R24, R25, R58

10 R6-R11, R32-R35

VISHAY, CRCW040224R9FKED

NIC, NRC04Z0TRF

11 R12, R13, R15, R16, R18, R39,

R40, R44, R45, R46, R57

24

25

5

0

R14, R17, R41, R56, R61

RES., CHIP, 100Ω, 1/16W, 1%, 0402

RES., 0402

NIC, NRC04F1000TRF

OPT

R19-R23, R42, R43, R48-R53,

R54, R55, R60

26

27

28

29

30

31

32

33

34

35

2

3

5

2

3

1

R26, R29

R27, R28

R30, R31

R36, R37,R38

R47, R62,R63,R64,R65

R66, R67

T1, T2, T3

U2

RES., CHIP, 20Ω, 1/16W, 1%, 0402

RES., CHIP, 49.9Ω, 1/16W, 1%, 0402

RES., CHIP, 300Ω, 1/16W, 1%, 0402

RES., CHIP, 4.99k, 1/16W, 1%, 0402

RES., CHIP, 4.99Ω, 1/16W, 1%, 0402

RES., CHIP, 100Ω, 1/20W, 1%, 0201

XFMR., MABA-007159-000000

NIC, NRC04F20R0TRF

VISHAY, CRCW040249R9FKED

NIC, NRC04F3000TRF

VISHAY, CRCW04024K99FKED

NIC, NRC04F4R99TRF

NIC, NRC02F1000TRF

M/A-COM, MABA-007159-000000

LINEAR TECH., LT3080EDD#PBF

LINEAR TECH., LT1763CDE-3.3#PBF

MICROCHIP, 24LC32A-I/ST

I.C., LT3080EDD#PBF, DFN 3X3

U3

I.C., LT1763CDE-3.3#PBF, DFN12DE-4X3

I.C. EEPROM 32KBIT 400KHz, TSSOP8

U6

dc1974fa

10

DEMO MANUAL DC1974

PARTS LIST

ITEM QTY REFERENCE

PART DESCRIPTION

MANUFACTURER/PART #

36

37

38

39

40

1

0

U7

I.C., NC7WZ14P6X, SC70-6

FAIRCHILD SEMI., NC7WZ14P6X

U9

I.C., LTC6957IDD-2#PBF, DFN12DD-3X3

SHUNT, 0.079" CENTER

LINEAR TECH., LTC6957IDD-2#PBF

SAMTEC, 2SN-BK-G

SHUNTS FOR JP1 & JP2

MH1, MH2

SCREW, M3 THREAD, #4-40x5/8"

KEYSTONE, 29316 (DO NOT INSTALL)

KEYSTONE, 24438 (DO NOT INSTALL)

MH1, MH2

STAND-OFF, ALUM., M3 THREAD, 5.0 HEX,

#4-40X1"

41

2

STENCILS

STENCILS (TOP & BOTTOM)

STENCIL DC1974A-3

DC1974A-B Required Circuit Components

1

2

1

DC1974A

U1

GENERAL BOM

I.C., 14-BIT, 250Msps, QFN48UK-7X7

LINEAR TECH., LTC2123IUK#PBF

LINEAR TECH., LTC2122IUK#PBF

DC1974A-C Required Circuit Components

1

2

1

DC1974A

U1

GENERAL BOM

I.C., 14-BIT, 170Msps, QFN48UK-7X7

dc1974fa

11

DEMO MANUAL DC1974

SCHEMATIC DIAGRAM

P E

3 1

V D D

7 3

8 3

4 2

3 2

V D D

C

D N

S Y N C _ N

9 3

0 4

1 4

2 4

2 2

S Y N C _ P

1 2

-

N F O

+ N F O

D N G

0 2

S D O

S D I

S C K

S Y S R E F _ N

3 4

4 4

5 4

6 4

9 1

S Y S R E F _ P

8 1

S C

D N G

7 1

D E V C L K +

P E

3 1

7

6 1

D N G

V D D

D E V C L K -

5 1

4 1

3 1

D N G

V D D

D N G

7 4

8 4

9 4

dc1974fa

12

DEMO MANUAL DC1974

SCHEMATIC DIAGRAM

V C C D N G

8

4

M

Y

R O E E P

A R R A

dc1974fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

13

DEMO MANUAL DC1974

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:

Thisdemonstrationboard(DEMOBOARD)kitbeingsoldorprovidedbyLinearTechnologyisintendedforuseforENGINEERINGDEVELOPMENT

OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete

in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety

measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union

directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date

of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU

OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS

FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR

ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims

arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all

appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or

agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,

customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and

observe good laboratory practice standards. Common sense is encouraged.

Thisnoticecontainsimportantsafetyinformationabouttemperaturesandvoltages. Forfurthersafetyconcerns, pleasecontact aLTCapplication

engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

dc1974fa

LT 0315 REV A • PRINTED IN USA

14 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2122
厂家：	Linear
描述：	14-Bit, 250Msps to 170Msps Dual ADCs with JESD204B Outputs
文件：	总14页 (文件大小：834K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2122 [Linear]

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