LTC2143IUP-14#TRPBF [Linear]
LTC2143-14 - 14-Bit, 80Msps Low Power Dual ADCs; Package: QFN; Pins: 64; Temperature Range: -40°C to 85°C;型号: | LTC2143IUP-14#TRPBF |
厂家: | Linear |
描述: | LTC2143-14 - 14-Bit, 80Msps Low Power Dual ADCs; Package: QFN; Pins: 64; Temperature Range: -40°C to 85°C 转换器 |
文件: | 总38页 (文件大小:662K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2145-14/
LTC2144-14/LTC2143-14
14-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
FEATURES
DESCRIPTION
TheLTC®2145-14/LTC2144-14/LTC2143-14are2-channel
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.1dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
n
Two-Channel Simultaneously Sampling ADC
n
73.1dB SNR
n
90dB SFDR
Low Power: 189mW/149mW/113mW Total
95mW/75mW/57mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
n
n
n
of0.08ps
allowsundersamplingofIFfrequencieswith
RMS
n
excellent noise performance.
Selectable Input Ranges: 1V to 2V
P-P
P-P
n
n
n
n
n
n
750MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm × 9mm) QFN Package
DC specs include 1LSB INL (typ), 0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.2LSB
.
RMS
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
APPLICATIONS
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Nondestructive Testing
TYPICAL APPLICATION
64k Point 2-Tone FFT, fIN = 69MHz,
70MHz, –1dBFS, 125Msps
1.8V
1.8V
OV
V
DD
DD
0
–10
–20
CH 1
ANALOG
INPUT
14-BIT
D1_13
S/H
S/H
t
–30
–40
–50
–60
–70
ADC CORE
t
t
CMOS,
D1_0
DDR CMOS
OR DDR LVDS
OUTPUTS
D2_13
t
t
t
OUTPUT
DRIVERS
CH 2
ANALOG
INPUT
14-BIT
ADC CORE
–80
–90
D2_0
–100
–110
–120
125MHz
CLOCK
CLOCK
CONTROL
0
20
30
40
50
60
10
FREQUENCY (MHz)
21454314 TA03b
21454314 TA01a
GND
OGND
21454314fa
1
LTC2145-14/
LTC2144-14/LTC2143-14
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltages (V , OV )....................... –0.3V to 2V
Digital Output Voltage ................–0.3V to (OV + 0.3V)
DD
DD
DD
+
–
Analog Input Voltage (A , A
,
Operating Temperature Range
IN
IN
PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)
LTC2145C, LTC2144C, LTC2143C............. 0°C to 70°C
LTC2145I, LTC2144I, LTC2143I............–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
DD
+
–
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
PIN CONFIGURATIONS
FULL RATE CMOS OUTPUT MODE
TOP VIEW
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
V
1
2
48 D1_3
47 D1_2
46 D1_1
45 D1_0
44 DNC
43 DNC
V
1
2
48 D1_2_3
47 DNC
46 D1_0_1
45 DNC
44 DNC
43 DNC
DD
DD
V
V
CM1
CM1
GND 3
GND 3
+
+
A
A
4
5
A
A
4
5
IN1
IN1
–
–
IN1
IN1
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
42 OV
42 OV
DD
DD
41 OGND
40 CLKOUT
39 CLKOUT
38 D2_13
37 D2_12
36 D2_11
35 D2_10
34 D2_9
41 OGND
40 CLKOUT
39 CLKOUT
38 D2_12_13
37 DNC
36 D2_10_11
35 DNC
65
GND
65
GND
+
–
+
–
PAR/SER 11
PAR/SER 11
+
+
A
A
12
13
A
A
12
13
IN2
IN2
GND 14
IN2
IN2
GND 14
–
–
V
15
16
V
15
16
34 D2_8_9
33 DNC
CM2
CM2
V
DD
33 D2_8
V
DD
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
T
= 150°C, θ = 20°C/W
T
= 150°C, θ = 20°C/W
JMAX
JA
JMAX JA
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
21454314fa
2
LTC2145-14/
LTC2144-14/LTC2143-14
PIN CONFIGURATIONS
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
+
V
1
2
48 D1_2_3
47 D1_2_3
46 D1_0_1
45 D1_0_1
44 DNC
43 DNC
DD
–
V
CM1
+
GND 3
+
–
A
A
4
5
IN1
–
IN1
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
42 OV
DD
41 OGND
65
GND
+
–
40 CLKOUT
39 CLKOUT
+
–
+
–
PAR/SER 11
38 D2_12_13
37 D2_12_13
36 D2_10_11
35 D2_10_11
+
A
A
12
13
IN2
–
IN2
GND 14
+
V
V
15
16
34 D2_8_9
CM2
–
33 D2_8_9
DD
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
T
JMAX
= 150°C, θ = 20°C/W
JA
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2145CUP-14#PBF
LTC2145IUP-14#PBF
LTC2144CUP-14#PBF
LTC2144IUP-14#PBF
LTC2143CUP-14#PBF
LTC2143IUP-14#PBF
TAPE AND REEL
PART MARKING*
LTC2145UP-14
LTC2145UP-14
LTC2144UP-14
LTC2144UP-14
LTC2143UP-14
LTC2143UP-14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2145CUP-14#TRPBF
LTC2145IUP-14#TRPBF
LTC2144CUP-14#TRPBF
LTC2144IUP-14#TRPBF
LTC2143CUP-14#TRPBF
LTC2143IUP-14#TRPBF
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21454314fa
3
LTC2145-14/
LTC2144-14/LTC2143-14
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2145-14
TYP
LTC2144-14
TYP
LTC2143-14
TYP MAX
PARAMETER
CONDITIONS
MIN
14
MAX
MIN
14
MAX
MIN
14
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–2.6
–0.9
–9
1
2.6
0.9
9
–2.6
–0.9
–9
1
2.6
0.9
9
–2.6
–0.8
–9
1
2.6
0.8
9
LSB
LSB
mV
0.3
1.5
0.3
1.5
0.3
1.5
Gain Error
Internal Reference
External Reference
1.5
–0.4
1.5
–0.3
1.5
–0.3
%FS
%FS
l
–1.8
0.9
–1.5
1.1
–1.5
1.1
Offset Drift
10
10
10
μV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
30
10
30
10
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
0.2
1.5
0.2
1.5
0.2
1.5
%FS
mV
1.25
1.28
1.20
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
1.7V < V < 1.9V
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)
0.7
V
CM
1.25
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE External Reference Mode
0.625
1.250
1.300
V
I
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
μA
μA
μA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A , A < V
–1.5
–3
1.5
3
μA
μA
μA
ns
IN1
IN
IN
DD
DD
0 < PAR/SER < V
IN2
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
–3
3
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
0
AP
Single-Ended Encode
Differential Encode
0.08
0.10
ps
ps
JITTER
RMS
RMS
CMRR
BW-3B
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
80
dB
Figure 6 Test Circuit
750
MHz
21454314fa
4
LTC2145-14/
LTC2144-14/LTC2143-14
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2145-14
TYP
LTC2144-14
TYP
LTC2143-14
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
SNR
Signal-to-Noise Ratio
5MHz Input
73.1
73
72.9
72.8
72.4
73.4
73.3
72.9
dBFS
dBFS
dBFS
l
l
l
l
l
70MHz Input
140MHz Input
71.4
71.2
71.7
72.6
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
90
89
84
90
89
84
90
89
84
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
76
79
77
79
78
81
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
90
89
84
90
89
84
90
89
84
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
95
95
95
95
95
95
95
95
95
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
86
86
86
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
73
72.8
72.2
72.8
72.6
72
73.2
73.1
72.4
dBFS
dBFS
dBFS
70.8
70.8
71.4
Crosstalk
10MHz Input
–110
–110
–110
dBc
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600μA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400μA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
21454314fa
5
LTC2145-14/
LTC2144-14/LTC2143-14
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
(Note 8)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
3.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
0.6
3.6
DD
+
ENC to GND
(See Figure 11)
(Note 8)
V
R
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
IH
IL
DD
DD
IN
l
l
= 1.8V
0.6
10
I
= 0V to 3.6V
–10
μA
pF
IN
C
Input Capacitance
(Note 8)
3
200
3
IN
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
DD
= 1.8V, SDO = 0V
Ω
μA
pF
OL
l
I
OH
SDO = 0V to 3.6V
(Note 8)
–10
10
C
OUT
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV = 1.8V
DD
l
l
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.750
1.790
0.010
V
V
OH
OL
O
I = 500μA
O
0.050
OV = 1.5V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.488
0.010
V
V
O
I = 500μA
O
OV = 1.2V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.185
0.010
V
V
O
I = 500μA
O
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
350
175
454
mV
mV
OD
V
OS
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.250
1.250
1.375
V
V
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
21454314fa
6
LTC2145-14/
LTC2144-14/LTC2143-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2145-14
TYP
LTC2144-14
TYP
LTC2143-14
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
CMOS Output Modes: Full Data Rate and Double Data Rate
l
l
l
V
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
Analog Supply Current DC Input
1.7
1.1
1.8
1.8
1.9
1.9
1.7
1.1
1.8
1.8
1.9
1.9
92
1.7
1.1
1.8
1.8
1.9
1.9
70
V
V
DD
OV
DD
I
105.2 116
105.9
82.8
83.3
62.8
63.2
mA
mA
VDD
Sine Wave Input
I
Digital Supply Current Sine Wave Input, OV = 1.2V
8.5
7.1
5.4
mA
OVDD
DD
l
P
Power Dissipation
DC Input
Sine Wave Input, OV = 1.2V
189
201
209
149
159
166
113
120
126
mW
mW
DISS
DD
LVDS Output Mode
Analog Supply Voltage (Note 10)
l
l
V
DD
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
OV
DD
Output Supply Voltage (Note 10)
I
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
107.3
84.7
86.1
64.6
66.1
mA
mA
VDD
l
l
l
108.7 123
97
76
75
76
I
Digital Supply Current Sine Input, 1.75mA Mode
35.1
66.3
34.8
66
34.5
65.7
mA
mA
OVDD
(0V = 1.8V)
Sine Input, 3.5mA Mode
77
DD
P
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
256
315
215
274
178
237
mW
mW
DISS
360
312
272
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
NAP
16
20
16
20
16
20
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
DIFFCLK
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2145-14
TYP
LTC2144-14
TYP
LTC2143-14
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
TYP MAX UNITS
l
f
t
Sampling Frequency
(Note 10)
1
125
1
105
1
80
MHz
S
L
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
H
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
AP
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
21454314fa
7
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.8
1.5
0.3
6.5
3.2
2.7
0.6
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
ns
SKEW
D
C
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 20pF, R
= 2k
= 2k
250
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
125
SDO
PULLUP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V , they
Note 8: Guaranteed by design, not subject to test.
DD
will be clamped by internal diodes. This product can handle input currents
Note 9: V = 1.8V, f
= 125MHz (LTC2145), 105MHz (LTC2144),
DD
SAMPLE
+
of greater than 100mA below GND or above V without latchup.
DD
or 80MHz (LTC2143), CMOS outputs, ENC = single-ended 1.8V square
–
Note 4: When these pin voltages are taken below GND they will be
wave, ENC = 0V, input range = 2V with differential drive, 5pF load on
P-P
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
each digital output unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
DD
Note 5: V = OV = 1.8V, f
(LTC2144), or 80MHz (LTC2143), LVDS outputs, differential ENC /ENC
= 125MHz (LTC2145), 105MHz
DD
DD
SAMPLE
+
–
= 2V sine wave, input range = 2V with differential drive, unless
P-P
P-P
otherwise noted.
21454314fa
8
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-14: Integral
Nonlinearity (INL)
LTC2145-14: Differential
Nonlinearity (DNL)
LTC2145-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.8
2.0
1.5
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
20
30
40
50
60
10
0
4096
8192
12288
16384
0
8192
12288
16384
4096
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
21454314 G03
21454314 G02
21454314 G01
LTC2145-14: 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
60
0
20
30
40
50
60
0
20
30
40
50
60
10
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
21454314 G04
21454314 G05
21454314 G06
LTC2145-14: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–1dBFS, 125Msps
LTC2145-14: SNR vs Input
LTC2145-14: Shorted Input
Histogram
Frequency, –1dBFS, 125Msps,
2V Range
74
73
72
71
70
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
2000
1000
0
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
0
50
100
150
200
250
300
0
20
30
40
50
60
10
8183
8187
8189
8191
8185
INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
21454314 G09
21454314 G08
21454314 G07
21454314fa
9
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 2V Range
LTC2145-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
LTC2145-14: SFDR vs Input Level,
fIN = 70MHz, 125Msps, 2V Range
120
110
100
90
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
dBFS
3RD
2ND
3RD
2ND
80
dBc
70
60
50
40
30
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
218543 G11
21454314 G10
21454314 G12
LTC2145-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2145-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2145-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
70
60
50
40
30
20
10
0
74
73
72
71
70
69
68
67
66
110
105
100
95
3.5mA LVDS
1.75mA LVDS
LVDS OUTPUTS
CMOS OUTPUTS
90
85
80
1.8V CMOS
75
0
25
50
75
100
125
0
25
50
75
100
125
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
21454314 G15
21454314 G14
21454314 G13
LTC2144-14: Integral
Nonlinearity (INL)
LTC2144-14: Differential
Nonlinearity (DNL)
LTC2144-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
2.0
1.5
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.8
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
4096
0
10
20
30
40
50
0
8192
12288
16384
4096
OUTPUT CODE
FREQUENCY (MHz)
OUTPUT CODE
21454314 G16
21454314 G1
21454314 G17
21454314fa
10
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2144-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
LTC2144-14: 64k Point FFT,
LTC2144-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
f
IN = 30MHz, –1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
20
30
40
50
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
21454314 G19
21454314 G20
21454314 G21
LTC2144-14: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–1dBFS, 105Msps
LTC2144-14: SNR vs Input
Frequency, –1dBFS, 105Msps,
2V Range
LTC2144-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
74
73
72
71
70
6000
5000
4000
3000
2000
1000
0
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
0
10
20
30
40
50
0
50
100
150
200
250
300
8190
8194
8196
8198
8192
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
OUTPUT CODE
21454314 G22
21454314 G24
21454314 G23
LTC2144-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 2V Range
LTC2144-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
LTC2144-14: SFDR vs Input Level,
fIN = 70MHz, 105Msps, 2V Range
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
120
110
100
90
dBFS
3RD
2ND
3RD
2ND
80
dBc
70
60
50
40
30
0
50
100
150
200
250
300
0
50
100
150
200
250
300
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
218543 G26
21454314 G25
21454314 G27
21454314fa
11
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2144-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2144-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2144-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
74
73
72
71
70
69
68
67
66
70
60
50
40
30
20
10
0
90
85
80
75
70
65
60
55
3.5mA LVDS
1.75mA LVDS
LVDS OUTPUTS
CMOS OUTPUTS
1.8V CMOS
0
25
50
75
100
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
25
50
75
100
SAMPLE RATE (Msps)
SENSE PIN (V)
SAMPLE RATE (Msps)
21454314 G30
21454314 G29
21454314 G28
LTC2143-14: Integral
Nonlinearity (INL)
LTC2143-14: Differential
Nonlinearity (DNL)
LTC2143-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
0
2.0
1.5
1.0
0.8
–10
–20
–30
–40
–50
–60
–70
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
4096
8192
12288
16384
0
10
20
30
40
0
8192
12288
16384
4096
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
21454314 G32
21454314 G31
21454314 G33
LTC2143-14: 64k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
LTC2143-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
LTC2143-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
20
30
40
0
10
20
30
40
0
10
20
30
40
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
21454314 G34
21454314 G35
21454314 G36
21454314fa
12
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2143-14: 64k Point 2-Tone FFT,
LTC2143-14: SNR vs Input
fIN = 69MHz, 70MHz, –1dBFS,
80Msps
LTC2143-14: Shorted Input
Histogram
Frequency, –1dBFS, 80Msps,
2V Range
0
–10
–20
–30
–40
–50
–60
–70
74
6000
5000
4000
3000
2000
1000
0
SINGLE-ENDED
73
ENCODE
72
DIFFERENTIAL
ENCODE
–80
–90
71
70
–100
–110
–120
0
10
20
30
40
0
50
100
150
200
250
300
8183
8187
8189
8191
8185
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
OUTPUT CODE
21454314 G39
21454314 G37
21454314 G38
LTC2143-14: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
2V Range
LTC2143-14: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
1V Range
LTC2143-14: SFDR vs Input Level,
fIN = 70MHz, 80Msps, 2V Range
100
95
90
85
80
75
70
65
120
110
100
90
100
95
90
85
80
75
70
65
dBFS
3RD
2ND
3RD
2ND
80
dBc
70
60
50
40
30
0
50
100
150
200
250
300
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
21454314 G40
218543 G41
21454314 G42
LTC2143-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2143-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2143-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
70
60
50
40
30
20
10
0
74
73
72
71
70
69
68
67
66
70
65
60
55
50
45
40
3.5mA LVDS
1.75mA LVDS
LVDS OUTPUTS
CMOS OUTPUTS
1.8V CMOS
0
20
40
60
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
20
40
60
80
SAMPLE RATE (Msps)
SENSE PIN (V)
SAMPLE RATE (Msps)
21454314 G44
21454314 G45
21454314 G43
21454314fa
13
LTC2145-14/
LTC2144-14/LTC2143-14
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL
CS (Pin 20): In Serial Programming Mode, (PAR/SER =
0V), CS Is the Serial Interface Chip Select Input. When
CS is low, SCK is enabled for shifting data on SDI into the
modecontrolregisters. Intheparallelprogrammingmode
OUTPUT MODES
V
(Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
DD
1.9V. Bypass to ground with 0.1μF ceramic capacitors.
(PAR/SER=V ),CScontrolstheclockdutycyclestabilizer
DD
Adjacent pins can share a bypass capacitor.
(See Table 2). CS can be driven with 1.8V to 3.3V logic.
V
(Pin2):CommonModeBiasOutput,NominallyEqual
CM1
to V /2. V
SCK (Pin 21): In Serial Programming Mode, (PAR/SER =
should be used to bias the common mode
DD
CM1
0V), SCK Is the Serial Interface Clock Input. In the parallel
of the analog inputs to channel 1. Bypass to ground with
a 0.1μF ceramic capacitor.
programming mode (PAR/SER = V ), SCK controls the
DD
digital output mode (see Table 2). SCK can be driven with
GND (Pins 3, 6, 14): ADC Power Ground.
1.8V to 3.3V logic.
+
A
IN1
A
IN1
(Pin4):Channel1PositiveDifferentialAnalogInput.
(Pin5):Channel1NegativeDifferentialAnalogInput.
SDI (Pin 22): In Serial Programming Mode, (PAR/SER =
0V), SDI Is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming mode (PAR/
–
REFH (Pins 7, 9): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
SER = V ), SDI can be used together with SDO to power
DD
down the part (see Table 2). SDI can be driven with 1.8V
to 3.3V logic.
REFL (Pins 8, 10): ADC Low Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
PAR/SER (Pin 11): Programming Mode Selection Pin.
Connecttogroundtoenabletheserialprogrammingmode.
CS, SCK, SDI, SDO become a serial interface that control
OV (Pin 42): Output Driver Supply. Bypass to ground
DD
with a 0.1μF ceramic capacitor.
the A/D operating modes. Connect to V to enable the
DD
SDO (Pin 61): In Serial Programming Mode, (PAR/SER
= 0V), SDO Is the Optional Serial Interface Data Output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directlytogroundorV andnotbedrivenbyalogicsignal.
DD
+
A
A
V
(Pin12):Channel2PositiveDifferentialAnalogInput.
(Pin13):Channel2NegativeDifferentialAnalogInput.
(Pin 15): Common Mode Bias Output, Nominally
IN2
–
IN2
CM2
parallel programming mode (PAR/SER = V ), SDO can
DD
Equal to V /2. V
should be used to bias the common
DD
CM2
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1μF ceramic capacitor.
+
ENC (Pin 18): Encode Input. Conversion starts on the
V
(Pin 62): Reference Voltage Output. Bypass to
REF
rising edge.
ground with a 2.2μF ceramic capacitor. The output voltage
–
ENC (Pin 19): Encode Complement Input. Conversion
is nominally 1.25V.
starts on the falling edge. Tie to GND for single-ended
encode mode.
21454314fa
14
LTC2145-14/
LTC2144-14/LTC2143-14
PIN FUNCTIONS
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT is high.
SENSE(Pin63):ReferenceProgrammingPin.Connecting
+
SENSEtoV selectstheinternalreferenceanda 1Vinput
DD
range. Connecting SENSE to ground selects the internal
reference and a 0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
DNC (Pins 23, 24, 25, 27, 29, 31, 33, 35, 37, 43, 44, 45,
47, 49, 51, 53, 55, 57, 59): Do not connect these pins.
–
+
CLKOUT (Pin 39): Inverted Version of CLKOUT .
input range of 0.8 • V
.
SENSE
+
CLKOUT (Pin40):DataOutputClock. TheDigitalOutputs
Ground (Exposed Pad Pin 65): The exposed pad must be
soldered to the PCB ground.
normally transition at the same time as the falling and ris-
+
+
ing edges of CLKOUT . The phase of CLKOUT can also
be delayed relative to the Digital Outputs by programming
the mode control registers.
FULL RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
D1_0_1 to D1_12_13 (Pins 46, 48, 50, 52, 54, 56, 58):
Channel 1 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
(OGND to OV )
DD
D2_0 to D2_13 (Pins 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_13 is
the MSB.
+
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
+
appear when CLKOUT is high.
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is
high when an overflow or underflow has occurred. The
over/under flow for both channels are multiplexed onto
–
+
CLKOUT (Pin 39): Inverted Version of CLKOUT .
+
CLKOUT (Pin 40): Data Output Clock. The digital outputs
+
normally transition at the same time as the falling edge
this pin. Channel 2 appears when CLKOUT is low, and
+
+
+
of CLKOUT . The phase of CLKOUT can also be delayed
relative to the Digital Outputs by programming the mode
control registers.
Channel 1 appears when CLKOUT is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
D1_0 to D1_13 (Pins 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_13 is
the MSB.
All Pins Below Have LVDS Output Levels. The Output
Current Level Is Programmable. There Is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
OF2 (Pin 59): Channel 2 Over/Underflow Digital Output.
OF2 is high when an overflow or underflow has occurred.
–
+
–
+
D2_0_1 /D2_0_1 toD2_12_13 /D2_12_13 (Pins25/26,
27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel
2 Double Data Rate Digital Outputs. Two data bits are
multiplexed onto each differential output pair. The even
data bits (D0, D2, D4, D6, D8, D10, D12) appear when
OF1 (Pin 60): Channel 1 Over/Underflow Digital Output.
OF1 is high when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
+
CLKOUT is low. The odd data bits (D1, D3, D5, D7, D9,
+
D11, D13) appear when CLKOUT is high.
(OGND to OV )
–
+
DD
CLKOUT /CLKOUT (Pins 39/40): Data Output Clock.
D2_0_1 to D2_12_13 (Pins 26, 28, 30, 32, 34, 36, 38):
Channel 2 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
The digital outputs normally transition at the same time
+
as the falling and rising edges of CLKOUT . The phase of
+
CLKOUT canalsobedelayedrelativetothedigitaloutputs
+
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT
by programming the mode control registers.
21454314fa
15
LTC2145-14/
LTC2144-14/LTC2143-14
PIN FUNCTIONS
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
–
+
+
OF2_1 /OF2_1 (Pins 59/60): Over/Underflow Digital
Output. OF2_1 is high when an overflow or underflow
has occurred. The over/under flow for both channels
are multiplexed onto this pin. Channel 2 appears when
CLKOUT is low, and Channel 1 appears when CLKOUT
is high.
–
+
–
+
D1_0_1 /D1_0_1 to D1_12_13 /D1_12_13 (Pins
45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58):
Channel 1 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each differential output pair.
The even data bits (D0, D2, D4, D6, D8, D10, D12) ap-
+
+
+
pear when CLKOUT is low. The odd data bits (D1, D3,
+
D5, D7, D9, D11, D13) appear when CLKOUT is high.
FUNCTIONAL BLOCK DIAGRAM
OV
DD
CH 1
ANALOG
INPUT
OF1
14-BIT
ADC CORE
S/H
OF2
CORRECTION
LOGIC
D1_13
t
t
t
CH 2
ANALOG
INPUT
D1_0
14-BIT
ADC CORE
S/H
OUTPUT
DRIVERS
+
CLKOUT
CLKOUT
D2_13
–
V
REF
1.25V
REFERENCE
t
t
t
2.2μF
D2_0
RANGE
SELECT
OGND
REFH
REFL INTERNAL CLOCK SIGNALS
REF
BUF
V
DD
SENSE
DIFF
REF
AMP
CLOCK/DUTY
CYCLE
CONTROL
MODE
CONTROL
REGISTERS
V
CM1
V
DD
/2
0.1μF
V
CM2
0.1μF
+
–
GND
REFH
REFL
ENC
ENC
PAR/SER CS SCK SDI SDO
21454314 F01
2.2μF
0.1μF
0.1μF
Figure 1. Functional Block Diagram
21454314fa
16
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING DIAGRAMS
Full Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
CH 1
ANALOG
INPUT
A + 4
B + 4
A + 2
B + 2
A
B
A + 3
B + 3
t
A + 1
B + 1
AP
CH 2
ANALOG
INPUT
t
H
t
L
–
ENC
+
ENC
t
t
D
A – 6
A – 5
B – 5
A – 4
B – 4
A – 3
B – 3
A – 2
B – 2
D1_0 - D1_13, OF1
D2_0 - D2_13, OF2
B – 6
C
+
CLKOUT
–
CLKOUT
21454314 TD01
21454314fa
17
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
AP
CH 1
ANALOG
INPUT
A + 4
B + 4
A + 2
B + 2
A
B
A + 3
B + 3
t
A + 1
B + 1
CH 2
ANALOG
INPUT
t
H
t
L
–
ENC
+
ENC
t
t
D
D
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
D1_0_1
t
t
t
BIT 12
A-6
BIT 13 BIT 12
BIT 13
A-5
BIT 12
A-4
BIT 13
A-4
BIT 12
A-3
BIT 13
A-3
BIT 12
A-2
D1_12_13
A-6
A-5
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
D2_0_1
t
t
t
BIT 12
B-6
BIT 13 BIT 12
BIT 13
B-5
BIT 12
B-4
BIT 13
B-4
BIT 12
B-3
BIT 13
B-3
BIT 12
B-2
D2_12_13
B-6
B-5
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
OF2_1
t
t
C
C
+
CLKOUT
–
CLKOUT
21454314 TD02
21454314fa
18
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
AP
CH 1
ANALOG
INPUT
A + 4
B + 4
A + 2
B + 2
A
B
A + 3
B + 3
t
AP
A + 1
B + 1
CH 2
ANALOG
INPUT
t
H
t
L
–
ENC
+
ENC
t
D
t
D
+
D1_0_1
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
BIT 0
A-3
BIT 1
BIT 0
A-2
A-4
A-3
–
D1_0_1
t
t
t
+
D1_12_13
BIT 12
A-6
BIT 13 BIT 12
A-6
BIT 13
A-5
BIT 12
A-4
BIT 13
A-4
BIT 12
A-3
BIT 13
A-3
BIT 12
A-2
A-5
–
D1_12_13
+
D2_0_1
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
–
D2_0_1
t
t
t
+
D2_12_13
BIT 12
B-6
BIT 13 BIT 12
B-6
BIT 13
B-5
BIT 12
B-4
BIT 13
B-4
BIT 12
B-3
BIT 13
B-3
BIT 12
B-2
B-5
–
D2_12_13
+
OF2_1
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
–
OF2_1
t
C
t
C
+
CLKOUT
–
CLKOUT
21454314 TD03
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
21454314 TD04
HIGH IMPEDANCE
21454314fa
19
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
to V + 0.5V. There should be 180° phase difference
CM
between the inputs.
The LTC2145-14/LTC2144-14/LTC2143-14 are low power,
two-channel, 14-bit, 125Msps/105Msps/80Msps A/D
converters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen
by programming the mode control registers through a
serial SPI port.
Thetwochannelsaresimultaneouslysampledbyashared
encode circuit (Figure 2).
Single-Ended Input
For applications less sensitive to harmonic distortion, the
+
A
input can be driven single-ended with a 1V signal
IN
P-P
–
centered around V . The A input should be connected
CM
IN
to V and the V bypass capacitor should be increased
CM
CM
to2.2μF.Withasingle-endedinput,theharmonicdistortion
and INL will degrade, but the noise and DNL will remain
unchanged.
ANALOG INPUT
INPUT DRIVE CIRCUITS
Input Filtering
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the V
or
CM1
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
V
output pins, which are nominally V /2. For the 2V
CM2
DD
input range, the inputs should swing from V – 0.5V
CM
LTC2145-14
V
DD
C
C
SAMPLE
5pF
R
ON
10Ω
10ꢀ
15Ω
+
–
A
A
IN
C
PARASITIC
1.8pF
V
DD
Transformer Coupled Circuits
SAMPLE
5pF
R
ON
15Ω
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
IN
C
1.8pF
PARASITIC
tap is biased with V , setting the A/D input at its optimal
CM
V
DD
DC level. At higher input frequencies a transmission line
baluntransformer(Figure4toFigure6)hasbetterbalance,
resulting in lower A/D distortion.
1.2V
10k
50Ω
V
CM
+
–
ENC
0.1μF
0.1μF
T1
1:1
ENC
+
25Ω
A
IN
ANALOG
INPUT
10k
LTC2145-14
0.1μF
25Ω
25Ω
1.2V
12pF
21454314 F02
–
25Ω
A
IN
Figure 2. Equivalent Input Circuit. Only One of the Two
Analog Channels Is Shown
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
21454314 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
21454314fa
20
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Amplifier Circuits
Reference
TheLTC2145-14/LTC2144-14/LTC2143-14hasaninternal
1.25V voltage reference. For a 2V input range using the
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
internal reference, connect SENSE to V . For a 1V input
DD
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figure 4
to Figure 6) should convert the signal to differential before
driving the A/D.
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • V
.
SENSE
The V , REFH and REFL pins should be bypassed as
REF
50Ω
V
CM
shown in Figure 8. A low inductance 2.2μF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
0.1μF
0.1μF
0.1μF
+
12Ω
A
ANALOG
INPUT
IN
T2
LTC2145-14
T1
0.1μF
25Ω
25Ω
8.2pF
–
12Ω
50Ω
V
A
IN
CM
0.1μF
21454314 F04
0.1μF
4.7nH
0.1μF
+
A
IN
IN
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
ANALOG
INPUT
LTC2145-14
T1
25Ω
25Ω
0.1μF
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 5MHz to 150MHz
–
4.7nH
A
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
21454314 F06
50Ω
V
CM
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 250MHz
0.1μF
0.1μF
0.1μF
+
A
ANALOG
INPUT
IN
T2
LTC2145-14
T1
0.1μF
25Ω
25Ω
1.8pF
V
CM
–
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
A
IN
0.1μF
200Ω 200Ω
25Ω
0.1μF
0.1μF
+
–
A
IN
21454314 F05
LTC2145-14
ANALOG
INPUT
12pF
+
+
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
–
–
25Ω
A
IN
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 150MHz to 250MHz
12pF
21454314 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
21454314fa
21
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
LTC2145-14
5Ω
V
REF
1.25V BANDGAP
REFERENCE
1.25V
2.2μF
0.625V
RANGE
DETECT
AND
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
3"/(&ꢀꢁꢀꢂꢃꢄꢀtꢀ7
FOR
SENSE
BUFFER
0.625V < V
< 1.300V
SENSE
INTERNAL ADC
HIGH REFERENCE
REFH
REFL
C2
–
+
–
0.1μF
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
+
0.8x
DIFF AMP
C1
REFH
REFL
–
+
+
–
C3
0.1μF
INTERNAL ADC
LOW REFERENCE
C1: 2.2μF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
21454314 F08a
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
OR EQUIVALENT
Figure 8a. Reference Circuit
V
REF
Alternatively, C1 can be replaced by a standard 2.2μF
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
2.2μF
LTC2145-14
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
21454314 F09
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1)isconnectedsincethepinsarenotinternallyconnected
Figure 9. Using an External 1.25V Reference
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
LTC2145-14
REFH
REFL
C3
0.1μF
C1
2.2μF
REFH
C2
0.1μF
REFL
21454314 F08b
CAPACITORS ARE 0402 PACKAGE SIZE
The differential encode mode is recommended for si-
nusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
Figure 8b. Alternative REFH/REFL Bypass Circuit
21454314fa
22
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
LTC2145-14
through 10kꢀ equivalent resistance. The encode inputs
V
DD
can be taken above V (up to 3.6V), and the common
DD
DIFFERENTIAL
COMPARATOR
mode range is from 1.1V to 1.6V. In the differential encode
V
DD
–
mode, ENC should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
15k
30k
+
–
+
–
For good jitter performance ENC and ENC should have
fast rise and fall times.
ENC
ENC
Thesingle-endedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected to
+
groundandENC isdrivenwithasquarewaveencodeinput.
21454314 F10
+
ENC can be taken above V (up to 3.6V) so 1.8V to 3.3V
DD
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
+
CMOSlogiclevelscanbeused.TheENC thresholdis0.9V.
For good jitter performance ENC should have fast rise
+
and fall times. If the encode signal is turned off or drops
below approximately 500kHz, the A/D enters nap mode.
LTC2145-14
+
1.8V TO 3.3V
0V
ENC
Clock Duty Cycle Stabilizer
–
30k
ENC
CMOS LOGIC
BUFFER
For good performance the encode signal should have a
50% ( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
21454314 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
0.1μF
0.1μF
+
ENC
50ꢀ
50ꢀ
T1
100ꢀ
LTC2145-14
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% ( 5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
–
ENC
0.1μF
21454314 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
DIGITAL OUTPUTS
Digital Output Modes
0.1μF
+
ENC
The LTC2145-14/LTC2144-14/LTC2143-14 can operate in
three digital output modes: full rate CMOS, double data
rateCMOS(tohalvethenumberofoutputlines), ordouble
data rate LVDS (to reduce digital noise in the system.) The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
PECL OR
LTC2145-14
LVDS
CLOCK
0.1μF
–
ENC
21454314 F13
Figure 13. PECL or LVDS Encode Drive
21454314fa
23
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
mode).NotethatdoubledatarateCMOScannotbeselected
in the parallel programming mode.
–
–
+
+
–
–
+
D1_0_1 through D1_12_13 /D1_12_13 and D2_0_1 /
D2_0_1 through D2_12_13 /D2_12_13 ) for the digital
+
–
output data. Overflow (OF2_1 /OF2_1 ) and the data
+
–
Full Rate CMOS Mode
output clock (CLKOUT /CLKOUT ) each have an LVDS
output pair. Note that the overflow for both ADC channels
In full rate CMOS mode the data outputs (D1_0 to D1_13
and D2_0 to D2_13), overflow (OF2, OF1), and the data
+
–
is multiplexed onto the OF2_1 /OF2_1 output pair.
+
–
output clocks (CLKOUT , CLKOUT ) have CMOS output
levels. TheoutputsarepoweredbyOV andOGNDwhich
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100ꢀ differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
DD
are isolated from the A/D core power and ground. OV
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
DD
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground. In LVDS
mode, OV must be 1.8V.
DD
Double Data Rate CMOS Mode
Programmable LVDS Output Current
In double data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces
the number of digital lines by fifteen, simplifying board
routing and reducing the number of input pins needed
to receive the data. The data outputs (D1_0_1, D1_2_3,
D1_4_5,D1_6_7,D1_8_9,D1_10_11,D1_12_13,D2_0_1,
D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
D2_12_13), overflow (OF2_1), and the data output clocks
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100ꢀ termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100ꢀ termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
+
–
(CLKOUT , CLKOUT ) have CMOS output levels. The out-
puts are powered by OV and OGND which are isolated
DD
from the A/D core power and ground. OV can range
DD
from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic
outputs. Note that the overflow for both ADC channels is
multiplexed onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Overflow Bit
Theoverflowoutputbitoutputsalogichighwhentheanalog
input is either overranged or underranged. The overflow
bit has the same pipeline latency as the data bits. In full
rate CMOS mode each ADC channel has its own overflow
pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS
or DDR LVDS mode the overflow for both ADC channels
is multiplexed onto the OF2_1 output.
When using double data rate CMOS at sample rates above
100Msps the SNR may degrade slightly, about 0.1dB to
0.3dB depending on load capacitance and board layout.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
+
are seven LVDS output pairs per ADC channel (D1_0_1 /
21454314fa
24
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
DATA FORMAT
In full rate CMOS mode the data output bits normally
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
+
change at the same time as the falling edge of CLKOUT ,
+
so the rising edge of CLKOUT can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
thefallingandrisingedgesofCLKOUT .Toallowadequate
Table 1. Output Codes vs Input Voltage
+
set-up and hold time when latching the data, the CLKOUT
+
–
A
– A
D13-D0
D13-D0
IN
IN
signal may need to be phase shifted relative to the data
outputbits. MostFPGAshavethisfeature;thisisgenerally
the best place to adjust the timing.
(2V Range)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
OF (OFFSET BINARY)
(2’s COMPLEMENT)
1
0
0
0
0
0
0
0
0
1
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
TheLTC2145-14/LTC2144-14/LTC2143-14canalsophase
+
–
shift the CLKOUT /CLKOUT signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90°, or 135°. To use the phase shift-
ing feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
+
–
CLKOUT and CLKOUT , independently of the phase shift.
Thecombinationofthesetwofeaturesenablesphaseshifts
of 45° up to 315° (Figure 14).
+
ENC
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1 CLKPHASE0
0°
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
135°
180°
225°
270°
+
CLKOUT
315°
21454314 F14
Figure 14. Phase Shifting CLKOUT
21454314fa
25
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Digital Output Randomizer
CLKOUT
CLKOUT
OF
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
OF
D13
D13/D0
D12/D0
D12
D2
t
t
t
D2/D0
D1/D0
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
RANDOMIZER
ON
D1
D0
D0
21454314 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
Alternate Bit Polarity
Anotherfeaturethatreducesdigitalfeedbackonthecircuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
PC BOARD
FPGA
CLKOUT
OF
D13/D0
D13
D12
When there is a very small signal at the input of the A/D
thatiscenteredaroundmid-scale,thedigitaloutputstoggle
between mostly 1’s and mostly 0’s. This simultaneous
switchingofmostofthebitswillcauselargecurrentsinthe
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
D12/D0
LTC2145-14
t
t
t
D2/D0
D1/D0
D2
D1
D0
D0
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13). The alternate
bit polarity mode is independent of the digital output ran-
domizer – either, both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
21454314 F16
Figure 16. Unrandomizing a Randomized Digital
Output Signal
21454314fa
26
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Digital Output Test Patterns
allowedsotheon-chipreferencescansettlefromtheslight
temperature shift caused by the change in supply current
astheA/Dleavesnapmode. Eitherchannel2orbothchan-
nels can be placed in nap mode; it is not possible to have
channel 1 in nap mode and channel 2 operating normally.
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
Alternating: Outputs change from all 1s to all 0s on
alternating samples.
DEVICE PROGRAMMING MODES
Checkerboard: Outputs change from
101010101010101 to 010101010101010 on alternat-
ing samples.
The operating modes of the LTC2145-14/LTC2144-14/
LTC2143-14 can be programmed by either a parallel in-
terface or a simple serial interface. The serial interface has
more flexibility and can program all available modes. The
parallel interface is more limited and can only program
some of the more commonly used modes.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the Test Patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Parallel Programming Mode
Output Disable
To use the parallel programming mode, PAR/SER should
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehigh-impedancedisabled
state is intended for in-circuit testing or long periods of
inactivity – it is too slow to multiplex a data bus between
multiple converters at full speed. When the outputs are
disabled both channels should be put into either sleep or
nap mode.
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
can be tied to V or ground, or driven by 1.8V, 2.5V, or
DD
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
Sleep and Nap Modes
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
Digital Output Mode Control Bit
0 = Full Rate CMOS Output Mode
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resultingin1mWpowerconsumption.Theamountoftime
required to recover from sleep mode depends on the size
of the bypass capacitors on V , REFH, and REFL. For the
suggested values in Fig. 8, the A/D will stabilize after 2ms.
SCK
1 = Double Data Rate LVDS Output Mode
REF
(3.5mA LVDS Current, Internal Termination Off)
SDI/SDO Power Down Control Bit
InnapmodetheA/Dcoreispowereddownwhiletheinternal
reference circuits stay active, allowing faster wakeup than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50μs should be
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
21454314fa
27
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Serial Programming Mode
GROUNDING AND BYPASSING
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serialinterfacethatprogramtheA/Dmodecontrolregisters.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
The LTC2145-14/LTC2144-14/LTC2143-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
High quality ceramic bypass capacitors should be used at
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
capacitors must be located as close to the pins as pos-
sible.Size0402ceramiccapacitorsarerecommended.The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
The SDO pin is an open drain output that pulls to ground
with a 200ꢀ impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serialdataisonlywrittenandreadbackisnotneeded, then
SDO can be left floating and no pull-up resistor is needed.
HEAT TRANSFER
Table 3 shows a map of the mode control registers.
Most of the heat generated by the LTC2145-14/LTC2144-
14/LTC2143-14 is transferred from the die through the
bottom-side exposed pad and package leads onto the
printed circuit board. For good electrical and thermal
performance, the exposed pad must be soldered to a large
grounded pad on the PC board. This pad should be con-
nected to the internal ground planes by an array of vias.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
21454314fa
28
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is
automatically set back to zero at the end of the SPI write command. The reset register is write only. Data read back from the reset
register will be random.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
D0
PWROFF1
PWROFF0
Bits 7-2
Bits 1-0
Unused, Don’t Care Bits.
PWROFF1:PWROFF0
Power Down Control Bits
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
+
–
01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period • 1/8)
+
–
10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period • 1/4)
+
–
11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
DCS Clock Duty Cycle Stabilizer Bit
Bit 0
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
21454314fa
29
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
Bit 2
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
OUTOFF
0 = Digital Outputs Are Enabled
Output Disable Bit
1 = Digital Outputs Are Disabled and Have High Output Impedance
Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels).
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 1 01 0101 0101 0101 and 0 10 1010 1010 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 0 00 0000 0000 0000 and 1 11 1111 1111 1111
Note: Other Bit Combinations Are not Used
Bit 2
Bit 1
Bit 0
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
21454314fa
30
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
21454314fa
31
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
21454314fa
32
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
21454314fa
33
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
Bottom Side
21454314fa
34
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
LTC2145-14 Schematic
SDO
C23
2.2μF
SENSE
C17
1μF
V
DD
C19
0.1μF
C20
0.1μF
DIGITAL
OUTPUTS
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
+
–
+
–
V
V
D1_2_3
D1_2_3
D1_0_1
D1_0_1
DD
CM1
3
GND
4
+
+
A
A
A
A
IN1
IN1
IN1
IN1
5
–
–
DNC
DNC
6
GND
C15
7
0.1μF
REFH
REFL
REFH
REFL
OV
DD
OV
DD
–
+
+
–
C37
0.1μF
8
OGND
LTC2145-14
9
+
CLKOUT
CN1
10
11
12
13
14
15
16
–
CLKOUT
–
+
+
–
+
PAR/SER
D2_12_13
C21
0.1μF
+
–
A
D2_12_13
IN2
–
+
A
D2_10_11
IN2
–
GND
D2_10_11
DIGITAL
OUTPUTS
+
V
V
D2_8_9
CM2
DD
–
D2_8_9
PAR/SER
65
PAD
+
A
A
IN2
IN2
–
V
DD
C67
0.1μF
C18
0.1μF
C78
0.1μF
C79
0.1μF
R51
100Ω
ENCODE
CLOCK
SPI BUS
21454314 TA02
21454314fa
35
LTC2145-14/
LTC2144-14/LTC2143-14
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm w 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 0.05
7.ꢀ5 0.05
7.50 REF
8.ꢀ0 0.05 9.50 0.05
(4 SIDES)
7.ꢀ5 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀ0
TYP
R = 0.ꢀꢀ5
TYP
9 .00 0.ꢀ0
(4 SIDES)
63 64
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 5)
ꢀ
2
PIN ꢀ
CHAMFER
C = 0.35
7.ꢀ5 0.ꢀ0
7.50 REF
(4-SIDES)
7.ꢀ5 0.ꢀ0
(UP64) QFN 0406 REV C
0.200 REF
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
21454314fa
36
LTC2145-14/
LTC2144-14/LTC2143-14
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
07/12 Corrected Channel 1 Data Bus (D1_*) Pin Description to state “Channel 1”
16
21454314fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
64k Point 2-Tone FFT, fIN = 69MHz,
70MHz, –1dBFS, 125Msps
1.8V
1.8V
OV
V
DD
DD
0
–10
–20
–30
–40
–50
–60
–70
CH 1
ANALOG
INPUT
14-BIT
D1_13
S/H
S/H
t
t
t
ADC CORE
CMOS,
D1_0
DDR CMOS
OR DDR LVDS
OUTPUTS
D2_13
t
t
t
OUTPUT
DRIVERS
CH 2
ANALOG
INPUT
14-BIT
ADC CORE
D2_0
–80
–90
–100
–110
–120
125MHz
CLOCK
CLOCK
CONTROL
0
20
30
40
50
60
10
FREQUENCY (MHz)
21454314 TA03a
21454314 TA03b
GND
OGND
RELATED PARTS
PART NUMBER
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COMMENTS
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6mm × 6mm QFN-40
LTC2268-12
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LTC2183/LTC2184/
LTC2185
16-Bit, 80Msps/105Msps/125Msps
1.8V Dual ADCs, Ultralow Power
370mW/308mW/200mW, 76.8dB SNR, 90dV SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, Pin Compatible with LTC2145 Family, 9mm × 9mm QFN-64
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5557
LTC5575
400MHz to 3.8GHz High Linearity
Downconverting Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,
Variable Gain Amplifier
4mm × 4mm QFN-24
LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
LTC6605-14
Filters with ADC Drivers
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband
Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
21454314fa
LT 0712 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
38
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© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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