LTC2203CUK#PBF [Linear]
LTC2203 - 16-Bit, 25Msps ADCs; Package: QFN; Pins: 48; Temperature Range: 0°C to 70°C;
| 型号： | LTC2203CUK#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2203 - 16-Bit, 25Msps ADCs; Package: QFN; Pins: 48; Temperature Range: 0°C to 70°C 转换器 模数转换器 |
| 文件： | 总24页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2201
16-Bit, 20Msps ADC
FEATURES
DESCRIPTION
Sample Rate: 20Msps
TheLTC®2201isa20Msps,sampling16-bitA/Dconverter
designedfordigitizinghighfrequency,widedynamicrange
signals with input frequencies up to 380MHz. The input
range of the ADC can be optimized with the PGA front end.
n
n
81.6dB SNR and 100dB SFDR (2.5V Range)
n
90dB SFDR at 70MHz (1.667V Input Range)
PGA Front End (2.5V or 1.667V Input Range)
380MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
P-P
n
n
n
n
n
n
n
n
n
P-P
P-P
The LTC2201 is perfect for demanding applications, with
AC performance that includes 81.6dB SNR and 100dB
spurious free dynamic range (SFDR). Maximum DC specs
include ±±LSB ꢀNL, ±1LSB DNL (no missing codes).
Power Dissipation: 211mW
Clock Duty Cycle Stabilizer
Out-of-Range ꢀndicator
A separate output power supply allows the CMOS output
swing to range from 0.±V to 3.6V.
Pin Compatible Family
Asingle-endedCLKinputcontrolsconverteroperation.An
optionalclockdutycyclestabilizerallowshighperformance
at full speed with a wide range of clock duty cycles.
2±Msps: LTC2203 (16-Bit)
10Msps: LTC2202 (16-Bit)
48-Pin (7mm × 7mm) QFN Package
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIONS
n
Telecommunications
n
Receivers
n
Cellular Base Stations
n
Spectrum Analysis
n
ꢀmaging Systems
n
ATE
TYPICAL APPLICATION
Integral Nonlinearity (INL)
vs Output Code
3.3V
SENSE
2.0
OV
DD
1.2±V
COMMON MODE
BꢀAS VOLTAGE
ꢀNTERNAL ADC
REFERENCE
GENERATOR
V
0.±V TO 3.6V
1.±
CM
1μF
2.2μF
1.0
OF
CLKOUT+
CLKOUT–
+
A
0.±
ꢀN
+
16-BꢀT
PꢀPELꢀNED
ADC CORE
OUTPUT
DRꢀVERS
CORRECTꢀON
LOGꢀC AND
SHꢀFT REGꢀSTER
ANALOG
ꢀNPUT
S/H
CMOS
OUTPUTS
0.0
–0.±
–1.0
–1.±
–2.0
D1±
AMP
t
t
–
–
A
ꢀN
t
D0
OGND
CLOCK/DUTY
CYCLE
3.3V
1μF
V
DD
CONTROL
1μF
1μF
GND
32768
CODE
0
16384
491±2
6±±36
CLK
2201 TA02
PGA SHDN DꢀTH MODE
ADC CONTROL ꢀNPUTS
RAND
OE
2201 TA01
2201f
1
LTC2201
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
OVDD = VDD (Notes 1 and 2)
TOP VꢀEW
Supply Voltage (V ).................................. –0.3V to 4V
DD
Digital Output Supply Voltage (OV )......... –0.3V to 4V
DD
Digital Output Ground Voltage (OGND)........–0.3V to 1V
SENSE 1
36 OV
DD
Analog ꢀnput Voltage (Note 3) .....–0.3V to (V + 0.3V)
DD
V
V
V
2
3
4
3± D11
34 D10
33 D9
CM
Digital ꢀnput Voltage ....................–0.3V to (V + 0.3V)
DD
DD
DD
Digital Output Voltage............... –0.3V to (OV + 0.3V)
DD
GND ±
32 D8
+
Power Dissipation............................................2000mW
A
A
6
7
31 OGND
30 CLKOUT
29 CLKOUT
28 D7
27 D6
26 D±
ꢀN
49
–
+
–
ꢀN
Operating Temperature Range
GND 8
GND 9
CLK 10
GND 11
LTC2201C ............................................... 0°C to 70°C
LTC2201ꢀ ............................................–40°C to 8±°C
Storage Temperature Range ................. –6±°C to 1±0°C
V
DD
12
2± OV
DD
UK PACKAGE
48-LEAD (7mm s 7mm) PLASTꢀC QFN
EXPOSED PAD ꢀS GND (PꢀN 49)
MUST BE SOLDERED TO PCB BOARD
T
= 1±0°C, θ = 29°C/W
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC2201CUK#PBF
LTC2201ꢀUK#PBF
TAPE AND REEL
PART MARKING*
LTC2201UK
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2201CUK#TRPBF
LTC2201ꢀUK#TRPBF
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
LTC2201UK
–40°C to 8±°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2201f
2
LTC2201
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No missing codes)
ꢀntegral Linearity Error
Differential Linearity Error
Offset Error
16
l
l
l
Differential Analog ꢀnput (Note ±)
Differential Analog ꢀnput
(Note 6)
±1.±
±0.3
±2
±±
±1
LSB
LSB
±10
mV
Offset Drift
±10
±0.2
μV/°C
%FS
l
Gain Error
External Reference
±1.±
Full-Scale Drift
ꢀnternal Reference
External Reference
±30
±1±
ppm/°C
ppm/°C
Transition Noise
External Reference (2.±V Range, PGA = 0)
1.92
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.667 or 2.±
1.2±
MAX
UNITS
+
–
V
3.13±V ≤ V ≤ 3.46±V
V
P-P
Analog ꢀnput Range (A
–
A
ꢀN
)
ꢀN
DD
ꢀN
l
l
l
V
ꢀ
Analog ꢀnput Common Mode
Differential ꢀnput (Note 7)
1
1.±
1
V
μA
μA
μA
μA
ꢀN, CM
+
–
Analog ꢀnput Leakage Current
SENSE ꢀnput Leakage Current
–1
–3
0V ≤ A
,
A
≤ V (Note 9)
ꢀN
ꢀN
ꢀN DD
ꢀ
ꢀ
ꢀ
0V ≤ SENSE ≤ V (Note 10)
3
SENSE
MODE
OE
DD
MODE Pin Pull-Down Current to GND
OE Pin Pull-Down Current to GND
Analog ꢀnput Capacitance
10
10
C
Sample Mode CLK = 0
Hold Mode CLK = 0
10.±
1.4
pF
pF
ꢀN
t
t
Sample-and-Hold
0.9
200
80
ns
AP
Acquisition Delay Time
Sample-and-Hold
Acquisition Delay Time Jitter
fs
RMS
JꢀTTER
+
–
CMRR
Analog ꢀnput
Common Mode Rejection Ratio
1V < (A = A ) <1.±V
dB
ꢀN
ꢀN
BW-3dB
Full Power Bandwidth
R < 20Ω
S
380
MHz
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
1MHz ꢀnput (2.2±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
81.6
79.4
dBFS
dBFS
l
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
80
81.6
79.4
dBFS
dBFS
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
81.4
79.3
dBFS
dBFS
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
80.8
78.9
dBFS
dBFS
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA =1 )
78.3
77.2
dBFS
dBFS
2201f
3
LTC2201
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SFDR
Spurious Free
1MHz ꢀnput (2.±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
100
100
dBc
dBc
Dynamic Range
nd
rd
2
or 3 Harmonic
l
l
l
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
8±
100
100
dBc
dBc
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
9±
100
dBc
dBc
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
90
9±
dBc
dBc
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA = 1)
8±
90
dBc
dBc
SFDR
Spurious Free
1MHz ꢀnput (2.±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
100
100
dBc
dBc
Dynamic Range
4th Harmonic or Higher
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
90
100
100
dBc
dBc
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
100
100
dBc
dBc
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
100
100
dBc
dBc
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA = 1)
90
90
dBc
dBc
S/(N+D)
Signal-to-Noise
Plus Distortion Ratio
1MHz ꢀnput (2.±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
81.±
79.3
dBFS
dBFS
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
79.7
81.±
79.3
dBFS
dBFS
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
81.3
79.2
dBFS
dBFS
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
80.6
78.6
dBFS
dBFS
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA = 1)
78.1
77
dBFS
dBFS
SFDR
Spurious Free
Dynamic Range
at –2±dBFS
1MHz ꢀnput (2.±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
10±
10±
dBFS
dBFS
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
10±
10±
dBFS
dBFS
Dither “OFF”
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
10±
10±
dBFS
dBFS
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
10±
10±
dBFS
dBFS
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA = 1)
100
100
dBFS
dBFS
2201f
4
LTC2201
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SFDR
Spurious Free
Dynamic Range
at –2±dBFS
1MHz ꢀnput (2.±V Range, PGA = 0)
1MHz ꢀnput (1.667V Range, PGA = 1)
11±
11±
dBFS
dBFS
±MHz ꢀnput (2.±V Range, PGA = 0)
±MHz ꢀnput (1.667V Range, PGA = 1)
11±
11±
dBFS
dBFS
Dither “ON”
12.±MHz ꢀnput (2.±V Range, PGA = 0)
12.±MHz ꢀnput (1.667V Range, PGA = 1)
11±
11±
dBFS
dBFS
30MHz ꢀnput (2.±V Range, PGA = 0)
30MHz ꢀnput (1.667V Range, PGA = 1)
11±
11±
dBFS
dBFS
70MHz ꢀnput (2.±V Range, PGA = 0)
70MHz ꢀnput (1.667V Range, PGA = 1)
110
110
dBFS
dBFS
COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
1.2±
±40
1
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
ꢀ
ꢀ
= 0
= 0
1.1±
1.3±
CM
CM
CM
CM
OUT
OUT
ppm/°C
3.13±V ≤ V ≤ 3.46±V
mV/V
Ω
DD
1mA ≤ | ꢀ
| ≤ 1mA
2
OUT
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, DITH, PGA, SHDN, RAND)
l
l
l
V
V
High Level ꢀnput Voltage
Low Level ꢀnput Voltage
Digital ꢀnput Current
V
V
V
= 3.3V
= 3.3V
2
V
V
ꢀH
DD
DD
ꢀN
0.8
ꢀL
ꢀ
= 0V to V
±10
μA
pF
ꢀN
DD
C
Digital ꢀnput Capacitance
(Note 7)
1.±
ꢀN
LOGIC OUTPUTS
OV = 3.3V
DD
V
High Level Output Voltage
Low Level Output Voltage
V
V
= 3.3V
= 3.3V
ꢀ = –10μA
O
3.299
3.29
V
V
OH
DD
O
l
l
ꢀ = –200μA
3.1
V
ꢀ = 160μA
0.01
0.10
V
V
OL
DD
O
ꢀ = 1.6mA
0.4
O
ꢀ
ꢀ
Output Source Current
Output Sink Current
V
V
= 0V
–±0
±0
mA
mA
SOURCE
OUT
= 3.3V
SꢀNK
OUT
OV = 2.5V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
V
V
= 3.3V
= 3.3V
ꢀ = –200μA
2.49
0.1
V
V
DD
O
ꢀ = 1.60mA
O
DD
OV = 1.8V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
V
V
= 3.3V
= 3.3V
ꢀ = –200μA
1.79
0.1
V
V
DD
O
ꢀ = 1.60mA
O
DD
2201f
5
LTC2201
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3.3
2
MAX
UNITS
V
l
V
P
Analog Supply Voltage
Shutdown Power
3.13±
3.46±
DD
SHDN = V , CLK = V
DD
mW
V
SHDN
DD
l
l
l
OV
Output Supply Voltage
Analog Supply Current
Power Dissipation
0.±
3.6
80
DD
ꢀ
64
mA
mW
VDD
P
DꢀS
211
264
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
f
S
t
L
Sampling Frequency
CLK Low Time
1
20
MHz
l
l
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
20
±
2±
2±
±00
±00
ns
ns
l
l
t
t
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
20
±
2±
2±
±00
±00
ns
ns
H
Sample-and-Hold
Aperture Delay
0.9
ns
AP
l
l
l
t
t
t
CLK to DATA Delay
C = ±pF (Note 7)
1.3
1.3
3.1
3.1
0
4.9
4.9
0.6
ns
ns
ns
D
L
CLK to CLKOUT Delay
DATA to CLKOUT Skew
C = ±pF (Note 7)
L
C
C = ±pF (Note 7)
L
–0.6
SKEW
l
l
DATA Access Time
Bus Relinquish Time
C = ±pF (Note 7)
±
±
1±
1±
ns
ns
L
(Note 7)
Pipeline
Latency
7
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 5: ꢀntegral nonlinearity is defined as the deviation of a code from a
“best fit straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: Dynamic current from switched capacitor inputs is large compared
to DC leakage current, and will vary with sample rate.
Note 10: Leakage current will experience transient at power up. Keep
DD
of greater than 100mA below GND or above V without latchup.
DD
Note 4: V = 3.3V, f
= 20MHz, input range = 2.±V with
DD
SAMPLE
P-P
differential drive (PGA = 0), unless otherwise specified.
resistance < 1kΩ.
2201f
6
LTC2201
TIMING DIAGRAM
t
AP
N + 1
N + 4
ANALOG
ꢀNPUT
N + 3
N
N + 2
t
L
t
H
CLK
t
D
N – 7
N – 6
N – ±
N – 4
N – 3
D0-D1±, OF
t
C
+
CLKOUT
–
2201 TD01
CLKOUT
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
vs Output Code
Differential Nonlinearity (DNL)
vs Output Code
AC Grounded Input Histogram
(256k Samples)
1.0
0.8
60000
2.0
1.±
±0000
0.6
1.0
0.4
40000
30000
0.±
0.2
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.±
–1.0
–1.±
–2.0
20000
10000
0
32812 32816 32820 32824 32828 32832
32768
CODE
0
16384
32768
CODE
6±±36
0
16384
491±2
6±±36
491±2
OUTPUT CODE
2201 G03
2201 G02
2201 G01
SFDR vs Input Level,
fIN = 5MHz, PGA = 0, Dither “Off”
SFDR vs Input Level,
IN = 5MHz, PGA = 0, Dither “On”
SFDR vs Input Level, fIN = 12.7MHz,
PGA = 0, Dither “Off”
f
140
120
140
120
140
120
100
100
100
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
–60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–70 –60 –±0 –40 –30 –20 –10
0
–70
–70
ꢀNPUT LEVEL (dBFS)
2201 G0±
2201 G06
2201 G04
2201f
7
LTC2201
TYPICAL PERFORMANCE CHARACTERISTICS
SFDR vs Input Level, fIN = 12.7MHz,
PGA = 0, Dither “On”
SFDR vs Input Level, fIN = 30.1MHz,
PGA = 0, Dither “Off”
SFDR vs Input Level, fIN = 30.1MHz,
PGA = 0, Dither “On”
140
120
140
120
140
120
100
100
100
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
–70 –60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–70 –60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–70 –60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
–80
2201 G07
2201 G08
2201 G09
SFDR vs Input Level, fIN = 70.1MHz,
PGA = 0, Dither “Off”
SFDR vs Input Level, fIN = 70.1MHz,
PGA = 0, Dither “On”
SFDR (HD2 or HD3)
vs Input Frequency
140
120
140
120
110
10±
100
9±
100
100
PGA = 1
80
60
40
20
80
60
40
20
90
8±
PGA = 0
80
7±
70
0
0
–70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70 –60 –±0 –40 –30 –20 –10
ꢀNPUT LEVEL (dBFS)
0
20
40
80
0
100
60
ꢀNPUT FREQUENCY (MHz)
2201 G10
2201 G11
2201 G12
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5MHz
IVDD vs Sample Rate,
5MHz Sine Wave, –1dBFS
SNR vs Input Frequency
82
81
80
79
78
77
76
7±
74
110
10±
68
6±
62
±9
±6
±3
UPPER LꢀMꢀT
LOWER LꢀMꢀT
PGA = 0
SFDR
100
9±
90
8±
80
PGA = 1
SNR
7±
73
2.9 3.0 3.1 3.2 3.3
SUPPLY VOLTAGE (V)
3.6
0
4
8
12
16
20
2.8
3.4 3.±
0
20
40
60
140
80 100 120
ꢀNPUT FREQUENCY (MHz)
SAMPLE RATE (Msps)
2201 G13
2201 G14
2201 G1±
2201f
8
LTC2201
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Full Scale
SFDR vs Input Common Mode
Voltage, fIN = 5MHz, –1dBFS,
PGA = 0
vs Temperature, Internal
Reference, 5 Units
Offset Voltage
vs Temperature, 5 Units
1.01
1.00±
1
6
4
2
0
110
10±
100
9±
90
8±
80
–2
–4
–6
7±
0.99±
70
6±
60
0.99
–40
–20
0
20
40
60
80
40
TEMPERATURE (˚C)
80
0.±
0.7±
1.2± 1.±0 1.7±
2
–40
–20
0
20
60
1
TEMPERATURE (°C)
ꢀNPUT COMMON MODE VOLTAGE (V)
2201 G16
2201 G17
2201 G18
Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
1.0
0.8
±
4
0.6
3
0.4
2
0.2
1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–±
0
±0 100 1±0 200 2±0 300 3±0 400 4±0 ±00
TꢀME AFTER WAKE-UP OR CLOCK START (μs)
2201 G19
0
100 200 300 400 ±00 600 700 800 9001000
TꢀME FROM WAKE-UP OR CLOCK START (μs)
2201 G20
2201f
9
LTC2201
PIN FUNCTIONS
–
–
SENSE(Pin1):ReferenceModeSelectandExternalRefer-
CLKOUT (Pin29):DataValidOutput.CLKOUT willtoggle
ence ꢀnput. Tie SENSE to V with 1k Ω or less to select
at the sample rate. Latch the data on the falling edge of
DD
–
theinternal2.±Vbandgapreference.Anexternalreference
of 2.±V or 1.2±V may be used; both reference values will
set a full scale ADC range of 2.±V (PGA = 0).
CLKOUT .
+
+
CLKOUT (Pin 30): ꢀnverted Data Valid Output. CLKOUT
will toggle at the sample rate. Latch the data on the rising
+
V
(Pin2):1.2±VOutput.Optimumvoltageforinputcom-
edge of CLKOUT .
CM
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under flow has occurred.
V
(Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
DD
OE (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
Bypass to GND with 0.1μF ceramic chip capacitors.
GND (Pins 5, 8, 9, 11, 15, 48, 49): ADC Power
Ground.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
+
A
IN
A
IN
(Pin 6): Positive Differential Analog ꢀnput.
(Pin 7): Negative Differential Analog ꢀnput.
cyclestabilizer.ConnectingMODEto1/3V selectsoffset
–
DD
binary output format and enables the clock duty cycle sta-
CLK (Pin 10): Clock ꢀnput. The hold phase of the sample-
and-hold circuit begins on the falling edge. The output
data may be latched on the rising edge of CLK.
bilizer.ConnectingMODEto2/3V selects2’scomplement
DD
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V selects 2’s complement output
DD
format and disables the clock duty cycle stabilizer.
SHDN(Pin16):PowerShutdownPin. SHDN=lowresults
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
RAND(Pin46):DigitalOutputRandomizationSelectionPin.
RAND low results in normal operation. RAND high selects
D1-D1± to be EXCLUSꢀVE-ORed with D0 (the LSB). The
outputcanbedecodedbyagainapplyinganXORoperation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
DITH (Pin 17): ꢀnternal Dither Enable Pin. DꢀTH = low
disables internal dither. DꢀTH = high enables internal
dither. Refer to ꢀnternal Dither section of this data sheet
for details on dither operation.
PGA(Pin47):ProgrammableGainAmplifierControlPin.Low
selects a front-end gain of 1, input range of 2.±V . High
D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital
Outputs. D1± is the MSB.
P-P
selects a front-end gain of 1.±, input range of 1.667V
.
P-P
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
OGND (Pins 23, 31 and 38): Output Driver Ground.
OV (Pins24, 25, 36, 37):PositiveSupplyfortheOutput
DD
Drivers. Bypass to ground with 0.1μF capacitors.
2201f
10
LTC2201
BLOCK DIAGRAM
+
A
A
ꢀN
ꢀN
V
DD
ꢀNPUT
S/H
FꢀRST PꢀPELꢀNED
ADC STAGE
SECOND PꢀPELꢀNED
ADC STAGE
THꢀRD PꢀPELꢀNED
ADC STAGE
FOURTH PꢀPELꢀNED
ADC STAGE
FꢀFTH PꢀPELꢀNED
ADC STAGE
–
GND
DꢀTHER
SꢀGNAL
GENERATOR
CORRECTꢀON LOGꢀC
AND
SHꢀFT REGꢀSTER
ADC CLOCKS
RANGE
SELECT
OV
DD
+
–
CLKOUT
CLKOUT
OF
SENSE
LOW JꢀTTER
CLOCK
DRꢀVER
ADC
REFERENCE
PGA
D1±
D14
CONTROL
LOGꢀC
OUTPUT
DRꢀVERS
t
t
t
V
CM
BUFFER
D1
D0
VOLTAGE
REFERENCE
2201 F01
OGND
CLK
SHDN PGA RAND M0DE DꢀTH
OE
Figure 1. Functional Block Diagram
2201f
11
LTC2201
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
ꢀf two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n =
0, 1, 2, 3, etc. For example, the 3rd order ꢀMD terms
include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The
3rd order ꢀMD is defined as the ratio of the RMS value
of either input tone to the RMS value of the largest 3rd
order ꢀMD product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio
The ratio of the RMS input signal amplitude to the RMS
valueofthepeakspuriousspectralcomponentexpressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
The signal-to-noise (SNR) is the ratio between the RMS
amplitudeofthefundamentalinputfrequencyandtheRMS
amplitude of all other frequency components, except the
first five harmonics.
Full Power Bandwidth
Total Harmonic Distortion
TheFullPowerbandwidthisthatinputfrequencyatwhich
theamplitudeofthereconstructedfundamentalisreduced
by 3dB for a full scale input signal.
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
Aperture Delay Time
The time from when CLK reaches 0.4± of VDD to the
instant that the input signal is held by the sample-and-
hold circuit.
2
2
2
2
THD = –20Log
(
√
(V + V + V + ... V )/V
)
2
3
4
N
1
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
2
N
through nth harmonics.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
Intermodulation Distortion
ꢀf the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (ꢀMD) in addition to
THD. ꢀMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
SNR
= –20log (2
π
• f • t
ꢀN JꢀTTER
)
JꢀTTER
2201f
12
LTC2201
APPLICATIONS INFORMATION
CONVERTER OPERATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
The LTC2201 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
TimingDiagramsection).Theanaloginputisdifferentialfor
improvedcommonmodenoiseimmunityandtomaximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample-and-hold
circuit.
Sample/Hold Operation
Figure2showsanequivalentcircuitfortheLTC2201CMOS
differentialsampleandhold. Thedifferentialanaloginputs
are sampled directly onto sampling capacitors (C
through NMOS transitors. The capacitors shown attached
)
SAMPLE
to each input (C
) are the summation of all other
PARASꢀTꢀC
capacitance associated with each input.
LTC2201
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. ꢀn op-
eration, the ADC quantizes the input to the stage and the
quantized value is subtracted from the input by the DAC
to produce a residue. The residue is amplified and output
by the residue amplifier. Successive stages operate out of
phasesothatwhenoddstagesareoutputtingtheirresidue,
the even stages are acquiring that residue and vice versa.
V
V
DD
C
SAMPLE
9.1pF
R
R
R
ON
PARASꢀTꢀC
3Ω
20Ω
+
A
A
ꢀN
C
1.4pF
PARASꢀTꢀC
DD
C
SAMPLE
9.1pF
R
ON
PARASꢀTꢀC
3Ω
20Ω
–
ꢀN
The phase of operation is determined by the state of the
CLK input pin.
C
PARASꢀTꢀC
1.4pF
When CLK is high, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that CLK transitions from high to low, the voltage
on the sample capacitors is held. While CLK is low, the
held input voltage is buffered by the S/H amplifier which
drivesthefirstpipelinedADCstage.Thefirststageacquires
the output of the S/H amplifier during the low phase of
CLK. When CLK goes back high, the first stage produces
its residue which is acquired by the second stage. At the
sametime,theinputS/Hgoesbacktoacquiringtheanalog
input. When CLK goes low, the second stage produces its
residue which is acquired by the third stage. An identi-
cal process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
CLK
2201 F02
Figure 2. Equivalent Input Circuit
During the sample phase when CLK is high, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When CLK transitions from high to low, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when CLK is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As CLK
transitions from low to high, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time at the input of
the converter. ꢀf the change between the last sample and
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
2201f
13
LTC2201
APPLICATIONS INFORMATION
the new sample is small, the charging glitch seen at the
input will be small. ꢀf the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than ±0Ω can reduce
the input bandwidth and increase high frequency distor-
tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input may
swing ±0.62±V for the 2.±V range (PGA = 0) or ±0.417V
for the 1.667V range (PGA = 1), around a common mode
V
CM
2.2μF
0.1μF
T1
1:1
+
voltage of 1.2±V. The V output pin (Pin 2) is designed
2±Ω
A
CM
ꢀN
ANALOG
ꢀNPUT
LTC2201
to provide the common mode bias level. V can be tied
CM
0.1μF
12pF
2±Ω
2±Ω
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
12pF
12pF
–
2±Ω
A
ꢀN
driver circuit. The V pin must be bypassed to ground
CM
T1 = COꢀLCRAFT WBCꢀ-ꢀT OR
MA/COM ETC1-1T.
close to the ADC with 2.2μF or greater.
2201 F03
RESꢀSTORS, CAPACꢀTORS ARE
0402 PACKAGE SꢀZE, EXCEPT 2.2μF.
Input Drive Impedence
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 1MHz to 100MHz
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2201 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reac-
tance can influence SFDR. At the rising edge of CLK the
sample and hold circuit will connect the 9.1pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK falls, holding the
sampled input on the sampling capacitor. ꢀdeally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4 shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
muchbetterhighfrequencyresponseandbalancethanflux
coupled center tap transformers. Coupling capacitors are
added at the ground and input primary terminals to allow
the secondary terminals to be biased at 1.2±V.
1/(2F ); however, this is not always possible and the
CLK
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
V
CM
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
2.2μF
2±Ω
0.1μF
+
10Ω
A
A
ꢀN
ꢀN
ANALOG
ꢀNPUT
LTC2201
0.1μF
4.7pF
2±Ω
2±Ω
2±Ω
T1
1:1
4.7pF
0.1μF
–
10Ω
INPUT DRIVE CIRCUITS
4.7pF
T1 = MA/COM ETC1-1-13.
RESꢀSTORS, CAPACꢀTORS
ARE 0402 PACKAGE SꢀZE,
EXCEPT 2.2μF.
2201 F04
Figure 3 shows the LTC2201 being driven by an RF trans-
former with a center-tapped secondary. The secondary
center tap is DC biased with V , setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
Figure 4. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 50MHz to 250MHz
CM
2201f
14
LTC2201
APPLICATIONS INFORMATION
Figure ± demonstrates the use of an LTC1994 differential
amplifier to convert a single ended input signal into a
differential input signal. The advantage of this method is
that it provides low frequency input response; however,
the limited gain bandwidth of any op amp will limit the
SFDR at high input frequencies.
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
LTC2201
RANGE
SELECT
AND GAꢀN
CONTROL
TꢀE TO V TO USE
DD
V
ꢀNTERNAL
ADC
REFERENCE
CM
ꢀNTERNAL 2.±V
REFERENCE
2.2 μF
499Ω
100pF
OR ꢀNPUT FOR
EXTERNAL 2.±V
REFERENCE
SENSE
+
PGA
LTC2201
2±Ω
±23Ω
A
A
ꢀN
OR ꢀNPUT FOR
EXTERNAL 1.2±V
REFERENCE
–
+
100pF
100pF
CM LT1994
2.±V
499Ω
–
2±Ω
–
+
ꢀN
BANDGAP
REFERENCE
±3.6Ω
V
2201 F0±
CM
1.2±V
499Ω
BUFFER
2.2μF
Figure 5. DC Coupled Input with Differential Amplifier
2201 F06
The 2±Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
Figure 6. Reference Circuit
TheSENSEpincanbedriven±±%aroundthenominal2.±V
or 1.2±V external reference input. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
Reference Operation
Figure6showstheLTC2201referencecircuitryconsisting
of a 2.±V bandgap reference, a programmable gain ampli-
fier and control circuit. The LTC2201 has three modes of
reference operation: ꢀnternal Reference, 1.2±V external
reference or 2.±V external reference. To use the internal
SENSE pin should be tied to V as close to the converter
DD
as possible. ꢀf the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with at least a 1μF ceramic capacitor.
reference, tie the SENSE pin to V . To use the external
DD
V
CM
1.2±V
reference, simply apply either a 1.2±V or 2.±V reference
2.2μF
voltagetotheSENSEinputpin.Both1.2±Vand2.±Vapplied
LTC2201
to SENSE will result in a full scale range of 2.±V (PGA =
SENSE
2.2μF
P-P
6
2
3.3V
1μF
LT1461-2.±
4
0). A 1.2±V output, V , is provided for a common mode
CM
biasforinputdrivecircuitry.Anexternalbypasscapacitoris
requiredfortheV output.Thisprovidesahighfrequency
CM
2201 F07
low impedance path to ground for internal and external
circuitry. This is also the compensation capacitor for the
reference; it will not be stable without this capacitor. The
minimum value required for stability is 2.2μF.
Figure 7. A 2.5V Range ADC
with an External 2.5V Reference
2201f
15
LTC2201
APPLICATIONS INFORMATION
PGA Pin
ꢀn applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. ꢀt is also helpful to drive the CLK pin with a
low-jitter high frequency source which has been divided
down to the appropriate sample rate. ꢀf the ADC is clocked
with a sinusoidal signal, filter the CLK signal to reduce
wideband noise and distortion products generated by
the source.
ThePGApinselectsbetweentwogainsettingsfortheADC
front-end.PGA=0selectsaninputrangeof2.±V ;PGA=
P-P
1selectsaninputrangeof1.667V .The2.±Vinputrange
P-P
hasthebestSNR;however, thedistortionwillbehigherfor
inputfrequenciesabove100MHz.Forapplicationswithhigh
input frequencies, the low input range will have improved
distortion; however, the SNR will be 2.4dB worse. See the
Typical Performance Characteristics section.
Maximum and Minimum Conversion Rates
Driving the Clock Input
ThemaximumconversionratefortheLTC2201is20Msps.
For the ADC to operate properly the CLK signal should
have a ±0% (±10%) duty cycle. Each half cycle must have
at least 20ns for the LTC2201 internal circuitry to have
enough settling time for proper operation.
The CLK input can be driven directly with a CMOS or TTL
levelsignal.Asinusoidalclockcanalsobeusedalongwitha
low-jitter squaring circuit before the CLK pin (Figure 8).
CLEAN 3.3V
An on-chip clock duty cycle stabilizer may be activated if
theinputclockdoesnothavea±0%dutycycle.Thiscircuit
usesthefallingedgeofCLKpintosampletheanaloginput.
The rising edge of CLK is ignored and an internal rising
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant ±0% internal duty
cycle. ꢀf the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
SUPPLY
4.7μF
FERRꢀTE
BEAD
0.1μF
1k
0.1μF
SꢀNUSOꢀDAL
CLOCK
CLK
LTC2201
ꢀNPUT
±6Ω
NC7SVU04
1k
2201 F08
Figure 8. Sinusoidal Single-Ended CLK Drive
connected to 1/3V or 2/3V using external resistors.
DD
DD
The noise performance of the LTC2201 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
The lower limit of the LTC2201 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architectureofthisADCreliesonstoringanalogsignalson
small valued capacitors. Junction leakage will discharge
thecapacitors.Thespecifiedminimumoperatingfrequency
for the LTC2201 is 1Msps.
2201f
16
LTC2201
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Data Format
TheLTC2201paralleldigitaloutputcanbeselectedforoffset
binary or 2’s complement format. The format is selected
with the MODE pin. This pin has a four level logic input,
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS Mode. Each buffer is powered by OVDD
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as ±0Ω
to external circuitry and eliminates the need for external
damping resistors.
centered at 0, 1/3V , 2/3V and V . An external resis-
DD
DD
DD
tor divider can be user to set the 1/3V and 2/3V logic
DD
DD
levels. Table 1 shows the logic states for the MODE pin.
Table 1. MODE Pin Function
CLOCK DUTY
MODE
OUTPUT FORMAT
CYCLE STABILIZER
0(GND)
Offset Binary
Off
On
On
Off
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digitaloutputsoftheLTC2201shoulddriveasmallcapaci-
tive load to avoid possible interaction between the digital
outputs and sensitive input circuitry. The output should
be buffered with a device such as a ALVCH16373 CMOS
latch. For full speed operation the capacitive load should
be kept under 10pF. A resistor in series with the output
may be used but is not required since the ADC has a series
resistor of 43Ω on chip.
1/3V
2/3V
Offset Binary
DD
DD
2’s Complement
2’s Complement
V
DD
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
Output Clock
Lower OV voltages will also help reduce interference
DD
from the digital outputs.
The ADC has a delayed version of the CLK input available
+
as a digital output. Both a noninverted version, CLKOUT
LTC2201
–
and an inverted version CLKOUT are provided. The
OV
DD
0.±V
+
–
TO 3.6V
CLKOUT /CLKOUT can be used to synchronize the con-
verter data to the digital system. This is necessary when
using a sinusoidal clock. Data can be latched on the rising
V
V
DD
DD
0.1μF
OV
DD
+
–
+
edgeofCLKOUT orthefallingedgeofCLKOUT .CLKOUT
falls and CLKOUT rises as the data outputs are updated.
DATA
FROM
LATCH
–
PREDRꢀVER
LOGꢀC
43Ω
TYPꢀCAL
DATA
OUTPUT
OGND
2201 F09
Figure 9. Equivalent Circuit for a Digital Output Buffer
2201f
17
LTC2201
APPLICATIONS INFORMATION
Digital Output Randomizer
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
ꢀnterference from the ADC digital outputs is sometimes
unavoidable. ꢀnterference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
offchip,theseunwantedtonescanberandomized,trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
supply for the digital output buffers, OV , should be tied
DD
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a
1.8V supply, then OV should be tied to that same 1.8V
DD
supply. ꢀn CMOS mode OV can be powered with any
DD
logic voltage up to 3.6V. OGND can be powered with any
voltagefromgroundupto1VandmustbelessthanOV
.
DD
.
The logic outputs will swing between OGND and OV
DD
The digital output is “Randomized” by applying an exclu-
sive-ORlogicoperationbetweentheLSBandallotherdata
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
PC BOARD
FPGA
CLKOUT
OF
LTC2201
D1±/D0
D1±
CLKOUT
CLKOUT
OF
D14/D0
D14
OF
LTC2201
t
t
D1±
D2/D0
t
D1±/D0
D14/D0
D2
D14
D1/D0
D1
t
t
t
D0
D2
D1
D0
D2/D0
D1/D0
RAND = HꢀGH,
SCRAMBLE
ENABLED
2201 F11
RAND
D0
Figure 11. Descrambling a Scrambled Digital Output
D0
2201 F10
Figure 10. Functional Equivalent of Digital Output Randomizer
2201f
18
LTC2201
APPLICATIONS INFORMATION
Internal Dither
Grounding and Bypassing
The LTC2201 is a 16-bit ADC with a very linear transfer
function;however,atlowinputlevelsevenslightimperfec-
tions in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input’s location
on the ADC transfer curve, resulting in improved SFDR
for low signal levels.
The LTC2201 require a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2201 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. ꢀn particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC.
As shown in Figure 12, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. ꢀf the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
thatdoesleakthroughwillappearaswhitenoise.Thedither
DAC is calibrated to result in less than 0.±dB elevation in
the noise floor of the ADC, as compared to the noise floor
with dither off.
High quality ceramic bypass capacitors should be used
at the V , V , and OV pins. Bypass capacitors must
DD CM
DD
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2201 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
+
–
LTC2201
CLKOUT
CLKOUT
+
Heat Transfer
OF
D1±
t
A
ꢀN
16-BꢀT
PꢀPELꢀNED
ADC CORE
DꢀGꢀTAL
SUMMATꢀON
ANALOG
ꢀNPUT
OUTPUT
DRꢀVERS
S/H
AMP
t
Most of the heat generated by the LTC2201 is transferred
from the die through the bottom-side exposed pad. For
good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. ꢀt is critical that the exposed pad and all ground
pins are connected to a ground plane of sufficient area
with as many vias as possible.
t
D0
–
A
ꢀN
CLOCK/DUTY
CYCLE
CONTROL
MULTꢀBꢀT DEEP
PSEUDO-RANDOM
NUMBER
PRECꢀSꢀON
DAC
GENERATOR
2201 F12
CLK
DꢀTH
DꢀTHER ENABLE
HꢀGH = DꢀTHER ON
LOW = DꢀTHER OFF
Figure 12. Functional Equivalent Block Diagram of
Internal Dither Circuit
2201f
19
LTC2201
APPLICATIONS INFORMATION
G N D
4 9
2 4
D D
D D
O V
O V
3 7
O G N D
O G N D
2 3
2 2
2 1
2 0
3 8
D 1 2
3 9
D 1 3
D 4
D 3
D 2
D 1
4 0
D 1 4
4 1
D 1 ±
1 9
4 2
O F
4 3
D 0
1 8
1 7
O E
D ꢀ T H
S H D N
G N D
4 4
M O D E
4 ±
1 6
1 ±
R A N D
4 6
D D
P G A
V
1 4
1 3
4 7
D D
G N D
4 8
V
2201f
20
LTC2201
APPLICATIONS INFORMATION
Silkscreen Top
Inner Layer 2
Silkscreen Topside
Inner Layer 3
2201f
21
LTC2201
APPLICATIONS INFORMATION
Silkscreen Bottom Side
Silkscreen Bottom
2201f
22
LTC2201
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 0±-08-1704 Rev C)
0.70 ±0.0±
±.1± ± 0.0±
±.±0 REF
6.10 ±0.0± 7.±0 ±0.0±
(4 SꢀDES)
±.1± ± 0.0±
PACKAGE OUTLꢀNE
0.2± ±0.0±
0.±0 BSC
RECOMMENDED SOLDER PAD PꢀTCH AND DꢀMENSꢀONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.7± ± 0.0±
R = 0.11±
TYP
7.00 ± 0.10
(4 SꢀDES)
R = 0.10
TYP
47 48
0.40 ± 0.10
PꢀN 1 TOP MARK
(SEE NOTE 6)
1
2
PꢀN 1
CHAMFER
C = 0.3±
±.1± ± 0.10
±.±0 REF
(4-SꢀDES)
±.1± ± 0.10
(UK48) QFN 0406 REV C
0.200 REF
0.2± ± 0.0±
0.±0 BSC
BOTTOM VꢀEW—EXPOSED PAD
0.00 – 0.0±
NOTE:
1. DRAWꢀNG CONFORMS TO JEDEC PACKAGE OUTLꢀNE MO-220 VARꢀATꢀON (WKKD-2)
2. DRAWꢀNG NOT TO SCALE
3. ALL DꢀMENSꢀONS ARE ꢀN MꢀLLꢀMETERS
4. DꢀMENSꢀONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT ꢀNCLUDE
MOLD FLASH. MOLD FLASH, ꢀF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SꢀDE, ꢀF PRESENT
±. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA ꢀS ONLY A REFERENCE FOR PꢀN 1 LOCATꢀON ON THE TOP AND BOTTOM OF PACKAGE
2201f
ꢀnformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2201
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC2202
LTC2203
LTC6404-1
16-Bit, 10Msps, 3.3V ADC
140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
1.±nV/√Hz Noise, –90dBc Distortion at 10MHz
16-Bit, 2±Msps, 3.3V ADC
600MHz Low Noise, Low Distortion, Differential
ADC Driver
LT1994
Low Noise, Low Distortion Fully
Differential ꢀnput/Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2204
LTC220±
LTC2206
LTC2207
LTC2208
LTC2224
LTC2242-12
LTC22±±
LTC2284
LT±±12
16-Bit, 40Msps, 3.3V ADC
480mW, 79.1dB SNR, 100dB SFDR, 48-Pin QFN
610mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
72±mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
12±0mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
740mW, 6±.4dB SNR, 84dB SFDR, 64-Pin QFN
39±mW, 72.±dB SNR, 88dB SFDR, 32-Pin QFN
±40mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN
DC to 3GHz, 21dBm ꢀꢀP3, ꢀntegrated LO Buffer
16-Bit, 6±Msps, 3.3V ADC
16-Bit, 80Msps, 3.3V ADC
16-Bit, 10±Msps, 3.3V ADC
16-Bit, 130Msps, 3,3V ADC, LVDS Outputs
12-Bit, 13±Msps, 3.3V ADC, High ꢀF Sampling
12-Bit, 2±0Msps, 2.±V ADC, LVDS Outputs
14-Bit, 12±Msps, 3V ADC, Lowest Power
14-Bit, Dual, 10±Msps, 3V ADC, Low Crosstalk
DC-3GHz High Signal Level
Downconverting Mixer
LT±±14
LT±±1±
LT±±16
LT±±17
LT±±22
Ultralow Distortion ꢀF Amplifier/ADC Driver
with Digitally Controlled Gain
4±0MHz to 1dB BW, 47dB OꢀP3, Digital Gain Control 10.±dB to 33dB in 1.±dB/Step
High ꢀꢀP3: 20dBm at 1.9GHz, ꢀntegrated LO Quadrature Generator
High ꢀꢀP3: 21.±dBm at 900MHz, ꢀntegrated LO Quadrature Generator
High ꢀꢀP3: 21dBm at 800MHz, ꢀntegrated LO Quadrature Generator
1.±GHz to 2.±GHz Direct Conversion
Quadrature Demodulator
800MHz to 1.±GHz Direct Conversion
Quadrature Demodulator
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
600MHz to 2.7GHz High Linearity
Downconverting Mixer
4.±V to ±.2±V Supply, 2±dBm ꢀꢀP3 at 900MHz. NF = 12.±dB, ±0Ω Single Ended
RF and LO Ports
2201f
LT 0412 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 9±03±-7417
24
l
l
(408)432-1900 FAX: (408) 434-0±07
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2012
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