LTC2257-14_15 [Linear]
14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs;型号: | LTC2257-14_15 |
厂家: | Linear |
描述: | 14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs |
文件: | 总34页 (文件大小:1355K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2258-14
LTC2257-14/LTC2256-14
14-Bit, 65/40/25Msps
Ultralow Power 1.8V ADCs
FeaTures
DescripTion
The LTC®2258-14/LTC2257-14/LTC2256-14 are sam-
pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 74dB SNR and 88dB spurious
n
74dB SNR
n
n
n
n
n
n
n
n
n
n
n
n
88dB SFDR
Low Power: 81mW/49mW/35mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1V to 2V
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
free dynamic range (SFDR). Ultralow jitter of 0.17ps
allows undersampling of IF frequencies with excellent
noise performance.
P-P
P-P
RMS
DCspecsinclude 1LSBINL(typical), 0.3LSBDNL(typi-
cal)andnomissingcodesovertemperature.Thetransition
noise is a low 1.13LSB
.
RMS
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
applicaTions
n
+
–
Communications
The ENC and ENC inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Cellular Base Stations
n
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
n
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
LTC2258-14 2-Tone FFT,
fIN = 68MHz and 69MHz
1.8V
V
1.2V
0
–10
–20
–30
–40
–50
–60
–70
TO 1.8V
DD
OV
DD
D13
+
14-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
–80
–90
OGND
–100
–110
–120
CLOCK/DUTY
CYCLE
CONTROL
0
20
10
FREQUENCY (MHz)
30
225814 TA01a
GND
65MHz
CLOCK
225814 TA01b
225814fc
1
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
absoluTe MaxiMuM raTings (Notes 1, 2)
Supply Voltages (V , OV )....................... –0.3V to 2V
Digital Output Voltage................ –0.3V to (OV + 0.3V)
DD
DD
DD
+
–
Analog Input Voltage (A , A
,
Operating Temperature Range:
IN
IN
PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)
LTC2258C, LTC2257C, LTC2256C............ 0°C to 70°C
LTC2258I, LTC2257I, LTC2256I...........–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
DD
+
–
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
pin conFiguraTions
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
40 39 38 37 36 35 34 33 32 31
+
A
A
1
2
30
29
28
D9
IN
A
A
1
2
30
29
28
D8_9
IN
IN
–
–
D8
IN
DNC
+
–
+
–
GND
REFH
3
CLKOUT
GND
REFH
3
CLKOUT
4
27 CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
REFH
5
26 OV
DD
41
41
REFL
6
25
OGND
24 D7
23
REFL
6
25
OGND
REFL
7
REFL
7
24 D6_7
PAR/SER
8
D6
22 D5
21
PAR/SER
8
23
22
21
DNC
D4_5
DNC
V
DD
9
V
DD
9
V
10
D4
DD
V
10
DD
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 150°C, θ = 32°C/W
JA
JMAX
T
= 150°C, θ = 32°C/W
JMAX JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
–
+
–
A
A
1
2
30
29
28
D8_9
D8_9
IN
IN
+
–
GND
REFH
3
CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
41
REFL
6
25
OGND
+
REFL
7
24 D6_7
–
+
–
PAR/SER
8
23
D6_7
22 D4_5
21
V
DD
9
V
DD
10
D4_5
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 150°C, θ = 32°C/W
JA
JMAX
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
225814fc
2
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
orDer inForMaTion
LEAD FREE FINISH
LTC2258CUJ-14#PBF
LTC2258IUJ-14#PBF
LTC2257CUJ-14#PBF
LTC2257IUJ-14#PBF
LTC2256CUJ-14#PBF
LTC2256IUJ-14#PBF
TAPE AND REEL
PART MARKING*
LTC2258UJ-14
LTC2258UJ-14
LTC2257UJ-14
LTC2257UJ-14
LTC2256UJ-14
LTC2256UJ-14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2258CUJ-14#TRPBF
LTC2258IUJ-14#TRPBF
LTC2257CUJ-14#TRPBF
LTC2257IUJ-14#TRPBF
LTC2256CUJ-14#TRPBF
LTC2256IUJ-14#TRPBF
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2258-14
TYP
LTC2257-14
TYP
LTC2256-14
MIN TYP MAX
PARAMETER
CONDITIONS
MIN
14
MAX
MIN
14
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
14
–2.5
–0.8
–9
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–3
1
3
0.8
9
–2.5
–0.8
–9
1
2.5
0.8
9
1
2.5
0.8
9
LSB
LSB
mV
–0.8
–9
0.3
1.5
0.3
1.5
0.3
1.5
Gain Error
Internal Reference
External Reference
1.5
0.4
1.5
0.4
1.5
0.4
%FS
%FS
l
–1.5
1.5
–1.5
1.5
–1.5
1.5
Offset Drift
20
20
20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
30
10
30
10
ppm/°C
ppm/°C
Transition Noise
External Reference
1.13
1.13
1.13
LSB
RMS
225814fc
3
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
analog inpuT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
1.7V < V < 1.9V
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)
V
CM
– 100mV
0.625
V
CM
V
CM
+ 100mV
1.300
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE External Reference Mode
1.250
V
I
Analog Input Common Mode Current
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
81
50
31
µA
µA
µA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current
0 < A , A < V , No Encode
–1
–3
–6
1
3
6
µA
µA
µA
ns
IN1
IN
IN
DD
PAR/SER Input Leakage Current
SENSE Input Leakage Current
0 < PAR/SER < V
IN2
DD
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
0
AP
0.17
80
ps
RMS
JITTER
CMRR
BW-3B
dB
Figure 6 Test Circuit
800
MHz
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2258-14
TYP
LTC2257-14
TYP
LTC2256-14
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
TYP MAX UNITS
SNR
Signal-to-Noise Ratio
5MHz Input
74
73.8
73.7
73
73.4
73.2
73.1
72.6
72.9
72.8
72.1
71.8
dB
dB
dB
dB
l
l
l
l
30MHz Input
70MHz Input
140MHz Input
72.4
71.9
71.2
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
90
90
90
84
90
90
90
84
90
90
90
84
dB
dB
dB
dB
30MHz Input
70MHz Input
140MHz Input
78
85
80
85
80
85
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
90
90
90
90
90
90
90
90
90
90
90
84
dB
dB
dB
dB
30MHz Input
70MHz Input
140MHz Input
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
73.8
73.7
73.6
72.5
73.2
73.1
73
72.8
72.7
72
dB
dB
dB
dB
30MHz Input
70MHz Input
140MHz Input
71.5
71.5
70.7
72.3
71.2
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600µA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400µA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
225814fc
4
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
(Note 8)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
3.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
DD
0.6
3.6
+
ENC to GND
(See Figure 11)
(Note 8)
V
R
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK)
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
IH
IL
DD
DD
IN
= 1.8V
0.6
10
I
IN
= 0V to 3.6V
–10
µA
pF
C
IN
Input Capacitance
(Note 8)
3
200
4
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
= 1.8V, SDO = 0V
DD
Ω
µA
pF
OL
l
I
SDO = 0V to 3.6V
(Note 8)
–10
10
OH
C
OUT
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV = 1.8V
DD
l
l
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.750
1.790
0.010
V
V
O
I = 500µA
O
0.050
OV = 1.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.488
0.010
V
V
OH
OL
O
I = 500µA
O
OV = 1.2V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.185
0.010
V
V
OH
OL
O
I = 500µA
O
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
350
175
454
mV
mV
OD
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.250
1.250
1.375
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
225814fc
5
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2258-14
TYP
LTC2257-14
TYP
LTC2256-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
1.7
1.1
1.8
1.9
1.9
1.7
1.1
1.8
1.9
1.9
30
1.7
1.1
1.8
1.9
1.9
22
V
V
DD
OV
DD
I
DC Input
Sine Wave Input
44.7
45.3
49.5
27
27.9
19.5
19.9
mA
mA
VDD
I
Digital Supply Current
Power Dissipation
Sine Wave Input, OV =1.2V
2.6
1.6
1.1
mA
OVDD
DD
l
P
DC Input
80.5
84.7
90
48.6
52.1
54
35.1
37.1
40
mW
mW
DISS
Sine Wave Input, OV =1.2V
DD
LVDS Output Mode
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(Note 10)
1.7
1.7
1.8
1.9
1.9
54
1.7
1.7
1.8
1.9
1.9
35
1.7
1.7
1.8
1.9
1.9
26
V
V
DD
OV
(Note 10)
DD
I
I
Sine Wave Input
48.9
31.4
23.5
mA
VDD
OVDD
l
l
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
20.7
40.5
23
44
20.7
40.5
23
44
20.7
40.5
23
44
mA
mA
(0V = 1.8V)
DD
l
l
P
DISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
125.3 139
160.9 177
93.8
105
79.6
89
mW
mW
129.4 143
115.2 126
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
0.5
9
0.5
9
0.5
9
mW
mW
mW
SLEEP
NAP
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
10
10
DIFFCLK
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2258-14
TYP
LTC2257-14
TYP
LTC2256-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
l
f
S
t
L
Sampling Frequency
(Note 10)
1
65
1
40
1
25
MHz
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2.0
7.69
7.69
500 11.88 12.5
500 2.00 12.5
500
500
19
2.00
20
20
500
500
ns
ns
l
l
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2.0
7.69
7.69
500 11.88 12.5
500
500
19
2.00
20
20
500
500
ns
ns
500
2.00
12.5
t
AP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
Cycles
225814fc
6
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.8
1.5
0.3
5.5
3.2
2.7
0.6
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
ns
SKEW
D
C
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 20pF, R
= 2k
= 2k
250
SDO
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
125
PULLUP
+
–
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
termination disabled, differential ENC /ENC = 2V sine wave, input
P-P
range = 2V with differential drive, unless otherwise noted.
P-P
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
DD
of greater than 100mA below GND or above V without latchup.
DD
Note 8: Guaranteed by design, not subject to test.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 9: V = 1.8V, f
25MHz (LTC2256), ENC = single-ended 1.8V square wave, ENC = 0V,
= 65MHz (LTC2258), 40MHz (LTC2257), or
DD
SAMPLE
+
–
DD
input range = 2V with differential drive, 5pF load on each digital output
P-P
unless otherwise noted.
Note 5: V = OV = 1.8V, f = 65MHz (LTC2258),
40MHz (LTC2257), or 25MHz (LTC2256), LVDS outputs with internal
DD
DD
SAMPLE
Note 10: Recommended operating conditions.
225814fc
7
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
TiMing DiagraMs
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D13, OF
t
C
+
CLKOUT
–
CLKOUT
225814 TD01
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
D0_1
D0
D1
D0
D1
D0
N-3
D1
D0
D1
N-2
N-5
N-5
N-4
N-4
N-3
N-2
•
•
•
D12_13
OF
D12
D13
D12
OF
D13
D12
D13
D12
D13
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
OF
OF
OF
N-2
N-5
N-4
N-3
t
t
C
C
+
CLKOUT
–
CLKOUT
225814 TD02
225814fc
8
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
TiMing DiagraMs
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
+
D0_1
D0
D1
D0
N-4
D1
D0
D1
D0
D1
N-2
N-5
N-5
N-4
N-3
N-3
N-2
–
D0_1
•
•
•
+
D12_13
D12
D13
D12
D13
D12
D13
D12
D13
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
–
D12_13
+
OF
OF
N-5
OF
N-4
OF
N-3
OF
N-3
–
OF
t
C
t
C
+
CLKOUT
–
CLKOUT
225814 TD03
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
225814 TD04
225814fc
9
HIGH IMPEDANCE
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical perForMance characTerisTics
LTC2258-14: Integral
Nonlinearity (INL)
LTC2258-14: Differential
Nonlinearity (DNL)
LTC2258-14: 8k Point FFT,
fIN = 5MHz, –1dBFS, 65Msps
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
2.0
1.5
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
4096
0
20
10
FREQUENCY (MHz)
30
0
8192
12288
16384
4096
OUTPUT CODE
OUTPUT CODE
225814 G02
225814 G03
225814 G01
LTC2258-14: 8k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
LTC2258-14: 8k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
LTC2258-14: 8k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
0
10
20
30
0
20
10
FREQUENCY (MHz)
30
FREQUENCY (MHz)
225814 G04
225814 G05
225814 G06
LTC2258-14: SNR vs Input
Frequency, –1dB, 2V Range,
65Msps
LTC2258-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
65Msps
LTC2258-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
10
FREQUENCY (MHz)
30
8197
8201
8203
8205
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
8199
50
OUTPUT CODE
225814 G07
225814 G08
225814 G09
225814fc
10
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical perForMance characTerisTics
LTC2258-14: SFDR vs Input
Frequency, –1dB, 2V Range,
65Msps
LTC2258-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
LTC2258-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
50
45
40
95
90
85
80
75
70
65
110
100
90
dBFS
LVDS OUTPUTS
CMOS OUTPUTS
80
70
60
dBc
50
40
30
20
10
0
35
30
0
20
40
60
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
SAMPLE RATE (Msps)
225814 G13
225814 G10
225814 G12
LTC2258-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
LTC2258-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2257-14: Integral Nonlinearity
(INL)
–1dB, 5pF on Each Data Output
45
40
35
30
25
20
15
2.0
1.5
75
74
73
72
71
70
3.5mA LVDS
1.0
0.5
1.75mA LVDS
0
–0.5
–1.0
–1.5
–2.0
69
68
67
10
5
1.2V CMOS
1.8V CMOS
0
0
20
40
60
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
8192
12288
16384
4096
SAMPLE RATE (Msps)
SENSE PIN (V)
OUTPUT CODE
225814 G14
225814 G15
225814 G21
LTC2257-14: 8k Point FFT,
fIN = 5MHz, –1dBFS, 40Msps
LTC2257-14: 8k Point FFT,
fIN = 29MHz, –1dBFS, 40Msps
LTC2257-14: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
0
8192
12288
16384
0
20
4096
10
0
20
10
OUTPUT CODE
FREQUENCY (MHz)
FREQUENCY (MHz)
225814 G22
225814 G23
225814 G24
225814fc
11
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical perForMance characTerisTics
LTC2257-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
40Msps
LTC2257-14: 8k Point FFT,
LTC2257-14: 8k Point FFT,
fIN = 139MHz, –1dBFS, 40Msps
fIN = 69MHz, –1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
0
20
10
10
0
20
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
225814 G27
225814 G26
225814 G25
LTC2257-14: SNR vs Input
Frequency, –1dB, 2V Range,
40Msps
LTC2257-14: SFDR vs Input
Frequency, –1dB, 2V Range,
40Msps
LTC2257-14: Shorted Input
Histogram
74
73
72
71
70
6000
5000
4000
3000
95
90
85
80
75
70
65
69
68
67
66
2000
1000
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
8198
8202
8204
8206
8200
0
100 150 200 250 300 350
50
OUTPUT CODE
INPUT FREQUENCY (MHz)
225814 G30
225814 G29
225814 G28
LTC2257-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2257-14: SFDR vs Input Level,
LTC2257-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
f
IN = 70MHz, 2V Range, 40Msps
45
40
35
30
25
20
15
110
100
90
35
30
25
20
15
3.5mA LVDS
dBFS
LVDS OUTPUTS
80
70
60
1.75mA LVDS
dBc
50
40
30
20
10
0
CMOS OUTPUTS
1.2V CMOS
1.8V CMOS
10
5
0
0
20
40
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
20
40
–70
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
225814 G34
225814 G32
225814 G33
225814fc
12
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical perForMance characTerisTics
LTC2257-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2256-14: Integral Nonlinearity
(INL)
LTC2256-14: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
2.0
1.5
74
73
72
71
70
69
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
68
67
66
0
8192
12288
16384
0
8192
12288
16384
4096
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
4096
OUTPUT CODE
OUTPUT CODE
SENSE PIN (V)
225814 G42
225814 G41
225814 G35
LTC2256-14: 8k Point FFT,
fIN = 5MHz, –1dBFS, 25Msps
LTC2256-14: 8k Point FFT,
fIN = 30MHz, –1dBFS, 25Msps
LTC2256-14: 8k Point FFT,
fIN = 70MHz, –1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
0
10
5
5
0
10
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
225814 G44
225814 G43
225814 G45
LTC2256-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
25Msps
LTC2256-14: Shorted Input
Histogram
LTC2256-14: 8k Point FFT,
IN = 140MHz, –1dBFS, 25Msps
f
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
2000
1000
0
0
10
5
0
10
5
8198
8202
8204
8206
8200
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
225814 G46
225814 G47
225814 G48
225814fc
13
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical perForMance characTerisTics
LTC2256-14: SNR vs Input
Frequency, –1dB, 2V Range,
25Msps
LTC2256-14: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
LTC2256-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 25Msps
95
90
85
80
75
70
65
110
100
90
74
73
72
71
70
dBFS
80
70
dBc
60
50
40
30
20
10
0
69
68
67
66
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
225814 G50
225814 G52
225814 G49
LTC2256-14: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
LTC2256-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2256-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
25
45
40
35
30
25
20
15
74
73
72
71
70
69
3.5mA LVDS
LVDS OUTPUTS
1.75mA LVDS
20
15
CMOS OUTPUTS
68
67
66
10
5
1.2V CMOS
20
1.8V CMOS
10
0
0
10
20
0
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
225814 G54
225814 G53
225814 G55
225814fc
14
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
pin FuncTions
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
parallel programming mode (PAR/SER = V ), SCK
DD
controls the digital output mode. When SCK is low,
the full-rate CMOS output mode is enabled. When SCK
is high, the double data rate LVDS output mode (with
3.5mA output current) is enabled. SCK can be driven
with 1.8V to 3.3V logic.
+
A
IN
A
IN
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
–
GND (Pin 3): ADC Power Ground.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
V ), SDI can be used to power down the part. When SDI
DD
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
PAR/SER(Pin8):ProgrammingModeSelectionPin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessaryandSDOcanbeleftunconnected.Intheparallel
the A/D operating modes. Connect to V to enable the
DD
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V of the part and not be driven by a
DD
logic signal.
programming mode (PAR/SER = V ), SDO is not used
DD
V
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
DD
and should not be connected.
to ground with 0.1µF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
OGND (Pin 25): Output Driver Ground.
+
ENC (Pin 11): Encode Input. Conversion starts on the
OV (Pin 26): Output Driver Supply. Bypass to ground
DD
rising edge.
with a 0.1µF ceramic capacitor.
–
ENC (Pin 12): Encode Complement Input. Conversion
V
(Pin 37): Common Mode Bias Output, Nominally
CM
starts on the falling edge.
Equal to V /2. V should be used to bias the common
DD
CM
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
V
(Pin38):ReferenceVoltageOutput,Nominally1.25V.
REF
Bypass to ground with a 1µF ceramic capacitor.
mode (PAR/SER = V ), CS controls the clock duty cycle
DD
SENSE(Pin39):ReferenceProgrammingPin.Connecting
stabilizer. WhenCS islow, theclockduty cyclestabilizeris
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SENSEtoV selectstheinternalreferenceanda 1Vinput
DD
range. Connecting SENSE to ground selects the internal
reference and a 0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
SCK (Pin 14): In serial programming mode, (PAR/SER
= 0V), SCK is the serial interface clock input. In the
input range of ±0.8 • V
.
SENSE
225814fc
15
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
OV )
DD
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
–
+
–
+
D0_1 /D0_1 to D12_13 /D12_13 (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
–
+
CLKOUT (Pin 27): Inverted version of CLKOUT .
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
+
+
+
of CLKOUT . The phase of CLKOUT can also be delayed
relative to the digital outputs by programming the mode
control registers.
D6, D8, D10, D12) appear when CLKOUT is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
+
CLKOUT is high.
–
+
DNC (Pin 35): Do not connect this pin.
CLKOUT /CLKOUT (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
+
as the falling and rising edges of CLKOUT . The phase of
+
CLKOUT canalsobedelayedrelativetothedigitaloutputs
by programming the mode control registers.
DOUBLE DATA RATE CMOS OUTPUT MODE
–
+
OF /OF (Pins 35/36): Over/Under Flow Digital Output.
OF is high when an overflow or underflow has occurred.
+
All Pins Below Have CMOS Output Levels (OGND to
OV )
DD
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double
Data Rate Digital Outputs. Two data bits are multiplexed onto
eachoutputpin. Theevendatabits(D0, D2, D4, D6, D8, D10,
+
D12) appear when CLKOUT is low. The odd data bits (D1,
+
D3, D5, D7, D9, D11, D13) appear when CLKOUT is high.
–
+
CLKOUT (Pin 27): Inverted version of CLKOUT .
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
+
+
ing edges of CLKOUT . The phase of CLKOUT can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
225814fc
16
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LTC2258-14
LTC2257-14/LTC2256-14
FuncTional block DiagraM
+
A
A
IN
IN
V
DD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
–
GND
V
CM
V
/2
DD
0.1µF
V
REF
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
1µF
RANGE
SELECT
REFH
REFL INTERNAL CLOCK SIGNALS
REF
BUF
OV
OF
DD
SENSE
D13
•
•
•
DIFF
REF
AMP
CLOCK/DUTY
CYCLE
CONTROL
MODE
OUTPUT
DRIVERS
CONTROL
REGISTERS
D0
+
–
CLKOUT
CLKOUT
225814 F01
REFH
REFL
OGND
0.1µF
+
–
ENC
ENC
PAR/SER CS SCK SDI SDO
2.2µF
0.1µF
0.1µF
Figure 1. Functional Block Diagram
225814fc
17
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LTC2258-14
LTC2257-14/LTC2256-14
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CONVERTER OPERATION
ANALOG INPUT
TheLTC2258-14/LTC2257-14/LTC2256-14arelowpower
14-bit 65Msps/40Msps/25Msps A/D converters that are
poweredbyasingle1.8Vsupply.Theanaloginputsshould
be driven differentially. The encode input can be driven
differentially, or single ended for lower power consump-
tion. The digital outputs can be CMOS, double data rate
CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.)
Many additional features can be chosen by programming
the mode control registers through a serial SPI port. See
the Serial Programming Mode section.
The analog input is a differential CMOS sample-and-hold
circuit(Figure2).Theinputsshouldbedrivendifferentially
around a common mode voltage set by the V output
CM
pin, which is nominally V /2. For the 2V input range,
DD
the inputs should swing from V – 0.5V to V + 0.5V.
CM
CM
Thereshouldbe180°phasedifferencebetweentheinputs.
LTC2258-14
V
DD
C
C
SAMPLE
3.5pF
R
ON
10Ω
10Ω
25Ω
+
–
A
A
IN
C
PARASITIC
1.8pF
V
DD
SAMPLE
3.5pF
R
25Ω
ON
IN
C
PARASITIC
1.8pF
V
DD
1.2V
10k
+
–
ENC
ENC
10k
1.2V
225814 F02
Figure 2. Equivalent Input Circuit
225814fc
18
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LTC2258-14
LTC2257-14/LTC2256-14
applicaTions inForMaTion
INPUT DRIVE CIRCUITS
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
showsanexampleofaninputRCfilter.TheRCcomponent
values should be chosen based on the application’s input
frequency.
tap is biased with V , setting the A/D input at its optimal
CM
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
50Ω
V
CM
50Ω
V
CM
0.1µF
0.1µF
0.1µF
0.1µF
+
A
ANALOG
INPUT
IN
T2
0.1µF
T1
1:1
+
LTC2258-14
25Ω
T1
A
IN
ANALOG
INPUT
0.1µF
25Ω
25Ω
LTC2258-14
1.8pF
0.1µF
25Ω
25Ω
–
A
12pF
IN
–
25Ω
A
IN
225814 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
225814 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 270MHz
50Ω
50Ω
V
V
CM
CM
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+
2.7nH
0.1µF
+
–
A
A
A
ANALOG
INPUT
IN
IN
IN
T2
ANALOG
INPUT
LTC2258-14
LTC2258-14
T1
0.1µF
25Ω
25Ω
25Ω
25Ω
T1
4.7pF
–
2.7nH
A
IN
T1: MA/COM ETC1-1-13
225814 F04
225814 F06
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 270MHz
225814fc
19
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LTC2257-14/LTC2256-14
applicaTions inForMaTion
Amplifier Circuits
LTC2258-14
5Ω
V
REF
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
1.25V BANDGAP
REFERENCE
1.25V
1µF
0.625V
RANGE
DETECT
AND
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
blockissingle-ended,thenatransformercircuit(Figures 4
to 6) should convert the signal to differential before driv-
ing the A/D.
CONTROL
TIE TO V FOR 2V RANGE;
DD
TIE TO GND FOR 1V RANGE;
SENSE
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.65V < V
SENSE
< 1.300V
INTERNAL ADC
HIGH REFERENCE
0.1µF
REFH
0.1µF
Reference
The LTC2258-14/2257-14/2256-14 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to V . For a 1V input range
2.2µF
0.1µF
0.8x
DIFF AMP
DD
REFL
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9.)
INTERNAL ADC
LOW REFERENCE
225814 F08
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
Figure 8. Reference Circuit
will then be 1.6 • V
.
SENSE
The V , REFH and REFL pins should be bypassed as
REF
V
REF
shown in Figure 8. The 0.1µF capacitor between REFH
and REFL should be as close to the pins as possible (not
on the back side of the circuit board).
1µF
LTC2258-14
1.25V
EXTERNAL
REFERENCE
SENSE
1µF
225814 F09
V
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
Figure 9. Using an External 1.25V Reference
200Ω 200Ω
25Ω
0.1µF
0.1µF
+
–
A
IN
LTC2258-14
ANALOG
INPUT
+
+
12pF
–
–
25Ω
A
IN
12pF
225814 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
225814fc
20
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LTC2257-14/LTC2256-14
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Encode Input
Thesingle-endedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
+
to ground and ENC is driven with a square wave encode
+
input. ENC can be taken above V (up to 3.6V) so 1.8V
DD
+
to3.3VCMOSlogiclevelscanbeused.TheENC threshold
is0.9V. ForgoodjitterperformanceENC shouldhavefast
+
rise and fall times.
Clock Duty Cycle Stabilizer
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
For good performance the encode signal should have a
50%( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
above V (up to 3.6V), and the common mode range
DD
is from 1.1V to 1.6V. In the differential encode mode,
–
ENC should stay at least 200mV above ground to avoid
falselytriggeringthesingle-endedencodemode.Forgood
+
–
jitter performance ENC and ENC should have fast rise
and fall times.
LTC2258-14
0.1µF
V
DD
+
25Ω
ENC
T1
1:4
DIFFERENTIAL
COMPARATOR
100Ω
100Ω
V
DD
D1
LTC2258-14
–
ENC
15k
30k
+
–
ENC
0.1µF
225814 F12
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
ENC
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
225814 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1µF
+
ENC
LTC2258-14
+
1.8V TO 3.3V
0V
ENC
PECL OR
LTC2258-14
LVDS
–
CLOCK
30k
ENC
0.1µF
–
CMOS LOGIC
BUFFER
ENC
225814 F11
225814 F13
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
Figure 13. PECL or LVDS Encode Drive
225814fc
21
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LTC2257-14/LTC2256-14
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by mode control register A2 (serial programming mode),
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
or by CS (parallel programming mode).
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50%( 5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are
multiplexed and output on each differential output pair.
+
–
There are 7 LVDS output pairs (D0_1 /D0_1 through
+
–
D12_13 /D12_13 ) for the digital output data. Overflow
(OF /OF )andthedataoutputclock(CLKOUT /CLKOUT )
each have an LVDS output pair.
+
–
+
–
DIGITAL OUTPUTS
Digital Output Modes
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
TheLTC2258-14/LTC2257-14/LTC2256-14canoperatein
three digital output modes: full rate CMOS, double data
rateCMOS(tohalvethenumberofoutputlines), ordouble
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode).NotethatdoubledatarateCMOScannotbeselected
in the parallel programming mode.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground. In LVDS
mode, OV must be 1.8V.
DD
Full-Rate CMOS Mode
Programmable LVDS Output Current
In full-rate CMOS mode the 14 digital outputs (D0-D13),
+
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
overflow (OF), and the data output clocks (CLKOUT ,
–
CLKOUT ) have CMOS output levels. The outputs are
powered by OV and OGND which are isolated from the
DD
A/D core power and ground. OV can range from 1.1V
DD
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
Optional LVDS Driver Internal Termination
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 7 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13), overflow (OF), and the data
output clocks (CLKOUT , CLKOUT ) have CMOS output
levels. TheoutputsarepoweredbyOV andOGNDwhich
are isolated from the A/D core power and ground. OV
Overflow Bit
+
–
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
DD
DD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
225814fc
22
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Phase Shifting the Output Clock
DATA FORMAT
In full-rate CMOS mode the data output bits normally
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
+
change at the same time as the falling edge of CLKOUT ,
+
so the rising edge of CLKOUT can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
thefallingandrisingedgesofCLKOUT .To allowadequate
Table 1. Output Codes vs Input Voltage
+
setup-and-hold time when latching the data, the CLKOUT
+
–
A
IN
– A
D13-D0
D13-D0
IN
signal may need to be phase shifted relative to the data
outputbits. MostFPGAshavethisfeature;thisisgenerally
the best place to adjust the timing.
(2V Range)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
OF (OFFSET BINARY)
(2’s COMPLEMENT)
1
0
0
0
0
0
0
0
0
1
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
TheLTC2258-14/LTC2257-14/LTC2256-14canalsophase
+
–
shift the CLKOUT /CLKOUT signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
+
–
CLKOUT and CLKOUT , independently of the phase shift.
Thecombinationofthesetwofeaturesenablesphaseshifts
of 45° up to 315° (Figure 14).
+
ENC
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1 CLKPHASE0
0°
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
135°
180°
225°
270°
315°
+
CLKOUT
225814 F14
Figure 14. Phase Shifting CLKOUT
225814fc
23
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Digital Output Randomizer
Alternate Bit Polarity
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
Anotherfeaturethatreducesdigitalfeedbackonthecircuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is “randomized” by applying an
exclusive-OR logic operation between the LSB and all
other data output bits. To decode, the reverse opera-
tion is applied—an exclusive-OR operation is applied
between the LSB and all other bits. The LSB, OF and
CLKOUT outputs are not affected. The output random-
izer is enabled by serially programming mode control
register A4.
When there is a very small signal at the input of the A/D
thatiscenteredaroundmid-scale,thedigitaloutputstoggle
between mostly 1s and mostly 0s. This simultaneous
switchingofmostofthebitswillcauselargecurrentsinthe
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. To first order, this cancels
currentflowinthegroundplane,reducingthedigitalnoise.
PC BOARD
FPGA
CLKOUT
CLKOUT
CLKOUT
OF
OF
OF
D13/D0
D13
D13/D0
D12/D0
D13
D12
D12/D0
D12
D2
LTC2258-14
•
•
•
•
•
•
D2/D0
D1/D0
D2/D0
D1/D0
D2
D1
D0
RANDOMIZER
ON
D1
D0
D0
D0
225814 F16
225814 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital
Output Signal
225814fc
24
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The digital output is decoded at the receiver by invert-
ing the odd bits (D1, D3, D5, D7, D9, D11, D13.) The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function
can be on at the same time. When alternate bit polarity
mode is on, the data format is offset binary and the 2’s
complement control bit has no effect. The alternate bit
polarity mode is enabled by serially programming mode
control register A4.
depends on the size of the bypass capacitors on V
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
,
REF
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the applica-
tion demands very accurate DC settling then an additional
50µs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
DEVICE PROGRAMMING MODES
The operating modes of the LTC2258-14/LTC2257-14/
LTC2256-14 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK and SDI pins are binary logic
DD
inputs that set certain operating modes. These pins can
Output Disable
be tied to V or ground, or driven by 1.8V, 2.5V or 3.3V
DD
CMOS logic. Table 2 shows the modes set by CS, SCK
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehighimpedancedisabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
Sleep and Nap Modes
SCK
SDI
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
225814fc
25
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Serial Programming Mode
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serialinterfacethatprogramtheA/Dmodecontrolregisters.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serialdataisonlywrittenandreadbackisnotneeded, then
SDO can be left floating and no pull-up resistor is needed.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero at the end of the SPI
Write Command.
The Reset Register is Write Only.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
D5
X
D4
X
D3
X
D2
X
D1
D0
X
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
Power Down Control Bits
10 = Not Used
11 = Sleep Mode
225814fc
26
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
applicaTions inForMaTion
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
D5
X
D4
X
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
+
+
+
–
–
–
01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
LVDS Internal Termination Bit
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
225814fc
27
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
applicaTions inForMaTion
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 101 0101 0101 0101 and 010 1010 1010 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 000 0000 0000 0000 and 111 1111 1111 1111
Note: Other Bit Combinations are not Used
Bit 2
Bit 1
Bit 0
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 Forces the Output Format to be Offset Binary
GROUNDING AND BYPASSING
The V capacitor should be located as close to the pin
CM
as possible. To make space for this the capacitor on V
REF
The LTC2258-14/LTC2257-14/LTC2256-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane is rec-
ommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
High quality ceramic bypass capacitors should be used at
HEAT TRANSFER
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
between REFH and REFL can be somewhat further away.
Most of the heat generated by the ADC is transferred from
the diethrough the bottom-side exposed pad and package
leadsontotheprintedcircuitboard.Forgoodelectricaland
thermal performance, the exposed pad must be soldered
to a large grounded pad on the PC board.
225814fc
28
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical applicaTions
LTC2258 Schematic
T2
MABAES0060
R9 10Ω
SENSE
•
•
C23
1µF
R39
ANALOG INPUT
33.2Ω
1%
R14
1k
C51
4.7pF
R40
33.2Ω
1%
C17
1µF
R10 10Ω
R16
100Ω
R15 100Ω
V
DD
C12
0.1µF
C13
1µF
C19
0.1µF
DIGITAL
OUTPUTS
40
39
38
37
36
+
35
–
34
33
32
31
V
SENSE V
V
CM
OF
OF D13 D12 D11 D10
DD
REF
R27 10Ω
R28 10Ω
1
2
30
29
28
27
26
25
24
23
22
21
+
–
AIN
D9
AIN
D8
+
3
GND
CLKOUT
4
–
REFH
REFH
REFL
REFL
CLKOUT
U2
LTC2258CUJ
5
C15
0.1µF
0V
OV
DD
DD
C20
2.2µF
C37
0.1µF
6
OGND
7
D7
D6
D5
D4
8
PAR/SER
C21
0.1µF
PAR/SER
9
V
DD
DD
10
V
DD
V
C18
0.1µF
+
–
GND ENC ENC CS SCK SDI SDO D0 D1 D2 D3
DIGITAL
OUTPUTS
41
11
12
13
14
15
16
17
18
19
20
R13
100Ω
ENCODE CLOCK
225814 TA02
SPI BUS
225814fc
29
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical applicaTions
Top Side
Silkscreen Top
225814 TA04
225814 TA03
Inner Layer 2 GND
Inner Layer 3
225814 TA04
225814 TA06
225814fc
30
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
Typical applicaTions
Inner Layer 4
Inner Layer 5 Power
225814 TA08
225814 TA07
Bottom Side
225814 TA09
225814fc
31
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
225814fc
32
For more information www.linear.com/LTC2258-14
LTC2258-14
LTC2257-14/LTC2256-14
revision hisTory (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
08/12 Corrected IO
to I
11, 12, 14
VDD
OVDD
Corrected RESET REGISTER A0, D7 description
26
29
20
Attached V to pins 9, 10 and 40 on schematic
DD
C
1/14
Corrected "external reference” to "internal reference” for 1V input range.
225814fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC2258-14
LTC2257-14/LTC2256-14
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LT1993-2
LT1994
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
LTC2202
LTC2203
LTC2204
LTC2205
LTC2206
LTC2207
LTC2208
LTC2209
LTC2220
LTC2220-1
LTC2224
LTC2249
LTC2250
LTC2251
LTC2252
LTC2253
LTC2254
LTC2255
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
16-Bit, 25Msps, 3.3V ADC, Lowest Noise
16-Bit, 40Msps, 3.3V ADC
140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
230mW, 73dB SNR, 5mm × 5mm QFN Package
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
16-Bit, 65Msps, 3.3V ADC
16-Bit, 80Msps, 3.3V ADC
16-Bit, 105Msps, 3.3V ADC
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
16-Bit, 160Msps, 3.3V ADC, LVDS Outputs
12-Bit, 170Msps ADC
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
14-Bit, 80Msps ADC
10-Bit, 105Msps ADC
10-Bit, 125Msps ADC
12-Bit, 105Msps ADC
12-Bit, 125Msps ADC
14-Bit, 105Msps ADC
14-Bit, 125Msps, 3V ADC, Lowest Power
12-Bit, 25/40/65Msps 1.8V ADCs, Ultralow Power
LTC2256-12/
LTC2257-12/
LTC2258-12
34mW/47mW/79mW, 71.1dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, 6mm × 6mm QFN Package
LTC2259-12/
LTC2260-12/
LTC2261-12
12-Bit, 80/105/125Msps 1.8V ADCs, Ultralow
Power
87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, 6mm × 6mm QFN Package
LTC2259-14/
LTC2260-14/
LTC2261-14
14-Bit, 80/105/125Msps 1.8V ADCs, Ultralow
Power
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, 6mm × 6mm QFN Package
LTC2284
LTC2299
LT5517
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
Dual 14-Bit, 80Msps ADC
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
LT5527
400MHz to 3.7GHz High Linearity Downconverting
Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5557
400MHz to 3.8GHz High Linearity Downconverting
Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB,
3.3V Supply Operation, Integrated Transformer
LT5575
800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
Integrated RF and LO Transformer
LTC6400-20
1.8GHz Low Noise, Low Distortion Differential ADC Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
Driver for 300MHz IF
LT6604-2.5/
LT6604-5/
LT6604-10/
LT6604-15
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
with ADC Driver
Distortion Amplifiers
225814fc
LT 0114 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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