LTC2259CUJ-16#TRPBF [Linear]
LTC2259-16 - 16-Bit, 80Msps Ultralow Power 1.8V ADC; Package: QFN; Pins: 40; Temperature Range: 0°C to 70°C;
| 型号： | LTC2259CUJ-16#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC2259-16 - 16-Bit, 80Msps Ultralow Power 1.8V ADC; Package: QFN; Pins: 40; Temperature Range: 0°C to 70°C |
| 文件： | 总28页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2259-16
16-Bit, 80Msps Ultralow
Power 1.8V ADC
FEATURES
DESCRIPTION
The LTC®2259-16 is a sampling 16-bit A/D converter de-
signed for digitizing high frequency, wide dynamic range
signals. It is perfect for demanding communications ap-
plications with AC performance that includes 73.1dB SNR
and 88dB spurious free dynamic range (SFDR). Ultralow
n
73.1dB SNR
n
88dB SFDR
n
Low Power: 89mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS or DDR LVDS Outputs
n
jitterof0.17ps
allowsundersamplingofIFfrequencies
Selectable Input Ranges: 1V to 2V
RMS
P-P
P-P
n
n
n
n
n
n
with excellent noise performance.
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
DC specs include 4LSB INL (typical) and 0.5LSB DNL
(typical).
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
Serial SPI Port for Configuration
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
+
–
The ENC and ENC inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
TYPICAL APPLICATION
1.8V
2-Tone FFT, fIN = 70MHz and 75MHz
0
1.2V
TO 1.8V
V
DD
OV
DD
–10
–20
–30
–40
–50
–60
–70
D15
+
–
16-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
D0
OGND
–80
–90
CLOCK/DUTY
CYCLE
CONTROL
–100
–110
–120
225916 TA01a
GND
0
20
30
40
10
80MHz
CLOCK
FREQUENCY (MHz)
225916 TA01b
225916f
1
LTC2259-16
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltages (V , OV )....................... –0.3V to 2V
Digital Output Voltage................–0.3V to (OV + 0.3V)
DD
DD
DD
+
–
Analog Input Voltage (A , A
,
Operating Temperature Range:
IN
IN
PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)
LTC2259C................................................ 0°C to 70°C
LTC2259I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
DD
+
–
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
PIN CONFIGURATION
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
40 39 38 37 36 35 34 33 32 31
+
A
A
1
2
30
29
28
D11
IN
A
A
1
2
30
29
28
D10_11
DNC
IN
–
–
D10
IN
IN
+
–
+
–
GND
REFH
3
CLKOUT
GND
REFH
3
CLKOUT
4
27 CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
REFH
41
GND
5
26 OV
DD
41
GND
REFL
6
25
OGND
24 D9
23
REFL
6
25
OGND
REFL
7
REFL
7
24 D8_9
PAR/SER
8
D8
22 D7
21
PAR/SER
8
23
22
21
DNC
D6_7
DNC
V
DD
9
V
DD
9
V
10
D6
DD
V
DD
10
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
T
= 150°C, θ = 32°C/W
JA
JMAX
T
= 150°C, θ = 32°C/W
JMAX JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
–
+
–
A
A
1
2
30
29
28
D10_11
D10_11
IN
IN
+
–
GND
REFH
3
CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
41
GND
REFL
6
25
OGND
+
REFL
7
24 D8_9
–
+
–
PAR/SER
8
23
D8_9
22 D6_7
21
V
DD
9
V
DD
10
D6_7
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
T
= 150°C, θ = 32°C/W
JA
JMAX
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
225916f
2
LTC2259-16
ORDER INFORMATION
LEAD FREE FINISH
LTC2259CUJ-16#PBF
LTC2259IUJ-16#PBF
TAPE AND REEL
PART MARKING*
LTC2259UJ-16
LTC2259UJ-16
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2259CUJ-16#TRPBF
LTC2259IUJ-16#TRPBF
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
CONVERTER CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
16
TYP
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–12
–1
4
12
1.2
9
LSB
LSB
mV
0.5
1.5
–9
Gain Error
Internal Reference
External Reference
1.5
0.4
%FS
%FS
l
–1.5
1.5
Offset Drift
20
μV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
ppm/°C
ppm/°C
Transition Noise
External Reference
5
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
1.7V < V < 1.9V
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)
V
– 100mV
0.625
V
CM
V
+ 100mV
1.300
V
INCM
SENSE
INCM
IN1
IN
IN
CM
CM
External Voltage Reference Applied to SENSE External Reference Mode
1.250
100
V
μA
μA
μA
μA
ns
I
I
I
I
t
t
Analog Input Common Mode Current
Analog Input Leakage Current
Per Pin, 80Msps
+
–
l
l
l
0 < A , A < V , No Encode
–1
–3
–6
1
3
6
IN
IN
DD
PAR/SER Input Leakage Current
SENSE Input Leakage Current
0 < PAR/SER < V
IN2
DD
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
0
AP
0.17
80
ps
RMS
JITTER
CMRR
BW-3B
dB
Figure 6 Test Circuit
800
MHz
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER
SNR Signal-to-Noise Ratio
CONDITIONS
MIN
TYP
MAX
UNITS
5MHz Input
70MHz Input
140MHz Input
73.1
72.9
72.4
dBFS
dBFS
dBFS
l
70.9
225916f
3
LTC2259-16
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SFDR
Spurious Free Dynamic Range 2nd or 3rd
5MHz Input
88
85
82
dBFS
dBFS
dBFS
l
l
l
Harmonic
70MHz Input
140MHz Input
79
Spurious Free Dynamic Range 4th Harmonic or
Higher
5MHz Input
70MHz Input
140MHz Input
90
90
90
dBFS
dBFS
dBFS
85
S/(N+D) Signal-to-Noise Plus Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
72.9
72.6
72
dBFS
dBFS
dBFS
70.4
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600μA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400μA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
(Note 8)
V
kΩ
pF
IN
R
10
IN
C
Input Capacitance
3.5
IN
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
0.6
3.6
DD
+
ENC to GND
(See Figure 11)
(Note 8)
V
R
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK)
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
DD
V
DD
V
IN
= 1.8V
1.3
V
V
IH
IL
= 1.8V
0.6
10
I
IN
= 0V to 3.6V
–10
μA
C
IN
Input Capacitance
(Note 8)
3
pF
225916f
4
LTC2259-16
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
200
4
MAX
UNITS
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
DD
= 1.8V, SDO = 0V
Ω
μA
pF
OL
l
I
OH
SDO = 0V to 3.6V
(Note 8)
–10
10
C
OUT
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE-DATA RATE)
OV = 1.8V
DD
l
l
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.750
1.790
0.010
V
V
O
I = 500μA
O
0.050
OV = 1.5V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.488
0.010
V
V
O
I = 500μA
O
OV = 1.2V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.185
0.010
V
V
O
I = 500μA
O
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
350
175
454
mV
mV
OD
V
OS
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.250
1.250
1.375
V
V
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Output Modes: Full Data Rate and Double-Data Rate
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
1.7
1.1
1.8
1.9
1.9
V
V
DD
OV
DD
I
DC Input
Sine Wave Input
49.2
50.2
58.1
mA
mA
VDD
I
Digital Supply Current
Power Dissipation
Sine Wave Input, OV =1.2V
2.5
mA
OVDD
DD
l
P
DC Input
89
93
105
mW
mW
DISS
Sine Wave Input, OV =1.2V
DD
LVDS Output Mode
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(Note 10)
1.7
1.7
1.8
1.9
1.9
V
V
DD
OV
(Note 10)
DD
I
I
Sine Wave Input
53.8
63.5
mA
VDD
OVDD
l
l
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
20.7
40.5
26
47.8
mA
mA
(0V = 1.8V)
DD
l
l
P
DISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
134
170
161
201
mW
mW
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
0.5
9
mW
mW
mW
SLEEP
NAP
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
DIFFCLK
225916f
5
LTC2259-16
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
f
t
Sampling Frequency
(Note 10)
1
80
MHz
S
L
l
l
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
5.93
2.00
6.25
6.25
500
500
ns
ns
l
l
t
t
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
5.93
2.00
6.25
6.25
500
500
ns
ns
H
Sample-and-Hold Acquisition Delay
Time
0
ns
AP
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double-Data Rate Mode
5.0
5.5
Cycles
Cycles
Digital Data Outputs (LVDS Mode)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.8
1.5
0.3
5.5
3.2
2.7
0.6
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
ns
SKEW
D
C
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 20pF, R
= 2k
= 2k
250
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
125
SDO
PULLUP
Note 5: V = OV = 1.8V, f = 80MHz, LVDS outputs with internal
SAMPLE
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
DD
DD
+
–
termination disabled, differential ENC /ENC = 2V sine wave, input
P-P
range = 2V with differential drive, unless otherwise noted.
P-P
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
DD
of greater than 100mA below GND or above V without latchup.
DD
Note 8: Guaranteed by design, not subject to test.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
+
DD
Note 9: V = 1.8V, f
wave, ENC = 0V, input range = 2V with differential drive, 5pF load on
= 80MHz, ENC = single-ended 1.8V square
DD
SAMPLE
–
P-P
each digital output unless otherwise noted.
Note 10: Recommended operating conditions.
225916f
6
LTC2259-16
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D15
t
C
+
CLKOUT
–
CLKOUT
225916 TD01
Double-Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
t
D
D0_1
D0
D1
D0
D1
N-4
D0
D1
D0
D1
N-2
N-5
N-5
N-4
N-3
N-3
N-2
•
•
•
D14_15
D14
D15
D14
D15
D14
D15
D14
D15
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
t
t
C
C
+
CLKOUT
–
CLKOUT
225916 TD02
225916f
7
LTC2259-16
TIMING DIAGRAMS
Double-Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
t
D
+
D0_1
D0
D1
D0
D1
N-4
D0
D1
D0
D1
N-2
N-5
N-5
N-4
N-3
N-3
N-2
–
D0_1
•
•
•
+
D14_15
D14
D15
D14
D15
D14
D15
D14
D15
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
–
D14_15
t
t
C
C
+
CLKOUT
–
CLKOUT
225916 TD03
SPI Port Timing (Readback Mode)
t
t
DS
t
t
t
H
S
DH
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
226114 TD04
HIGH IMPEDANCE
225916f
8
LTC2259-16
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-16: 8k Point FFT,
fIN = 5MHz –1dBFS, 80Msps
LTC2259-16: Integral
Non-Linearity (INL)
LTC2259-16: Differential
Non-Linearity (DNL)
1.0
0.8
0
–10
–20
–30
–40
–50
–60
–70
4
3
0.6
2
0.4
1
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–80
–90
–100
–110
–120
0
32768
49152
65536
16384
0
20
30
40
10
0
32768
49152
65536
16384
OUTPUT CODE
FREQUENCY (MHz)
OUTPUT CODE
225916 G02
225916 G03
225916 G01
LTC2259-16: 8k Point FFT,
fIN = 30MHz –1dBFS, 80Msps
LTC2259-16: 8k Point FFT,
fIN = 70MHz –1dBFS, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–100
–110
–120
0
20
30
40
0
20
30
40
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
225916 G04
225916 G05
LTC2259-16: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2259-16: 8k Point FFT,
IN = 140MHz –1dBFS, 80Msps
f
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
0
20
30
40
10
0
20
30
40
10
FREQUENCY (MHz)
FREQUENCY (MHz)
225916 G07
225916 G06
225916f
9
LTC2259-16
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-16: SNR vs Input
Frequency, –1dBFS, 2V Range,
80Msps
LTC2259-16: SFDR vs Input
Frequency, –1dBFS, 2V Range,
80Msps
LTC2259-16: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
110
100
90
74
73
72
71
70
95
90
85
80
75
70
65
dBFS
80
70
dBc
60
50
40
30
20
10
0
69
68
67
66
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
50
225916 G10
225916 G08
225916 G09
LTC2259-16: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS,
5pF on Each Data Output
LTC2259-16: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2259-16: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
55
50
45
45
40
35
30
25
20
15
74
73
72
71
70
69
3.5mA LVDS
LVDS OUTPUTS
CMOS OUTPUTS
1.75mA LVDS
40
35
68
67
66
10
5
1.2V CMOS
1.8V CMOS
0
0
20
40
60
80
0
20
40
60
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
225916 G11
225916 G12
225916 G13
225916f
10
LTC2259-16
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V ), SCK controls the
DD
+
A
A
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
IN
IN
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double-
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
–
GND (Pin 3, Exposed Pad Pin 41): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
V ), SDI can be used to power down the part. When SDI
DD
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
PAR/SER(Pin8):ProgrammingModeSelectionPin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessaryandSDOcanbeleftunconnected.Intheparallel
the A/D operating modes. Connect to V to enable the
DD
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V of the part and not be driven by a
DD
logic signal.
V
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
DD
programming mode (PAR/SER = V ), SDO is not used
DD
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
and should not be connected.
can share a bypass capacitor.
OGND (Pin 25): Output Driver Ground.
+
ENC (Pin 11): Encode Input. Conversion starts on the
OV (Pin 26): Output Driver Supply. Bypass to ground
DD
rising edge.
with a 0.1μF ceramic capacitor.
–
ENC (Pin 12): Encode Complement Input. Conversion
V
(Pin 37): Common Mode Bias Output, Nominally
CM
starts on the falling edge.
Equal to V /2. V should be used to bias the common
DD
CM
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
V
(Pin38):ReferenceVoltageOutput.Bypasstoground
REF
with a 1μF ceramic capacitor, nominally 1.25V.
mode (PAR/SER = V ), CS controls the clock duty cycle
DD
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SENSE(Pin39):ReferenceProgrammingPin.Connecting
SENSEtoV selectstheinternalreferenceanda 1Vinput
DD
range. Connecting SENSE to ground selects the internal
reference and a 0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of 0.8 • V
.
SENSE
225916f
11
LTC2259-16
PIN FUNCTIONS
FULL-RATE CMOS OUTPUT MODE
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
+
+
All Pins Below Have CMOS Output Levels (OGND to
ing edges of CLKOUT . The phase of CLKOUT can also
be delayed relative to the digital outputs by programming
the mode control registers.
OV )
DD
D0 to D15 (Pins 35, 36, 17-24, 29-34): Digital Outputs.
D15 is the MSB. D0 is the LSB.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
–
+
CLKOUT (Pin 27): Inverted Version of CLKOUT .
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
DOUBLE-DATA RATE LVDS OUTPUT MODE
normally transition at the same time as the falling edge
+
+
of CLKOUT . The phase of CLKOUT can also be delayed
relative to the digital outputs by programming the mode
control registers.
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
DOUBLE-DATA RATE CMOS OUTPUT MODE
–
+
–
+
D0_1 /D0_1 to D14_15 /D14_15 (Pins 35/36, 17/18,
19/20, 21/22, 23/24, 29/30, 31/32, 33/34): Double-Data
Rate Digital Outputs. Two data bits are multiplexed onto
each differential output pair. The even data bits (D0, D2,
All Pins Below Have CMOS Output Levels (OGND to
OV )
DD
+
D0_1 to D14_15 (Pins 36,18, 20, 22, 24, 30, 32, 34):
Double-Data Rate Digital Outputs. Two data bits are multi-
plexed onto each output pin. The even data bits (D0, D2, D4,
D4, D6, D8, D10, D12, D14) appear when CLKOUT is low.
The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)
+
appear when CLKOUT is high.
+
D6, D8, D10, D12, D14) appear when CLKOUT is low. The
–
+
CLKOUT /CLKOUT (Pins 27/28): Data Output Clock.
odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear
The digital outputs normally transition at the same time
+
when CLKOUT is high.
+
as the falling and rising edges of CLKOUT . The phase of
–
+
+
CLKOUT (Pin 27): Inverted Version of CLKOUT .
CLKOUT canalsobedelayedrelativetothedigitaloutputs
by programming the mode control registers.
225916f
12
LTC2259-16
FUNCTIONAL BLOCK DIAGRAM
+
A
IN
V
DD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
–
A
IN
GND
V
CM
V
/2
DD
0.1μF
V
REF
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
1μF
RANGE
SELECT
REFH
REFL INTERNAL CLOCK SIGNALS
REF
BUF
OV
DD
SENSE
D15
•
•
•
DIFF
CLOCK/DUTY
CYCLE
CONTROL
MODE
OUTPUT
DRIVERS
REF
CONTROL
AMP
REGISTERS
D0
+
–
CLKOUT
CLKOUT
225916 F01
REFH
REFL
0.1μF
2.2μF
OGND
+
–
PAR/SER
SCK SDI
SDO
ENC
ENC
CS
0.1μF
0.1μF
Figure 1. Functional Block Diagram
APPLICATIONS INFORMATION
CONVERTER OPERATION
LTC2259-16
10Ω
V
DD
C
C
The LTC2259-16 is a low power 16-bit 80Msps A/D
converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double-data rate CMOS (to halve the number of output
lines), or double-data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen by
programming the mode control registers through a serial
SPI port. See the Serial Programming Mode section.
SAMPLE
3.5pF
R
ON
25Ω
+
–
A
A
IN
IN
C
PARASITIC
1.8pF
V
DD
SAMPLE
3.5pF
R
25Ω
ON
10ꢀ
C
PARASITIC
1.8pF
V
DD
1.2V
10k
ANALOG INPUT
+
–
ENC
The analog input is a differential CMOS sample-and-hold
circuit(Figure2).Theinputsshouldbedrivendifferentially
ENC
10k
around a common mode voltage set by the V output
CM
1.2V
pin, which is nominally V /2. For the 2V input range, the
DD
225916 F02
inputs should swing from V – 0.5V to V + 0.5V. There
CM
CM
Figure 2. Equivalent Input Circuit
should be 180° phase difference between the inputs.
225916f
13
LTC2259-16
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Input Filtering
Transformer-Coupled Circuits
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with V , setting the A/D input at its optimal
CM
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
50Ω
V
50Ω
V
CM
CM
0.1μF
0.1μF
0.1μF
+
0.1μF
T1
1:1
A
IN
ANALOG
INPUT
T2
+
25Ω
A
IN
ANALOG
INPUT
LTC2259-16
T1
0.1μF
25Ω
25Ω
LTC2259-16
0.1μF
25Ω
25Ω
4.7pF
12pF
0.1μF
–
A
IN
–
25Ω
A
IN
225916 F04
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
225916 F03
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 70MHz to 170MHz
50Ω
V
50Ω
V
CM
CM
0.1μF
0.1μF
0.1μF
0.1μF
+
2.7nH
0.1μF
+
A
A
A
ANALOG
INPUT
IN
T2
IN
ANALOG
INPUT
LTC2259-16
T1
LTC2259-16
0.1μF
25Ω
25Ω
25Ω
25Ω
T1
1.8pF
0.1μF
0.1μF
–
–
2.7nH
A
IN
IN
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
225916 F05
225916 F06
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 170MHz to 270MHz
Figure 6. Recommended Front-End Circuit for
Input Frequencies Above 270MHz
225916f
14
LTC2259-16
APPLICATIONS INFORMATION
Amplifier Circuits
LTC2259-16
5Ω
V
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
REF
1.25V BANDGAP
REFERENCE
1.25V
1μF
0.625V
RANGE
DETECT
AND
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
blockissingle-ended,thenatransformercircuit(Figures 4
to 6) should convert the signal to differential before driv-
ing the A/D.
CONTROL
TIE TO V FOR 2V RANGE;
DD
TIE TO GND FOR 1V RANGE;
SENSE
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.65V < V
SENSE
< 1.300V
INTERNAL ADC
HIGH REFERENCE
0.1μF
REFH
0.1μF
Reference
The LTC2259-16 has an internal 1.25V voltage reference.
For a 2V input range using the internal reference, connect
SENSE to V . For a 1V input range using the internal
2.2μF
0.1μF
0.8x
DIFF AMP
DD
REFL
reference, connect SENSE to ground. For a 2V input range
withanexternalreference, applya1.25Vreferencevoltage
to SENSE (Figure 9.)
INTERNAL ADC
LOW REFERENCE
225916 F08
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
Figure 8. Reference Circuit
will then be 1.6 • V
.
SENSE
The V , REFH and REFL pins should be bypassed as
V
REF
REF
shown in Figure 8. The 0.1μF capacitor between REFH
and REFL should be as close to the pins as possible (not
on the back side of the circuit board).
1μF
LTC2259-16
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
225916 F09
V
CM
Figure 9. Using an External 1.25V Reference
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1μF
200Ω 200Ω
25Ω
0.1μF
0.1μF
+
–
A
IN
LTC2259-16
ANALOG
INPUT
+
+
12pF
–
–
25Ω
A
IN
225916 F07
Figure 7. Front-End Circuit Using a High
Speed Differential Amplifier
225916f
15
LTC2259-16
APPLICATIONS INFORMATION
Encode Input
Thesingle-endedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
+
to ground and ENC is driven with a square wave encode
+
input. ENC can be taken above V (up to 3.6V) so 1.8V
DD
+
to3.3VCMOSlogiclevelscanbeused.TheENC threshold
+
is 0.9V. For good jitter performance ENC should have fast
rise and fall times.
Clock Duty Cycle Stabilizer
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
For good performance the encode signal should have a
50%( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
above V (up to 3.6V), and the common mode range
DD
is from 1.1V to 1.6V. In the differential encode mode,
–
ENC should stay at least 200mV above ground to avoid
falselytriggeringthesingle-endedencodemode.Forgood
+
–
jitter performance ENC and ENC should have fast rise
and fall times.
LTC2259-16
V
DD
0.1μF
+
DIFFERENTIAL
COMPARATOR
25Ω
ENC
T1
1:4
V
DD
100Ω
100Ω
D1
LTC2259-16
15k
30k
–
+
–
ENC
ENC
0.1μF
225916 F12
ENC
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
225916 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
Figure 12. Sinusoidal Encode Drive
0.1μF
+
LTC2259-16
+
ENC
1.8V TO 3.3V
0V
ENC
ENC
PECL OR
LTC2259-16
LVDS
–
30k
CLOCK
0.1μF
CMOS LOGIC
BUFFER
–
ENC
225916 F11
225916 F13
Figure 13. PECL or LVDS Encode Drive
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
225916f
16
LTC2259-16
APPLICATIONS INFORMATION
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
thedutycyclestabilizerisdisabled,careshouldbetakento
makethesamplingclockhavea50%( 5%)dutycycle.The
duty cycle stabilizer should not be used below 5Msps.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate LVDS Mode
In double-data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
DIGITAL OUTPUTS
+
–
+
are8LVDSoutputpairs(D0_1 /D0_1 throughD14_15 /
–
Digital Output Modes
D14_15 )forthedigitaloutputdata.Thedataoutputclock
+
–
(CLKOUT /CLKOUT ) has an LVDS output pair.
The LTC2259-16 can operate in three digital output
modes: full-rate CMOS, double-data rate CMOS (to halve
the number of output lines), or double-data rate LVDS
(to reduce digital noise in the system). The output mode
is set by mode control register A3 (serial programming
mode), orbySCK(parallelprogrammingmode). Notethat
double-data rate CMOS cannot be selected in the parallel
programming mode.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100ꢀ differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground. In LVDS
Full-Rate CMOS Mode
mode, OV must be 1.8V.
DD
In full-rate CMOS mode the 16 digital outputs (D0-D15),
+
–
and the data output clocks (CLKOUT , CLKOUT ) have
Programmable LVDS Output Current
CMOS output levels. The outputs are powered by OV
DD
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
and OGND which are isolated from the A/D core power
and ground. OV can range from 1.1V to 1.9V, allowing
DD
1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Optional LVDS Driver Internal Termination
In most cases using just an external 100ꢀ termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100ꢀ termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Double-Data Rate CMOS Mode
In double-data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of data lines by eight, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 8 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13, D14_15), and the data output
+
–
clocks (CLKOUT , CLKOUT ) have CMOS output levels.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground. OV can
DD
rangefrom1.1Vto1.9V,allowing1.2Vthrough1.8VCMOS
logic outputs.
225916f
17
LTC2259-16
APPLICATIONS INFORMATION
Phase-Shifting the Output Clock
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A4. Note that when the analog input is
outside the normal operating range the two LSBs (D1,
D0) can change and should be ignored.
In full-rate CMOS mode the data output bits normally
+
change at the same time as the falling edge of CLKOUT ,
+
so the rising edge of CLKOUT can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
thefallingandrisingedgesofCLKOUT .Toallowadequate
+
setup-and-hold time when latching the data, the CLKOUT
signal may need to be phase shifted relative to the data
outputbits. MostFPGAshavethisfeature;thisisgenerally
the best place to adjust the timing.
Table 1. Output Codes vs Input Voltage
+
–
A
– A
D15-D0
(OFFSET BINARY)
D15-D0
(2’s COMPLEMENT)
IN
IN
(2V Range)
+
>1.000000V
+0.999970V
+0.999939V
+0.999909V
+0.999978V
1111 1111 1111 11XX
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
0111 1111 1111 11XX
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0111 1111 1111 1100
The LTC2259-16 can also phase shift the CLKOUT /CLK-
–
OUT signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90° or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
+0.000030V
+0.000000V
+0.000030V
+0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
+
trol register bit can invert the polarity of CLKOUT and
CLKOUT , independently of the phase shift. The combina-
–
–0.999878V
–0.999909V
–0.999939V
–1.000000V
< –1.000000V
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 00XX
1000 0000 0000 0011
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 00XX
tion of these two features enables phase shifts of 45° up
to 315° (Figure 14).
Note: X means data could be 1 or 0.
+
ENC
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
0
CLKPHASE1 CLKPHASE0
0°
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
0
0
0
1
1
1
1
135°
180°
225°
270°
315°
+
CLKOUT
225916 F14
Figure 14. Phase-Shifting CLKOUT
225916f
18
LTC2259-16
APPLICATIONS INFORMATION
Digital Output Randomizer
Alternate Bit Polarity
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
Anotherfeaturethatreducesdigitalfeedbackonthecircuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13, D15)areinvertedbeforetheoutputbuffers. Theeven
bits (D0, D2, D4, D6, D8, D10, D12, D14) and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
Thedigitaloutputisrandomized byapplyinganexclusive-
OR logic operation between D2 and all other data output
bits. To decode, the reverse operation is applied—an ex-
clusive-OR operation is applied between D2 and all other
bits. The D2 and CLKOUT outputs are not affected. The
output randomizer is enabled by serially programming
mode control register A4.
When there is a very small signal at the input of the A/D
thatiscenteredaroundmid-scale,thedigitaloutputstoggle
between mostly 1s and mostly 0s. This simultaneous
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alter-
nate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To first order,
this cancels current flow in the ground plane, reducing
the digital noise.
PC BOARD
CLKOUT
D15
CLKOUT
FPGA
CLKOUT
D15 D2
D14 D2
D15 D2
D15
D14
D14
D14 D2
•
•
•
•
•
•
•
•
•
D3
•
•
•
D3 D2
D2
LTC2259-16
D3 D2
D3
D2
D2
D1
D2
D1 D2
D1 D2
D1
D0
D0
D0 D2
D0 D2
RANDOMIZER
ON
D2
225916 F15
225916 F16
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. De-Randomizing a Randomized
Digital Output Signal
225916f
19
LTC2259-16
APPLICATIONS INFORMATION
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13, D15). The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function can
be on at the same time. When alternate bit polarity mode
is on, the data format is offset binary and the 2’s comple-
ment control bit has no effect. The alternate bit polarity
mode is enabled by serially programming mode control
register A4.
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on V
,
REF
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force most of the
A/D data outputs (D15-D2) to known values. Note that the
two LSBs, D1 and D0, are not controlled in the test pattern
mode and can have unknown values.
All 1s: Outputs are 1111 1111 1111 11XX
All 0s: Outputs are 0000 0000 0000 00XX
DEVICE PROGRAMMING MODES
The operating modes of the LTC2259-16 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Alternating: On alternating samples, the outputs
change from 1111 1111 1111 11XX to 0000 0000
0000 00XX.
Checkerboard: On alternating samples, the outputs
change from 1010 1010 1010 10XX to 0101 0101
0101 01XX.
Parallel Programming Mode
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK and SDI pins are binary logic
DD
inputs that set certain operating modes. These pins can
be tied to V or ground, or driven by 1.8V, 2.5V or 3.3V
DD
CMOS logic. Table 2 shows the modes set by CS, SCK
Output Disable
and SDI.
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
CLKOUT are disabled. The high impedance disabled state
is intended for long periods of inactivity—it is too slow
to multiplex a data bus between multiple converters at
full speed.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
SCK
SDI
Sleep and Nap Modes
1 = Double-Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
225916f
20
LTC2259-16
APPLICATIONS INFORMATION
Serial Programming Mode
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
The SDO pin is an open-drain output that pulls to ground
with a 200ꢀ impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
D5
X
D4
X
D3
X
D2
X
D1
D0
X
PWROFF1
PWROFF0
Bits 7-2
Bits 1-0
Unused, Don’t Care Bits.
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
Power-Down Control Bits
225916f
21
LTC2259-16
APPLICATIONS INFORMATION
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
D5
X
D4
X
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the timing diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the timing diagrams)
+
+
+
–
–
–
01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 1.6× the current set by ILVDS2:ILVDS0.
LVDS Internal Termination Bit
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled and have high output impedance.
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double-Data Rate LVDS Output Mode
10 = Double-Data Rate CMOS Output Mode
11 = Not Used
225916f
22
LTC2259-16
APPLICATIONS INFORMATION
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = Digital Outputs = 0000 0000 0000 00XX
011 = Digital Outputs = 1111 1111 1111 11XX
101 = Checkerboard Output Pattern. D15-D0 alternate between 0101 0101 0101 01XX and 1010 1010 1010 10XX.
111 = Alternating Output Pattern. D15-D0 alternate between 0000 0000 0000 00XX and 1111 1111 1111 11XX.
Note: Other bit combinations are not used. D1 and D0 are not controlled by the digital output test patterns.
Bit 2
Bit 1
Bit 0
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 forces the output format to be offset binary.
GROUNDING AND BYPASSING
The V capacitor should be located as close to the pin
CM
as possible. To make space for this the capacitor on V
REF
The LTC2259-16 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane in the first layer beneath the ADC is
recommended. Layoutfortheprintedcircuitboardshould
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
High quality ceramic bypass capacitors should be used at
HEAT TRANSFER
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
between REFH and REFL can be somewhat further away.
MostoftheheatgeneratedbytheLTC2259-16istransferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electricalandthermalperformance,theexposedpadmust
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
225916f
23
LTC2259-16
TYPICAL APPLICATIONS
LTC2259-16 Schematic
T2
C23
1μF
SENSE
MABAES0060
R9 10Ω
•
•
R39
33.2Ω
1%
ANALOG INPUT
R14
1k
C51
4.7pF
R40
33.2Ω
1%
C17
1μF
R10 10Ω
R15 100Ω
C12
0.1μF
C13
1μF
C19
0.1μF
DIGITAL
OUTPUTS
40
39
38
37
36
35
34
33
32
31
V
SENSE V
V
CM
D1 D0 D15 D14 D13 D12
DD
REF
R27 10Ω
R28 10Ω
1
2
30
29
28
27
26
25
24
23
22
21
+
–
AIN
AIN
D11
D10
+
3
GND
CLKOUT
4
–
REFH
REFH
REFL
REFL
CLKOUT
5
C15
0.1μF
0V
DD
OV
DD
C20
2.2μF
LTC2259-16
C37
0.1μF
6
OGND
7
D9
D8
D7
D6
8
PAR/SER
C21
0.1μF
PAR/SER
9
V
V
DD
DD
10
C18
0.1μF
+
–
DIGITAL
OUTPUTS
GND ENC ENC CS SCK SDI SDO D2 D3 D4 D5
41
11
12
13
14
15
16
17
18
19
20
R13
100Ω
ENCODE CLOCK
225916 TA02
SPI BUS
225916f
24
LTC2259-16
TYPICAL APPLICATIONS
Top Side
Silkscreen Top
225916 TA04
225916 TA03
Inner Layer 2 GND
Inner Layer 3
225916 TA04
225916 TA06
225916f
25
LTC2259-16
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
225916 TA08
225916 TA07
Bottom Side
225916 TA09
225916f
26
LTC2259-16
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.115
TYP
6.00 0.10
(4 SIDES)
R = 0.10
TYP
39 40
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45°
CHAMFER
4.42 0.10
4.50 REF
(4-SIDES)
4.42 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
225916f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2259-16
TYPICAL APPLICATION
T2
C23
1μF
SENSE
MABAES0060
R9 10Ω
•
•
R39
33.2Ω
1%
ANALOG INPUT
R14
1k
C51
4.7pF
R40
33.2Ω
1%
C17
1μF
R10 10Ω
R15 100Ω
C12
0.1μF
C13
1μF
C19
0.1μF
DIGITAL
OUTPUTS
40
39
38
37
36
35
34
33 32
31
V
SENSE V
V
CM
D1 D0 D15 D14 D13 D12
DD
REF
R27 10Ω
R28 10Ω
1
30
29
28
27
26
25
24
23
22
21
+
AIN
D11
2
3
–
AIN
D10
+
GND
CLKOUT
4
–
REFH
REFH
REFL
REFL
CLKOUT
OV
5
C15
0.1μF
0V
DD
DD
C20
2.2μF
LTC2259-16
C37
0.1μF
6
OGND
7
D9
D8
D7
D6
8
PAR/SER
C21
0.1μF
PAR/SER
9
V
V
DD
DD
10
C18
0.1μF
+
–
DIGITAL
OUTPUTS
GND ENC ENC CS SCK SDI SDO D2 D3 D4 D5
41
11
12
13
14
15
16
17
18
19
20
R13
100Ω
ENCODE CLOCK
225916 TA10
SPI BUS
RELATED PARTS
PART NUMBER
LTC1993-2
LTC1994
DESCRIPTION
High Speed Differential Op-Amp/ADC Driver
COMMENTS
800MHz 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
Low Noise, Low Distortion Fully Differential Input/Output
Amplifier/Driver
LTC6406
3GHz, Low Noise, Rail-to-Rail Input Differential Amplifier/Driver Low Noise: 1.6nV/√Hz RTI
LTC2259-14/
LTC2260-14/
LTC2261-14
14-Bit, 80Msps/105Msps/125Msps Ultralow Power 1.8V ADCs
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR
CMOS/CMOS Outputs, 6mm × 6mm QFN Package
LTC2259-12/
LTC2260-12/
LTC2261-12
12-Bit, 80Msps/105Msps/125Msps Ultralow Power 1.8V ADCs
87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR, DDR LVDS/DDR
CMOS/CMOS Outputs, 6mm × 6mm QFN Package
225916f
LT 0310 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC2259IUJ-14#PBF
LTC2259-14 - 14-Bit, 80Msps Ultra-Low Power 1.8V ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
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