LTC2260CUJ-14-TRPBF [Linear]
14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs; 14位,一百○五分之一百二十五/ 80Msps的超低功耗1.8V的ADC型号: | LTC2260CUJ-14-TRPBF |
厂家: | Linear |
描述: | 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs |
文件: | 总32页 (文件大小:461K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2261-14
LTC2260-14/LTC2259-14
14-Bit, 125/105/80Msps
Ultralow Power 1.8V ADCs
FEATURES
DESCRIPTION
The LTC®2261-14/LTC2260-14/LTC2259-14 are sam-
pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performancethatincludes73.4dBSNRand85dBspurious
n
73.4dB SNR
n
85dB SFDR
n
Low Power: 127mW/106mW/89mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS or DDR LVDS Outputs
n
free dynamic range (SFDR). Ultralow jitter of 0.17ps
Selectable Input Ranges: 1V to 2V
RMS
P-P
P-P
n
n
n
n
n
n
n
allows undersampling of IF frequencies with excellent
800MHz Full-Power Bandwidth S/H
noise performance.
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
DC specs include 1LSB INL (typical), 0.3LSB DNL (typi-
cal)andnomissingcodesovertemperature.Thetransition
Serial SPI Port for Configuration
noise is a low 1.2LSB
.
RMS
Pin Compatible 14-Bit and 12-Bit Versions
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n
+
–
Communications
The ENC and ENC inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Cellular Base Stations
n
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
n
n
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 75MHz
1.8V
V
1.2V
0
–10
–20
–30
–40
–50
–60
–70
TO 1.8V
DD
OV
DD
D13
+
14-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
–80
–90
OGND
–100
–110
–120
CLOCK/DUTY
CYCLE
CONTROL
0
20
30
40
50
60
10
226114 TA01a
GND
FREQUENCY (MHz)
125MHz
CLOCK
226114 TA01b
226114f
1
LTC2261-14
LTC2260-14/LTC2259-14
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltages (V , OV )....................... –0.3V to 2V
Digital Output Voltage ................ –0.3V to (OV + 0.3V)
DD
DD
DD
+
–
Analog Input Voltage (A , A
,
Operating Temperature Range:
IN
IN
PAR/SER, SENSE) (Note 3)...........–0.3V to (V + 0.2V)
LTC2261C, LTC2260C, LTC2259C............. 0°C to 70°C
LTC2261I, LTC2260I, LTC2259I............ –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
DD
+
–
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
PIN CONFIGURATIONS
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
40 39 38 37 36 35 34 33 32 31
+
A
A
1
2
30
29
28
D9
IN
A
A
1
2
30
29
28
D8_9
IN
–
–
D8
IN
DNC
IN
+
–
+
–
GND
REFH
3
CLKOUT
GND
REFH
3
CLKOUT
4
27 CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
REFH
5
26 OV
DD
41
41
REFL
6
25
OGND
24 D7
23
REFL
6
25
OGND
REFL
7
REFL
7
24 D6_7
PAR/SER
8
D6
22 D5
21
PAR/SER
8
23
22
21
DNC
D4_5
DNC
V
DD
9
V
DD
9
V
10
D4
DD
V
DD
10
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
T
= 150°C, θ = 32°C/W
JA
JMAX
T
= 150°C, θ = 32°C/W
JMAX JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
+
–
+
–
A
A
1
2
30
29
28
D8_9
D8_9
IN
IN
+
–
GND
REFH
3
CLKOUT
4
27 CLKOUT
REFH
5
26 OV
DD
41
REFL
6
25
OGND
+
REFL
7
24 D6_7
–
+
–
PAR/SER
8
23
D6_7
22 D4_5
21
V
DD
9
V
DD
10
D4_5
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
T
JMAX
= 150°C, θ = 32°C/W
JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226114f
2
LTC2261-14
LTC2260-14/LTC2259-14
ORDER INFORMATION
LEAD FREE FINISH
LTC2261CUJ-14#PBF
LTC2261IUJ-14#PBF
LTC2260CUJ-14#PBF
LTC2260IUJ-14#PBF
LTC2259CUJ-14#PBF
LTC2259IUJ-14#PBF
TAPE AND REEL
PART MARKING*
LTC2261UJ-14
LTC2261UJ-14
LTC2260UJ-14
LTC2260UJ-14
LTC2259UJ-14
LTC2259UJ-14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2261CUJ-14#TRPBF
LTC2261IUJ-14#TRPBF
LTC2260CUJ-14#TRPBF
LTC2260IUJ-14#TRPBF
LTC2259CUJ-14#TRPBF
LTC2259IUJ-14#TRPBF
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2261-14
TYP
LTC2260-14
TYP
LTC2259-14
TYP MAX
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
14
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
14
14
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–3.75
–0.9
–9
1
3.75 –3.75
1
3.75
0.9
9
–3.5
–0.9
–9
1
3.5
0.9
9
LSB
LSB
mV
0.3
1.5
0.9
9
–0.9
–9
0.3
1.5
0.3
1.5
Gain Error
Internal Reference
External Reference
1.5
0.4
1.5
0.4
1.5
0.4
%FS
%FS
l
–1.5
1.5
–1.5
1.5
–1.5
1.5
Offset Drift
20
20
20
μV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
30
10
30
10
ppm/°C
ppm/°C
Transition Noise
External Reference
1.2
1.2
1.2
LSB
RMS
226114f
3
LTC2261-14
LTC2260-14/LTC2259-14
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
1.7V < V < 1.9V
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)
V
– 100mV
0.625
V
CM
V
+ 100mV
1.300
V
IN(CM)
SENSE
INCM
IN
IN
CM
CM
External Voltage Reference Applied to SENSE External Reference Mode
1.250
V
I
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
μA
μA
μA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current
0 < A , A < V , No Encode
–1
–3
–6
1
3
6
μA
μA
μA
ns
IN1
IN
IN
DD
DD
PAR/SER Input Leakage Current
SENSE Input Leakage Current
0 < PAR/SER < V
IN2
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
0
AP
0.17
80
ps
RMS
JITTER
CMRR
BW-3B
dB
Figure 6 Test Circuit
800
MHz
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2261-14
TYP
LTC2260-14
TYP
LTC2259-14
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
SNR
Signal-to-Noise Ratio
5MHz Input
73.4
73.2
72.7
73.4
73.2
72.7
73.1
72.9
72.4
dB
dB
dB
l
l
l
l
70MHz Input
140MHz Input
71.3
71.3
70.9
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
88
85
82
88
85
82
88
85
82
dB
dB
dB
70MHz Input
140MHz Input
76
85
76
83
79
85
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
90
90
90
90
90
90
90
90
90
dB
dB
dB
70MHz Input
140MHz Input
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
73
72.6
72
73
72.6
72
72.9
72.6
72
dB
dB
dB
70.2
70.2
70.4
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600μA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400μA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
226114f
4
LTC2261-14
LTC2260-14/LTC2259-14
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
(Note 8)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
3.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
0.6
3.6
DD
+
ENC to GND
(See Figure 11)
(Note 8)
V
R
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK)
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
IH
IL
DD
DD
IN
= 1.8V
0.6
10
I
= 0V to 3.6V
–10
μA
pF
IN
C
Input Capacitance
(Note 8)
3
200
4
IN
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
DD
= 1.8V, SDO = 0V
Ω
μA
pF
OL
l
I
OH
SDO = 0V to 3.6V
(Note 8)
–10
10
C
OUT
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV = 1.8V
DD
l
l
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.750
1.790
0.010
V
V
OH
OL
O
I = 500μA
O
0.050
OV = 1.5V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.488
0.010
V
V
O
I = 500μA
O
OV = 1.2V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –500μA
1.185
0.010
V
V
O
I = 500μA
O
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
350
175
454
mV
mV
OD
V
OS
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.250
1.250
1.375
V
V
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
226114f
5
LTC2261-14
LTC2260-14/LTC2259-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2261-14
TYP
LTC2260-14
TYP
LTC2259-14
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
CMOS Output Modes: Full Data Rate and Double Data Rate
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
1.7
1.1
1.8
1.9
1.9
1.7
1.1
1.8
1.9
1.9
1.7
1.1
1.8
1.9
1.9
V
V
DD
OV
DD
I
DC Input
Sine Wave Input
70.5
71.8
83.2
58.6
59.8
69.1
49.2 58.1
50.2
mA
mA
VDD
I
Digital Supply Current
Power Dissipation
Sine Wave Input, OV =1.2V
3.9
3.3
2.5
mA
OVDD
DD
l
P
DC Input
127
134
150
106
112
125
89
93
105
mW
mW
DISS
Sine Wave Input, OV =1.2V
DD
LVDS Output Mode
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(Note 10)
1.7
1.7
1.8
1.9
1.9
89
1.7
1.7
1.8
1.9
1.9
1.7
1.7
1.8
1.9
1.9
V
V
DD
OV
(Note 10)
DD
I
I
Sine Wave Input
75.4
63.4
74.8
53.8 63.5
20.7 26
40.5 47.8
mA
VDD
OVDD
l
l
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
20.7
40.5
26
47.8
20.7
40.5
26
47.8
mA
mA
(0V = 1.8V)
DD
l
l
P
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
173
209
207
246
151
187
182
221
134
170
161
201
mW
mW
DISS
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
0.5
9
0.5
9
0.5
9
mW
mW
mW
SLEEP
NAP
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
10
10
DIFFCLK
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2261-14
TYP
LTC2260-14
TYP
LTC2259-14
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
TYP MAX UNITS
l
f
t
Sampling Frequency
(Note 10)
1
125
1
105
1
80
MHz
S
L
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
H
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
AP
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
Cycles
226114f
6
LTC2261-14
LTC2260-14/LTC2259-14
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.8
1.5
0.3
5.5
3.2
2.7
0.6
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
ns
SKEW
D
C
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 20pF, R
= 2k
= 2k
250
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
125
SDO
PULLUP
+
–
termination disabled, differential ENC /ENC = 2V sine wave, input
P-P
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
range = 2V with differential drive, unless otherwise noted.
P-P
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
DD
of greater than 100mA below GND or above V without latchup.
DD
Note 8: Guaranteed by design, not subject to test.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 9: V = 1.8V, f
or 80MHz (LTC2259), ENC = single-ended 1.8V square wave, ENC = 0V,
= 125MHz (LTC2261), 105MHz (LTC2260),
DD
SAMPLE
+
–
DD
input range = 2V with differential drive, 5pF load on each digital output
P-P
unless otherwise noted.
Note 5: V = OV = 1.8V, f
105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal
= 125MHz (LTC2261),
DD
DD
SAMPLE
Note 10: Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D13, OF
t
C
+
CLKOUT
–
CLKOUT
226114 TD01
226114f
7
LTC2261-14
LTC2260-14/LTC2259-14
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
D0_1
D0
D1
D0
D1
D0
D1
D0
N-2
D1
N-2
N-5
N-5
N-4
N-4
N-3
N-3
•
•
•
D12_13
OF
D12
D13
D12
OF
D13
D12
D13
D12
D13
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
OF
OF
OF
N-2
N-5
N-4
N-3
t
t
C
C
+
CLKOUT
–
CLKOUT
226114 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
+
D0_1
D0
D1
D0
D1
N-4
D0
N-3
D1
D0
D1
N-2
N-5
N-5
N-4
N-3
N-2
–
D0_1
•
•
•
+
D12_13
D12
D13
D12
D13
D12
D13
D12
D13
N-2
N-5
N-5
N-4
N-4
N-3
N-3
N-2
–
D12_13
+
OF
OF
OF
OF
OF
N-3
N-5
N-4
N-3
–
OF
t
C
t
C
+
CLKOUT
–
CLKOUT
226114 TD03
226114f
8
LTC2261-14
LTC2260-14/LTC2259-14
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
t
t
t
t
t
H
S
DS
DH
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
226114 TD04
HIGH IMPEDANCE
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: Integral
Non-Linearity (INL)
LTC2261-14: Differential
Non-Linearity (DNL)
LTC2261-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
2.0
1.5
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
0
8192
12288
16384
0
10
20
30
40
50
60
4096
4096
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
226114 G01
226114 G02
226114 G03
226114f
9
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
LTC2261-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 125Msps
LTC2261-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
60
0
20
30
40
50
60
10
10
0
20
30
40
50
60
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226114 G05
226114 G06
226114 G04
LTC2261-14: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTC2261-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
LTC2261-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
30
40
50
60
8178
8182
8184
8186
10
8180
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
FREQUENCY (MHz)
OUTPUT CODE
226114 G07
226114 G08
226114 G09
LTC2261-14: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTC2261-14: SFDR vs Input Level,
LTC2261-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
f
IN = 70MHz, 2V Range, 125Msps
80
75
70
65
95
90
85
80
75
70
65
110
100
90
dBFS
80
LVDS OUTPUTS
CMOS OUTPUTS
70
dBc
60
50
40
30
20
10
0
60
55
50
0
25
50
75
100
125
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
50
–70
SAMPLE RATE (Msps)
226114 G13
226114 G10
226114 G12
226114f
10
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: IOVDD vs Sample
LTC2261-14: 128k Point Averaged FFT,
fIN = 70MHz, –65dBFS, 125Msps,
RAND OFF, ABP OFF
LTC2261-14: SNR vs SENSE,
IN = 5MHz, –1dB
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
f
45
40
35
30
25
20
15
0
–10
–20
74
73
72
71
70
69
3.5mA LVDS
–30
–40
–50
–60
–70
1.75mA LVDS
–80
–90
68
67
66
–100
–110
–120
–130
10
5
1.8V CMOS
1.2V CMOS
100 125
0
0
25
50
75
0
20
30
40
50
60
10
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
FREQUENCY (MHz)
SENSE PIN (V)
226114 G14
226114 G16
226114 G15
LTC2261-14: 128k Point Averaged FFT,
fIN = 70MHz, –65dBFS, 125Msps,
RAND ON, ABP ON
LTC2261-14: SNR vs Sample Rate
and Digital Output Mode, 30MHz Sine
Wave Input, –1dB
LTC2260-14: Integral Non-Linearity
(INL)
74
2.0
1.5
0
–10
–20
–30
–40
LVDS
CMOS
1.0
72
70
68
66
DDR CMOS
0.5
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
–0.5
–1.0
–1.5
–2.0
0
50
75
100
125
0
8192
12288
16384
25
4096
0
20
30
40
50
60
10
SAMPLE RATE (Msps)
OUTPUT CODE
FREQUENCY (MHz)
226114 G18
226114 G21
226114 G17
LTC2260-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
LTC2260-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
LTC2260-14: Differential
Non-Linearity (DNL)
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
0
20
30
40
50
0
8192
12288
16384
0
20
30
40
50
10
4096
10
FREQUENCY (MHz)
OUTPUT CODE
FREQUENCY (MHz)
226114 G24
226114 G22
226114 G23
226114f
11
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2260-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
LTC2260-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
LTC2260-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
0
20
30
40
50
0
20
30
40
50
10
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226114 G27
226114 G25
226114 G26
LTC2260-14: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2260-14: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2260-14: Shorted Input
Histogram
95
90
85
80
75
70
65
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
2000
1000
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
8195
8199
OUTPUT CODE
8201
8203
0
50 100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
8197
226114 G30
226114 G28
226114 G29
LTC2260-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2260-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
LTC2260-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
100
90
65
60
55
50
45
40
35
30
25
20
15
dBFS
3.5mA LVDS
LVDS OUTPUTS
CMOS OUTPUTS
80
70
dBc
60
1.75mA LVDS
50
40
30
20
10
0
10
5
45
40
1.8V CMOS
1.2V CMOS
0
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
0
25
50
75
100
0
25
50
75
100
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
226114 G32
226114 G33
226114 G34
226114f
12
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2260-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2259-14: Integral Non-Linearity
(INL)
LTC2259-14: Differential
Non-Linearity (DNL)
1.0
0.8
0.6
74
73
72
71
70
69
2.0
1.5
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
68
67
66
0
8192
12288
16384
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
8192
12288
16384
4096
4096
OUTPUT CODE
SENSE PIN (V)
OUTPUT CODE
226114 G42
226114 G35
226114 G41
LTC2259-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
LTC2259-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 80Msps
LTC2259-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
0
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
0
20
30
40
0
20
30
40
10
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226114 G44
226114 G45
226114 G43
LTC2259-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2259-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
LTC2259-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
2000
1000
0
0
20
30
40
10
0
20
30
40
10
8184
8188
8190
8192
8186
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
226114 G46
226114 G47
226114 G48
226114f
13
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-14: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2259-14: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2259-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
95
90
85
80
75
70
65
110
100
90
74
73
72
71
70
dBFS
80
70
dBc
60
50
40
30
20
10
0
69
68
67
66
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
226114 G50
226114 G52
226114 G49
LTC2259-14: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
LTC2259-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2259-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
55
50
45
45
40
35
30
25
20
15
74
3.5mA LVDS
73
72
71
70
69
LVDS OUTPUTS
CMOS OUTPUTS
1.75mA LVDS
40
35
68
67
66
10
5
1.2V CMOS
1.8V CMOS
0
0
20
40
60
80
0
20
40
60
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
226114 G53
226114 G54
226114 G55
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
+
A
A
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
IN
IN
PAR/SER(Pin8):ProgrammingModeSelectionPin.Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
–
GND (Pin 3): ADC Power Ground.
the A/D operating modes. Connect to V to enable the
DD
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
226114f
14
LTC2261-14
LTC2260-14/LTC2259-14
PIN FUNCTIONS
operating modes. PAR/SER should be connected directly
OGND (Pin 25): Output Driver Ground.
to ground or the V of the part and not be driven by a
DD
OV (Pin 26): Output Driver Supply. Bypass to ground
DD
logic signal.
with a 0.1μF ceramic capacitor.
V
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
DD
V
(Pin 37): Common Mode Bias Output, Nominally
CM
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
Equal to V /2. V should be used to bias the common
DD
CM
can share a bypass capacitor.
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
+
ENC (Pin 11): Encode Input. Conversion starts on the
rising edge.
V
(Pin38):ReferenceVoltageOutput.Bypasstoground
REF
–
ENC (Pin 12): Encode Complement Input. Conversion
with a 1μF ceramic capacitor, nominally 1.25V.
starts on the falling edge.
SENSE(Pin39):ReferenceProgrammingPin.Connecting
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
SENSEtoV selectstheinternalreferenceanda 1Vinput
DD
range. Connecting SENSE to ground selects the internal
reference and a 0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
mode (PAR/SER = V ), CS controls the clock duty cycle
DD
input range of 0.8 • V
.
SENSE
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
FULL-RATE CMOS OUTPUT MODE
SCK (Pin 14): In serial programming mode, (PAR/SER =
All Pins Below Have CMOS Output Levels (OGND to
0V), SCK is the serial interface clock input. In the parallel
OV )
DD
programming mode (PAR/SER = V ), SCK controls the
DD
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
–
+
CLKOUT (Pin 27): Inverted version of CLKOUT .
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
normally transition at the same time as the falling edge
+
+
of CLKOUT . The phase of CLKOUT can also be delayed
relative to the digital outputs by programming the mode
control registers.
V ), SDI can be used to power down the part. When SDI
DD
DNC (Pin 35): Do not connect this pin.
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessaryandSDOcanbeleftunconnected.Intheparallel
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV )
DD
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double
DataRateDigitalOutputs.Twodatabitsaremultiplexedonto
eachoutputpin. Theevendatabits(D0, D2, D4, D6, D8, D10,
programming mode (PAR/SER = V ), SDO is not used
DD
and should not be connected.
226114f
15
LTC2261-14
LTC2260-14/LTC2259-14
PIN FUNCTIONS
D12) appear when CLKOUT is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT is high.
+
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
+
–
+
–
+
–
+
CLKOUT (Pin 27): Inverted version of CLKOUT .
D0_1 /D0_1 to D12_13 /D12_13 (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
+
CLKOUT (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
+
+
ing edges of CLKOUT . The phase of CLKOUT can also
be delayed relative to the digital outputs by programming
the mode control registers.
+
D6, D8, D10, D12) appear when CLKOUT is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
+
CLKOUT is high.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
–
+
CLKOUT /CLKOUT (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
+
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
as the falling and rising edges of CLKOUT . The phase of
+
CLKOUT canalsobedelayedrelativetothedigitaloutputs
by programming the mode control registers.
–
+
+
DOUBLE DATA RATE LVDS OUTPUT MODE
OF /OF (Pins35/36):Over/UnderFlowDigitalOutput.OF
is high when an overflow or underflow has occurred.
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
FUNCTIONAL BLOCK DIAGRAM
+
A
IN
V
DD
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
–
A
IN
GND
V
CM
V
DD
/2
0.1μF
V
REF
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
1μF
RANGE
SELECT
REFH
REFL INTERNAL CLOCK SIGNALS
REF
BUF
OV
OF
DD
SENSE
D13
•
•
•
DIFF
CLOCK/DUTY
CYCLE
CONTROL
MODE
OUTPUT
DRIVERS
REF
CONTROL
AMP
REGISTERS
D0
+
–
CLKOUT
CLKOUT
226114 F01
REFH
REFL
0.1μF
2.2μF
OGND
+
–
PAR/SER
SCK SDI
SDO
ENC
ENC
CS
0.1μF
0.1μF
Figure 1. Functional Block Diagram
226114f
16
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
inputs should swing from V – 0.5V to V + 0.5V. There
CM CM
should be 180° phase difference between the inputs.
The LTC2261-14/LTC2260-14/LTC2259-14 are low power
14-bit125Msps/105Msps/80MspsA/Dconvertersthatare
poweredbyasingle1.8Vsupply. Theanaloginputsshould
be driven differentially. The encode input can be driven
differentially, or single ended for lower power consump-
tion. The digital outputs can be CMOS, double data rate
CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.)
Many additional features can be chosen by programming
the mode control registers through a serial SPI port. See
the Serial Programming Mode section.
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
showsanexampleofaninputRCfilter. TheRCcomponent
values should be chosen based on the application’s input
frequency.
ANALOG INPUT
Transformer Coupled Circuits
The analog input is a differential CMOS sample-and-hold
circuit(Figure2).Theinputsshouldbedrivendifferentially
around a common mode voltage set by the V output
pin, which is nominally V /2. For the 2V input range, the
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
CM
tap is biased with V , setting the A/D input at its optimal
CM
DD
50Ω
V
CM
0.1μF
LTC2261-14
0.1μF
T1
1:1
V
DD
+
25Ω
A
C
C
IN
ANALOG
INPUT
SAMPLE
3.5pF
R
ON
LTC2261-14
10Ω
10ꢀ
25Ω
0.1μF
25Ω
25Ω
+
–
A
A
IN
12pF
C
PARASITIC
1.8pF
V
DD
–
25Ω
A
IN
SAMPLE
3.5pF
R
25Ω
ON
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226114 F03
IN
C
1.8pF
PARASITIC
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to
V
DD
1.2V
10k
+
–
ENC
ENC
10k
1.2V
226114 F02
Figure 2. Equivalent Input Circuit
226114f
17
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
blockissingle-ended,thenatransformercircuit(Figures 4
to 6) should convert the signal to differential before driv-
ing the A/D.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speeddifferentialamplifier.TheoutputoftheamplifierisAC
coupledtotheA/Dsotheamplifier’soutputcommonmode
voltage can be optimally set to minimize distortion.
50Ω
V
CM
0.1μF
0.1μF
0.1μF
+
A
ANALOG
INPUT
IN
T2
LTC2261-14
T1
0.1μF
25Ω
25Ω
1.8pF
50Ω
–
V
CM
A
IN
0.1μF
226114 F05
0.1μF
0.1μF
+
A
ANALOG
INPUT
IN
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
LTC2261-14
T1
0.1μF
25Ω
25Ω
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
4.7pF
–
A
IN
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 170MHz to 270MHz
226114 F04
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
50Ω
V
CM
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 70MHz to 170MHz
0.1μF
0.1μF
0.1μF
2.7nH
0.1μF
+
–
A
A
IN
IN
ANALOG
INPUT
LTC2261-14
25Ω
25Ω
T1
2.7nH
T1: MA/COM ETC1-1-13
226114 F06
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 6. Recommended Front-End Circuit for
Input Frequencies Above 270MHz
226114f
18
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Reference
The V , REFH and REFL pins should be bypassed as
REF
shown in Figure 8. The 0.1μF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the back side of the circuit board).
The LTC2261-14/2260-14/2259-14 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to V . For a 1V input range
DD
using the external reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9.)
LTC2261-14
5Ω
V
REF
1.25V BANDGAP
REFERENCE
1.25V
1μF
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
0.625V
will then be 1.6 • V
.
SENSE
RANGE
DETECT
AND
CONTROL
TIE TO V FOR 2V RANGE;
DD
TIE TO GND FOR 1V RANGE;
SENSE
V
CM
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.65V < V
< 1.300V
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
SENSE
0.1μF
200Ω 200Ω
INTERNAL ADC
HIGH REFERENCE
0.1μF
0.1μF
+
–
0.1μF
25Ω
A
IN
REFH
0.1μF
LTC2261-14
ANALOG
INPUT
+
+
12pF
2.2μF
–
–
0.8x
DIFF AMP
25Ω
A
IN
0.1μF
226114 F07
REFL
Figure 7. Front-End Circuit Using a High
Speed Differential Amplifier
INTERNAL ADC
LOW REFERENCE
226114 F08
Figure 8. Reference Circuit
V
REF
1μF
LTC2261-14
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
226114 F09
Figure 9. Using an External 1.25V Reference
226114f
19
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Encode Input
The single-ended encode mode should be used with CMOS
–
encode inputs. To select this mode, ENC is connected
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
+
to ground and ENC is driven with a square wave encode
+
input. ENC can be taken above V (up to 3.6V) so 1.8V
DD
+
to3.3VCMOSlogiclevelscanbeused.TheENC threshold
+
is0.9V. ForgoodjitterperformanceENC should have fast
rise and fall times.
Clock Duty Cycle Stabilizer
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
For good performance the encode signal should have a
50%( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
above V (up to 3.6V), and the common mode range
DD
is from 1.1V to 1.6V. In the differential encode mode,
–
ENC should stay at least 200mV above ground to avoid
falselytriggeringthesingle-endedencodemode.Forgood
+
–
jitter performance ENC and ENC should have fast rise
and fall times.
0.1μF
LTC2261-14
+
25Ω
V
ENC
DD
T1
1:4
DIFFERENTIAL
COMPARATOR
100Ω
D1
V
DD
LTC2261-14
100Ω
–
ENC
15k
30k
+
–
0.1μF
ENC
ENC
226114 F12
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
226114 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1μF
+
ENC
PECL OR
LTC2261-14
+
LTC2261-14
LVDS
CLOCK
0.1μF
1.8V TO 3.3V
0V
ENC
ENC
–
ENC
–
30k
CMOS LOGIC
BUFFER
226114 F13
226114 F11
Figure 13. PECL or LVDS Encode Drive
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
226114f
20
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
thedutycyclestabilizerisdisabled,careshouldbetakento
makethesamplingclockhavea50%( 5%)dutycycle.The
duty cycle stabilizer should not be used below 5Msps.
When using Double Data Rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100MHz.
Double Data Rate LVDS Mode
DIGITAL OUTPUTS
In double data rate LVDS mode, two data bits are mul-
tiplexed and output on each differential output pair.
+
–
Digital Output Modes
There are 7 LVDS output pairs (D0_1 /D0_1 through
+
–
–
D12_13 /D12_13 ) for the digital output data. Overflow
The LTC2261-14/LTC2260-14/LTC2259-14 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode). Note that double data rate CMOS cannot be selected
in the parallel programming mode.
+
+
–
(OF /OF )andthedataoutputclock(CLKOUT /CLKOUT )
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100ꢀ differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Full-Rate CMOS Mode
The outputs are powered by OV and OGND which are
DD
In full-rate CMOS mode the 14 digital outputs (D0-D13),
isolated from the A/D core power and ground. In LVDS
+
overflow (OF), and the data output clocks (CLKOUT ,
mode, OV must be 1.8V.
DD
–
CLKOUT ) have CMOS output levels. The outputs are
powered by OV and OGND which are isolated from the
DD
Programmable LVDS Output Current
A/D core power and ground. OV can range from 1.1V to
DD
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Optional LVDS Driver Internal Termination
Double Data Rate CMOS Mode
In most cases using just an external 100ꢀ termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100ꢀ termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
In double data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 7 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9,D10_11,D12_13),overflow(OF),andthedataoutput
+
–
clocks (CLKOUT , CLKOUT ) have CMOS output levels.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground. OV can
DD
range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS
logic outputs.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
data bits.
226114f
21
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
DATA FORMAT
In full-rate CMOS mode the data output bits normally
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
+
change at the same time as the falling edge of CLKOUT ,
+
so the rising edge of CLKOUT can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
thefallingandrisingedgesofCLKOUT . Toallowadequate
Table 1. Output Codes vs Input Voltage
+
setup-and-hold time when latching the data, the CLKOUT
+
–
A
IN
– A
D13-D0
D13-D0
IN
(2V Range)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
OF (OFFSET BINARY)
(2’s COMPLEMENT)
signal may need to be phase shifted relative to the data
outputbits.MostFPGAshavethisfeature;thisisgenerally
the best place to adjust the timing.
1
0
0
0
0
0
0
0
0
1
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
The LTC2261-14/LTC2260-14/LTC2259-14 can also phase
+
–
shift the CLKOUT /CLKOUT signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
+
–
CLKOUT and CLKOUT , independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
+
ENC
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1 CLKPHASE0
0°
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
135°
180°
225°
270°
315°
+
CLKOUT
226114 F14
Figure 14. Phase Shifting CLKOUT
226114f
22
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Digital Output Randomizer
Alternate Bit Polarity
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
Anotherfeaturethatreducesdigitalfeedbackonthecircuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is “randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is ap-
plied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
When there is a very small signal at the input of the A/D
thatiscenteredaroundmidscale,thedigitaloutputstoggle
between mostly 1s and mostly 0s. This simultaneous
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alter-
nate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To first order,
this cancels current flow in the ground plane, reducing
the digital noise.
CLKOUT
CLKOUT
OF
PC BOARD
OF
FPGA
CLKOUT
D13
D13/D0
D12/D0
OF
D12
D2
D13/D0
D13
D12
•
•
•
D12/D0
D2/D0
D1/D0
LTC2261-14
•
•
•
RANDOMIZER
ON
D2/D0
D1/D0
D1
D2
D1
D0
D0
D0
116114 F15
D0
Figure 15. Functional Equivalent of Digital Output Randomizer
116114 F16
Figure 16. Unrandomizing a Randomized Digital
Output Signal
226114f
23
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either, both or neither function can be on at the
sametime.Whenalternatebitpolaritymodeison,thedata
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
DEVICE PROGRAMMING MODES
The operating modes of the LTC2261-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK and SDI pins are binary logic
DD
inputs that set certain operating modes. These pins can
Output Disable
be tied to V or ground, or driven by 1.8V, 2.5V or 3.3V
DD
CMOS logic. Table 2 shows the modes set by CS, SCK
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehighimpedancedisabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
Sleep and Nap Modes
SCK
SDI
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
depends on the size of the bypass capacitors on V
,
REF
226114f
24
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
Serial Programming Mode
The SDO pin is an open-drain output that pulls to ground
with a 200ꢀ impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Table 3 shows a map of the mode control registers.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible af ter the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
D5
X
D4
X
D3
X
D2
X
D1
D0
X
PWROFF1
PWROFF0
Bits 7-2
Bits 1-0
Unused, Don’t Care Bits.
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
Power Down Control Bits
226114f
25
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
D5
X
D4
X
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
+
+
+
–
–
–
01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
LVDS Internal Termination Bit
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
226114f
26
LTC2261-14
LTC2260-14/LTC2259-14
APPLICATIONS INFORMATION
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 101 0101 1010 0101 and 010 1010 0101 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 000 0000 0000 0000 and 111 1111 1111 1111
Note: Other Bit Combinations are not Used
Bit 2
Bit 1
Bit 0
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 Forces the Output Format to be Offset Binary
GROUNDING AND BYPASSING
The V capacitor should be located as close to the pin
CM
as possible. To make space for this the capacitor on V
REF
The LTC2261-14 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
High quality ceramic bypass capacitors should be used at
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
HEAT TRANSFER
capacitors must be located as close to the pins as possible.
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
between REFH and REFL can be somewhat further away.
MostoftheheatgeneratedbytheLTC2261-14istransferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electricalandthermalperformance,theexposedpadmust
be soldered to a large grounded pad on the PC board.
226114f
27
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL APPLICATIONS
LTC2261 Schematic
T2
MABAES0060
R9 10Ω
SENSE
•
•
C23
1μF
R39
ANALOG INPUT
33.2Ω
1%
R14
1k
C51
4.7pF
R40
33.2Ω
1%
C17
1μF
R10 10Ω
R16
100Ω
R15 100Ω
C12
0.1μF
C13
1μF
C19
0.1μF
DIGITAL
OUTPUTS
40
39
38
37
36
+
35
–
34
33
32
31
V
SENSE V
V
CM
OF
OF D13 D12 D11 D10
DD
REF
R27 10Ω
R28 10Ω
1
2
30
29
28
27
26
25
24
23
22
21
+
–
AIN
AIN
D9
D8
+
3
GND
CLKOUT
4
–
REFH
REFH
REFL
REFL
CLKOUT
U2
LTC2261CUJ
5
C15
0.1μF
0V
DD
OV
DD
C20
2.2μF
C37
0.1μF
6
OGND
7
D7
D6
D5
D4
8
PAR/SER
C21
0.1μF
PAR/SER
9
V
V
DD
DD
10
C18
0.1μF
+
–
GND ENC ENC CS SCK SDI SDO D0 D1 D2 D3
DIGITAL
OUTPUTS
41
11
12
13
14
15
16
17
18
19
20
R13
100Ω
ENCODE CLOCK
226114 TA02
SPI BUS
226114f
28
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL APPLICATIONS
Top Side
Silkscreen Top
226114 TA04
226114 TA03
Inner Layer 2 GND
Inner Layer 3
226114 TA04
226114 TA06
226114f
29
LTC2261-14
LTC2260-14/LTC2259-14
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
226114 TA08
226114 TA07
Bottom Side
226114 TA09
226114f
30
LTC2261-14
LTC2260-14/LTC2259-14
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.115
TYP
6.00 0.10
(4 SIDES)
R = 0.10
TYP
39 40
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45°
CHAMFER
4.42 0.10
4.50 REF
(4-SIDES)
4.42 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
226114f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
31
LTC2261-14
LTC2260-14/LTC2259-14
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1993-2
LTC1994
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
LTC2215
LTC2216
LTC2217
LTC2202
LTC2203
LTC2204
LTC2205
LTC2206
LTC2207
LTC2208
LTC2209
LTC2220
LTC2220-1
LTC2224
LTC2249
LTC2250
LTC2251
LTC2252
LTC2253
LTC2254
LTC2255
16-Bit, 65Msps, Low Noise ADC
16-Bit, 80Msps, Low Noise ADC
16-Bit, 105Msps, Low Noise ADC
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
16-Bit, 25Msps, 3.3V ADC, Lowest Noise
16-Bit, 40Msps, 3.3V ADC
700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN
970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN
1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN
140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
230mW, 73dB SNR, 5mm × 5mm QFN Package
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
16-Bit, 65Msps, 3.3V ADC
16-Bit, 80Msps, 3.3V ADC
16-Bit, 105Msps, 3.3V ADC
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
16-Bit, 160Msps, 3.3V ADC, LVDS Outputs
12-Bit, 170Msps ADC
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
14-Bit, 80Msps ADC
10-Bit, 105Msps ADC
10-Bit, 125Msps ADC
12-Bit, 105Msps ADC
12-Bit, 125Msps ADC
14-Bit, 105Msps ADC
14-Bit, 125Msps, 3V ADC, Lowest Power
LTC2259-12/
LTC2260-12/
LTC2261-12
12-Bit, 80/105/125Msps 1.8V ADCs, Ultralow
Power
87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, 6mm × 6mm QFN Package
LTC2284
LTC2299
LTC5517
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
Dual 14-Bit, 80Msps ADC
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5527
LTC5557
LTC5575
LTC6400-20
400MHz to 3.7GHz High Linearity Downconverting
Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
400MHz to 3.8GHz High Linearity Downconverting
Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB,
3.3V Supply Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
Integrated RF and LO Transformer
1.8GHz Low Noise, Low Distortion Differential ADC Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
Driver for 300MHz IF
LTC6604-2.5/
LTC6604 -5/
LTC6604-10/
LTC6604-15
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
with ADC Driver
Distortion Amplifiers
226114f
LT 1208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTC2260IUJ-12#TRPBF
LTC2260-12 - 12-Bit, 105Msps Ultralow Power 1.8V ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC2260IUJ-14#PBF
LTC2260-14 - 14-Bit, 105Msps Ultra-Low Power 1.8V ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
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