LTC2267CUJ-12TRPBF [Linear]
12-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs; 12位，125Msps / 105MSPS / 80Msps的低功耗双通道ADC
| 型号： | LTC2267CUJ-12TRPBF |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs |
| 文件： | 总32页 (文件大小：1053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2268-12/
LTC2267-12/LTC2266-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
FEATURES
DESCRIPTION
TheLTC®2268-12/LTC2267-12/LTC2266-12are2-channel,
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
n
2-Channel Simultaneous Sampling ADC
n
70.6dB SNR
n
88dB SFDR
n
Low Power: 292mW/2ꢀ8mW/200mW Total,
146mW/119mW/100mW per Channel
n
Single 1.8V Supply
n
Serial LVDS Outputs: 1 or 2 Bits per Channel
of0.15ps
allowsundersamplingofIFfrequencieswith
RMS
n
Selectable Input Ranges: 1V to 2V
excellent noise performance.
P-P
P-P
n
n
n
n
n
800MHz Full Power Bandwidth S/H
DC specs include 0.ꢀLSB INL (typ), 0.1LSB DNL (typ)
and no missing codes over temperature. The transition
Shutdown and Nap Modes
Serial SPI Port for Configuration
noise is a low 0.ꢀLSB
.
RMS
Pin Compatible 14-Bit and 12-Bit Versions
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
LTC2268-12, 125Msps,
1.8V
V
1.8V
OV
2-Tone FFT, fIN = 70MHz and 75MHz
DD
DD
0
–10
–20
–30
–40
CH.1
ANALOG
INPUT
OUT1A
OUT1B
12-BIT
S/H
S/H
ADC CORE
SERIALIZED
DATA
SERIALIZER
OUT2A
OUT2B
CH.2
ANALOG
INPUT
–50
–60
–70
12-BIT
ADC CORE
LVDS
OUTPUTS
DATA
CLOCK
OUT
–80
–90
ENCODE
INPUT
PLL
FRAME
–100
–110
–120
GND
OGND
0
20
30
40
50
60
10
FREQUENCY (MHz)
226812 TA01
226812 TA01b
22687612f
1
LTC2268-12/
LTC2267-12/LTC2266-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages
V , OV ................................................ –0.ꢀV to 2V
DD
DD
+
–
Analog Input Voltage (A , A
,
IN
IN
40 ꢀ9 ꢀ8 ꢀ7 ꢀ6 ꢀ5 ꢀ4 ꢀꢀ ꢀ2 ꢀ1
+
PAR/SER, SENSE) (Note ꢀ).............–0.ꢀV to (V +0.2V)
DD
+
–
A
A
1
2
ꢀ0
29
28
OUT1B
+
–
IN1
IN1
Digital Input Voltage (ENC , ENC , CS,
–
OUT1B
SDI, SCK) (Note 4).................................... –0.ꢀV to ꢀ.9V
SDO (Note 4) ............................................ –0.ꢀV to ꢀ.9V
+
V
ꢀ
DCO
CM1
–
REFH
REFH
REFL
REFL
4
27 DCO
26 OV
Digital Output Voltage .................. –0.ꢀV to (OV +0.ꢀV)
Operating Temperature Range
LTC2268C, 2267C, 2266C........................ 0°C to 70°C
LTC2268I, 2267I, 2266I ....................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
5
41
GND
DD
DD
6
25 OGND
+
7
24 FR
–
V
8
2ꢀ
FR
CM2
+
+
–
A
9
22 OUT2A
21
IN2
–
A
10
OUT2A
IN2
11 12 1ꢀ 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 150°C, θ = ꢀ2°C/W
JMAX
JA
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2268CUJ-12#PBF
LTC2268IUJ-12#PBF
LTC2267CUJ-12#PBF
LTC2267IUJ-12#PBF
LTC2266CUJ-12#PBF
LTC2266IUJ-12#PBF
TAPE AND REEL
LTC2268CUJ-12#TRPBF LTC2268UJ-12
LTC2268IUJ-12#TRPBF LTC2268UJ-12
LTC2267CUJ-12#TRPBF LTC2267UJ-12
LTC2267IUJ-12#TRPBF LTC2267UJ-12
LTC2266CUJ-12#TRPBF LTC2266UJ-12
LTC2266IUJ-12#TRPBF LTC2266UJ-12
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
22687612f
2
LTC2268-12/
LTC2267-12/LTC2266-12
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2268-12
TYP
LTC2267-12
TYP
LTC2266-12
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
l
l
Resolution
12
12
12
Bits
(No Missing Codes)
Integral Linearity Error
Differential Analog Input
(Note 6)
–1
0.ꢀ
1
–1
0.ꢀ
1
–1
0.ꢀ
1
LSB
l
l
Differential Linearity Error
Offset Error
Differential Analog Input
(Note 7)
–0.5
–12
0.1
ꢀ
0.5
12
–0.4
–12
0.1
ꢀ
0.4
12
–0.4
–12
0.1
ꢀ
0.4
12
LSB
mV
Gain Error
Internal Reference
External Reference
–0.9
–0.9
–0.9
–0.9
–0.9
–0.9
%FS
%FS
l
–2.4
0.6
–2.4
0.6
–2.4
0.6
Offset Drift
20
20
20
μV/°C
Full-Scale Drift
Internal Reference
External Reference
ꢀ0
10
ꢀ0
10
ꢀ0
10
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
External Reference
0.2
ꢀ
0.2
ꢀ
0.2
ꢀ
%FS
mV
External Reference
0.ꢀ
0.ꢀ
0.ꢀ
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
l
l
l
l
V
V
V
Analog Input Range (A – A
)
1.7V < V < 1.9V
1 to 2
V
P–P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A – A )/2
Differential Analog Input (Note 8)
V – 100mV
CM
0.625
V
CM
V
CM
+100mV
1.ꢀ
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE External Reference Mode
1.25
V
I
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
1ꢀ0
100
μA
μA
μA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A , A < V
–1
–ꢀ
–6
1
ꢀ
6
μA
μA
μA
ns
IN1
IN
IN
DD
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.625 < SENSE < 1.ꢀV
INꢀ
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
0
AP
0.15
80
ps
RMS
JITTER
CMRR
BW-ꢀB
dB
Figure 6 Test Circuit
800
MHz
22687612f
3
LTC2268-12/
LTC2267-12/LTC2266-12
DIGITAL ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2268-12
LTC2267-12
LTC2266-12
TYP MAX
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN
TYP MAX MIN
UNITS
SNR
Signal-to-Noise Ratio
5MHz Input
70.6
70.6
69.2 70.5
70.ꢀ
70.6
69.4 70.5
70.ꢀ
dBFS
dBFS
dBFS
l
l
l
l
70MHz Input
140MHz Input
69.6 70.6
70.ꢀ
SFDR
Spurious Free Dynamic Range
5MHz Input
70MHz Input
140MHz Input
88
85
82
88
88
dBFS
dBFS
dBFS
nd
rd
2
or ꢀ Harmonic
75
84
69
76
82
85
82
76
84
69
85
82
Spurious Free Dynamic Range
5MHz Input
70MHz Input
140MHz Input
90
90
90
90
90
90
90
90
90
dBFS
dBFS
dBFS
th
4
Harmonic or Higher
S/(N+D) Signal-to-Noise Plus Distortion 5MHz Input
70.6
70.4
70
70.6
68.8 70.4
70
70.4
70.ꢀ
69.9
dBFS
dBFS
dBFS
Ratio
70MHz Input
140MHz Input
Crosstalk
10MHz Input
–105
–105
–105
dBc
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
±25
4
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.V + 25mV
0.5 • V – 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600μA < I
< 1mA
< 1mA
OUT
I
= 0
1.225
1.25
±25
7
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400μA < I
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
DIFFERENTIAL ENCODE MODE (ENC NOT TIED TO GND)
l
V
Differential Input Voltage
(Note 8)
0.2
V
ID
V
Common Mode Input Voltage
Internally Set
1.2
V
V
ICM
l
l
Externally Set (Note 8)
1.1
0.2
1.6
ꢀ.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
ꢀ.5
–
SINGLE-ENDED ENCODE MODE (ENC TIED TO GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
=1.8V
=1.8V
1.2
0
V
IH
IL
IN
DD
DD
V
0.6
ꢀ.6
V
V
+
ENC to GND
R
(See Figure 11)
ꢀ0
kΩ
IN
IN
C
Input Capacitance
ꢀ.5
pF
22687612f
4
LTC2268-12/
LTC2267-12/LTC2266-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
=1.8V
1.ꢀ
V
V
IH
IL
DD
DD
IN
l
l
V
=1.8V
0.6
10
I
IN
= 0V to ꢀ.6V
–10
μA
pF
C
Input Capacitance
ꢀ
200
ꢀ
IN
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
DD
=1.8V, SDO = 0V
Ω
μA
pF
OL
l
I
OH
SDO = 0V to ꢀ.6V
–10
10
C
OUT
DIGITAL DATA OUTPUTS
l
l
V
OD
Differential Output Voltage
100Ω Differential Load, ꢀ.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
125
ꢀ50
175
454
250
mV
mV
l
l
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, ꢀ.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.125
1.25
1.25
1.ꢀ75
1.ꢀ75
V
V
OS
R
Termination Enabled, OV =1.8V
100
Ω
TERM
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2268-12
TYP MAX MIN
LTC2267-12
TYP MAX MIN
LTC2266-12
TYP MAX
SYMBOL PARAMETER
CONDITIONS
MIN
1.7
UNITS
l
l
l
V
DD
Analog Supply Voltage (Note 10)
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
96
1.9
1.9
V
V
OV
Output Supply Voltage (Note 10)
1.7
DD
I
I
Analog Supply Current Sine Wave Input
146
165
116
129
109
mA
VDD
OVDD
l
l
Digital Supply Current 2-Lane Mode, 1.75mA Mode
2-Lane Mode, ꢀ.5mA Mode
16
ꢀ0
20
ꢀ4
16
29
19
ꢀꢀ
15
29
18
ꢀ2
mA
mA
l
l
P
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, ꢀ.5mA Mode
292
ꢀ17
ꢀꢀꢀ
ꢀ58
2ꢀ8
261
266
292
200
225
229
254
mW
mW
DISS
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
70
20
70
20
70
20
NAP
Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
DIFFCLK
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2268-12
LTC2267-12
TYP MAX MIN
LTC2266-12
TYP MAX
SYMBOL PARAMETER
CONDITIONS
MIN
TYP MAX MIN
UNITS
l
f
t
Sampling Frequency
(Notes 10, 11)
5
125
5
105
5
80
MHz
S
l
l
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
ꢀ.8
2
4
4
100
100
4.52 4.76
4.76
100
100
5.9ꢀ 6.25
2
100
100
ns
ns
ENCL
2
6.25
l
l
t
Analog Supply Current
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
ꢀ.8
2
4
4
100
100
4.52 4.76
100
100
5.9ꢀ 6.25
100
100
ns
ns
ENCH
AP
2
4.76
2
6.25
t
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
22687612f
5
LTC2268-12/
LTC2267-12/LTC2266-12
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
= 100Ω Differential, C = 2pF to GND on Each Output)
MIN
TYP
MAX
UNITS
DIGITAL DATA OUTPUTS (R
TERM
L
t
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 • f )
s
SER
S
1/(7 • f )
S
1/(6 • f )
S
1/(16 • f )
S
1/(14 • f )
S
1/(12 • f )
S
l
l
l
t
t
t
t
t
FR to DCO Delay
DATA to DCO Delay
Propagation Delay
Output Rise Time
Output Fall Time
(Note 8)
0.ꢀ5 • t
0.ꢀ5 • t
0.5 • t
0.5 • t
0.65 • t
0.65 • t
s
s
FRAME
DATA
PD
SER
SER
SER
SER
SER
(Note 8)
SER
(Note 8)
0.7n + 2 • t
1.1n + 2 • t
1.5n + 2 • t
SER
s
SER
SER
Data, DCO, FR, 20% to 80%
Data, DCO, FR, 20% to 80%
0.17
0.17
60
ns
ns
R
F
DCO Cycle-Cycle Jitter
Pipeline Latency
t
= 1ns
ps
P-P
SER
6
Cycles
SPI PORT TIMING (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 2k
= 2k
250
SDO
PULLUP
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK falling to SDO Valid
Readback Mode, C
= 20pF, R
125
SDO
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V
,
DD
Note 8: Guaranteed by design, not subject to test.
they will be clamped by internal diodes. This product can handle input
Note 9: V = OV = 1.8V, f
(LTC2267), or 80MHz (LTC2266), 2-lane output mode, ENC = single-
ended 1.8V square wave, ENC = 0V, input range = 2V with differential
= 125MHz (LTC2268), 105MHz
DD
DD
SAMPLE
+
currents of greater than 100mA below GND or above V without latchup.
DD
–
Note 4: When these pin voltages are taken below GND they will be
P-P
clamped by internal diodes. When these pin voltages are taken above
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
V
DD
they will not be clamped by internal diodes. This product can handle
input currents of greater than 100mA below GND without latchup.
Note 10: Recommended operating conditions.
Note 5: V = OV = 1.8V, f = 125MHz (LTC2268), 105MHz
DD
DD
SAMPLE
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
+
(LTC2267), or 80MHz (LTC2266), 2-lane output mode, differential ENC /
–
ENC = 2V sine wave, input range = 2V with differential drive, unless
P-P
P-P
data rate is 1000Mbps so t
must be greater than or equal to 1ns.
SER
otherwise noted.
22687612f
6
LTC2268-12/
LTC2267-12/LTC2266-12
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
Dꢀ
D1
D0
D *
0
0
D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D *
0
D11 D9
D10 D8
D7
X
X
+
OUT#A
–
OUT#B
D2
D *
Y
D10 D8
D *
Y
0
D6
+
OUT#B
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
226812 TD01
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
t
AP
ANALOG
INPUT
N + 2
N + 1
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D5
D4
Dꢀ
D2
D1
D0
D * D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D11 D9
D7
D6
X
X
X
+
OUT#A
–
OUT#B
D * D10 D8
Y
D * D10 D8
Y
D * D10 D8
Y
+
OUT#B
SAMPLE N-6
SAMPLE N-5
–
SAMPLE N-4
–
SAMPLE N-ꢀ
226812 TD02
+
+
NOTE THAT IN THIS MODE, FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
22687612f
7
LTC2268-12/
LTC2267-12/LTC2266-12
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
+
FR
–
FR
t
PD
t
SER
–
OUT#A
D7
D6
D5
D4
Dꢀ
D2
D1 D11 D9
D7
D6
D5
Dꢀ
D2
D1 D11 D9
D7
D6
+
OUT#A
–
OUT#B
D0 D10 D8
SAMPLE N-5
D4
D0 D10 D8
SAMPLE N-4
+
OUT#B
SAMPLE N-6
226812 TD0ꢀ
1-Lane Output Mode, 16-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D * D *
0
0
D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D *
0
0
D11 D10 D9
SAMPLE N-4
D8
X
Y
X
Y
+
OUT#A
SAMPLE N-6
–
226812 TD04
+
OUT#B , OUT#B ARE DISABLED
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
22687612f
8
LTC2268-12/
LTC2267-12/LTC2266-12
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D1
D0
D * D * D11 D10 D9
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D * D11 D10 D9
D8
X
Y
X
Y
+
OUT#A
SAMPLE N-6
–
SAMPLE N-5
SAMPLE N-4
226812 TD05
+
OUT#B , OUT#B ARE DISABLED
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
Dꢀ
D2
D1
D0 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0 D11 D10 D9
+
OUT#A
SAMPLE N-6
–
SAMPLE N-4
+
226812 TD06
OUT#B , OUT#B ARE DISABLED
22687612f
9
LTC2268-12/
LTC2267-12/LTC2266-12
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
t
t
DS
t
DH
t
t
H
S
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
Aꢀ
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
Dꢀ
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
Aꢀ
A2
A1
A0
D7
D6
D5
D4
Dꢀ
D2
D1
D0
R/W
SDO
226812 TD07
HIGH IMPEDANCE
22687612f
10
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2268-12: Integral
Nonlinearity (INL)
LTC2268-12: Differential
Nonlinearity (DNL)
LTC2268-12: 8k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
1.0
0.8
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
0.6
0.4
0.4
0.2
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–80
–90
–100
–110
–120
–0.8
–1.0
0
2048
3072
4096
0
2048
3072
4096
1024
1024
0
20
30
40
50
60
10
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
226812 G01
226812 G02
226812 G03
LTC2268-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
LTC2268-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
LTC2268-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
60
0
20
30
40
50
60
0
20
30
40
50
60
10
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226812 G04
226812 G05
226812 G06
LTC2268-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
LTC2268-12: SNR vs Input
LTC2268-12: Shorted Input
Histogram
Frequency, –1dBFS, 2V Range,
125Msps
18000
16000
14000
12000
10000
8000
0
–10
–20
–30
–40
–50
–60
–70
72
71
70
69
68
67
66
6000
4000
2000
0
–80
–90
–100
–110
–120
2041
2042
2043
2044
2045
0
20
30
40
50
60
10
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
OUTPUT CODE
FREQUENCY (MHz)
226812 G08
226812 G07
226812 G09
22687612f
11
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2268-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
125Msps
LTC2268-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTC2268-12: SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
95
90
85
80
75
70
65
80
70
60
50
40
30
20
10
0
110
100
90
dBFS
dBFS
80
dBc
70
dBc
60
50
40
30
20
10
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
–60
–50
–40
–30
–20
–10
0
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
INPUT LEVEL (dBFS)
226812 G10
226812 G50
226812 G12
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dBFS, 5pF on Each
Data Output
LTC2268-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2268-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
72
71
70
69
68
67
66
30
20
10
0
160
150
140
130
120
110
100
2-LANE, 3.5mA
1-LANE, 3.5mA
2-LANE, 1.75mA
1-LANE, 1.75mA
0
25
50
75
100
125
0.6 0.7 0.8 0.9
1
1.1 1.2 1.ꢀ
0
25
50
75
100
125
SAMPLE RATE (Msps)
SENSE PIN (V)
SAMPLE RATE (Msps)
226812 G51
226812 G15
226812 G53
LTC2267-12: Integral
Nonlinearity (INL)
LTC2267-12: Differential
Nonlinearity (DNL)
LTC2267-12: 8k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
0
–10
–20
–ꢀ0
–40
–50
–60
–70
1.0
0.8
0.6
1.0
0.8
0.6
0.4
0.2
0
0.4
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–90
–100
–110
–120
–0.4
–0.6
–0.8
–1.0
0
20
ꢀ0
40
50
0
2048
ꢀ072
4096
10
1024
0
2048
3072
4096
1024
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
226812 G2ꢀ
22687612f
226812 G22
226812 G21
12
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2267-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
LTC2267-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
LTC2267-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
0
–10
–20
–ꢀ0
–40
–50
–60
–70
0
–10
–20
–ꢀ0
–40
–50
–60
–70
0
–10
–20
–ꢀ0
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
ꢀ0
40
50
0
20
ꢀ0
40
50
10
0
20
ꢀ0
40
50
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226812 G24
226812 G26
226812 G25
LTC2267-12: 8k Point 2-Tone FFT,
IN = 70MHz, 75MHz, –1dBFS,
105Msps
LTC2267-12: SNR vs Input
f
LTC2267-12: Shorted Input
Histogram
Frequency, –1dBFS, 2V Range,
105Msps
0
–10
–20
–ꢀ0
–40
–50
–60
–70
18000
16000
14000
12000
72
71
70
69
68
67
10000
8000
6000
4000
2000
0
–80
–90
–100
–110
–120
66
0
20
ꢀ0
40
50
2044
2045
2046
2047
2048
10
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
FREQUENCY (MHz)
OUTPUT CODE
226812 G27
226812 G28
226812 G49
LTC2267-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
105Msps
LTC2267-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
LTC2267-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
95
90
85
80
75
70
65
110
100
90
130
120
110
100
dBFS
80
70
dBc
60
50
40
30
20
10
0
90
80
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
50
–70
0
25
50
75
100
SAMPLE RATE (Msps)
226812 G30
226812 G32
226812 G54
22687612f
13
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2267-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2266-12: Integral
Nonlinearity (INL)
LTC2266-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
72
1.0
0.8
0.6
0.4
0.2
0
71
70
69
68
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
67
66
0
2048
3072
4096
1024
0.6 0.7 0.8 0.9
1
1.1 1.2 1.ꢀ
0
2048
3072
4096
1024
OUTPUT CODE
SENSE PIN (V)
OUTPUT CODE
226812 G42
226812 Gꢀ5
226812 G41
LTC2266-12: 8k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
LTC2266-12: 8k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
LTC2266-12: 8k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
10
0
20
30
40
0
20
30
40
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
226812 G43
226812 G44
226812 G45
LTC2266-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2266-12: 8k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
LTC2266-12:
Shorted Input Histogram
18000
16000
14000
12000
10000
8000
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
6000
4000
2000
0
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
2052
2053
2054
2055
2056
0
20
30
40
0
20
30
40
10
10
OUTPUT CODE
FREQUENCY (MHz)
FREQUENCY (MHz)
226812 G48
226812 G46
226812 G47
22687612f
14
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2266-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
80Msps
LTC2266-12: SFDR vs Input
LTC2266-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
Frequency, –1dBFS, 2V Range,
80Msps
72
71
70
69
68
67
95
90
85
80
75
70
65
110
100
90
dBFS
80
70
dBc
60
50
40
30
20
10
0
66
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
50
226812 G35a
226812 G52
226812 G49
LTC2266-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2266-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
DCO Cycle-Cycle Jitter vs Serial
Data Rate
350
300
250
200
150
110
100
90
72
71
70
69
68
67
66
100
50
0
80
70
0
20
40
60
80
0
200
400
600
800
1000
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.ꢀ
SENSE PIN (V)
SAMPLE RATE (Msps)
SERIAL DATA RATE (Mbps)
226812 G55a
226812 G52a
226812 G55
22687612f
15
LTC2268-12/
LTC2267-12/LTC2266-12
PIN FUNCTIONS
+
A
(Pin 1): Channel 1 Positive Differential Analog
SCK (Pin 16): In serial programming mode, (PAR/SER =
IN1
Input.
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER= V ), SCK selects ꢀ.5mA
–
DD
A
(Pin 2): Channel 1 Negative Differential Analog
IN1
or 1.75mA LVDS output currents. SCK can be driven with
Input.
1.8V to ꢀ.ꢀV logic.
V
(Pin3):CommonModeBiasOutput,NominallyEqual
CM1
SDI (Pin 17): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
to V /2. V should be used to bias the common mode
DD
CM
of the analog inputs of channel 1. Bypass to ground with
a 0.1μF ceramic capacitor.
REFH (Pins 4,5): ADC High Reference. Bypass to pins 6, 7
with a 2.2μF ceramic capacitor and to ground with a 0.1μF
ceramic capacitor.
V ), SDI can be used to power down the part. SDI can
DD
be driven with 1.8V to ꢀ.ꢀV logic.
GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
REFL (Pins 6,7): ADC Low Reference. Bypass to pins 4, 5
with a 2.2μF ceramic capacitor and to ground with a 0.1μF
ceramic capacitor.
OGND (Pin 25): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
V
(Pin8):CommonModeBiasOutput,NominallyEqual
CM2
to V /2. V should be used to bias the common mode
DD
CM
of the analog inputs of channel 2. Bypass to ground with
a 0.1μF ceramic capacitor.
OV (Pin 26): Output Driver Supply, 1.7V to 1.9V. Bypass
DD
to ground with a 0.1μF ceramic capacitor.
+
A
(Pin 9): Channel 2 Positive Differential Analog
(Pin 10): Channel 2 Negative Differential Analog
IN2
SDO (Pin 34): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V – ꢀ.ꢀV. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessaryandSDOcanbeleftunconnected.Intheparallel
Input.
–
A
IN2
Input.
V
(Pins 11, 12, 39, 40): Analog Power Supply, 1.7V
DD
to 1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
+
ENC (Pin 13): Encode Input. Conversion starts on the
programmingmode(PAR/SER=V ),SDOisaninputthat
DD
rising edge.
enables internal 100Ω termination resistors on the digital
outputs. When used as an input, SDO can be driven with
1.8V to ꢀ.ꢀV logic through a 1k series resistor.
–
ENC (Pin 14): Encode Complement Input. Conversion
starts on the falling edge.
PAR/SER (Pin 35): Programming Mode Selection Pin.
Connecttogroundtoenabletheserialprogrammingmode.
CS, SCK, SDI, SDO become a serial interface that control
CS(Pin15):Inserialprogrammingmode,(PAR/SER=0V),
CS is the serial interface chip select input. When CS is low,
SCKisenabledforshiftingdataonSDIintothemodecontrol
registers. In the parallel programming mode (PAR/SER =
the A/D operating modes. Connect to V to enable the
DD
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
V ), CS selects 2-lane or 1-lane output mode. CS can
DD
be driven with 1.8V to ꢀ.ꢀV logic.
22687612f
16
LTC2268-12/
LTC2267-12/LTC2266-12
PIN FUNCTIONS
the A/D operating modes. PAR/SER should be connected
LVDS Outputs
directly to ground or the V of the part and not be driven
DD
All pins below are differential LVDS outputs. The output
current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
by a logic signal.
V
(Pin36):ReferenceVoltageOutput.Bypasstoground
REF
with a 1μF ceramic capacitor, nominally 1.25V.
–
+
–
+
SENSE(Pin38):ReferenceProgrammingPin.Connecting
OUT2B /OUT2B , OUT2A /OUT2A (Pins 19/20,
SENSEtoV selectstheinternalreferenceanda±1Vinput
Pins 21/22): Serial Data Outputs for Channel 2. In 1-lane
output mode only OUT2A /OUT2A are used.
DD
–
+
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.ꢀV applied to SENSE selects an
–
+
FR /FR (Pins 23/24): Frame Start Outputs.
–
+
DCO /DCO (Pins 27/28): Data Clock Outputs.
input range of ±0.8 • V
.
SENSE
–
+
–
+
OUT1B /OUT1B , OUT1A /OUT1A (Pins 29/30,
Pins 31/32): Serial Data Outputs for Channel 1. In 1-lane
–
+
output mode only OUT1A /OUT1A are used.
22687612f
17
LTC2268-12/
LTC2267-12/LTC2266-12
BLOCK DIAGRAM
1.8V
1.8V
+
–
OV
DD
V
ENC
ENC
DD
+
–
OUT1A
OUT1A
PLL
CHANNEL 1
ANALOG INPUT
+
+
OUT1B
–
12-BIT
ADC CORE
OUT1B
SAMPLE-
AND-HOLD
CHANNEL 1
ANALOG INPUT
–
+
OUT2A
–
OUT2A
CHANNEL 2
DATA
SERIALIZER
+
–
ANALOG INPUT
+
–
OUT2B
OUT2B
12-BIT
ADC CORE
SAMPLE-
AND-HOLD
CHANNEL 2
ANALOG INPUT
DATA
+
CLOCK OUT
DATA
V
REF
–
1.25V
REFERENCE
CLOCK OUT
1μF
+
FRAME
RANGE
SELECT
–
FRAME
OGND
REFH
REFL
REF
BUF
SENSE
V
DD
/2
DIFF
REF
AMP
MODE
CONTROL
REGISTERS
REFH
0.1μF
REFL
VCM1
VCM2
PAR/SER
CS
SCK SDI
SDO
GND
226812 F01
0.1μF
0.1μF
2.2μF
0.1μF
0.1μF
Figure 1. Functional Block Diagram
22687612f
18
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits(Figure2).Theinputsshouldbedrivendifferentially
The LTC2268-12/LTC2267-12/LTC2266-12 are low power,
2-channel, 12-bit, 125Msps/105Msps/80Msps A/D con-
verters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially for optimal jitter perfor-
mance, or single ended for lower power consumption.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
perchanneloption(1-lanemode).Manyadditionalfeatures
canbechosenbyprogrammingthemodecontrolregisters
through a serial SPI port.
around a common mode voltage set by the V
or V
CM1
CM2
output pins, which are nominally V /2. For the 2V input
DD
range, the inputs should swing from V – 0.5V to V
CM
CM
+ 0.5V. There should be 180° phase difference between
the inputs.
Thetwochannelsaresimultaneouslysampledbyashared
encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input filtering
LTC2268-12
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure ꢀ
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
V
DD
C
C
SAMPLE
ꢀ.5pF
R
ON
10Ω
10ꢁ
25Ω
+
–
A
A
IN
C
PARASITIC
1.8pF
V
DD
SAMPLE
ꢀ.5pF
R
25Ω
ON
IN
C
PARASITIC
1.8pF
V
DD
50Ω
V
CM
0.1μF
0.1μF
T1
1:1
1.2V
+
25Ω
A
IN
ANALOG
INPUT
10k
LTC2268-12
0.1μF
25Ω
25Ω
+
–
ENC
12pF
–
ENC
25Ω
A
IN
10k
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226812 F0ꢀ
1.2V
226812 F02
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
Figure 2. Equivalent Input Circuit. Only One
of the Two Analog Channels Is Shown
22687612f
19
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
Transformer Coupled Circuits
Amplifier Circuits
Figure ꢀ shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distor-
tion.
tap is biased with V , setting the A/D input at its optimal
CM
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
At very high frequencies an RF gain block will often
have lower distortion than a differential amplifier. If the
gain block is single-ended, then a transformer circuit
(Figures 4 to 6) should convert the signal to differential
before driving the A/D.
50Ω
V
CM
0.1μF
0.1μF
0.1μF
+
A
ANALOG
INPUT
IN
T2
LTC2268-12
T1
0.1μF
25Ω
25Ω
50Ω
V
CM
4.7pF
0.1μF
–
A
IN
0.1μF
0.1μF
2.7nH
0.1μF
+
–
A
A
IN
IN
ANALOG
INPUT
226812 F04
LTC2268-12
25Ω
25Ω
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1
2.7nH
T1: MA/COM ETC1-1-1ꢀ
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226812 F06
Figure 4.Recommended Front End Circuit for Input
Frequencies from 70MHz to 170MHz
Figure 6. Recommended Front End Circuit for Input
Frequencies Above 300MHz
50Ω
V
CM
0.1μF
0.1μF
0.1μF
+
V
CM
A
ANALOG
INPUT
IN
T2
LTC2268-12
T1
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1μF
0.1μF
25Ω
25Ω
200Ω 200Ω
25Ω
0.1μF
0.1μF
1.8pF
+
–
A
IN
–
LTC2268-12
A
ANALOG
INPUT
IN
+
+
12pF
226812 F05
–
–
25Ω
A
IN
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
226812 F07
Figure 7. Front End Circuit Using a High Speed
Differential Amplifier
Figure 5. Recommended Front End Circuit for Input
Frequencies from 170MHz to 300MHz
22687612f
20
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
Reference
The reference is shared by both ADC channels, so it is
not possible to independently adjust the input range of
individual channels.
TheLTC2268-12/LTC2267-12/LTC2266-12hasaninternal
1.25V voltage reference. For a 2V input range using the
The V , REFH and REFL pins should be bypassed as
internal reference, connect SENSE to V . For a 1V input
REF
DD
shown in Figure 8. The 0.1μF capacitor between REFH
and REFL should be as close to the pins as possible (not
on the backside of the circuit board).
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.ꢀ0V. The input range
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should be
treated as analog signals — do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
will then be 1.6 • V
.
SENSE
LTC2268-12
5Ω
V
REF
1.25V BANDGAP
REFERENCE
1.25V
1μF
0.625V
RANGE
DETECT
AND
LTC2268-12
V
DD
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
DIFFERENTIAL
COMPARATOR
RANGE = 1.6 • V
FOR
SENSE
V
DD
BUFFER
0.625V < V
< 1.ꢀ00V
SENSE
INTERNAL ADC
HIGH REFERENCE
0.1μF
15k
ꢀ0k
REFH
0.1μF
+
–
ENC
ENC
2.2μF
0.8x
DIFF AMP
0.1μF
REFL
226812 F10
INTERNAL ADC
LOW REFERENCE
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
226812 F08
Figure 8. Reference Circuit
LTC2268-12
+
1.8V TO ꢀ.ꢀV
0V
ENC
ENC
V
REF
–
ꢀ0k
1μF
CMOS LOGIC
BUFFER
LTC2268-12
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
226812 F11
226812 F09
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
Figure 9. Using an External 1.25V Reference
22687612f
21
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 1ꢀ).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be
Clock PLL and Duty Cycle Stabilizer
Theencodeclockismultipliedbyaninternalphase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25μs to lock onto the input clock.
taken above V (up to ꢀ.6V), and the common mode
DD
range is from 1.1V to 1.6V. In the differential encode
–
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from ꢀ0% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
mode, ENC should stay at least 200mV above ground to
avoid falsely triggering the single-ended encode mode.
+
For good jitter performance ENC should have fast rise
and fall times.
Thesingle-endedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected
+
to ground and ENC is driven with a square wave encode
+
DIGITAL OUTPUTS
input. ENC can be taken above V (up to ꢀ.6V) so 1.8V
DD
+
toꢀ.ꢀVCMOSlogiclevelscanbeused.TheENC threshold
The digital outputs of the LTC2268-12/LTC2267-12/
LTC2266-12 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode). At lower sam-
pling rates there is a one bit per channel option (1-lane
mode). The data can be serialized with 16-, 14-, or 12-bit
serialization (see Timing Diagrams for details).
+
is 0.9V. For good jitter performance ENC should have fast
rise and fall times.
0.1μF
0.1μF
+
T1
ENC
LTC2268-12
50ꢁ
50ꢁ
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversionresultbegins. Inthe2-lane, 14-bitserialization
mode, the frequency of the FR output is halved.
100ꢁ
–
0.1μF
ENC
226812 F12
T1 = MA/COM ETC1-1-1ꢀ
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
Figure 12. Sinusoidal Encode Drive
0.1μF
+
ENC
PECL OR
LTC2268-12
LVDS
CLOCK
0.1μF
–
ENC
226812 F1ꢀ
Figure 13. PECL or LVDS Encode Drive
22687612f
22
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2268-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2267-12) or 80MHz (LTC2266-12).
MAXIMUM SAMPLING
SERIALIZATION MODE
2-Lane
FREQUENCY, f (MHz)
DCO FREQUENCY
4 • f
FR FREQUENCY
SERIAL DATA RATE
S
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
125
125
125
62.5
71.4
8ꢀ.ꢀ
f
8 • f
7 • f
6 • f
S
S
S
S
S
2-Lane
ꢀ.5 • f
0.5 • f
S
S
2-Lane
ꢀ • f
8 • f
7 • f
6 • f
f
f
f
f
S
S
S
S
S
1-Lane
16 • f
14 • f
12 • f
S
S
S
S
S
S
1-Lane
1-Lane
By default the outputs are standard LVDS levels: ꢀ.5mA
output current and a 1.25V output common mode volt-
age. An external 100ꢁ differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
The outputs are powered by OV and OGND which are
DD
In addition to the 12 data bits (D11 - D0), two additional
bits (DX and DY) are sent out in the 14-bit and 16-bit
serialization modes. These extra bits are to ensure com-
plete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, DX and DY are always logic 0.
When the analog inputs are overranged positive, DX and
DYbecomelogic1.Whentheanaloginputsareoverranged
negative, DX and DY become logic 0. DX and DY can also
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is ꢀ.5mA. This current
can be adjusted by control register A2 in the serial pro-
gramming mode. Available current levels are 1.75mA,
2.1mA, 2.5mA, ꢀmA, ꢀ.5mA, 4mA and 4.5mA. In the
parallel programming mode the SCK pin can select either
ꢀ.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
Table 2. Output Codes vs Input Voltage
In most cases using just an external 100ꢁ termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100ꢁ termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
In the Parallel Programming Mode, the SDO pin enables
internal termination. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current
modes.
+
–
A
– A
D11-D0
D11-D0
IN
IN
(2V RANGE)
>+1.000000V
+0.999512V
+0.999024V
+0.000488V
0.000000V
(OFFSET BINARY)
(2’s COMPLEMENT)
D , D
X
Y
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
11
00
00
00
00
00
00
00
00
00
–0.000488V
–0.000976V
–0.999512V
–1.000000V
≤–1.000000V
22687612f
23
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
Digital Output Randomizer
In nap mode any combination of A/D channels can be
powereddownwhiletheinternalreferencecircuitsandthe
PLL stay active, allowing faster wake-up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50μs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2268-12/LTC2267-12/
LTC2266-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
Parallel Programming Mode
(D11-D0, D , D ) of both channels to known values. The
X
Y
To use the parallel programming mode, PAR/SER should
digitaloutputtestpatternsareenabledbyseriallyprogram-
ming mode control registers Aꢀ and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
can be tied to V or ground, or driven by 1.8V, 2.5V, or
DD
ꢀ.ꢀV CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table ꢀ shows the
modes set by CS, SCK, SDI and SDO.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
powerorenablein-circuittesting.Whendisabledthecom-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
2-Lane/1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
LVDS Current Selection Bit
0 = ꢀ.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Power Down Control Bit
SCK
SDI
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
0 = Normal Operation
1 = Sleep Mode
SDO
Internal 100Ω Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
depends on the size of the bypass capacitors on V
,
REF
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
22687612f
24
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
Serial Programming Mode
will be read back on the SDO pin (see the Timing Diagrams
section). During a read back command the register is not
updated and data on SDI is ignored.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that programs the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
The SDO pin is an open-drain output that pulls to ground
with a 200ꢁ impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serialdataisonlywrittenandreadbackisnotneeded, then
SDO can be left floating and no pull-up resistor is needed.
Table 4 shows a map of the mode control registers.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written
to the register set by the address bits (A6:A0). If the R/W bit
is high, data in the register set by the address bits (A6:A0)
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
Dꢀ
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode.
This Bit Is Automatically Set Back to Zero After the Reset Is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
Dꢀ
D2
X
D1
X
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
NAP_1
Bit 7
Bit 6
Bit 5
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Two’s Complement Mode Control Bit
Bits 4,ꢀ,0
SLEEP:NAP_2:NAP_1
000 = Normal Operation
Sleep/Nap Mode Control Bits
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
Bits 2,1
Unused, Don’t Care Bits.
22687612f
25
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
Dꢀ
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = ꢀ.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = ꢀ.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Bit ꢀ
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
X
D5
D4
Dꢀ
D2
D1
D0
OUTTEST
TP11
TP10
TP9
TP8
TP7
TP6
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bits 5-0
TP11:TP6
Test Pattern Data Bits (MSB)
TP11:TP6 Set the Test Pattern for Data Bit 11 (MSB) Through Data Bit 6.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
Dꢀ
D2
D1
D0
TP5
TP4
TPꢀ
TP2
TP1
TP0
TPX
TPY
Bits 7-2
TP5:TP0
Test Pattern Data Bits (LSB)
TP5:TP0 Set the Test Pattern for Data Bit 5 Through Data Bit 0 (LSB).
Bits 1-0
TPX:TPY
Set the Test Pattern for Extra Bits D and D . These Bits are for Compatibility with the 14-Bit Version of the A/D.
X Y
22687612f
26
LTC2268-12/
LTC2267-12/LTC2266-12
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
between REFH and REFL can be somewhat further away.
Thetracesconnectingthepinsandbypasscapacitorsmust
be kept short and should be made as wide as possible.
The LTC2268-12/LTC2267-12/LTC2266-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
High quality ceramic bypass capacitors should be used at
MostoftheheatgeneratedbytheLTC2268-12/LTC2267-12/
LTC2266-12 is transferred from the die through the
bottom-side Exposed Pad and package leads onto the
printed circuit board. For good electrical and thermal
performance, theExposedPadmustbesolderedtoalarge
grounded pad on the PC board. This pad should be con-
nected to the internal ground planes by an array of vias.
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
22687612f
27
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
Inner Layer 2 GND
Inner Layer 3
22687612f
28
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
Bottom Side
Silkscreen Bottom
22687612f
29
LTC2268-12/
LTC2267-12/LTC2266-12
TYPICAL APPLICATIONS
LTC2268 Schematic
PAR/SER
C4
1μF
SDO
SENSE
V
DD
C5
1μF
40 ꢀ9 ꢀ8 ꢀ7 ꢀ6 ꢀ5 ꢀ4 ꢀꢀ ꢀ2 ꢀ1
A
A
IN1
IN1
DIGITAL
OUTPUTS
1
2
ꢀ0
29
28
27
26
25
24
2ꢀ
22
21
+
–
+
–
+
–
C29
OUT1B
A
A
V
IN1
IN1
0.1μF
OUT1B
DCO
DCO
OV
ꢀ
CM1
4
REFH
REFH
REFL
REFL
5
LTC2268
OV
DD
DD
C1
2.2μF
Cꢀ0
0.1μF
6
C16
0.1μF
C2
0.1μF
OGND
7
+
FR
8
–
Cꢀ
0.1μF
FR
V
A
A
CM2
9
+
+
C59
0.1μF
OUT2A
IN2
10
–
–
OUT2A
IN2
A
A
IN2
IN2
DIGITAL
OUTPUTS
11 12 1ꢀ 14 15 16 17 18 19 20
V
DD
C7
0.1μF
SPI BUS
C47
0.1μF
C46
0.1μF
226812 TA02
ENCODE
CLOCK
ENCODE
CLOCK
22687612f
30
LTC2268-12/
LTC2267-12/LTC2266-12
PACKAGE DESCRIPTION
UJ Package
40-Lead (6mm × 6mm) Plastic QFN
(Reference LTC DWG # 05-08-1728)
0.70 p 0.05
6.50 p 0.05
5.10 p 0.05
4.42 p 0.05
4.50 p 0.05
(4 SIDES)
4.42 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
R = 0.115
TYP
6.00 p 0.10
(4 SIDES)
R = 0.10
TYP
ꢀ9 40
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.ꢀ5 s 45o
CHAMFER
4.42 p 0.10
4.50 REF
(4-SIDES)
4.42 p 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 p 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
ꢀ. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
22687612f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2268-12/
LTC2267-12/LTC2266-12
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2172-14 Quad ADCs, Ultralow Power
178mW/2ꢀ4mW/ꢀ60mW, 7ꢀ.4dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2172-12 Quad ADCs, Ultralow Power
178mW/2ꢀ4mW/ꢀ60mW, 70.5dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC217ꢀ-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps
LTC2175-14 1.8V Quad ADCs, Ultralow Power
ꢀ7ꢀmW/445mW/551mW, 7ꢀ.2 dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC217ꢀ-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps 1.8V 412mW/481mW/567mW, 70.5 dB SNR, 88dB SFDR, Serial LVDS Outputs,
LTC2175-12
LTC2256-14/LTC2257-14/ 14-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2258-14 ADCs, Ultralow Power
Quad ADCs, Ultralow Power
7mm × 8mm QFN-52
ꢀ5mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-ꢀ6
LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps 1.8V 89mW/106mW/127mW, 7ꢀ.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
LTC2261-14
ADCs, Ultralow Power
Outputs, 6mm × 6mm QFN-ꢀ6
LTC2262-14
14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-ꢀ6
LTC226ꢀ-14/LTC2264-14/ 14-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2265-14 Dual ADCs, Ultralow Power
99mW/126mW/191mW, 7ꢀ.4dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-ꢀ6
LTC226ꢀ-12/LTC2264-12/ 12-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2265-12 Dual ADCs, Ultralow Power
99mW/126mW/191mW, 70.5dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-ꢀ6
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps
216mW/250mW/29ꢀmW, 7ꢀ.4dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-ꢀ6
LTC2268-14
1.8V Dual ADCs, Ultralow Power
RF Mixers/Demodulators
LT5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIPꢀ: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5527
LT5557
LT5575
400MHz to ꢀ.7GHz High Linearity
Downconverting Mixer
24.5dBm IIPꢀ at 900MHz, 2ꢀ.5dBm IIPꢀ at ꢀ.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
400MHz to ꢀ.8GHz High Linearity
Downconverting Mixer
2ꢀ.7dBm IIPꢀ at 2.6GHz, 2ꢀ.5dBm IIPꢀ at ꢀ.5GHz, NF = 1ꢀ.2dB, ꢀ.ꢀV Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIPꢀ: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, ꢀ1dB Range, Analog-Controlled Continuously Adjustable Gain Control, ꢀ5dBm OIPꢀ at 240MHz, 10dB Noise
Variable Gain Amplifier
Figure, 4mm × 4mm QFN-24
LTC6420-20
LTC6421-20
1.8GHz Dual Low Noise, Low Distortion
Differential ADC Drivers for ꢀ00MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier,
ꢀmm × 4mm QFN-20
1.ꢀGHz Dual Low Noise, Low Distortion
Differential ADC Drivers
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier,
ꢀmm × 4mm QFN-20
LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
LTC6605-14
with ADC Drivers
Pin-Programmable Gain, 6mm × ꢀmm DFN-22
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
Subsystem
22687612f
LT 1009 • PRINTED IN USA
LinearTechnology Corporation
16ꢀ0 McCarthy Blvd., Milpitas, CA 950ꢀ5-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 4ꢀ2-1900 FAX: (408) 4ꢀ4-0507 www.linear.com
相关型号：
LTC2267IUJ-14#PBF
LTC2267-14 - 14-Bit, 105Msps Low Power Dual ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
LTC2267IUJ-14#TRPBF
LTC2267-14 - 14-Bit, 105Msps Low Power Dual ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
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