LTC2294UP [Linear]
Dual 12-Bit, 80Msps Low Power 3V ADC; 双12位，80Msps低功率3V ADC
| 型号： | LTC2294UP |
| 厂家： | 
Linear |
| 描述： | Dual 12-Bit, 80Msps Low Power 3V ADC |
| 文件： | 总24页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2294
Dual 12-Bit, 80Msps
Low Power 3V ADC
U
FEATURES
DESCRIPTIO
■
Integrated Dual 12-Bit ADCs
The LTC®2294 is a 12-bit 80Msps, low power dual 3V
A/Dconverterdesignedfordigitizinghighfrequency, wide
dynamic range signals. The LTC2294 is perfect for
demanding imaging and communications applications
with AC performance that includes 70.6dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
■
Sample Rate: 80Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 422mW
■
70.6dB SNR at 70MHz Input
■
90dB SFDR at 70MHz Input
■
110dB Channel Isolation at 100MHz
DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ)
■
Multiplexed or Separate Data Bus
and no missing codes over temperature. The transition
■
Flexible Input: 1VP-P to 2VP-P Range
noise is a low 0.3LSBRMS
.
■
575MHz Full Power Bandwidth S/H
■
■
■
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
Asingle-endedCLKinputcontrolsconverteroperation.An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
64-Pin (9mm × 9mm) QFN Package
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Spectral Analysis
Portable Instrumentation
■
U
TYPICAL APPLICATIO
SNR vs Input Frequency,
–1dB, 2V Range
OV
DD
+
12-BIT
PIPELINED
ADC CORE
INPUT
S/H
ANALOG
INPUT A
75
74
73
72
71
70
69
68
67
66
65
D11A
OUTPUT
DRIVERS
•
•
•
–
D0A
OGND
CLOCK/DUTY CYCLE
CONTROL
CLK A
CLK B
MUX
CLOCK/DUTY CYCLE
CONTROL
OV
DD
0
50
100
150
200
D11B
+
INPUT FREQUENCY (MHz)
OUTPUT
DRIVERS
•
•
•
12-BIT
PIPELINED
ADC CORE
ANALOG
INPUT B
INPUT
S/H
2294 TA02
D0B
–
OGND
2294 TA01
2294fa
1
LTC2294
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
OV = V (Notes 1, 2)
DD
SuDpDply Voltage (VDD)................................................. 4V
Digital Output Ground Voltage (OGND) .......–0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................–0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
TOP VIEW
+
A
1
2
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
INA
–
A
INA
REFHA 3
REFHA 4
REFLA 5
REFLA 6
V
DD
7
CLKA 8
CLKB 9
41 NC
65
40 OFB
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5
LTC2294C ............................................... 0°C to 70°C
LTC2294I.............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
V
10
DD
REFLB 11
REFLB 12
REFHB 13
REFHB 14
–
A
A
15
16
INB
INB
+
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
T
= 125°C, θ = 20°C/W
JA
JMAX
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
QFN PART*
MARKING
LTC2294UP
LTC2294IUP
LTC2294CUP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
●
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
–1.4
–0.8
–12
–2.5
±0.4
±0.2
±2
±0.5
±10
±30
±5
±0.3
±2
0.3
1.4
0.8
12
LSB
LSB
mV
Gain Error
External Reference
2.5
%FS
Offset Drift
µV/°C
ppm/°C
ppm/°C
%FS
Full-Scale Drift
Internal Reference
External Reference
External Reference
Gain Matching
Offset Matching
Transition Noise
mV
SENSE = 1V
LSB
RMS
2294fa
2
LTC2294
U
U
A ALOG I PUT
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
Analog Input Range (A –A
CONDITIONS
MIN
TYP
±0.5 to ±1
1.5
MAX
UNITS
V
+
–
V
V
)
2.7V < V < 3.4V (Note 7)
●
●
●
●
●
●
IN
IN
IN
DD
+
–
Analog Input Common Mode (A +A )/2
Differential Input (Note 7)
Single Ended Input (Note 7)
1
1.9
2
V
IN,CM
IN
IN
0.5
–1
–3
–3
1.5
V
+
–
I
I
I
t
t
Analog Input Leakage Current
0V < A , A < V
DD
1
µA
µA
µA
ns
IN
IN
IN
SENSEA, SENSEB Input Leakage
MODE Input Leakage Current
0V < SENSEA, SENSEB < 1V
0V < MODE < V
3
SENSE
MODE
AP
3
DD
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
0
0.2
80
ps
RMS
JITTER
CMRR
dB
Figure 8 Test Circuit
575
MHz
U W
DY A IC ACCURACY
The
IN
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
5MHz Input
MIN
TYP
70.6
70.6
70.6
70.3
90
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SNR
Signal-to-Noise Ratio
40MHz Input
70MHz Input
140MHz Input
5MHz Input
●
●
●
●
69.1
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
40MHz Input
70MHz Input
140MHz Input
5MHz Input
74
79
90
90
85
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
90
40MHz Input
70MHz Input
140MHz Input
5MHz Input
90
90
90
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
70.6
70.5
70.5
70
40MHz Input
70MHz Input
140MHz Input
68.7
I
Intermodulation Distortion
Crosstalk
f
f
= 40MHz, 41MHz
= 100MHz
90
MD
IN
IN
–110
2294fa
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LTC2294
U U
U
(Note 4)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
= 0
1.475 1.500 1.525
CM
CM
CM
CM
OUT
±25
3
ppm/°C
mV/V
Ω
2.7V < V < 3.4V
DD
–1mA < I
< 1mA
4
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3V
●
●
●
V
V
IH
IL
DD
DD
IN
= 3V
0.8
10
I
= 0V to V
–10
µA
pF
IN
DD
C
Input Capacitance
(Note 7)
3
IN
LOGIC OUTPUTS
OV = 3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = High (Note 7)
3
pF
mA
mA
OZ
I
I
V
V
= 0V
= 3V
50
50
SOURCE
SINK
OUT
OUT
V
High Level Output Voltage
I = –10µA
O
2.995
2.99
V
V
OH
O
I = –200µA
●
●
2.7
V
Low Level Output Voltage
I = 10µA
0.005
0.09
V
V
OL
O
I = 1.6mA
0.4
O
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
2.49
0.09
V
V
OH
OL
O
I = 1.6mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
1.79
0.09
V
V
OH
OL
O
I = 1.6mA
O
2294fa
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LTC2294
W U
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 8)
A
SYMBOL
PARAMETER
CONDITIONS
(Note 9)
MIN
2.7
TYP
3
MAX
3.4
UNITS
V
V
Analog Supply Voltage
Output Supply Voltage
Supply Current
●
●
●
●
DD
OV
(Note 9)
0.5
3
3.6
V
DD
IV
Both ADCs at f
Both ADCs at f
141
422
2
165
495
mA
mW
mW
mW
DD
S(MAX)
S(MAX)
P
P
P
Power Dissipation
DISS
SHDN
NAP
Shutdown Power (Each Channel)
Nap Mode Power (Each Channel)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
15
W U
TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
Sampling Frequency
CLK Low Time
(Note 9)
●
1
80
MHz
s
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
6.25
6.25
500
500
ns
ns
L
t
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
6.25
6.25
500
500
ns
ns
H
t
t
t
Sample-and-Hold Aperture Delay
CLK to DATA Delay
0
ns
ns
AP
D
C = 5pF (Note 7)
●
●
●
●
1.4
1.4
2.7
2.7
4.3
3.3
5
5.4
5.4
10
L
MUX to DATA Delay
C = 5pF (Note 7)
L
ns
MD
Data Access Time After OE↓
BUS Relinquish Time
C = 5pF (Note 7)
L
ns
(Note 7)
8.5
ns
Pipeline Latency
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
Note 2: All voltage values are with respect to ground with GND and OGND
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
wired together (unless otherwise noted).
Note 7: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
DD
Note 8: V = 3V, f
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
= 80MHz, input range = 1V with differential
P-P
DD
SAMPLE
of greater than 100mA below GND or above V without latchup.
DD
Note 4: V = 3V, f
drive, unless otherwise noted.
= 80MHz, input range = 2V with differential
P-P
DD
SAMPLE
Note 9: Recommended operating conditions.
2294fa
5
LTC2294
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Crosstalk vs Input Frequency
Typical INL, 2V Range, 80Msps
Typical DNL, 2V Range, 80Msps
1.0
0.8
1.0
0.8
–100
–105
0.6
0.6
0.4
0.4
–110
–115
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–120
–125
–130
2048
2048
0
1024
3072
4096
0
1024
3072
4096
0
20
40
60
80
100
CODE
CODE
INPUT FREQUENCY (MHz)
2294 G02
2294 G03
2294 G01
8192 Point FFT, f = 5MHz, –1dB,
8192 Point FFT, f = 30MHz,
8192 Point FFT, f = 70MHz,
IN
IN
IN
2V Range, 80Msps
–1dB, 2V Range, 80Msps
–1dB, 2V Range, 80Msps
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2294 G04
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2294 G05
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2294 G06
8192 Point 2-Tone FFT,
= 28.2MHz and 26.8MHz,
8192 Point FFT, f = 140MHz,
Grounded Input Histogram,
80Msps
f
IN
IN
–1dB, 2V Range, 80Msps
–1dB, 2V Range
140000
120000
0
–10
0
–10
116838
–20
–20
–30
–30
100000
80000
60000
40000
20000
0
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
8522
5712
2051
2052
2050
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
2294 G07
0
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
CODE
2294 G09
2294 G08
2294fa
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LTC2294
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Input Frequency, –1dB,
2V Range, 80Msps
SFDR vs Input Frequency, –1dB,
2V Range, 80Msps
SNR and SFDR vs Sample Rate,
2V Range, f = 5MHz, –1dB
IN
100
75
74
73
72
71
70
69
68
67
66
65
100
95
SFDR
SNR
90
80
90
85
80
75
70
65
70
60
50
50
100
200
10 20 30
60 70
0
150
0
40 50
80
90 100
110
0
50
100
150
200
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
SAMPLE RATE (Msps)
2294 G11
2294 G12
2294 G10
SNR and SFDR vs Clock Duty
Cycle, 80Msps
SNR vs Input Level, f = 70MHz,
SFDR vs Input Level, f = 70MHz,
IN
IN
2V Range, 80Msps
2V Range, 80Msps
120
110
100
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
80
70
60
50
dBFS
SFDR: DCS ON
SFDR: DCS OFF
dBFS
dBc
dBc
100dBc SFDR
40
30
REFERENCE LINE
20
10
0
SNR: DCS ON
SNR: DCS OFF
40 45 50 55
CLOCK DUTY CYCLE (%)
70
–40 –30
INPUT LEVEL (dBFS)
–10
30 35
60 65
–70 –60 –50
0
–40 –30
INPUT LEVEL (dBFS)
–20
–70 –60 –50
–20 –10
0
2294 G13
2294 G14
2294 G15
I
vs Sample Rate, 5MHz Sine
I
vs Sample Rate, 5MHz Sine
VDD
OVDD
Wave Input, –1dB
Wave Input, –1dB, O
= 1.8V
VDD
14
12
10
165
155
145
2V RANGE
135
125
115
105
8
6
4
2
1V RANGE
95
0
0
30
50 60 70 80 90 100
0
30
50 60 70 80 90 100
10 20
40
10 20
40
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
2294 G16
2294 G17
2294fa
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LTC2294
U
U
U
PI FU CTIO S
+
AINA (Pin 1): Channel A Positive Differential Analog
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
Input.
–
AINA (Pin 2): Channel A Negative Differential Analog
Input.
V
CMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMA
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
isHigh,ChannelAcomesoutonDA0-DA13,OFA;Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chipcapacitorasclosetothepinaspossible.Alsobypass
to Pins 13, 14 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chipcapacitorasclosetothepinaspossible.Alsobypass
to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
–
AINB (Pin 15): Channel B Negative Differential Analog
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
Input.
+
AINB (Pin 16): Channel B Positive Differential Analog
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
Input.
GND (Pins 17, 64): ADC Power Ground.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
SENSEB(Pin19):ChannelBReferenceProgrammingPin.
ConnectingSENSEBtoVCMB selectstheinternalreference
and a ±0.5V input range. VDD selects the internal reference
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
2294fa
8
LTC2294
U
U
U
PI FU CTIO S
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMB
.
SENSEA(Pin62):ChannelAReferenceProgrammingPin.
ConnectingSENSEAtoVCMA selectstheinternalreference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
U
U
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
–
A
IN
V
CM
1.5V
REFERENCE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
REFL
INTERNAL CLOCK SIGNALS
OV
DD
REF
BUF
SENSE
OF
D11
D0
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
2294 F01
REFH
REFL
0.1µF
2.2µF
OGND
SHDN
CLK
MODE
OE
1µF
1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
2294fa
9
LTC2294
W U
W
TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 1
N + 3
N + 5
t
t
H
L
CLK
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
N
D0-D11, OF
2294 TD01
Multiplexed Digital Output Bus Timing
t
APA
A + 4
A + 2
ANALOG
A
B
INPUT A
A + 1
B + 1
A + 3
B + 3
t
APB
B + 4
B + 2
ANALOG
INPUT B
t
t
H
L
CLKA = CLKB = MUX
A – 5
B – 5
A – 5
A – 4
B – 4
B – 4
A – 3
B – 3
B – 3
A – 2
B – 2
B – 2
A – 1
D0A-D11A, OFA
D0B-D11B, OFB
t
t
MD
D
B – 5
A – 4
A – 3
A – 2
B – 1
2294 TD02
2294fa
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LTC2294
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DYNAMIC PERFORMANCE
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
THD = 20Log ( )
√(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics. TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
Thevariationintheaperturedelaytimefromconversionto
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER
)
Crosstalk
Intermodulation Distortion
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
CONVERTER OPERATION
As shown in Figure 1, the LTC2294 is a dual CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2294fa
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LTC2294
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APPLICATIO S I FOR ATIO
applications, theanaloginputscanbedrivensingle-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2294 has two phases of operation,
determined by the state of the CLK input pin.
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
outputbytheresidueamplifier.Successivestagesoperate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2294
CMOSdifferentialsample-and-hold.Theanaloginputsare
connected to the sampling capacitors (CSAMPLE) through
NMOStransistors. Thecapacitorsshownattachedtoeach
input (CPARASITIC) are the summation of all other capaci-
tance associated with each input.
WhenCLKislow, theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltageisheldonthesamplingcapacitors.Duringthehold
phase when CLK is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
LTC2294
V
V
DD
DD
C
C
SAMPLE
4pF
15Ω
15Ω
+
–
A
A
IN
IN
C
PARASITIC
1pF
SAMPLE
4pF
C
1pF
PARASITIC
V
DD
CLK
2294 F02
Figure 2. Equivalent Input Circuit
2294fa
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U
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Single-Ended Input
Figure 3 shows the LTC2294 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
modepathforchargingglitchescausedbythesampleand
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
+
DNLwillremainunchanged.Forasingle-endedinput,AIN
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differentialdrivercircuit. TheVCM pinmustbebypassedto
ground close to the ADC with a 2.2µF or greater capacitor.
V
CM
2.2µF
0.1µF T1
+
25Ω
A
IN
1:1
ANALOG
INPUT
LTC2294
0.1µF
25Ω
25Ω
12pF
–
Input Drive Impedance
A
IN
25Ω
T1 = MA/COM ETC1-1T
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2294 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-holdcircuitwillconnectthe4pFsamplingcapacitorto
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degradetheSFDR. Thesamplingglitchhasbeendesigned
2294 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. Theadvantageofthismethodisthatitprovideslow
frequencyinputresponse;however,thelimitedgainband-
width of most op amps will limit the SFDR at high input
frequencies.
2294fa
13
LTC2294
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APPLICATIO S I FOR ATIO
V
V
CM
CM
2.2µF
2.2µF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
+
+
25Ω
25Ω
12Ω
A
A
IN
IN
ANALOG
INPUT
LTC2294
LTC2294
ANALOG
INPUT
+
+
0.1µF
25Ω
25Ω
T1
8pF
A
CM
12pF
A
–
–
0.1µF
–
–
12Ω
IN
IN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2294 F04
2294 F06
Figure 4. Differential Drive with an Amplifier
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
V
CM
2.2µF
V
CM
0.1µF
0.1µF
+
A
A
IN
IN
ANALOG
INPUT
LTC2294
2.2µF
1k
1k
25Ω
0.1µF
25Ω
25Ω
0.1µF
+
–
A
T1
IN
ANALOG
INPUT
LTC2294
–
12pF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2294 F07
25Ω
A
IN
2294 F05
0.1µF
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 5. Single-Ended Drive
V
CM
The25Ωresistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
2.2µF
0.1µF
0.1µF
+
6.8nH
A
IN
IN
ANALOG
INPUT
LTC2294
0.1µF
25Ω
25Ω
T1
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
6.8nH
–
A
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
2294 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
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Reference Operation
U
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Figure9showstheLTC2294referencecircuitryconsisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of2V(±1Vdifferential)or1V(±0.5Vdifferential).Tyingthe
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
inFigure10.Anexternalreferencecanbeusedbyapplying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
levelasclosetotheconverteraspossible. IftheSENSEpin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
Forthebestchannelmatching, connectanexternalreference
to SENSEA and SENSEB.
LTC2294
4Ω
V
CM
1.5V BANDGAP
REFERENCE
1.5V
1.5V
V
CM
2.2µF
1V
0.5V
2.2µF
12k
LTC2294
RANGE
DETECT
AND
0.75V
12k
SENSE
1µF
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
REFH
TIE TO V FOR 1V RANGE;
CM
RANGE = 2 • V
FOR
< 1V
SENSE
SENSE
2294 F10
BUFFER
0.5V < V
INTERNAL ADC
HIGH REFERENCE
1µF
Figure 10. 1.5V Range ADC
Input Range
2.2µF
1µF
0.1µF
The input range can be set based on the application. The
2Vinputrangewillprovidethebestsignal-to-noiseperfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 4dB. See the Typical Performance Character-
istics section.
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
2294 F09
Driving the Clock Input
Figure 9. Equivalent Reference Circuit
The CLK inputs can be driven directly with a CMOS or TTL
levelsignal. Asinusoidalclockcanalsobeusedalongwith
a low jitter squaring circuit before the CLK pin (Figure 11).
2294fa
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CLEAN
SUPPLY
CLEAN
SUPPLY
4.7µF
4.7µF
FERRITE
BEAD
FERRITE
BEAD
0.1µF
0.1µF
1k
0.1µF
LTC2294
SINUSOIDAL
CLOCK
CLK
CLK
LTC2294
100Ω
INPUT
50Ω 1k
NC7SVU04
2294 F11
2294 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 11. Sinusoidal Single-Ended CLK Drive
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
The noise performance of the LTC2294 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
ETC1-1T
CLK
LTC2294
5pF-30pF
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
DIFFERENTIAL
CLOCK
INPUT
2294 F13
0.1µF
FERRITE
BEAD
V
CM
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
areconsidered. Thecentertapmaybebypassedtoground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM,wherethenominalpowerlevelmustbeatleast6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
Maximum and Minimum Conversion Rates
ThemaximumconversionratefortheLTC2294is80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have
2294fa
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at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. Tousetheclockdutycyclestabilizer, theMODEpin
should be connected to 1/3VDD or 2/3VDD using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on or off for
both channels.
LTC2294
OV
DD
0.5V
TO 3.6V
V
DD
V
DD
0.1µF
OV
DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
The lower limit of the LTC2294 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architectureofthisADCreliesonstoringanalogsignalson
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2294 is 1Msps.
OE
OGND
2294 F14
Figure 14. Digital Output Buffer
Aswithallhighspeed/highresolutionconverters, thedigi-
tal output loading can affect the performance. The digital
outputs of the LTC2294 should drive a minimal capacitive
load to avoid possible interaction between the digital
outputsandsensitiveinputcircuitry. Theoutputshouldbe
buffered with a device such as an ALVCH16373 CMOS
latch. For full speed operation the capacitive load should
be kept under 10pF.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
+
–
A
IN
– A
D11 – D0
(OFFSET BINARY)
D11 – D0
(2’s COMPLEMENT)
IN
(2V RANGE)
OF
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
Lower OVDD voltages will also help reduce interference
from the digital outputs.
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
Data Format
Using the MODE pin, the LTC2294 parallel digital output
can be selected for offset binary or 2’s complement
format. Note that MODE controls both Channel A and
Channel B. Connecting MODE to GND or 1/3VDD selects
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
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offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normaloperation. ConnectingSHDNtoVDD andOEtoVDD
results in sleep mode, which powers down all circuitry
includingthereferenceandtypicallydissipates1mW.When
exiting sleep mode it will take milliseconds for the output
datatobecomevalidbecausethereferencecapacitorshave
torechargeandstabilize. ConnectingSHDNtoVDD andOE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on,sothatrecoveryfromnapmodeisfasterthanthatfrom
sleepmode,typicallytaking100clockcycles.Inbothsleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Table 2. MODE Pin Function
CLOCK DUTY
MODE PIN
OUTPUT FORMAN
CYCLE STABILIZER
0
Offset Binary
Off
On
On
Off
1/3V
2/3V
Offset Binary
DD
DD
2’s Complement
2’s Complement
V
DD
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
ChannelBiscontrolledbySHDNBandOEB.Thenap,sleep
andoutputenablemodesofthetwochannelsarecompletely
independent, so it is possible to have one channel operat-
ing while the other channel is in nap or sleep mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example,iftheconverterisdrivingaDSPpoweredbya1.8V
supply,thenOVDD shouldbetiedtothatsame1.8Vsupply.
Digital Output Multiplexer
ThedigitaloutputsoftheLTC2294canbemultiplexedonto
a single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is High, Channel A comes out
on DA0-DA11, OFA; Channel B comes out on DB0-DB11,
OFB. If MUX is Low, the output busses are swapped and
ChannelAcomesoutonDB0-DB11,OFB;ChannelBcomes
out on DA0-DA11, OFA. To multiplex both channels onto
asingleoutputbus,connectMUX,CLKAandCLKBtogether
(see the Timing Diagram for the multiplexed mode). The
multiplexed data is available on either data bus—the un-
used data bus can be disabled with its OE pin.
OVDD can be powered with any voltage from 500mV up to
3.6V.OGNDcanbepoweredwithanyvoltagefromGNDup
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
Theoutputsmaybedisabledwiththeoutputenablepin,OE.
OEhighdisablesalldataoutputsincludingOF.Thedataac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration.TheoutputHi-Zstateisintendedforuseduringlong
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Grounding and Bypassing
The LTC2294 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
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LTC2294
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circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
mayoccurevenoverafractionofaninchisadvisable.You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
High quality ceramic bypass capacitors should be used at
theVDD, OVDD, VCM, REFH, andREFLpins. Bypasscapaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF
capacitor between REFH and REFL can be somewhat
further away. The traces connecting the pins and bypass
capacitorsmustbekeptshortandshouldbemadeaswide
as possible.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
thefilterandtheADC. Ifyouaresensitivetoclose-inphase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
todrivedigitaldevicessuchasanFPGA, youshouldlocate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
The LTC2294 differential inputs should run parallel
and close to each other. The input traces should be as
shortaspossibletominimizecapacitanceandtominimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2294 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
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LTC2294
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D D
D D
O V
O V
O G N D
3 2
4 9
5 0
O G N D
3 1
D A 6
5 1
D B 4
3 0
D A 7
5 2
D B 3
2 9
D A 8
5 3
D B 2
2 8
D A 9
5 4
D B 1
2 7
D A 1 0
5 5
D B 0
2 6
D A 1 1
5 6
N C
2 5
2 4
O F A
5 7
N C
O E A
5 8
O E B
2 3
S H D N A
5 9
S H D N B
2 2
M O D E
6 0
M U X
2 1
V C M A
6 1
V C M B
2 0
S E N S E A
6 2
S E N S E B
1 9
D D
V
D D
V
1 8
G N D
1 7
6 3
6 4
G N D
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LTC2294
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APPLICATIO S I FOR ATIO
Silkscreen Top
Top Side
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21
LTC2294
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APPLICATIO S I FOR ATIO
Inner Layer 3 Power
Inner Layer 2 GND
Bottom Side
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22
LTC2294
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
(UP64) QFN 1003
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
2294fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC2294
RELATED PARTS
PART NUMBER
LTC2220
LTC2221
LTC2222
LTC2223
LTC2224
LTC2225
LTC2226
LTC2227
LTC2228
LTC2230
LTC2231
LTC2232
LTC2233
LTC2245
LTC2246
LTC2247
LTC2248
LTC2249
LTC2286
LTC2287
LTC2288
LTC2289
LTC2290
LTC2291
LTC2292
LTC2293
LTC2295
LTC2296
LTC2297
LTC2298
LTC2299
DESCRIPTION
COMMENTS
12-Bit, 170Msps ADC
12-Bit, 135Msps ADC
12-Bit, 105Msps ADC
12-Bit, 80Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
630mW, 67.5dB SNR, 9mm × 9mm QFN Package
475mW, 67.9dB SNR, 7mm × 7mm QFN Package
366mW, 68dB SNR, 7mm × 7mm QFN Package
630mW, 67.5dB SNR, 7mm × 7mm QFN Package
60mW, 71.4dB SNR, 5mm × 5mm QFN Package
75mW, 71.4dB SNR, 5mm × 5mm QFN Package
120mW, 71.4dB SNR, 5mm × 5mm QFN Package
205mW, 71.3dB SNR, 5mm × 5mm QFN Package
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
630mW, 67.5dB SNR, 9mm × 9mm QFN Package
475mW, 61.3dB SNR, 7mm × 7mm QFN Package
366mW, 61.3dB SNR, 7mm × 7mm QFN Package
60mW, 74.4dB SNR, 5mm × 5mm QFN Package
75mW, 74.5dB SNR, 5mm × 5mm QFN Package
120mW, 74.4dB SNR, 5mm × 5mm QFN Package
205mW, 74.3dB SNR, 5mm × 5mm QFN Package
222mW, 73dB SNR, 5mm × 5mm QFN Package
150mW, 61.8dB SNR, 9mm × 9mm QFN Package
235mW, 61.8dB SNR, 9mm × 9mm QFN Package
400mW, 61.8dB SNR, 9mm × 9mm QFN Package
422mW, 61dB SNR, 9mm × 9mm QFN Package
120mW, 71.3dB SNR, 9mm × 9mm QFN Package
150mW, 74.5dB SNR, 9mm × 9mm QFN Package
235mW, 74.4dB SNR, 9mm × 9mm QFN Package
400mW, 74.3dB SNR, 9mm × 9mm QFN Package
120mW, 74.4dB SNR, 9mm × 9mm QFN Package
150mW, 74.5dB SNR, 9mm × 9mm QFN Package
235mW, 74.4dB SNR, 9mm × 9mm QFN Package
400mW, 74.3dB SNR, 9mm × 9mm QFN Package
444mW, 73dB SNR, 9mm × 9mm QFN Package
12-Bit, 135Msps ADC
12-Bit, 10Msps ADC
12-Bit, 25Msps ADC
12-Bit, 40Msps ADC
12-Bit, 65Msps ADC
10-Bit, 170Msps ADC
10-Bit, 135Msps ADC
10-Bit, 105Msps ADC
10-Bit, 80Msps ADC
14-Bit, 10Msps ADC
14-Bit, 25Msps ADC
14-Bit, 40Msps ADC
14-Bit, 65Msps ADC
14-Bit, 80Msps ADC
10-Bit, Dual, 25Msps ADC
10-Bit, Dual, 40Msps ADC
10-Bit, Dual, 65Msps ADC
10-Bit, Dual, 80Msps ADC
12-Bit, Dual, 10Msps ADC
12-Bit, Dual, 25Msps ADC
12-Bit, Dual, 40Msps ADC
12-Bit, Dual, 65Msps ADC
14-Bit, Dual, 10Msps ADC
14-Bit, Dual, 25Msps ADC
14-Bit, Dual, 40Msps ADC
14-Bit, Dual, 65Msps ADC
14-Bit, Dual, 80Msps ADC
2294fa
RD/LT 0106 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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