LTC2297CUP#TR [Linear]
LTC2297 - Dual 14-Bit, 40Msps Low Power 3V ADCs; Package: QFN; Pins: 64; Temperature Range: 0°C to 70°C;
| 型号： | LTC2297CUP#TR |
| 厂家： | 
Linear |
| 描述： | LTC2297 - Dual 14-Bit, 40Msps Low Power 3V ADCs; Package: QFN; Pins: 64; Temperature Range: 0°C to 70°C 转换器 |
| 文件： | 总28页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2298/LTC2297/LTC2296
Dual 14-Bit, 65/40/25Msps
Low Power 3V ADCs
U
FEATURES
DESCRIPTIO
The LTC®2298/LTC2297/LTC2296 are 14-bit 65Msps/
40Msps/25Msps, low power dual 3V A/D converters de-
signed for digitizing high frequency, wide dynamic range
signals. The LTC2298/LTC2297/LTC2296 are perfect for
demanding imaging and communications applications
with AC performance that includes 74.3dB SNR and 90dB
SFDR for signals at the Nyquist frequency.
■
Integrated Dual 14-Bit ADCs
■
Sample Rate: 65Msps/40Msps/25Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 400mW/235mW/150mW
■
74.3dB SNR
90dB SFDR
■
■
110dB Channel Isolation at 100MHz
■
Multiplexed or Separate Data Bus
DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ)
■
Flexible Input: 1VP-P to 2VP-P Range
and no missing codes over temperature. The transition
■
575MHz Full Power Bandwidth S/H
noise is a low 1LSBRMS
.
■
Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
■
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
Asingle-endedCLKinputcontrolsconverteroperation.An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
64-Pin (9mm × 9mm) QFN Package
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Spectral Analysis
Portable Instrumentation
■
U
TYPICAL APPLICATIO
LTC2298: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
OV
DD
+
14-BIT
PIPELINED
ADC CORE
75
74
73
72
71
70
INPUT
S/H
ANALOG
INPUT A
D13A
OUTPUT
DRIVERS
•
•
•
–
D0A
OGND
CLOCK/DUTY CYCLE
CONTROL
CLK A
CLK B
MUX
CLOCK/DUTY CYCLE
CONTROL
OV
DD
D13B
+
50
100
150
0
200
OUTPUT
DRIVERS
•
•
•
14-BIT
PIPELINED
ADC CORE
ANALOG
INPUT B
INPUT
S/H
INPUT FREQUENCY (MHz)
D0B
229876 TA01b
–
OGND
229876 TA01
229876fa
1
LTC2298/LTC2297/LTC2296
W W
U W
ABSOLUTE AXI U RATI GS
OV = V (Notes 1, 2)
SuDpDply Voltage (VDD)................................................. 4V
Digital Output Ground Voltage (OGND) .......–0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
DD
LTC2298C, LTC2297C, LTC2296C........... 0°C to 70°C
LTC2298I, LTC2297I, LTC2296I ..........–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
U
Digital Output Voltage................–0.3V toW(OVDD + 0.3V)
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
QFN PART*
MARKING
+
A
1
2
48 DA7
47 DA6
46 DA5
45 DA4
44 DA3
43 DA2
42 DA1
41 DA0
40 OFB
39 DB13
38 DB12
37 DB11
36 DB10
35 DB9
34 DB8
33 DB7
INA
–
A
INA
REFHA 3
REFHA 4
REFLA 5
REFLA 6
LTC2298UP
LTC2297UP
LTC2296UP
LTC2298CUP
LTC2298IUP
LTC2297CUP
LTC2297IUP
LTC2296CUP
LTC2296IUP
V
7
DD
CLKA 8
CLKB 9
65
V
10
DD
REFLB 11
REFLB 12
REFHB 13
REFHB 14
–
A
A
15
16
INB
INB
+
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
T
= 125°C, θ = 20°C/W
JMAX JA
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2298
TYP
LTC2297
TYP
LTC2296
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Resolution
(No Missing Codes)
●
14
14
14
Bits
Integral Linearity Error Differential Analog Input (Note 5)
●
●
–5
–1
±1.2
±0.5
5
1
–5
–1
±1.2
±0.5
5
1
–5
–1
±1.2
±0.5
5
1
LSB
LSB
Differential
Differential Analog Input
Linearity Error
Offset Error
Gain Error
(Note 6)
●
●
–12
±2
±0.5
±10
±30
±5
±0.3
±2
1
12
–12
±2
±0.5
±10
±30
±5
±0.3
±2
1
12
–12
±2
±0.5
±10
±30
±5
±0.3
±2
1
12
mV
%FS
External Reference
–2.5
2.5
–2.5
2.5
–2.5
2.5
Offset Drift
Full-Scale Drift
µV/°C
ppm/°C
ppm/°C
%FS
Internal Reference
External Reference
Gain Matching
Offset Matching
Transition Noise
mV
SENSE = 1V
LSB
RMS
229876fa
2
LTC2298/LTC2297/LTC2296
U
U
A ALOG I PUT
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
Analog Input Range (A –A
CONDITIONS
MIN
TYP
±0.5V to ±1V
1.5
MAX
UNITS
V
+
–
V
V
)
2.7V < V < 3.4V (Note 7)
●
●
●
●
●
●
IN
IN
IN
DD
+
–
Analog Input Common Mode (A +A )/2
Differential Input (Note 7)
Single Ended Input (Note 7)
1
1.9
2
V
IN,CM
IN
IN
0.5
–1
–3
–3
1.5
V
+
–
I
I
I
t
t
Analog Input Leakage Current
0V < A , A < V
DD
1
µA
µA
µA
ns
IN
IN
IN
SENSEA, SENSEB Input Leakage
MODE Input Leakage Current
0V < SENSEA, SENSEB < 1V
0V < MODE < V
3
SENSE
MODE
AP
3
DD
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
0
0.2
80
ps
RMS
JITTER
CMRR
dB
Figure 8 Test Circuit
575
MHz
U W
DY A IC ACCURACY
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)
A
IN
LTC2298
TYP
LTC2297
TYP
LTC2296
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SNR
Signal-to-Noise Ratio 5MHz Input
12.5MHz Input
74.3
74.4
74.5
74.2
●
●
●
72.7
20MHz Input
72.4
74.4
30MHz Input
72.1
74.3
74.3
73.9
90
70MHz Input
73.9
73.3
90
73.4
73
140MHz Input
SFDR
SFDR
S/(N+D)
5MHz Input
90
Spurious Free
Dynamic Range
2nd or 3rd
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
●
●
●
76
80
90
75
80
90
Harmonic
75
78
90
85
80
90
85
80
90
85
80
90
90
Spurious Free
Dynamic Range
4th Harmonic
or Higher
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
●
●
●
90
90
90
90
90
90
90
90
Signal-to-Noise
Plus Distortion
Ratio
74.3
74.4
74.5
74.2
12.5MHz Input
20MHz Input
30MHz Input
70MHz Input
140MHz Input
●
●
●
72.2
71.9
74.3
71.6
74.2
74.1
71.9
90
73.6
71.9
90
73.4
71.8
90
I
Intermodulation
Distortion
f = Nyquist,
IN
Nyquist + 1MHz
MD
Crosstalk
f
= Nyquist
–110
–110
–110
dB
IN
229876fa
3
LTC2298/LTC2297/LTC2296
U U
U
(Note 4)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
= 0
MIN
TYP
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
1.475 1.500 1.525
CM
CM
CM
CM
OUT
±25
3
ppm/°C
mV/V
Ω
2.7V < V < 3.3V
DD
–1mA < I
< 1mA
4
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3V
●
●
●
V
V
IH
IL
DD
DD
IN
= 3V
0.8
10
I
= 0V to V
–10
µA
pF
IN
DD
C
Input Capacitance
(Note 7)
3
IN
LOGIC OUTPUTS
OV = 3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = High (Note 7)
3
pF
mA
mA
OZ
I
I
V
V
= 0V
= 3V
50
50
SOURCE
SINK
OUT
OUT
V
High Level Output Voltage
I = –10µA
O
2.995
2.99
V
V
OH
O
I = –200µA
●
●
2.7
V
Low Level Output Voltage
I = 10µA
0.005
0.09
V
V
OL
O
I = 1.6mA
0.4
O
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
2.49
0.09
V
V
OH
OL
O
I = 1.6mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
1.79
0.09
V
V
OH
OL
O
I = 1.6mA
O
229876fa
4
LTC2298/LTC2297/LTC2296
W U
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 8)
A
LTC2298
TYP
LTC2297
TYP
LTC2296
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
V
Analog Supply
Voltage
(Note 9)
●
●
2.7
3
3.4
2.7
3
3.4
2.7
3
3.4
V
DD
OV
Output Supply
Voltage
(Note 9)
0.5
3
3.6
0.5
3
3.6
0.5
3
3.6
V
DD
IV
Supply Current
Both ADCs at f
●
●
133
400
2
150
450
78
235
2
95
50
150
2
60
mA
mW
mW
DD
S(MAX)
S(MAX)
P
P
Power Dissipation Both ADCs at f
285
180
DISS
Shutdown Power
(Each Channel)
SHDN = H,
OE = H, No CLK
SHDN
P
Nap Mode Power
(Each Channel)
SHDN = H,
OE = L, No CLK
15
15
15
mW
NAP
W U
TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2298
TYP
LTC2297
TYP
LTC2296
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
f
t
Sampling Frequency (Note 9)
●
1
65
1
40
1
25
MHz
s
CLK Low Time
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
L
t
t
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
H
Sample-and-Hold
Aperture Delay
0
0
0
ns
AP
t
t
CLK to DATA Delay C = 5pF (Note 7)
●
●
●
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
1.4
1.4
2.7
2.7
4.3
5.4
5.4
10
ns
ns
ns
D
L
MUX to DATA Delay C = 5pF (Note 7)
MD
L
Data Access Time
C = 5pF (Note 7)
L
After OE↓
BUS Relinquish Time (Note 7)
●
3.3
5
8.5
3.3
5
8.5
3.3
5
8.5
ns
Pipeline
Latency
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
Note 7: Guaranteed by design, not subject to test.
DD
Note 8: V = 3V, f
= 65MHz (LTC2298), 40MHz (LTC2297), or
DD
SAMPLE
of greater than 100mA below GND or above V without latchup.
DD
25MHz (LTC2296), input range = 1V with differential drive. The supply
P-P
Note 4: V = 3V, f
= 65MHz (LTC2298), 40MHz (LTC2297), or
current and power dissipation are the sum total for both channels with
both channels active.
Note 9: Recommended operating conditions.
DD
SAMPLE
25MHz (LTC2296), input range = 2V with differential drive, unless
P-P
otherwise noted.
229876fa
5
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2298/LTC2297/LTC2296:
Crosstalk vs Input Frequency
LTC2298: Typical INL,
2V Range, 65Msps
LTC2298: Typical DNL,
2V Range, 65Msps
–100
–105
2.0
1.5
1.00
0.75
0.50
0.25
0
1.0
–110
–115
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
–120
–125
–130
0
20
40
60
80
100
0
4096
8192
12288
16384
0
4096
8192
12288
16384
INPUT FREQUENCY (MHz)
CODE
CODE
2298 G01
2298 G02
229876 G01
LTC2298: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
LTC2298: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
LTC2298: 8192 Point FFT,
= 5MHz, –1dB, 2V Range,
f
f
f
IN
IN
IN
65Msps
65Msps
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
30
30
30
0
5
10
15
20
25
0
5
10
15
20
25
0
5
10
15
20
25
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2298 G03
2298 G04
2298 G05
LTC2298: 8192 Point FFT,
= 140MHz, –1dB, 2V Range,
LTC2298: 8192 Point 2-Tone FFT,
f = 28.2MHz and 26.8MHz,
IN
–1dB, 2V Range, 65Msps
LTC2298: Grounded Input
Histogram, 65Msps
f
IN
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
25000
20000
15000
10000
5000
0
21824
20412
10224
9042
2116
172
1596
121
30
0
5
10
15
20
25
30
8196 8197 8198 8199 8200 8201 8202 8203
0
5
10
15
20
25
FREQUENCY (MHz)
FREQUENCY (MHz)
CODE
2298 G08
2298 G06
2298 G06a
229876fa
6
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2298: SNR and SFDR vs
Sample Rate, 2V Range,
IN
LTC2298: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
LTC2298: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
f
= 5MHz, –1dB
75
74
73
72
71
70
100
95
90
85
80
75
70
65
110
100
90
80
70
60
0
50
100
150
0
50
INPUT FREQUENCY (MHz)
100
150
200
200
0
10 20 30 40 50 60 70 80 90 100 110
INPUT FREQUENCY (MHz)
SAMPLE RATE (Msps)
2298 G09
2298 G10
2298 G11
LTC2298: SNR vs Input Level,
= 30MHz, 2V Range, 65Msps
LTC2298: SFDR vs Input Level,
IN
LTC2298: SNR and SFDR vs
Clock Duty Cycle, 65Msps
f
= 30MHz, 2V Range, 65Msps
f
IN
120
110
100
90
100
80
dBFS
SFDR: DCS ON
70
60
50
40
30
20
10
0
dBFS
95
90
85
80
75
70
80
SFDR: DCS OFF
dBc
dBc
70
90dBc SFDR
REFERENCE LINE
60
50
40
SNR: DCS ON
SNR: DCS OFF
30
20
–10
–60
–50
–40
–30
–20
0
30
50
60 65
–10
35 40 45
55
70
–60
–50
–40
–30
–20
0
INPUT LEVEL (dBFS)
CLOCK DUTY CYCLE (%)
INPUT LEVEL (dBFS)
2298 G14
2298 G13
2298 G12
LTC2298: I
vs Sample Rate,
OVDD
LTC2298: I
vs Sample Rate,
5MHz Sine Wave Input, –1dB,
= 1.8V
VDD
5MHz Sine Wave Input, –1dB
O
VDD
155
145
135
125
115
105
95
12
10
8
1V RANGE
6
2V RANGE
4
2
0
0
40
60 70
10 20 30
50
80
0
40
60 70
10 20 30
50
80
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
2298 G15
2298 G16
229876fa
7
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2297: 8192 Point FFT,
f = 5MHz, –1dB, 2V Range,
IN
40Msps
LTC2297: Typical INL,
2V Range, 40Msps
LTC2297: Typical DNL,
2V Range, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2.0
1.5
1.00
0.75
0.50
0.25
0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
0
5
10
15
20
0
4096
8192
12288
16384
0
4096
8192
12288
16384
FREQUENCY (MHz)
CODE
CODE
2297 G03
2297 G01
2297 G02
LTC2297: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
LTC2297: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
LTC2297: 8192 Point FFT,
f = 140MHz, –1dB, 2V Range,
IN
40Msps
f
f
IN
IN
40Msps
40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2297 G04
2297 G05
2297 G06
LTC2297: 8192 Point 2-Tone FFT,
= 21.6MHz and 23.6MHz,
f
LTC2297: Grounded Input
Histogram, 40Msps
LTC2297: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
IN
–1dB, 2V Range, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
30000
25000
20000
15000
10000
5000
0
75
74
73
72
71
70
24558
15714
14833
4641
4520
640
546
36
30
0
5
10
15
20
100
INPUT FREQUENCY (MHz)
0
50
150
200
8184 81858186 8187818881898190 81918192
FREQUENCY (MHz)
CODE
2297 G07
2297 G09
2297 G08
229876fa
8
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2297: SNR and SFDR vs
LTC2297: SNR vs Input Level,
IN
LTC2297: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
Sample Rate, 2V Range,
f
= 5MHz, 2V Range, 40Msps
f
IN
= 5MHz, –1dB
110
100
90
100
95
90
85
80
75
70
65
80
70
60
50
40
30
20
10
0
dBFS
SFDR
dBc
80
SNR
70
60
–10
–60
–50
–40
–30
–20
0
0
20
40
60
80
50
100
200
0
150
INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
INPUT FREQUENCY (MHz)
2297 G12
2297 G11
2297 G10
LTC2297: I
vs Sample Rate,
OVDD
LTC2297: SFDR vs Input Level,
IN
LTC2297: I
vs Sample Rate,
5MHz Sine Wave Input, –1dB,
VDD
f
= 5MHz, 2V Range, 40Msps
5MHz Sine Wave Input, –1dB
O
= 1.8V
VDD
120
110
100
90
100
90
80
70
60
8
6
4
2
0
dBFS
80
2V RANGE
1V RANGE
dBc
70
90dBc SFDR
60
REFERENCE LINE
50
40
30
20
–10
0
10
20
30
40
50
0
10
20
30
40
50
–60
–50
–40
–30
–20
0
INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
2297 G14
2297 G15
2297 G13
LTC2296: 8192 Point FFT,
= 5MHz, –1dB, 2V Range,
LTC2296: Typical INL,
2V Range, 25Msps
LTC2296: Typical DNL,
2V Range, 25Msps
f
IN
25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1.00
0.75
0.50
0.25
0
2.0
1.5
1.0
0.5
0
–0.25
–0.50
–0.75
–1.00
–0.5
–1.0
–1.5
–2.0
12
0
2
4
6
8
10
0
4096
8192
12288
16384
0
4096
8192
12288
16384
FREQUENCY (MHz)
CODE
CODE
2296 G02
2296 G03
2296 G01
229876fa
9
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2296: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
LTC2296: 8192 Point FFT,
f = 140MHz, –1dB, 2V Range,
IN
25Msps
LTC2296: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
f
f
IN
IN
25Msps
25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
12
0
2
4
6
8
10
12
12
0
2
4
6
8
10
0
2
4
6
8
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2296 G05
2296 G04
2296 G06
LTC2296: 8192 Point 2-Tone FFT,
= 10.9MHz and 13.8MHz,
f
LTC2296: Grounded Input
Histogram, 25Msps
LTC2296: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
IN
–1dB, 2V Range, 25Msps
25000
20000
15000
10000
5000
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
75
74
73
72
71
70
22016
18803
13373
6919
3227
853
43
278
12
0
2
4
6
8
10
50
100
150
8179 8180 8181 8182 8183 8184 8185 8186
0
200
FREQUENCY (MHz)
CODE
INPUT FREQUENCY (MHz)
2296 G07
2296 G08
2296 G09
LTC2296: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
LTC2296: SNR and SFDR vs
Sample Rate, 2V Range,
IN
LTC2296: SNR vs Input Level,
f = 5MHz, 2V Range, 25Msps
IN
f
= 5MHz, –1dB
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
110
100
90
dBFS
SFDR
dBc
80
SNR
70
60
–60 –50
–10
50
100
200
–40
–30
–20
0
0
150
0
10
20
30
40
50
INPUT LEVEL (dBFS)
INPUT FREQUENCY (MHz)
SAMPLE RATE (Msps)
2296 G12
2296 G10
2296 G11
229876fa
10
LTC2298/LTC2297/LTC2296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2296: I
vs Sample Rate,
OVDD
LTC2296: SFDR vs Input Level,
IN
LTC2296: I vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB,
f
= 5MHz, 2V Range, 25Msps
5MHz Sine Wave Input, –1dB
O
= 1.8V
VDD
70
60
50
40
30
120
110
100
90
6
4
2
0
dBFS
dBc
80
2V RANGE
1V RANGE
70
90dBc SFDR
60
REFERENCE LINE
50
40
30
20
30
0
20
25
30
0
5
10 15
20
25
35
–10
5
10 15
35
–60 –50 –40 –30 –20
INPUT LEVEL (dBFS)
0
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
2296 G13
2296 G14
2296 G15
U
U
U
PI FU CTIO S
+
AINA (Pin 1): Channel A Positive Differential Analog
chipcapacitorasclosetothepinaspossible.Alsobypass
to Pins 13, 14 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
Input.
–
AINA (Pin 2): Channel A Negative Differential Analog
Input.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chipcapacitorasclosetothepinaspossible.Alsobypass
to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
–
AINB (Pin 15): Channel B Negative Differential Analog
Input.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
+
AINB (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB(Pin19):ChannelBReferenceProgrammingPin.
ConnectingSENSEBtoVCMB selectstheinternalreference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
capacitor. Do not connect to VCMA
.
229876fa
11
LTC2298/LTC2297/LTC2296
U
U
U
PI FU CTIO S
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
isHigh,ChannelAcomesoutonDA0-DA13,OFA;Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital
Outputs. DB13 is the MSB.
capacitor. Do not connect to VCMB
.
OGND (Pins 31, 50): Output Driver Ground.
SENSEA(Pin62):ChannelAReferenceProgrammingPin.
ConnectingSENSEAtoVCMA selectstheinternalreference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital
Outputs. DA13 is the MSB.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
229876fa
12
LTC2298/LTC2297/LTC2296
U
U
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
–
A
IN
V
CM
1.5V
REFERENCE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
REFL
INTERNAL CLOCK SIGNALS
OV
DD
REF
BUF
SENSE
OF
D13
D0
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
229876 F01
REFH
REFL
0.1µF
2.2µF
OGND
SHDN
CLK
MODE
OE
1µF
1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
229876fa
13
LTC2298/LTC2297/LTC2296
W U
W
TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 1
N + 3
N + 5
t
t
H
L
CLK
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
N
D0-D13, OF
229876 TD01
Multiplexed Digital Output Bus Timing
t
APA
A + 4
A + 2
ANALOG
INPUT A
A
A + 1
B + 1
A + 3
B + 3
t
APB
B + 4
B + 2
ANALOG
INPUT B
B
t
t
H
L
CLKA = CLKB = MUX
A – 5
B – 5
A – 5
A – 4
B – 4
B – 4
A – 3
B – 3
B – 3
A – 2
B – 2
B – 2
A – 1
D0A-D13A, OFA
D0B-D13B, OFB
t
t
MD
D
B – 5
A – 4
A – 3
A – 2
B – 1
229876 TD02
229876fa
14
LTC2298/LTC2297/LTC2296
W U U
APPLICATIO S I FOR ATIO
U
DYNAMIC PERFORMANCE
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
THD = 20Log ( )
√(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics. TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
Thevariationintheaperturedelaytimefromconversionto
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER
)
Crosstalk
Intermodulation Distortion
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
CONVERTER OPERATION
AsshowninFigure1,theLTC2298/LTC2297/LTC2296are
dual CMOS pipelined multistep converters. The convert-
ers have six pipelined ADC stages; a sampled analog input
will result in a digitized value five cycles later (see the
Timing Diagram section). For optimal AC performance the
analog inputs should be driven differentially. For cost
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
229876fa
15
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
sensitive applications, the analog inputs can be driven
single-ended with slightly worse harmonic distortion. The
CLK input is single-ended. The LTC2298/LTC2297/
LTC2296havetwophasesofoperation, determinedbythe
state of the CLK input pin.
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
outputbytheresidueamplifier.Successivestagesoperate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2298/
LTC2297/LTC2296 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capaci-
tors (CSAMPLE) through NMOS transistors. The capacitors
shownattachedtoeachinput(CPARASITIC)arethesumma-
tion of all other capacitance associated with each input.
WhenCLKislow, theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltageisheldonthesamplingcapacitors.Duringthehold
phase when CLK is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
LTC2298/LTC2297/LTC2296
V
DD
C
C
SAMPLE
4pF
15Ω
15Ω
+
–
A
A
IN
IN
C
PARASITIC
1pF
V
DD
SAMPLE
4pF
C
PARASITIC
1pF
V
DD
CLK
229876 F02
Figure 2. Equivalent Input Circuit
229876fa
16
LTC2298/LTC2297/LTC2296
W U U
APPLICATIO S I FOR ATIO
U
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Single-Ended Input
Figure 3 shows the LTC2298/LTC2297/LTC2296 being
driven by an RF transformer with a center tapped second-
ary. The secondary center tap is DC biased with VCM
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
sourceimpedanceseenbytheADCdoesnotexceed100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies be-
low 1MHz.
+
DNLwillremainunchanged.Forasingle-endedinput,AIN
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differentialdrivercircuit. TheVCM pinmustbebypassedto
ground close to the ADC with a 2.2µF or greater capacitor.
V
CM
2.2µF
0.1µF T1
+
–
25Ω
A
IN
1:1
ANALOG
INPUT
LTC2298
LTC2297
LTC2296
0.1µF
25Ω
25Ω
Input Drive Impedance
12pF
A
As with all high performance, high speed ADCs, the
dynamicperformanceoftheLTC2298/LTC2297/LTC2296
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE);however, thisisnotalwayspossibleandthe
incomplete settling may degrade the SFDR. The sampling
IN
25Ω
T1 = MA/COM ETC1-1T
229876 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. Theadvantageofthismethodisthatitprovideslow
frequencyinputresponse;however,thelimitedgainband-
width of most op amps will limit the SFDR at high input
frequencies.
229876fa
17
LTC2298/LTC2297/LTC2296
W U U
U
APPLICATIO S I FOR ATIO
V
V
CM
CM
2.2µF
2.2µF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
+
+
25Ω
25Ω
12Ω
A
A
IN
IN
ANALOG
INPUT
LTC2298
LTC2297
LTC2296
LTC2298
LTC2297
LTC2296
ANALOG
INPUT
+
+
0.1µF
25Ω
25Ω
T1
8pF
A
CM
12pF
A
–
–
0.1µF
–
–
12Ω
IN
IN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
229876 F04
229876 F06
Figure 4. Differential Drive with an Amplifier
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
V
CM
2.2µF
V
CM
0.1µF
0.1µF
+
A
A
IN
IN
ANALOG
INPUT
LTC2298
2.2µF
LTC2297
LTC2296
1k
1k
25Ω
0.1µF
25Ω
25Ω
0.1µF
+
–
T1
A
IN
IN
ANALOG
INPUT
LTC2298
LTC2297
LTC2296
–
12pF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
229876 F07
25Ω
A
229876 F05
0.1µF
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 5. Single-Ended Drive
V
CM
The25Ωresistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
2.2µF
0.1µF
0.1µF
+
6.8nH
A
IN
IN
ANALOG
INPUT
LTC2298
LTC2297
LTC2296
0.1µF
25Ω
25Ω
T1
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
6.8nH
–
A
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
229876 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
229876fa
18
LTC2298/LTC2297/LTC2296
W U U
APPLICATIO S I FOR ATIO
Reference Operation
U
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Figure 9 shows the LTC2298/LTC2297/LTC2296 refer-
ence circuitry consisting of a 1.5V bandgap reference, a
difference amplifier and switching and control circuit. The
internal voltage reference can be configured for two pin
selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to VCM selects the 1V
range.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
inFigure10.Anexternalreferencecanbeusedbyapplying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
levelasclosetotheconverteraspossible. IftheSENSEpin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
Forthebestchannelmatching, connectanexternalreference
to SENSEA and SENSEB.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
LTC2298/LTC2297/LTC2296
4Ω
1.5V
V
CM
V
CM
1.5V BANDGAP
REFERENCE
1.5V
2.2µF
2.2µF
12k
1V
0.5V
LTC2298
LTC2297
LTC2296
0.75V
12k
SENSE
RANGE
DETECT
AND
1µF
CONTROL
TIE TO V FOR 2V RANGE;
DD
229876 F10
SENSE
REFH
TIE TO V FOR 1V RANGE;
CM
RANGE = 2 • V
FOR
< 1V
SENSE
SENSE
BUFFER
0.5V < V
Figure 10. 1.5V Range ADC
INTERNAL ADC
HIGH REFERENCE
1µF
Input Range
The input range can be set based on the application. The
2Vinputrangewillprovidethebestsignal-to-noiseperfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.8dB. See the Typical Performance Charac-
teristics section.
2.2µF
1µF
0.1µF
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
229876 F09
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or TTL
levelsignal. Asinusoidalclockcanalsobeusedalongwith
a low jitter squaring circuit before the CLK pin (Figure 11).
Figure 9. Equivalent Reference Circuit
229876fa
19
LTC2298/LTC2297/LTC2296
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APPLICATIO S I FOR ATIO
CLEAN
CLEAN
SUPPLY
SUPPLY
4.7µF
4.7µF
FERRITE
BEAD
FERRITE
BEAD
0.1µF
0.1µF
1k
0.1µF
LTC2298
LTC2297
LTC2296
SINUSOIDAL
CLOCK
LTC2298
LTC2297
LTC2296
CLK
CLK
INPUT
100Ω
50Ω 1k
NC7SVU04
229876 F11
229876 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 11. Sinusoidal Single-Ended CLK Drive
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
ThenoiseperformanceoftheLTC2298/LTC2297/LTC2296
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
resultinadditionalaperturejitterthatwillbeRMSsummed
with the inherent ADC aperture jitter.
ETC1-1T
CLK
LTC2298
LTC2297
LTC2296
5pF-30pF
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
DIFFERENTIAL
CLOCK
INPUT
229876 F13
0.1µF
FERRITE
BEAD
V
CM
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to
ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The use
of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω ohm series resistor to act as both a low pass filter
for high frequency noise that may be induced into the
clock line by neighboring digital signals, as well as a
damping mechanism for reflections.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM,wherethenominalpowerlevelmustbeatleast6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
229876fa
20
LTC2298/LTC2297/LTC2296
Table 1. Output Codes vs Input Voltage
Maximum and Minimum Conversion Rates
+
–
A
IN
– A
D13 – D0
D13 – D0
(2’s Complement)
IN
ThemaximumconversionratefortheLTC2298/LTC2297/
LTC2296 is 65Msps (LTC2298), 40Msps (LTC2297), and
25Msps (LTC2296). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2298), 11.8ns
(LTC2297), and 18.9ns (LTC2296) for the ADC internal
circuitrytohaveenoughsettlingtimeforproperoperation.
(2V Range)
OF
(Offset Binary)
>+1.000000V
+0.999878V
+0.999756V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
0.000000V
–0.000122V
–0.000244V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
<–1.000000V
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. Tousetheclockdutycyclestabilizer, theMODEpin
should be connected to 1/3VDD or 2/3VDD using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on of off for
both channels.
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
LTC2298/LTC2297/LTC2296
OV
DD
0.5V
TO 3.6V
ThelowerlimitoftheLTC2298/LTC2297/LTC2296sample
rate is determined by droop of the sample-and-hold cir-
cuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junc-
tion leakage will discharge the capacitors. The specified
minimumoperatingfrequencyfortheLTC2298/LTC2297/
LTC2296 is 1Msps.
V
V
DD
DD
0.1µF
OV
DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
229876 F14
DIGITAL OUTPUTS
Figure 14. Digital Output Buffer
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Aswithallhighspeed/highresolutionconverters, thedigi-
tal output loading can affect the performance. The digital
outputsoftheLTC2298/LTC2297/LTC2296shoulddrivea
minimal capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
229876fa
21
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Output Enable
Theoutputsmaybedisabledwiththeoutputenablepin,OE.
OEhighdisablesalldataoutputsincludingOF.Thedataac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration.TheoutputHi-Zstateisintendedforuseduringlong
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2298/LTC2297/LTC2296
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 2 shows the logic
states for the MODE pin.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normaloperation. ConnectingSHDNtoVDD andOEtoVDD
results in sleep mode, which powers down all circuitry
includingthereferenceandtypicallydissipates1mW.When
exiting sleep mode it will take milliseconds for the output
datatobecomevalidbecausethereferencecapacitorshave
torechargeandstabilize. ConnectingSHDNtoVDD andOE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on,sothatrecoveryfromnapmodeisfasterthanthatfrom
sleepmode,typicallytaking100clockcycles.Inbothsleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stabilizer
0
Offset Binary
Off
On
On
Off
1/3V
2/3V
Offset Binary
DD
DD
2’s Complement
2’s Complement
V
DD
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
ChannelBiscontrolledbySHDNBandOEB.Thenap,sleep
andoutputenablemodesofthetwochannelsarecompletely
independent, so it is possible to have one channel operat-
ing while the other channel is in nap or sleep mode.
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example,iftheconverterisdrivingaDSPpoweredbya1.8V
supply,thenOVDD shouldbetiedtothatsame1.8Vsupply.
Digital Output Multiplexer
ThedigitaloutputsoftheLTC2298/LTC2297/LTC2296can
be multiplexed onto a single data bus. The MUX pin is a
digitalinputthatswapsthetwodatabusses.IfMUXisHigh,
ChannelAcomesoutonDA0-DA13,OFA;ChannelBcomes
out on DB0-DB13, OFB. If MUX is Low, the output busses
areswappedandChannelAcomesoutonDB0-DB13,OFB;
ChannelBcomesoutonDA0-DA13,OFA.Tomultiplexboth
channelsontoasingleoutputbus,connectMUX,CLKAand
CLKBtogether(seetheTimingDiagramforthemultiplexed
mode). The multiplexed data is available on either data
OVDD can be powered with any voltage from 500mV up to
3.6V.OGNDcanbepoweredwithanyvoltagefromGNDup
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
bus—the unused data bus can be disabled with its OE pin.
229876fa
22
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
Grounding and Bypassing
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The LTC2298/LTC2297/LTC2296 requires a printed cir-
cuit board with a clean, unbroken ground plane. A multilayer
board with an internal ground plane is recommended.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track or under-
neath the ADC.
High quality ceramic bypass capacitors should be used at
theVDD, OVDD, VCM, REFH, andREFLpins. Bypasscapaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
thefilterandtheADC. Ifyouaresensitivetoclose-inphase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
todrivedigitaldevicessuchasanFPGA, youshouldlocate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the driver to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
TheLTC2298/LTC2297/LTC2296differentialinputsshould
run parallel and close to each other. The input traces
should be as short as possible to minimize capacitance
and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2298/LTC2297/
LTC2296 is transferred from the die through the bottom-
side exposed pad and package leads onto the printed
circuit board. For good electrical and thermal perfor-
mance, the exposed pad should be soldered to a large
grounded pad on the PC board. It is critical that all ground
pins are connected to a ground plane of sufficient area.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
229876fa
23
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
D D
D D
O V
O V
O G N D
3 2
4 9
O G N D
3 1
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
D A 8
D A 9
D A 1 0
D B 6
3 0
D B 5
2 9
D B 4
2 8
D A 1 1
D A 1 2
D A 1 3
D B 3
2 7
D B 2
2 6
D B 1
2 5
O F A
O E A
S H D N A
D B 0
2 4
O E B
2 3
S H D N B
2 2
M O D E
V C M A
M U X
2 1
V C M B
2 0
S E N S E A
S E N S E B
1 9
D D
V
D D
V
G N D
1 8
G N D
1 7
229876fa
24
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
Silkscreen Top
Top Side
229876fa
25
LTC2298/LTC2297/LTC2296
U
W U U
APPLICATIO S I FOR ATIO
Inner Layer 3 Power
Inner Layer 2 GND
Bottom Side
229876fa
26
LTC2298/LTC2297/LTC2296
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
(UP64) QFN 1003
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
229876fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC2298/LTC2297/LTC2296
RELATED PARTS
PART NUMBER
LTC1748
DESCRIPTION
COMMENTS
14-Bit, 80Msps 5V ADC
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
Up to 500MHz IF Undersampling, 90dB SFDR
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
LTC1750
LT®1993-2
14-Bit, 80Msps, 5V Wideband ADC
High Speed Differential Op Amp
LT1994
Low Noise, Low Distortion Fully Differential Input/Output
Amplifier/Driver
LTC2202
LTC2208
LTC2220-1
LTC2224
LTC2255
LTC2280
LTC2282
LTC2284
LTC2286
LTC2287
LTC2288
LTC2289
LTC2290
LTC2291
LTC2292
LTC2293
LTC2294
LTC2295
LTC2296
LTC2297
LTC2298
LTC2299
LT5512
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
320mW, 61.6dB SNR, 85dB SFDR, 64-Pin QFN
540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
150mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN
235mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN
400mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN
422mW, 61.6dB SNR, 85dB SFDR, 64-Pin QFN
120mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN
150mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN
235mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN
400mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN
422mW, 70.6dB SNR, 90dB SFDR, 64-Pin QFN
120mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN
150mW, 74.5dB SNR, 90dB SFDR, 64-Pin QFN
235mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN
400mW, 74.3dB SNR, 90dB SFDR, 64-Pin QFN
444mW, 73dB SNR, 90dB SFDR, 64-Pin QFN
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
14-Bit, 125Msps, 3V ADC, Lowest Power
10-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
10-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
10-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
10-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
10-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
12-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
14-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
DC-3GHz High Signal Level Downconverting Mixer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB
in 1.5dB/Step
LT5515
LT5516
LT5517
LT5522
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω
Single Ended RF and LO Ports
229876fa
RD/LT 0106 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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