LTC2302CDDXPBF [Linear]
Low Noise, 500ksps, 1-/2-Channel, 12-Bit ADCs; 低噪声， 500KSPS ， 1 / 2通道，12位ADC
| 型号： | LTC2302CDDXPBF |
| 厂家： | 
Linear |
| 描述： | Low Noise, 500ksps, 1-/2-Channel, 12-Bit ADCs |
| 文件： | 总20页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2302/LTC2306
Low Noise, 500ksps,
1-/2-Channel, 12-Bit ADCs
FEATURES
DESCRIPTION
TheLTC®2302/LTC2306arelownoise,500ksps,1-/2-chan-
nel, 12-bit ADCs with an SPI/MICROWIRE compatible
serial interface. These ADCs include a fully differential
sample-and-hold circuit to reduce common mode noise.
The internal conversion clock allows the external serial
output data clock (SCK) to operate at any frequency up
to 40MHz.
n
12-Bit Resolution
n
500ksps Sampling Rate
n
Low Noise: SINAD = 72.8dB
n
Guaranteed No Missing Codes
n
Single 5V Supply
n
Auto-Shutdown Scales Supply Current with Sample
Rate
n
Low Power: 14mW at 500ksps
The LTC2302/LTC2306 operate from a single 5V supply
and draw just 2.8mA at a sample rate of 500ksps. The
auto-shutdownfeaturereducesthesupplycurrentto14μA
at a sample rate of 1ksps.
70μW at 1ksps
35μW Sleep Mode
n
1-Channel (LTC2302) and 2-Channel (LTC2306)
Versions
n
The LTC2302/LTC2306 are packaged in a tiny 10-pin 3mm
× 3mm DFN. The low power consumption and small size
make the LTC2302/LTC2306 ideal for battery-operated
and portable applications, while the 4-wire SPI compat-
ible serial interface makes these ADCs a good match for
isolated or remote data acquisition systems.
Unipolar or Bipolar Input Ranges (Software
Selectable)
Internal Conversion Clock
n
n
n
n
n
™
SPI/MICROWIRE Compatible Serial Interface
Separate Output Supply OV (2.7V to 5.25V)
DD
Software Compatible with the LTC2308
10-Pin (3mm × 3mm) DFN Package
NUMBER OF INPUT CHANNELS
1
2
8
TYPE
APPLICATIONS
Int Reference
Ext Reference
LTC2308
LTC2302
LTC2306
n
High Speed Data Acquisition
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Industrial Process Control
n
Motor Control
n
Accelerometer Measurements
n
Battery-Operated Instruments
n
Isolated and/or Remote Data Acquisition
TYPICAL APPLICATION
8192 Point FFT, f = 1kHz (LTC2306)
IN
5V
0
–10
2.7V TO 5.25V
f
= 500kHz
SMPL
10μF
0.1μF
0.1μF
SINAD = 72.8dB
THD = –88.7dB
–20
–30
LTC2302
LTC2306
–40
–50
V
DD
OV
DD
–60
SDI
–70
–80
–90
–100
–110
–120
–130
–140
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
2.048V BIPOLAR
+
ANALOG
INPUT
MUX
CH0 (IN )
12-BIT
500ksps
ADC
+
–
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTER
SDO
SERIAL
PORT
–
CH1 (IN )
SCK
CONVST
V
REF
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
GND
0.1μF
10μF
0
50
100
150
200
250
23026 TA01
FREQUENCY (kHz)
23026 TA01b
23026f
1
LTC2302/LTC2306
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Digital Output Voltage ... (GND – 0.3V) to (OV + 0.3V)
Supply Voltage (V , OV )......................... –0.3V to 6V
DD
DD
DD
Power Dissipation...............................................500mW
Analog Input Voltage (Note 3)
+
–
Operating Temperature Range
CH0(IN )-CH1(IN ),
LTC2302C/LTC2306C ............................... 0°C to 70°C
LTC2302I/LTC2306I.............................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
REF ..............................(GND – 0.3V) to (V + 0.3V)
DD
Digital Input Voltage
(Note 3).............................(GND – 0.3V) to (V + 0.3V)
DD
PIN CONFIGURATION
LTC2302
LTC2306
TOP VIEW
TOP VIEW
SDO
1
2
3
4
5
10 OV
SDO
1
2
3
4
5
10 OV
DD
DD
CONVST
9
8
7
6
SCK
SDI
GND
CONVST
9
8
7
6
SCK
SDI
GND
11
11
V
V
DD
DD
+
IN
CH0
CH1
–
IN
V
REF
V
REF
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
T
= 150°C, θ = 43°C/W
T
= 150°C, θ = 43°C/W
JMAX
JA
JMAX JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2302CDD#PBF
LTC2302IDD#PBF
LTC2306CDD#PBF
LTC2306IDD#PBF
TAPE AND REEL
PART MARKING*
LDGV
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2302CDD#TRPBF
LTC2302IDD#TRPBF
LTC2306CDD#TRPBF
LTC2306IDD#TRPBF
0°C to 70°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
LDGV
–40°C to 85°C
0°C to 70°C
LDGW
LDGW
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
23026f
2
LTC2302/LTC2306
CONVERTER AND MULTIPLEXER CHARACTERISTICS The
l
denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4, 5)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
12
(Note 6)
0.3
0.25
1
1
1
6
LSB
Differential Linearity Error
Bipolar Zero Error
LSB
(Note 7)
LSB
Bipolar Zero Error Drift
0.002
1
LSB/°C
LSB
l
Unipolar Zero Error
(Note 7)
6
Unipolar Zero Error Drift
Unipolar Zero Error Match (LTC2306)
Bipolar Full-Scale Error
0.002
0.3
LSB/°C
LSB
3
8
l
l
(Note 8)
(Note 8)
1.5
LSB
Bipolar Full-Scale Error Drift
Unipolar Full-Scale Error
Unipolar Full-Scale Error Drift
Unipolar Full-Scale Error Match (LTC2306)
0.05
1.2
LSB/°C
LSB
6
3
0.05
0.3
LSB/°C
LSB
ANALOG INPUT The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
l
V
IN
V
IN
Absolute Input Range (CH0, CH1, IN )
(Note 9)
–0.05
V
V
DD
–
–
l
l
Absolute Input Range (CH0, CH1, IN )
Unipolar (Note 9)
Bipolar (Note 9)
–0.05
–0.05
V
/2
V
V
DD
V
DD
+
–
+
–
–
l
l
V
IN
– V
Input Differential Voltage Range
V
IN
V
IN
= V – V (Unipolar)
0 to V
REF
V
V
IN
IN
IN
+
= V – V (Bipolar)
V
/2
REF
IN
IN
l
I
Analog Input Leakage Current
Analog Input Capacitance
1
μA
IN
C
Sample Mode
Hold Mode
55
5
pF
pF
IN
CMRR
Input Common Mode Rejection Ratio
70
dB
REFERENCE INPUT The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
Input Range
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
0.1
V
DD
V
REF
l
l
I
Reference Input Current
f
f
= 0ksps, V = 4.096V
50
230
80
260
μA
μA
REF
SMPL
SMPL
REF
= 500ksps, V = 4.096V
REF
C
REF
Reference Input Capacitance
55
pF
23026f
3
LTC2302/LTC2306
DYNAMIC ACCURACY The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Notes 4, 10)
A
IN
SYMBOL
SINAD
SNR
PARAMETER
CONDITIONS
MIN
71
TYP
72.8
73.2
–88
89
MAX
UNITS
dB
l
l
l
l
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
IN
f
IN
f
IN
f
IN
f
IN
= 1kHz
= 1kHz
71
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Full Linear Bandwidth
= 1kHz, First 5 Harmonics
–78
dB
SFDR
= 1kHz
= 1kHz
79
dB
–109
700
25
dB
(Note 11)
kHz
MHz
ns
–3dB Input Linear Bandwidth
Aperature Delay
13
Transient Response
Full-Scale Step
240
ns
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Digital Input Capacitance
High Level Output Voltage
V
V
V
= 5.25V
= 4.75V
2.4
V
V
IH
IL
DD
DD
IN
0.8
10
I
IN
= V
μA
pF
DD
C
V
5
IN
OV = 4.75V, I
OV = 4.75V, I
= –10μA
= –200μA
4.74
V
V
OH
DD
DD
OUT
OUT
l
4
V
Low Level Output Voltage
OV = 4.75V, I
DD
= 160μA
= 1.6mA
0.05
V
V
OL
DD
OUT
OUT
l
l
OV = 4.75V, I
0.4
10
I
OZ
Hi-Z Output Leakage
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
V
OUT
= 0V to OV , CONVST High
μA
pF
DD
C
OZ
CONVST High
15
–10
10
I
I
V
OUT
V
OUT
= 0V
= OV
mA
mA
SOURCE
SINK
DD
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
4.75
2.7
TYP
MAX
5.25
5.25
UNITS
l
l
V
Supply Voltage
5
V
V
DD
OV
Output Driver Supply Voltage
DD
l
l
I
DD
Supply Current
Sleep Mode
C = 25pF
2.8
7
3.5
15
mA
μA
L
CONVST = 5V, Conversion Done
P
Power Dissipation
Sleep Mode
14
35
mW
μW
D
23026f
4
LTC2302/LTC2306
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
500
40
UNITS
kHz
MHz
ns
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Shift Clock Frequency
CONVST High Time
SMPL(MAX)
SCK
(Note 9)
20
2.5
0
WHCONV
HD
ns
Hold Time SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
ns
SUDI
WHCLK
WLCLK
WLCONVST
HCONVST
CONV
ACQ
f
f
= f
= f
10
10
410
20
ns
SCK
SCK
SCK(MAX)
SCK(MAX)
SCK Low Time
ns
CONVST Low Time During Data Transfer (Note 9)
ns
(Note 9)
ns
Hold Time CONVST Low After Last SCK↓
Conversion Time
1.3
1.6
μs
Acquisition Time
240
4
ns
7th SCK↑ to CONVST↑ (Note 9)
C = 25pF (Note 9)
L
10.8
12.5
ns
SDO Data Valid After SCK↓
SDO Hold Time SCK↓
SDO Valid After CONVST↓
Bus Relinquish Time
SDO Rise Time
dDO
C = 25pF
L
ns
hDO
C = 25pF
L
11
11
4
15
15
ns
en
C = 25pF
L
ns
dis
C = 25pF
L
ns
r
SDO Fall Time
C = 25pF
L
4
ns
f
Total Cycle Time
2
μs
CYC
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with V and OV
DD
DD
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above V without latchup.
,
DD
DD
Note 9: Guaranteed by design, not subject to test.
Note 4: V = 5V, OV = 5V, V = 4.096V, f
= 500ksps, unless
DD
DD
REF
SMPL
Note 10: All specifications in dB are referred to a full-scale 2.048V input
otherwise specified.
with a 4.096V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 5: Linearity, offset and full-scale specifications apply for a single-
+
ended analog input with respect to GND for the LTC2306 and IN with
–
respect to IN tied to GND for the LTC2302.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
23026f
5
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2302) T = 25°C, V = OV = 5V, V
= 4.096V, f
= 500ksps, unless otherwise noted.
SMPL
A
DD
DD
REF
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1kHz Sine Wave
8192 Point FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
SNR = 73.2dB
SINAD = 72.8dB
THD = –89.5dB
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–90
–100
–110
–120
–130
–140
50
100
150
250
0
200
2048
2048
0
1024
3072
4096
0
1024
3072
4096
FREQUENCY (kHz)
OUTPUT CODE
OUTPUT CODE
23026 G03
23026 G01
23026 G02
SINAD vs Input Frequency
THD vs Input Frequency
SNR vs Input Frequency
80
75
70
65
60
55
50
80
75
70
65
60
55
50
–60
–65
–70
–75
–80
–85
–90
–95
–100
1
10
100
1000
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
23026 G06
23026 G04
23026 G05
Supply Current vs
Sampling Frequency
Supply Current vs Temperature
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–50
0
25
50
75 100 125
–25
1
10
100
1000
TEMPERATURE (°C)
SAMPLING FREQUENCY (ksps)
23026 G07
23026 G08
23026f
6
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2302) T = 25°C, V = OV = 5V, V
= 4.096V, f
= 500ksps, unless otherwise noted.
A
DD
DD
REF
SMPL
Analog Input Leakage Current vs
Temperature
Sleep Current vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
10
9
8
7
6
5
4
3
2
1
0
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
23026 G10
23026 G09
Offset Error vs Temperature
Full-Scale Error vs Temperature
2.0
2.5
2.0
1.5
1.0
BIPOLAR
1.5
1.0
UNIPOLAR
0.5
0
BIPOLAR
0.5
0
UNIPOLAR
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
–2.0
–25
0
50
75 100 125
–50
25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
23026 G12
23026 G11
23026f
7
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2306) T = 25°C, V = OV = 5V, V
= 4.096V, f
= 500ksps, unless otherwise noted.
SMPL
A
DD
DD
REF
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1kHz Sine Wave
8192 Point FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
–80
–90
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–110
–120
–130
–140
50
100
150
250
2048
2048
0
200
0
1024
3072
4096
0
1024
3072
4096
FREQUENCY (kHz)
OUTPUT CODE
OUTPUT CODE
23026 G15
23026 G13
23026 G14
SNR vs Input Frequency
SINAD vs Input Frequency
THD vs Input Frequency
80
75
70
65
60
55
50
–60
–65
–70
–75
–80
–85
–90
–95
–100
80
75
70
65
60
55
50
1
10
100
1000
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
23026 G18
23026 G16
23026 G17
Supply Current vs
Sampling Frequency
Supply Current vs Temperature
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1
10
100
1000
–50
0
25
50
75
125
–25
100
TEMPERATURE (°C)
SAMPLING FREQUENCY (ksps)
23026 G19
23026 G20
23026f
8
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2306) T = 25°C, V = OV = 5V, V
= 4.096V, f
= 500ksps, unless otherwise noted.
A
DD
DD
REF
SMPL
Analog Input Leakage Current vs
Temperature
Sleep Current vs Temperature
10
9
8
7
6
5
4
3
2
1
0
1000
900
800
700
600
500
400
300
200
100
0
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
23026 G21
23026 G22
Offset Error vs Temperature
Full-Scale Error vs Temperature
2.0
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
UNIPOLAR
BIPOLAR
UNIPOLAR
BIPOLAR
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
–2.0
–2.0
–25
0
50
75 100 125
–50
25
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
23026 G23
23026 G24
23026f
9
LTC2302/LTC2306
PIN FUNCTIONS
LTC2302
LTC2306
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
conversion starts or after the conversion ends
.
V
(Pin3):5VSupply. TherangeofV is4.75Vto5.25V.
DD
V
(Pin3):5VSupply. TherangeofV is4.75Vto5.25V.
DD
DD
DD
Bypass V to GND with a 0.1μF ceramic capacitor and a
Bypass V to GND with a 0.1μF ceramic capacitor and a
DD
DD
10μF tantalum capacitor in parallel.
10μF tantalum capacitor in parallel.
+
–
+
–
CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog
Inputs. CH0, CH1 can be configured as single-ended or
differential input channels. See the Analog Input Multi-
plexer section.
IN , IN (Pin 4, Pin 5): Positive (IN ) and Negative (IN )
Differential Analog Inputs.
V
(Pin 6): Reference Input. Connect an external refer-
REF
ence at V . The range of the external reference is 0.1V
REF
V
(Pin 6): Reference Input. Connect an external refer-
to V . Bypass to GND with a minimum 10μF tantalum
REF
DD
ence at V .The range of the external reference is 0.1V
capacitor in parallel with a 0.1μF ceramic capacitor.
REF
to V . Bypass to GND with a minimum 10μF tantalum
capacitor in parallel with a 0.1μF ceramic capacitor.
DD
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OV (Pin 10): Output Driver Supply. Bypass OV to
DD
DD
GND with a 0.1μF ceramic capacitor close to the pin. The
OV (Pin 10): Output Driver Supply. Bypass OV to
range of OV is 2.7V to 5.25V.
DD
DD
DD
OGND with a 0.1μF ceramic capacitor close to the pin.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
The range of OV is 2.7V to 5.5V.
DD
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
23026f
10
LTC2302/LTC2306
BLOCK DIAGRAM
V
OV
DD
DD
LTC2302
LTC2306
SDI
+
ANALOG
INPUT
MUX
CH0 (IN )
12-BIT
500ksps
ADC
+
–
SDO
SERIAL
PORT
–
CH1 (IN )
SCK
CONVST
V
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
REF
23026 BD
GND
TEST CIRCUITS
Load Circuit for t Waveform 1
Load Circuit for t Waveform 2, t
dis en
dis
V
DD
3k
SDO
TEST POINT
L
SDO
TEST POINT
C
L
C
3k
23026 TC01
23026 TC02
TIMING DIAGRAMS
Voltage Waveforms for SDO Delay Times, t
and t
Voltage Waveforms for t
dis
dDO
hDO
SCK
V
IH
CONVST
V
IL
t
dDO
t
SDO
WAVEFORM 1
(SEE NOTE 1)
hDO
90%
10%
V
V
OH
OL
SDO
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
23026 TD01
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
23026 TD02
23026f
11
LTC2302/LTC2306
TIMING DIAGRAMS
t
(SCK Low Time)
(SCK High Time)
Voltage Waveforms for t
en
WLCLK
WHCLK
t
t
(Hold Time SDI After SCK↑)
HD
CONVST
SDO
t
(Setup Time SDI Stable Before SCK↑)
SUDI
t
t
WHCLK
23026 TD04
WLCLK
t
en
SCK
t
HD
Voltage Waveforms for SDO Rise and Fall Times t, t
r
f
SDI
23026 TD03
t
SUDI
V
OH
SDO
V
OL
t
r
t
23004 TD05
f
APPLICATIONS INFORMATION
Overview
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
TheLTC2302/LTC2306arelownoise,500ksps,1-/2-chan-
nel, 12-bit successive approximation register (SAR) A/D
converters. The LTC2306 includes a 2-channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI-compatible se-
rial port for easy data transfers and can operate in either
unipolar or bipolar mode. Unipolar mode should be used
forsingle-endedoperationwiththeLTC2306,sincesingle-
ended input signals are always referenced to GND. The
LTC2302/LTC2306 can be put into a power-down sleep
mode during idle periods to save power.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DACusingadifferentialcomparator.Attheendofaconver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
Programming the LTC2306 and LTC2302
restarted. Between conversions, a 6-bit input word (D )
IN
ThesoftwarecompatibleLTC2302/LTC2306/LTC2308fam-
at the SDI input configures the MUX and programs vari-
ily features a 6-bit D word to program various modes of
ous modes of operation. As the D bits are shifted in,
IN
IN
operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the first rising edge (see Figure 6 in the Timing
data from the previous conversion is shifted out on SDO.
After the 6 bits of the D word have been shifted in, the
IN
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
23026f
12
LTC2302/LTC2306
APPLICATIONS INFORMATION
and Control section). The input data word for the LTC2306
is defined as follows:
Table 1. Channel Configuration
for the LTC2306
S/D O/S CH0 CH1
S/D O/S
X
X
UNI
X
0
0
1
1
0
1
0
1
+
–
+
–
+
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
WITH RESPECT
TO GND
+
NOTE: UNIPOLAR MODE SHOULD BE USED
FOR SINGLE-ENDED OPERATION, SINCE INPUT
SIGNALS ARE ALWAYS REFERENCED TO GND
UNI = UNIPOLAR/BIPOLAR BIT
X = DON’T CARE
For the LTC2302, the input data word is defined as:
Table 2. Channel Configuration
for the LTC2302
X
O/S
X
X
UNI
X
+
–
O/S IN
IN
0
1
+
–
+
Analog Input Multiplexer
–
The analog input MUX is programmed by the S/D and O/S
Driving the Analog Inputs
bits of the D word for the LTC2306 and the O/S bit of the
IN
D word for the LTC2302. Table 1 and Table 2 list MUX
The analog inputs of the LTC2302/LTC2306 are easy to
drive. Each of the analog inputs of the LTC2306 (CH0
and CH1) can be used as a single-ended input relative
to GND or as a differential pair. The analog inputs of the
IN
configurations for all combinations of the configuration
bits.Figure1ashowsseveralpossibleMUXconfigurations
and Figure 1b shows how the MUX can be reconfigured
from one conversion to the next.
+
–
LTC2302 (IN , IN ) are always configured as a differential
pair. Regardless of the MUX configuration, the “+” and “–”
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample-and-hold cir-
cuit. The inputs draw only one small current spike while
1 Differential
2 Single-Ended
CH0
CH1
+ (
)
)
CH0
CH1
+
+
–
{
(
+
–
LTC2306
LTC2306
(–) GND
1st Conversion
2nd Conversion
CH0
CH1
+
–
CH0
CH1
+
+
{
1 Differential
LTC2306
LTC2306
+
IN
IN
+ (
)
)
–
+
–
{
(
–
(–) GND
LTC2302
23026 F01b
Figure 1b. Changing the MUX Assignment “On the Fly”
23026 F01a
Figure 1a. Example MUX Configurations
23026f
13
LTC2302/LTC2306
APPLICATIONS INFORMATION
chargingthesample-and-holdcapacitorsduringtheacquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
drivingcircuitislow, theADCinputscanbedrivendirectly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
should be filtered prior to the analog inputs to minimize
noise. A simple 1-pole RC filter is sufficient for many
applications.
TheanaloginputsoftheLTC2302/LTC2306canbemodeled
as a 55pF capacitor (C ) in series with a 100Ω resistor
IN
(R ) as shown in Figure 2a. C gets switched to the
ON
IN
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
Reference
A low noise, stable reference is required to ensure full
performance. The LT®1790 and LT6660 are adequate
for most applications. The LT6660 is available in 2.5V,
3V, 3.3V and 5V versions, and the LT1790 is available in
1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions. The
exceptionally low input noise allows the input range to be
optimized for the application by changing the reference
12-bit resolution within the acquisition time (t ) if DC
ACQ
accuracy is important.
When using a filter with a large C
value (e.g., 1μF),
FILTER
theinputsdonotcompletelysettleandthecapacitiveinput
switching currents are averaged into a net DC current
voltage. The V
input must be decoupled with a 10μF
REF
(I ). In this case, the analog input can be modeled by
DC
capacitor in parallel with a 0.1μF capacitor, so verify that
the device providing the reference voltage is stable with
capacitive loads.
an equivalent resistance (R = 1/(f
• C )) in series
EQ
SMPL
IN
with an ideal voltage source (V /2) as shown in Figure
REF
2b. ThemagnitudeoftheDCcurrentisthenapproximately
If the voltage reference is 5V and can supply 5mA, it can
I
= (V – V /2)/R , which is roughly proportional
DC
IN REF EQ
be used for both V
and V . V must be connected
REF
DD DD
to V . To prevent large DC drops across the resistor
IN
to a clean analog supply, and a quiet 5V reference voltage
R
, a filter with a small resistor and large capacitor
FILTER
makes a convenient supply for this purpose.
should be chosen. When running at the minimum cycle
time of 2μs, the input current equals 106μA at V = 5V,
IN
Input Filtering
which amounts to a full-scale error of 0.5LSB when using
a filter resistor (R
) of 4.7Ω. Applications requiring
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
FILTER
lower sample rates can tolerate a larger filter resistor for
the same amount of full-scale error.
LTC2302
LTC2306
INPUT
LTC2302
(CH0, CH1
INPUT
LTC2306
+
–
I
IN , IN )
(CH0, CH1
DC
R
FILTER
R
+
–
ON
IN , IN )
R
V
100Ω
SOURCE
IN
R
V
EQ
IN
C
FILTER
C
1/(f
• C )
SMPL IN
IN
C1
55pF
+
V
/2
REF
–
23026 F02a
23026 F02b
Figure 2b. Analog Input Equivalent Circuit for
Large Filter Capacitances
Figure 2a. Analog Input Equivalent Circuit
23026f
14
LTC2302/LTC2306
APPLICATIONS INFORMATION
Figures 3a and 3b show respective examples of input
filtering for single-ended and differential inputs. For the
single-ended case in Figure 3a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica type
dielectriccapacitorshaveexcellentlinearity.Carbonsurface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 4 shows a typical SINAD of 72.8dB with
a500kHzsamplingrateanda1kHzinput. ASNRof73.2dB
can be achieved with the LTC2302/LTC2306.
0
–10
–20
–30
–40
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
Dynamic Performance
–50
FFT(fastfouriertransform)testtechniquesareusedtotest
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
andanalyzingthedigitaloutputusinganFFTalgorithm,the
ADC’s spectral content can be examined for frequencies
outside the fundamental.
–60
–70
–80
–90
–100
–110
–120
–130
–140
50
100
150
250
0
200
FREQUENCY (kHz)
50Ω
ANALOG
INPUT
23026 F04
CH0, CH1
5V
2000pF
0.1μF
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot (LTC2306)
LTC2306
V
IN
LT1790A-4.096
Total Harmonic Distortion (THD)
V
V
OUT
REF
10μF
0.1μF
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
bandbetweenDCandhalfthesamplingfrequency(f
THD is expressed as:
23026 F03a
Figure 3a. Optional RC Input Filtering for Single-Ended Input
/2).
SMPL
1000pF
2
50Ω
V22 + V32 + V42...+ VN
+
CH0, IN
THD = 20log
5V
DIFFERENTIAL
V1
LTC2302
LTC2306
–
ANALOG
INPUTS
1000pF
50Ω
0.1μF
V
IN
CH1, IN
where V is the RMS amplitude of the fundamental fre-
quencyandV throughV aretheamplitudesofthesecond
1
1000pF
LT1790A-4.096
2
N
V
V
OUT
REF
through Nth harmonics.
10μF
0.1μF
23026 F03b
Figure 3b. Optional RC Input Filtering for Differential Inputs
23026f
15
LTC2302/LTC2306
APPLICATIONS INFORMATION
Internal Conversion Clock
Example 2 (Figure 7) shows CONVST returning low be-
fore the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conver-
sion is complete, the MSB of the output data sequence
at SDO becomes valid after the data bus is enabled. At
The internal conversion clock is factory trimmed to
achieve a typical conversion time (t ) of 1.3ꢀs and a
CONV
maximum conversion time of 1.6ꢀs over the full operating
temperature range. With a minimum acquisition time of
240ns, a throughput sampling rate of 500ksps is tested
and guaranteed.
this point(t
1.3μs after the rising edge of CONVST),
CONV
pulsing SCK will shift data out at SDO and load configura-
tion data (D ) into the LTC2302/LTC2306 at SDI. The first
IN
SCK rising edge loads the S/D bit. SDO transitions on the
Digital Interface
falling edge of each SCK pulse.
The LTC2302/LTC2306 communicate via a standard
4-wire SPI compatible digital interface. The rising edge
of CONVST initiates a conversion. After the conversion
is finished, pull CONVST low to enable the serial output
(SDO). The ADC then shifts out the digital data in 2’s
complement format when operating in bipolar mode or
in straight binary format when in unipolar mode, based
on the setting of the UNI bit.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings or in straight
binary for unipolar readings.
Sleep Mode
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (t ). The supply cur-
CONV
For best performance, ensure that CONVST returns low
within40nsaftertheconversionstarts(i.e.,beforethefirst
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
rentdecreasesto7ꢀAinsleepmodebetweenconversions,
thereby reducing the average power dissipation as the
sampleratedecreases.Forexample,theLTC2302/LTC2306
draw an average of 14μA with a 1ksps sampling rate. The
LTC2302/LTC2306 power down all circuitry when in sleep
mode.
Timing and Control
Board Layout and Bypassing
The start of a conversion is triggered by the rising edge
of CONVST. Once initiated, a new conversion cannot be
restarteduntilthecurrentconversioniscomplete.Figures6
and7showthetimingdiagramsfortwodifferentexamples
of CONVST pulses. Example 1 (Figure 6) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
Toobtainthebestperformance,aprintedcircuitboardwith
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal.
All analog inputs should be shielded by GND. V
and
REF
after the t
period, the LTC2302/LTC2306 enter sleep
CONV
V
should be bypassed to the ground plane as close to
DD
mode (see Sleep Mode for more details).
the pin as possible. Maintaining a low impedance path
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 5 for a
suggested layout.
When CONVST returns low, the ADC wakes up and the
most significant bit (MSB) of the output data sequence at
SDO becomes valid after the serial data bus is enabled. All
other data bits from SDO transition on the falling edge of
eachSCKpulse. Configurationdata(D )isloadedintothe
IN
LTC2302/LTC2306 at SDI, starting with the first SCK rising
edge after CONVST returns low. The S/D bit is loaded on
the first SCK rising edge.
23026f
16
LTC2302/LTC2306
APPLICATIONS INFORMATION
V
, BYPASS
DD
INPUT FILTER
CAPACITORS
0.1μF||10μF, 0603
SOLID GROUND
PLANE
OV , BYPASS
DD
0.1μF, 0603
23026 F05
V
, BYPASS
REF
0.1μF||10μF 0603
Figure 5. Suggested Layout
t
WLCONVST
t
ACQ
CONVST
t
SLEEP
CONV
t
CYC
1
2
3
4
5
6
7
8
9
10 11 12
SCK
SDI
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
S/D O/S
MSB
UNI
LSB
Hi-Z
Hi-Z
SDO
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
23026 F06
Figure 6. LTC2302/LTC2306 Timing with a Long CONVST Pulse
23026f
17
LTC2302/LTC2306
APPLICATIONS INFORMATION
t
t
HCONVST
WHCONV
t
ACQ
CONVST
t
CYC
t
CONV
1
2
3
4
5
6
7
8
9
10 11 12
SCK
SDI
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
S/D O/S
UNI
MSB
B11
LSB
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Hi-Z
Hi-Z
SDO
23026 F07
Figure 7. LTC2302/LTC2306 Timing with a Short CONVST Pulse
011...111
011...110
111...111
BIPOLAR
ZERO
111...110
000...001
000...000
111...111
111...110
100...001
100...000
011...111
011...110
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2
FS = 4.096V
1LSB = FS/2
100...001
100...000
000...001
000...000
N
N
1LSB = 1mV
1LSB = 1mV
–1 0V
LSB
INPUT VOLTAGE (V)
1
–FS/2
FS/2 – 1LSB
0V
FS – 1LSB
LSB
INPUT VOLTAGE (V)
23026 F08
20026 F09
Figure 8. LTC2302/LTC2306 Bipolar Transfer Characteristics
(2’s Complement)
Figure 9. LTC2302/LTC2306 Unipolar Transfer Characteristics
(Straight Binary)
23026f
18
LTC2302/LTC2306
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 0.05
3.50 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50
BSC
2.38 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 0.10
TYP
6
10
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
23026f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2302/LTC2306
TYPICAL APPLICATION
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
10μF
0.1μF
0.1μF
LTC2302
LTC2306
V
OV
DD
DD
SDI
SDO
+
ANALOG
INPUT
MUX
CH0 (IN )
12-BIT
500ksps
ADC
V
CC
+
–
SERIAL
PORT
SCK
–
CH1 (IN )
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
CONVST
PRE
Q
D
NL17SZ74
Q
CLR
CONVERT ENABLE
V
REF
GND
0.1μF
10μF
V
CC
1k
1k
0.1μF
MASTER
CLOCK
RF SIGNAL
GENERATOR
OR OTHER LOW
JITTER SOURCE
23026 TA02
50Ω
NC7SVU04P5X
MASTER
CLOCK
• • • • • •
• • • • • •
• • • • • •
• • • • • •
CONVERT
ENABLE
JITTER
CONVST
• • • • • •
• • • • • •
DATA TRANSFER
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
Low Input Offset: 75μV/125μV
LTC1468/LT1469
LTC1609
Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Op Amps
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
60μA Supply Current, 10ppm/°C, SOT-23 Package
LTC1790
Micropower Low Dropout Reference
LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
LTC1860L/LTC1861L
LTC1863/LTC1867
LTC1863L/LTC1867L
LTC1864/LTC1865
LTC1864L/LTC1865L
LTC2308
10-Bit/12-Bit, 8-channel, 1.25Msps ADCs
10-Bit/12-Bit, 8-channel, 400ksps ADCs
12-Bit, 1-/2-Channel 250ksps ADCs in MSOP
3V, 12-bit, 1-/2-Channel 150ksps ADCs
12-/16-Bit, 8-Channel 200ksps ADCs
3V, 12-/16-bit, 8-Channel 175ksps ADCs
16-Bit, 1-/2-Channel 250ksps ADCs in MSOP
3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP
12-Bit, 8-Channel 500ksps ADC
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
5V, Internal Reference, 4mm × 4mm QFN Packages
23026f
LT 0108 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
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© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC2302IDD#PBF
LTC2302 - Low Noise, 500ksps, 1-/2-Channel, 12-Bit ADC; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
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