LTC2309CUF-PBF [Linear]
8-Channel, 12-Bit SAR ADC with I2C Interface; 8通道， 12位SAR ADC，具有I2C接口
| 型号： | LTC2309CUF-PBF |
| 厂家： | 
Linear |
| 描述： | 8-Channel, 12-Bit SAR ADC with I2C Interface |
| 文件： | 总20页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2309
8-Channel, 12-Bit SAR ADC
2
with I C Interface
FEATURES
DESCRIPTION
The LTC®2309 is a low noise, low power, 8-channel, 12-bit
n
12-Bit Resolution
2
n
successive approximation ADC with an I C compatible
Low Power: 1.5mW at 1ksps, 35μW Sleep Mode
n
serial interface. This ADC includes an internal reference
and a fully differential sample-and-hold circuit to reduce
common mode noise. The LTC2309 operates from an
internal clock to achieve a fast 1.3μs conversion time.
14ksps Throughput Rate
n
Low Noise: SNR = 73.4dB
n
Guaranteed No Missing Codes
n
Single 5V Supply
2
n
2-wire I C Compatible Serial Interface with Nine
The LTC2309 operates from a single 5V supply and
draws just 300μA at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing
the power dissipation.
Addresses Plus One Global for Synchronization
n
Fast Conversion Time: 1.3μs
n
Internal Reference
n
Internal 8-Channel Multiplexer
The LTC2309 is available in a small 24-pin 4mm × 4mm
QFN package. The internal 2.5V reference and 8-channel
multiplexer further reduce PCB board space require-
ments.
n
Internal Conversion Clock
n
Unipolar or Bipolar Input Ranges (Software Selectable)
n
24-Pin 4mm × 4mm QFN Package
APPLICATIONS
The low power consumption and small size make the
LTC2309 ideal for battery-operated and portable applica-
n
Industrial Process Control
2
n
tions,whilethe2-wireI Ccompatibleserialinterfacemakes
Motor Control
n
this ADC a good match for space-constrained systems.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Accelerometer Measurements
Battery-Operated Instruments
Isolated and/or Remote Data Acquisition
n
n
n
Power Supply Monitoring
BLOCK DIAGRAM
5V
10μF
0.1μF
0.1μF
10μF
Integral Nonlinearity
vs Output Code
AV
DD
DV
DD
1.00
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
AD1
LTC2309
AD0
0.75
0.50
0.25
0
ANALOG
INPUT
MUX
SCL
SDA
+
–
2
12-BIT
SAR ADC
I C
ANALOG INPUTS
0V TO 4.096V UNIPOLAR
2.048V BIPOLAR
PORT
–0.25
–0.50
–0.75
–1.00
V
REF
INTERNAL
2.5V REF
2.2μF
2048
0
1024
3072
4096
REFCOMP
OUTPUT CODE
GND
0.1μF
10μF
2309 G01
2309 TA01
2309f
1
LTC2309
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
Supply Voltage (AV , DV ) ...................... –0.3V to 6V
DD
DD
Analog Input Voltage (Note 3)
TOP VIEW
CH0-CH7, COM, V
,
REF
REFCOMP...................(GND – 0.3V) to (AV + 0.3V)
DD
24 23 22 21 20 19
Digital Input Voltage (Note 3).................(GND – 0.3V) to
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
18 GND
(DV + 0.3V)
DD
SDA
SCL
17
16
Digital Output Voltage .... (GND – 0.3V) to (DV + 0.3V)
DD
Power Dissipation...............................................500mW
25
15 AD1
AD0
Operating Temperature Range
14
13 AV
LTC2309C ................................................ 0°C to 70°C
LTC2309I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
DD
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
T
= 150°C, θ = 37°C/W
JA
JMAX
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2309CUF#PBF
LTC2309IUF#PBF
TAPE AND REEL
PART MARKING*
2309
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2309CUF#TRPBF
LTC2309IUF#TRPBF
0°C to 70°C
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
2309
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2309f
2
LTC2309
CONVERTER AND MULTIPLEXER CHARACTERISTICS The
l
denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4, 5)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
12
(Note 6)
0.45
0.35
1
1
1
8
LSB
LSB
(Note 7)
LSB
Bipolar Zero Error Drift
Bipolar Zero Error Match
Unipolar Zero Error
0.002
0.1
LSB/°C
LSB
3
6
l
(Note 7)
0.4
LSB
Unipolar Zero Error Drift
Unipolar Zero Error Match
Bipolar Full-Scale Error
0.002
0.2
LSB/°C
LSB
1
l
l
External Reference (Note 8)
REFCOMP = 4.096V
0.5
0.4
10
9
LSB
LSB
Bipolar Full-Scale Error Drift
Bipolar Full-Scale Error Match
Unipolar Full-Scale Error
External Reference
0.05
0.4
LSB/°C
LSB
3
l
l
External Reference (Note 8)
REFCOMP = 4.096V
0.4
0.3
10
6
LSB
LSB
Unipolar Full-Scale Error Drift
Unipolar Full-Scale Error Match
External Reference
0.05
0.3
LSB/°C
LSB
2
ANALOG INPUT The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
AV
UNITS
+
l
V
V
Absolute Input Range (CH0 to CH7)
(Note 9)
–0.05
V
IN
IN
DD
–
+
l
l
Absolute Input Range (CH0 to CH7, COM) Unipolar (Note 9)
Bipolar (Note 9)
–0.05
–0.05
AV /2
V
V
DD
AV
DD
–
+
+
–
–
l
l
V
– V
Input Differential Voltage Range
V
IN
V
IN
= V – V (Unipolar)
0 to REFCOMP
REFCOMP/2
V
V
IN
IN
IN
IN
IN
= V – V (Bipolar)
IN
l
I
Analog Input Leakage Current
Analog Input Capacitance
1
μA
IN
C
Sample Mode
Hold Mode
55
5
pF
pF
IN
CMRR
Input Common Mode Rejection Ratio
70
dB
DYNAMIC ACCURACY The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Notes 4, 10)
A
IN
SYMBOL
SINAD
SNR
PARAMETER
CONDITIONS
MIN
71
TYP
73.3
73.4
–88
90
MAX
UNITS
dB
l
l
l
l
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
IN
f
IN
f
IN
f
IN
f
IN
= 1kHz
= 1kHz
71
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Full Linear Bandwidth
= 1kHz, First 5 Harmonics
–77
dB
SFDR
= 1kHz
= 1kHz
79
dB
–109
700
25
dB
(Note 11)
kHz
MHz
ns
–3dB Input Linear Bandwidth
Aperature Delay
13
Transient Response
Full-Scale Step
240
ns
2309f
3
LTC2309
INTERNAL REFERENCE CHARACTERISTICS The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
PARAMETER
CONDITIONS
MIN
TYP
2.50
25
MAX
UNITS
V
l
V
V
V
V
V
Output Voltage
Output Tempco
Output Impedance
I
I
= 0
= 0
2.47
2.53
REF
OUT
OUT
ppm/°C
kΩ
REF
–0.1mA ≤ I
≤ 0.1mA
8
REF
OUT
Output Voltage
I
= 0
4.096
0.8
V
REFCOMP
OUT
Line Regulation
AV = 4.75V to 5.25V
DD
mV/V
REF
I2C INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL PARAMETER
CONDITIONS
MIN
0.7V
TYP
MAX
0.3V
UNITS
l
l
l
l
l
V
V
V
V
High Level Input Voltage
V
V
IH
CC
Low Level Input Voltage
IL
CC
High Level Input Voltage for Address Pins A1, A0
Low Level Input Voltage for Address Pins A1, A0
0.95V
V
IHA
ILA
CC
0.05V
10
V
CC
R
R
R
Resistance from A1, A0, to V to Set Chip
kΩ
INH
INL
INF
CC
Address Bit to 1
l
l
Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
10
kΩ
Resistance from A1, A0 to GND or V to Set
Chip Address Bit to Float
2
MΩ
CC
l
l
l
l
l
l
I
Digital Input Current
–10
10
μA
V
I
V
V
Hysteresis of Schmitt Trigger Inputs
Low Level Output Voltage (SDA)
(Note 9)
I = 3mA
(Note 12)
0.05V
HYS
OL
CC
0.4
250
50
V
t
t
Output Fall Time V to V
20 + 0.1C
B
ns
ns
pF
OF
SP
H
IL(MAX)
Input Spike Suppression
C
External Capacitance Load On Chip Address Pins
(A1, A0) for Valid Float
10
CAX
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
AV
PARAMETER
CONDITIONS
MIN
4.75
4.75
TYP
5
MAX
5.25
5.25
UNITS
l
l
Analog Supply Voltage
Digital Supply Voltage
V
V
DD
DV
5
DD
l
l
l
I
Supply Current
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
2.3
210
7
3
350
15
mA
μA
μA
DD
P
Power Dissipation
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
11.5
1.05
35
15
1.75
75
mW
mW
μW
D
2309f
4
LTC2309
I2C TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
μs
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Pin
0.6
1.3
HD(SDA)
LOW
μs
High Period of the SCL Pin
0.6
μs
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
Set-Up Time for a Repeated Start Condition
Data Hold Time
0.6
μs
0
0.9
μs
Data Set-Up Time
100
ns
Rise Time for SDA/SCL Signals
Fall Time for SDA/SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
(Note 12)
(Note 12)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
B
ns
f
B
μs
SU(STO)
BUF
1.3
μs
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
1.3
MAX
14
UNITS
ksps
μs
l
l
l
f
t
t
t
Throughput Rate (Successive Reads)
Conversion Time
SMPL
CONV
(Note 9)
(Note 9)
1.8
Acquisition Time
240
ns
ACQ
REFCOMP Wake-Up Time (Note 13)
C
= 10μF, C = 2.2μF
200
ms
REFWAKE
REFCOMP
REF
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with AV and DV
DD
DD
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above V without latchup.
,
DD
DD
Note 9: Guaranteed by design, not subject to test.
Note 4: AV = 5V, DV = 5V, f = 14ksps internal reference unless
DD
DD
SMPL
Note 10: All specifications in dB are referred to a full-scale 2.048V input
otherwise noted.
with a 2.5V reference voltage.
Note 5: Linearity, offset and full-scale specifications apply for a
Note 11: Full linear bandwidth is defined as the full-scale input frequency
single-ended analog input with respect to COM.
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 12: C = capacitance of one bus line in pF (10pF ≤ C ≤ 400pF).
B
B
Note 13: REFCOMP wake-up time is the time required for the REFCOMP
pin to settle within 0.5LSB at 12-bit resolution of its final value after
waking up from SLEEP mode.
2309f
5
LTC2309
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, AV = DV = 5V, f = 14ksps, unless otherwise noted.
SMPL
A
DD
DD
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
1kHz Sine Wave
8192 Point FFT Plot
0
–20
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
–40
–60
–80
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
–100
–120
–140
2048
0
1
2
4
5
6
7
0
1024
3072
4096
3
2048
0
1024
3072
4096
FREQUENCY (kHz)
OUTPUT CODE
OUTPUT CODE
2309 G01
2309 G02
2309 G03
Supply Current vs
Sampling Frequency
Offset Error vs Temperature
Full-Scale Error vs Temperature
4
2
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
UNIPOLAR
BIPOLAR
0.5
0
0
UNIPOLAR
BIPOLAR
–2
–4
–6
–0.5
–1.0
–0.5
–2.0
–50 –25
0
25
50
75 100 125
0.1
1
10
100
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
SAMPLING FREQUENCY (ksps)
TEMPERATURE (°C)
2309 G06
3209 G04
2309 G05
Analog Input Leakage Current
vs Temperature
Supply Current vs Temperature
Sleep Current vs Temperature
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
10
8
1000
900
800
700
600
500
400
300
200
100
0
6
4
CH (ON)
CH (OFF)
2
0
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
–25
–50 –25
0
25
75 100
–50
0
25
50
75 100 125
TEMPERATURE (°C)
–25
TEMPERATURE (°C)
2309 G07
2309 G08
2309 G09
2309f
6
LTC2309
PIN FUNCTIONS
CH3-CH7 (Pins 1-5): Channel 3 to Channel 7 Analog
Inputs. CH3-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
AD1 (Pin 15): Chip Address Control Pin. This pin
is configured as a three-state (Low, High, Floating)
2
address control bit for the device I C address. See
Table 2 for address selection.
2
COM (Pin 6): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noise and should be connected to ground for unipolar
conversions and midway between GND and REFCOMP
for bipolar conversions.
SCL (Pin 16): Serial Clock Pin of the I C Interface. The
LTC2309 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into
the SDA pin on the rising edges of the SCL clock and
output through the SDA pin on the falling edges of the
SCL clock.
V
(Pin 7): 2.5V Reference Output. Bypass to GND
REF
2
with a minimum 2.2μF tantalum capacitor or low ESR
ceramic capacitor. The internal reference may be over-
driven by an external 2.5V reference at this pin.
SDA (Pin 17): Bidirectional Serial Data Line of the I C
Interface. In transmitter mode (Read), the conversion
result is output at the SDA pin, while in receiver mode
(Write), the D word is input at the SDA pin to con-
IN
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with a 10μF tantalum and 0.1μF ceramic capaci-
tor in parallel. Nominal output voltage is 4.096V. The
internal reference buffer driving this pin is disabled by
figure the ADC. The pin is high impedance during the
data input mode and is an open-drain output (requires
an appropriate pull-up device to V ) during the data
CC
output mode.
grounding V , allowing REFCOMP to be overdriven
REF
by an external source.
DV (Pin 21): 5V Digital Supply. The range of DV
DD
DD
is 4.75V to 5.25V. Bypass DV to GND with a 0.1μF
DD
GND (Pins 9-11, Pins 18-20): Ground. All GND pins
must be connected to a solid ground plane.
ceramic and a 10μF tantalum capacitor in parallel.
CH0-CH2 (Pins 22-24): Channel 0 to Channel 2 Analog
Inputs. CH0-CH2 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
AV (Pins 12, 13): 5V Analog Supply. The range of
DD
AV is4.75Vto5.25V.BypassAV toGNDwitha0.1μF
DD
DD
ceramic and a 10μF tantalum capacitor in parallel.
AD0 (Pin 14): Chip Address Control Pin. This pin is
GND (Pin 25): Exposed Pad Ground. Must be soldered
directly to ground plane.
configuredasathree-state(Low,High,Floating)address
2
control bit for the device I C address. See Table 2 for
address selection.
2309f
7
LTC2309
FUNCTIONAL BLOCK DIAGRAM
AV
DV
DD
DD
LTC2309
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
AD1
AD0
ANALOG
INPUT
MUX
SCL
SDA
+
–
2
12-BIT
SAR ADC
I C
PORT
V
REF
8k
INTERNAL
2.5V REF
GAIN = 1.6384x
REFCOMP
2308 BD
GND
TIMING DIAGRAM
2
Definition of Timing for Fast/Standard Mode Devices on the I C Bus
SDA
SCL
t
t
SU(DAT)
t
t
BUF
r
LOW
HD(SDA)
t
f
t
t
SP
t
t
f
r
t
t
t
SU(STO)
HD(SDA)
SU(STA)
t
t
HIGH
S
Sr
P
S
HD(DAT)
2309 TD
S = START, Sr = REPEATED START, P = STOP
2309f
8
LTC2309
APPLICATIONS INFORMATION
Overview
Programming the LTC2309
The various modes of operation of the LTC2309 are
The LTC2309 is a low noise, 8-channel, 12-bit succes-
siveapproximationregister(SAR)A/Dconverterwithan
programmed by a 6-bit D word. The SDI input data
IN
2
bits are loaded on the rising edge of SCL during a write
operation,withtheS/Dbitloadedonthefirstrisingedge
and the SLP bit on the sixth rising edge (see Figure 8b
I C compatible serial interface. The LTC2309 includes a
precision internal reference and a configurable 8-chan-
nel analog input multiplexer (MUX). The ADC may be
configuredtoacceptsingle-endedordifferentialsignals
and can operate in either unipolar or bipolar mode. A
sleep mode option is also provided to further reduce
power during inactive periods.
2
in the I C Interface section). The input data word is
defined as follows:
S/D O/S S1 S0 UNI SLP
2
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
The LTC2309 communicates through a 2-wire I C
compatible serial interface. Conversions are initiated
by signaling a Stop condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge (NAK) an external request
until the conversion is finished. After a conversion is
finished, the device is ready to accept a read/write
request. Once the LTC2309 is addressed for a read
operation, the device begins outputting the conversion
result under the control of the serial clock (SCL). There
is no latency in the conversion result. There are 12
bits of output data followed by 4 trailing zeros. Data is
updated on the falling edges of SCL, allowing the user
to reliably latch data on the rising edge of SCL. A write
operation may follow the read operation by using a
Repeat Start or a Stop condition may be given to start
a new conversion. By selecting a write operation, the
S1 = CHANNEL SELECT BIT 1
S0 = CHANNEL SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,
O/S, S1 and S0 bits of the D word. Table 1 lists the
IN
MUX configurations for all combinations of the con-
figuration bits. Figure 1a shows several possible MUX
configurations and Figure 1b shows how the MUX can
be reconfigured from one conversion to the next.
ADC can be programmed with a 6-bit D word. The
IN
Driving the Analog Inputs
D word configures the MUX and programs various
IN
The analog inputs of the LTC2309 are easy to drive.
Eachoftheanaloginputscanbeusedasasingle-ended
input relative to the COM pin (CH0-COM, CH1-COM,
etc.) or in differential input pairs (CH0 and CH1, CH2
and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows
how to drive COM for single-ended inputs in unipolar
and bipolar modes. Regardless of the MUX configura-
tion, the “+” and “–“ inputs are sampled at the same
instant. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection
of the sample-and-hold circuit. The inputs draw only
onesmallcurrentspikewhilechargingthesample-and-
holdcapacitorsduringtheacquiremode. Inconversion
modes of operation of the ADC.
During a conversion, the internal 12-bit capacitive
chargeredistributionDACoutputissequencedthrough
asuccessiveapproximationalgorithmbytheSARstart-
ing from the most significant bit (MSB) to the least
significantbit(LSB). Thesampledinputissuccessively
compared with binary weighted charges supplied by
the capacitive DAC using a differential comparator. At
the end of a conversion, the DAC output balances the
analog input. The SAR contents (a 12-bit data word)
that represent the sampled analog input are loaded into
12 output latches that allow the data to be shifted out
2
via the I C interface.
2309f
9
LTC2309
APPLICATIONS INFORMATION
4 Differential
8 Single-Ended
1st Conversion
2nd Conversion
CH0
CH1
+ (
)
)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+
+
+
+
+
+
+
+
–
{
{
{
{
(
+
–
+
–
+
–
CH2
CH3
–
+
CH2
CH3
{
{
{
{
+ (
)
)
CH2
CH3
–
(
+
–
CH4
CH5
+
+
CH4
CH5
+ (
)
)
CH4
CH5
–
(
+
–
COM
(UNUSED)
COM (
)
–
CH6
CH7
+ (
)
)
–
(
2328 F01b
+
COM (
)
–
–
Figure 1b. Changing the MUX Assignments “On the Fly”
Combinations of Differential
and Single-Ended
CH0
+
Unipolar Mode
Bipolar Mode
{
CH1
–
CH2
CH3
–
{
COM
COM
+
+
REFCOMP/2
+
+
+
+
CH4
CH5
CH6
CH7
–
2328 F02
Figure 2. Driving COM in Unipolar and Bipolar Modes
COM (
)
–
2309 F01a
mode, the analog inputs draw only a small leakage cur-
rent. If the source impedance of the driving circuit is
low, the ADC inputs can be driven directly. Otherwise,
more acquisition time should be allowed for a source
with higher impedance.
Figure 1a. Example of MUX Configurations
Table 1. Channel Configuration
S/D O/S S1 S0
0
1
2
3
4
5
6
+
–
+
7
–
+
COM
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
–
Input Filtering
+
–
The noise and distortion of the input amplifier and
other circuitry must be considered since they will add
to the ADC noise and distortion. Therefore, noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient
for many applications.
+
–
–
+
+
–
+
+
–
+
+
The analog inputs of the LTC2309 can be modeled as
–
–
–
–
–
–
–
–
a 55pF capacitor (C ) in series with a 100ꢀ resistor
IN
(R ) as shown in Figure 3a. C gets switched to the
ON
IN
selectedinputonceduringeachconversion.Largefilter
RC time constants will slow the settling of the inputs.
It is important that the overall RC time constants be
short enough to allow the analog inputs to completely
settle to 12-bit resolution within the acquisition time
+
+
+
(t ) if DC accuracy is important.
ACQ
+
2309f
10
LTC2309
APPLICATIONS INFORMATION
When using a filter with a large C
value (e.g. 1μF),
50Ω
FILTER
ANALOG
INPUT
CH0
the inputs do not completely settle and the capacitive
LTC2309
2000pF
10μF
input switching currents are averaged into a net DC
COM
current (I ). In this case, the analog input can be mod-
DC
eled by an equivalent resistance (R = 1/(f
in series with an ideal voltage source (V
• C ))
REFCOMP
EQ
SMPL
IN
/2) as
REFCOMP
0.1μF
2309 F04a
shown in Figure 3b. The magnitude of the DC current
is then approximately I = (V – V /2)/R ,
DC
IN
REFCOMP
EQ
Figure 4a. Optional RC Input Filtering for Single-Ended Input
which is roughly proportional to V . To prevent large
IN
DCdropsacrosstheresistorR
,afilterwithasmall
FILTER
resistor and large capacitor should be chosen. When
1000pF
50Ω
running at the maximum throughput rate of 14ksps,
CH0
the input current equals 1.5μA at V = 4.096V, which
DIFFERENTIAL
IN
LTC2309
ANALOG
INPUTS
1000pF
1000pF
amounts to a full-scale error of 0.5LSB when using a
50Ω
CH1
filter resistor (R
) of 333ꢀ. Applications requiring
FILTER
lower sample rates can tolerate a larger filter resistor
REFCOMP
for the same amount of full-scale error.
0.1μF
10μF
2309 F04b
INPUT
CH0-CH7
R
LTC2309
ON
Figure 4b. Optional RC Input Filtering for Differential Inputs
R
SOURCE
100Ω
V
IN
C
IN
C
FILTER
55pF
self heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
less susceptible to both problems.
2309 F03a
Figure 3a. Analog Input Equivalent Circuit
Dynamic Performance
INPUT
I
DC CH0-CH7
R
FILTER
FastFourierTransform(FFT)testtechniquesareusedto
testtheADC’sfrequencyresponse,distortionandnoise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
V
IN
LTC2309
R
EQ
SMPL
C
FILTER
1/(f
• C )
IN
+
V
/2
REFCOMP
–
2309 F03b
Figure 3b. Analog Input Equivalent
Circuit for Large Filter Capacitances
Signal-to-Noise and Distortion Ratio (SINAD)
Figures 4a and 4b show examples of input filtering for
The signal-to-noise and distortion ratio (SINAD) is the
single-ended and differential inputs. For the single- ratio between the RMS amplitude of the fundamental
ended case in Figure 4a, a 50ꢀ source resistor and a
input frequency to the RMS amplitude of all other fre-
2000pF capacitor to ground on the input will limit the quency components at the A/D output. The output is
inputbandwidthto1.6MHz.Highqualitycapacitorsand band-limited to frequencies from above DC and below
resistors should be used in the RC filter since these
half the sampling frequency. Figure 5 shows a typical
components can add distortion. NPO and silver mica SINAD of 73.3dB with a 14kHz sampling rate and a
typedielectriccapacitorshaveexcellentlinearity.Carbon 1kHz input. An SNR of 73.4dB can be achieved with
surface mount resistors can generate distortion from
the LTC2309.
2309f
11
LTC2309
APPLICATIONS INFORMATION
0
R1
8k
SNR = 73.4dB
V
REF
SINAD = 73.3dB
BANDGAP
–20
2.5V
THD = –88dB
REFERENCE
2.2μF
0.1μF
–40
REFCOMP
4.096V
10μF
–60
–80
REFERENCE
AMP
R2
–100
–120
–140
R3
GND
LTC2309
0
1
2
3
4
5
6
7
2309 F06a
FREQUENCY (kHz)
Figure 6a. LTC2309 Reference Circuit
2309 G03
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
5V
0.1μF
Total Harmonic Distortion (THD)
V
IN
LT1790A-2.5
V
Total harmonic distortion (THD) is the ratio of the
RMS sum of all harmonics of the input signal to the
fundamentalitself.Theout-of-bandharmonicsaliasinto
the frequency band between DC and half the sampling
V
OUT
REF
2.2μF
0.1μF
LTC2309
REFCOMP
+
10μF
frequency(f
/2). THD is expressed as:
SMPL
GND
V 2 + V 2 + V42...+ V 2
2309 F06b
2
3
N
THD= 20log
Figure 6b. Using the LT®1790A-2.5 as an External Reference
V
1
where V is the RMS amplitude of the fundamental
1
Internal Conversion Clock
frequency and V through V are the amplitudes of the
2
N
The internal conversion clock is factory trimmed to
second through Nth harmonics.
achieve a typical conversion time (t
) of 1.3ꢁs and
CONV
Internal Reference
a maximum conversion time of 1.8ꢁs over the full
operating temperature range.
The LTC2309 has an on-chip, temperature compen-
sated bandgap reference that is factory trimmed to
2.5V (Refer to Figure 6a). It is internally connected
2
I C Interface
2
The LTC2309 communicates through an I C interface.
to a reference amplifier and is available at V . V
REF REF
2
The I C interface is a 2-wire open-drain interface sup-
should be bypassed to GND with a 2.2ꢁF tantalum
capacitor to minimize noise. An 8k resistor is in series
with the output so that it can be easily overdriven by
an external reference if more accuracy and/or lower
drift are required as shown in Figure 6b. The reference
porting multiple devices and multiple masters on a
single bus. The connected devices can only pull the
serial data line (SDA) low and can never drive it high.
SDA is required to be externally connected to the sup-
ply through a pull-up resistor. When the data line is not
amplifier gains the V
voltage by 1.638 to 4.096V
REF
2
being driven low, it is high. Data on the I C bus can be
transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode.
at REFCOMP. To compensate the reference amplifier,
bypass REFCOMP with a 10ꢁF ceramic or tantalum
capacitor in parallel with a 0.1ꢁF ceramic capacitor for
best noise performance.
2309f
12
LTC2309
APPLICATIONS INFORMATION
2
Each device on the I C bus is recognized by a unique
Data Transferring
addressstoredinthedeviceandcanonlyoperateeither
as a transmitter or receiver, depending on the function
of the device. A device can also be considered as a
master or a slave when performing data transfers. A
master is the device which initiates a data transfer on
the bus and generates the clock signals to permit the
transfer. Devices addressed by the master are consid-
ered slaves.
2
After the Start condition, the I C bus is busy and data
transfercanbeginbetweenthemasterandtheaddressed
slave. Data is transferred over the bus in groups of
nine bits, one byte followed by one acknowledge (ACK)
bit. The master releases the SDA line during the ninth
SCL clock cycle. The slave device can issue an ACK by
pulling SDA low or issue a Not Acknowledge (NAK)
by leaving the SDA line high impedance (the external
The LTC2309 can only be addressed as a slave (see pull-up resistor will hold the line high). Change of data
Table 2). Once addressed, it can receive configuration only occurs while the SCL line is low.
bits(D word)ortransmitthelastconversionresult.The
IN
Data Format
serialclockline(SCL)isalwaysaninputtotheLTC2309
andtheserialdataline(SDA)isbidirectional.Thedevice
supports the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
After a Start condition, the master sends a 7-bit ad-
dress followed by a read/write (R/W) bit. The R/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309’s
9 pin-selectable addresses, the ADC is selected. When
the ADC is addressed during a conversion, it will not
2
section for definition of the I C timing).
The Start and Stop Conditions
Referring to Figure 7, a Start (S) condition is generated acknowledge R/W requests and will issue a NAK by
by transitioning SDA from high to low while SCL is leavingtheSDAlinehigh. Iftheconversioniscomplete,
high. The bus is considered to be busy after the Start
condition. When the data transfer is finished, a Stop
the LTC2309 issues an ACK by pulling the SDA line low.
The LTC2309 has two registers. The 12-bit wide output
(P) condition is generated by transitioning SDA from register contains the last conversion result. The 6-bit
low to high while SCL is high. The bus is free after a wide input register configures the input MUX and the
Stop condition is generated. Start and Stop conditions operating mode of the ADC.
are always generated by the master.
Output Data Format
When the bus is in use, it stays busy if a Repeated
The output register contains the last conversion result.
Start (Sr) is generated instead of a Stop condition.
The Repeated Start timing is functionally identical to
the Start and is used for writing and reading from the
device before the initiation of a new conversion.
Aftereachconversioniscompleted,thedeviceautomati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2309 is addressed for a read
operation, it acknowledges by pulling SDA low and acts
as a transmitter. The master/receiver can read up to two
bytes from the LTC2309. After a complete read opera-
tion of 2 bytes, a Stop condition is needed to initiate a
new conversion. The device will NAK subsequent read
operations while a conversion is being performed.
Start Condition
Stop Condition
SDA
SDA
SCL
S
P
2309 F07
SCL
Figure 7. Timing Diagrams of Start and Stop Conditions
2309f
13
LTC2309
APPLICATIONS INFORMATION
The data output stream is 16 bits long and is shifted
out on the falling edges of SCL (see Figure 8a). The
first bit is the MSB and the 12th bit is the LSB of the
conversion result. The remaining four bits are zero.
Figures 14 and 15 are the transfer characteristics for
the bipolar and unipolar modes. Data is output on the
SDA line in 2’s complement format for bipolar readings
or in straight binary for unipolar readings.
Input Data Format
When the LTC2309 is addressed for a write operation,
it acknowledges by pulling SDA low during the low
period before the 9th cycle and acts as a receiver. The
master/transmittercanthensend1bytetoprogramthe
device. The input byte consists of the 6-bit D word
IN
followed by two bits that are ignored by the ADC and
are considered don’t cares (X) (see Figure 8b). The
input bits are latched on the rising edge of SCL during
the write operation.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
• • •
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10 B9
B8
B7
B6
B5 B4
• • •
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
MOST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
1
2
3
4
5
6
7
8
9
SCL
• • •
• • •
(CONTINUED)
CONVERSION
INITIATED
SDA
(CONTINUED)
STOP
BY MASTER
B3
B2
B1
B0
NAK BY
MASTER
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
2309 F08a
Figure 8a. Timing Diagram for Reading from the LTC2309
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
CONVERSION
INITIATED
A6
A5
A4
A3
A2
A1
A0 R/W
S/D O/S S1
S0 UNI SLP
WORD
X
X
STOP BY
MASTER
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
D
IN
2309 F08b
ADDRESS FRAME
WRITE 1 BYTE
Figure 8b. Timing Diagram for Writing to the LTC2309
2309f
14
LTC2309
APPLICATIONS INFORMATION
Table 2. Address Assignment
After power-up, the ADC initiates an internal reset
AD1
LOW
AD0
LOW
ADDRESS
0001000
0001001
0001010
0001011
0011000
0011001
0011010
0011011
0101000
cycle which sets the D word to all 0s (S/D = O/S =
IN
S0 = S1 = UNI = SLP = 0). A write operation may be
performedifthedefaultstateoftheADC’sconfiguration
is not desired. Otherwise, the ADC must be properly
addressed and followed by a Stop condition to initiate
a conversion.
LOW
FLOAT
HIGH
HIGH
FLOAT
LOW
LOW
FLOAT
FLOAT
FLOAT
HIGH
HIGH
HIGH
Initiating a New Conversion
LOW
FLOAT
HIGH
The LTC2309 awakens from either nap or sleep when
properly addressed for a read/write operation. A Stop
command may then be issued after performing the
read/write operation to trigger a new conversion.
Continuous Read
Issuing a Stop command after the 8th SCL clock pulse
of the address frame and before the completion of a
read/write operation will also initiate new conversion,
but the output result may not be valid due to lack of
adequate acquisition time (see Acquisition section).
Inapplicationswherethesameinputchannelissampled
eachcycle,conversionscanbecontinuouslyperformed
and read without a write cycle (see Figure 9). The D
IN
word remains unchanged from the last value written
into the device. If the device has not been written to
since power-up, the D word defaults to all 0s (S/D =
IN
LTC2309 Address
O/S = S0 = S1 = UNI = SLP = 0). At the end of a read
operation, a Stop condition may be given to start a new
conversion. At the conclusion of the conversion cycle,
thenextresultmaybereadusingthemethoddescribed
above. If the conversion cycle is not concluded and a
valid address selects the device, the LTC2309 gener-
ates a NAK signal indicating the conversion cycle is in
progress.
The LTC2309 has two address pins (AD0 and AD1) that
may be tied high, low, or left floating to enable one of
9 possible addresses (see Table 2).
In addition to the configurable addresses listed in
Table 2, the LTC2309 also contains a global address
(1110111) which may be used for synchronizing mul-
2
tiple LTC2309s or other I C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2309s with Global Address
Call section).
S 7-BIT ADDRESS R ACK READ P
S 7-BIT ADDRESS R ACK READ P
CONVERSION
NAP
DATA OUTPUT CONVERSION
NAP
DATA
OUTPUT
CONVERSION
2309 F09
Figure 9. Consecutive Reading with the Same Configuration
2309f
15
LTC2309
APPLICATIONS INFORMATION
Continuous Read/Write
2
the same I C bus, all converters can be synchronized
through the use of a global address call. Prior to issu-
ing the global address call, all converters must have
completed a conversion cycle. The master then issues
a Start, followed by the global address 1110111, and
a write request. All converters will be selected and ac-
knowledge the request. The master then sends a write
byte(optional)followedbytheStopcommand.Thiswill
update the channel selection (optional) and simultane-
ously initiate a conversion for all ADCs on the bus (see
Figure 11). In order to synchronize multiple converters
without changing the channel, a Stop command may
be issued after acknowledgement of the global write
command. Global read commands are not allowed and
the converters will NAK a global read request.
Oncetheconversioncycleiscomplete,theLTC2309can
be written to and then read from using the Repeated
Start (Sr) command. Figure 10 shows a cycle which
begins with a data Write, a repeated Start, followed
by a Read and concluded with a Stop command. The
following conversion begins after all 16 bits are read
out of the device or after a Stop command. The fol-
lowing conversion will be performed using the newly
programmed data.
Synchronizing Multiple LTC2309s with a Global
Address Call
2
InapplicationswhereseveralLTC2309sorotherI CSAR
ADCs from Linear Technology Corporation are used on
S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P
CONVERSION
NAP
DATA OUTPUT
CONVERSION
DATA
OUTPUT
CONVERSION
2309 F10
Figure 10. Write, Read, Start Conversion
SCL
SDA
LTC2309
LTC2309
LTC2309
S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P
CONVERSION NAP DATA OUTPUT CONVERSION OF ALL LTC2309s
2309 F11
Figure 11. Syncrhonous Multiple LTC2309s with a Global Address Call
2309f
16
LTC2309
APPLICATIONS INFORMATION
Nap Mode
V
and REFCOMP pins. A new conversion should not
REF
be initiated before this time as shown in Figure 12.
The ADC enters nap mode after a conversion is com-
plete (t
) if the SLP bit is set to a logic 0. The sup-
CONV
Acquisition
ply current decreases to 210ꢁA in nap mode between
conversions, thereby reducing the average power
dissipation as the sample rate decreases. For example,
the LTC2309 draws an average of 300μA at a 1ksps
sampling rate. The LTC2309 keeps only the reference
The LTC2309 begins acquiring the input signal at dif-
ferent instances depending on whether a read or write
operation is being performed. If a read operation is
being performed, acquisition of the input signal begins
on the rising edge of the 9th clock pulse following the
address frame as shown in Figure 13a.
(V )andreferencebuffer(REFCOMP)circuitryactive
REF
when in nap mode.
If a write operation is being performed, acquisition of
the input signal begins on the falling edge of the sixth
Sleep Mode
clock cycle after the D word has been shifted in as
The ADC enters sleep mode after a conversion is com-
IN
shown in Figure 13b. The LTC2309 will acquire the
plete (t
) if the SLP bit is set to a logic 1. The ADC
CONV
signal from the input channel that was most recently
draws only 7μA in sleep mode, provided that none of
the digital inputs are switching. When the LTC2309 is
properlyaddressed,theADCisreleasedfromsleepmode
programmed by the D word. A minimum of 240ns is
IN
required to acquire the input signal before initiating a
new conversion.
and requires 200ms (t
therespective2.2ꢁFand10ꢁFbypasscapacitorsonthe
) to wake up and charge
REFWAKE
S 7-BIT ADDRESS R/W ACK
P
CONVERSION
SLEEP
t
CONVERSION
REFWAKE
2309 F12
Figure 12. Exiting Sleep Mode and Starting a New Conversion
1
2
3
4
5
6
7
8
9
1
2
SCL
SDA
ACQUISITION BEGINS
A6
A5
A4
A3
A2
A1
A0 R/W
B11 B10
2309 F13a
t
ACQ
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
ACQUISITION BEGINS
A2
A1
A0 R/W
S/D O/S S1 S0 UNI SLP
X
X
2309 F13b
t
ACQ
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
2309f
17
LTC2309
APPLICATIONS INFORMATION
111...111
111...110
011...111
BIPOLAR
ZERO
011...110
100...001
100...000
011...111
011...110
000...001
000...000
111...111
111...110
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2
000...001
000...000
FS = 4.096V
1LSB = FS/2
100...001
100...000
12
12
1LSB = 1mV
1LSB = 1mV
–1 0V
1
0V
FS – 1LSB
–FS/2
FS/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2309 F15
2309 F14
Figure 14. Bipolar Transfer Characteristics (2’s Complement)
Figure 15. Unipolar Transfer Characteristics (Straight Binary)
Board Layout and Bypassing
and AV should be bypassed to the ground plane as
DD
close to the pin as possible. Maintaining a low impedance
path for the common return of these bypass capacitors
is essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 16 for a
suggested layout.
Toobtainthebestperformance,aprintedcircuitboardwith
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
separated as much as possible. Care should be taken not
to run any digital signals alongside an analog signal. All
analoginputsshouldbeshieldedbyGND.V ,REFCOMP
REF
Figure 16. Suggested Layout
2309f
18
LTC2309
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.10 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER
0.75 0.05
4.00 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
2.45 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2309f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2309
TYPICAL APPLICATION
Driving the LTC2309 with 10V Input Signals Using a Precision Attenuator
5V
IN
OUT
1μF
0.1μF
LT1790-2.5
GND
10V
7
5V
450k
50k
8
9
150k
10μF
0.1μF
10μF
0.1μF
–
+
10
4pF
100Ω
47pF
450k
450k
AV
DD
DV
DD
AD1 AD0
6
CH0
1.7k 1.7k
LT1991
1
2
3
LTC2309
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
450k
150k
50k
SCL
SDA
CONTROL
LOGIC
ANALOG
INPUT
MUX
10V
INPUT
SIGNAL
+
–
2
12-BIT
SAR ADC
I C
4pF
LT1991
PORT
(FPGA, CPLD,
DSP, ETC)
4
5
–10V
INTERNAL
2.5V REF
V
REF
2.2μF
REFCOMP
GND
0.1μF
10μF
2309 TA02
RELATED PARTS
PART NUMBER
LTC1417
DESCRIPTION
14-Bit, 400ksps Serial ADC
COMMENTS
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
Low Input Offset: 75μV/125μV
LTC1468/LTC1469
Single/Dual 90MHz, 22V/μs, 16-bit Accurate
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65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
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Micropower Low Dropout Reference
10-Bit/12-Bit, 8-channel, 1.25Msps ADCs
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LTC1850/LTC1851
LTC1852/LTC1853
LTC1860/LTC1861
Parallel Output, Programmable MUX and Sequencer, 5V Supply
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP packages
6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308
LTC1860L/LTC1861L 3V, 12-bit, 1-/2-Channel 150ksps ADCs
LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADCs
LTC1863L/LTC1867L 3V, 12-/16-bit, 8-Channel 175ksps ADCs
LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADCs in MSOP
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP
LTC2302/LTC2306
12-Bit, 1-/2-Channel 500ksps SPI ADCs in
3mm × 3mm DFN
LTC2308
12-Bit, 8-Channel 500ksps SPI ADC
5V, Internal Reference, 4mm × 4mm QFN Package, Software Compatible with
LTC2302/LTC2306
2
LTC2453
Easy-to-Use, Ultra-Tiny 16-bit I C Delta Sigma ADC
2LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm × 2mm DFN Package
2
LTC2487/LTC2489/ 2-/4-Channel Easy Drive I C Delta Sigma ADCs
LTC2493
16-/24-Bits, PGA and Temperature Sensor, 15Hz Output Rate, 4mm × 3mm
DFN Packages
2
LTC2495/LTC2497/ 8-/16-Channel Easy Drive I C Delta Sigma ADCs
16-/24-Bits, PGA and Temperature Sensor, 15Hz Output Rate, 5mm × 7mm
QFN Packages
LTC2499
2309f
LT 0208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC2310CMSE-12#PBF
LTC2310-12 - 12-Bit + Sign, 2Msps Differential Input ADC with Wide Input Common Mode Range; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
Linear
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