LTC2325CUKG-12#PBF_技术文档

LTC2325-12

Quad, 12-Bit+Sign, 5Msps/Ch

Simultaneous Sampling ADC

FeaTures

DescripTion

The LTC^®2325-12 is a low noise, high speed quad 12-bit

+ sign successive approximation register (SAR) ADC with

differential inputs and wide input common mode range.

Operatingfromasingle3.3Vor5Vsupply,theLTC2325-12

n

5Msps/Ch Throughput Rate

n

Four Simultaneously Sampling Channels

n

Guaranteed 12-Bit, No Missing Codes

n

8V Differential Inputs with Wide Input

P-P

Common Mode Range

has an 8V differential input range, making it ideal for

P-P

n

77dB SNR (Typ) at f = 2.2MHz

applications which require a wide dynamic range with

high common mode rejection. The LTC2325-12 achieves

±±.5LSꢀ INL typical, no missing codes at 12 bits and

77dꢀ SNR.

IN

–86dB THD (Typ) at f = 2.2MHz

Guaranteed Operation to 125°C

Single 3.3V or 5V Supply

Low Drift (2±ppm/°C Max) 2.±48V or 4.±96V

Internal Reference

TheLTC2325-12hasanonboardlowdrift(2±ppm/°Cmax)

2.±48V or 4.±96V temperature-compensated reference.

The LTC2325-12 also has a high speed SPI-compatible

serial interface that supports CMOS or LVDS. The fast

5Msps per channel throughput with one cycle latency

makes the LTC2325-12 ideally suited for a wide variety

of high speed applications. The LTC2325-12 dissipates

only 45mW per channel and offers nap and sleep modes

to reduce the power consumption to 26μW for further

power savings during inactive periods.

n

1.8V to 2.5V I/O Voltages

CMOS or LVDS SPI-Compatible Serial I/O

Power Dissipation 45mW/Ch (Typ)

Small 52-Lead (7mm × 8mm) QFN Package

applicaTions

n

High Speed Data Acquisition Systems

n

Communications

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their

respective owners.

n

Optical Networking

Multiphase Motor Control

n

Typical applicaTion

32k Point FFT f_SMPL= 5Msps,

10µF

1µF

TRUE DIFFERENTIAL INPUTS

NO CONFIGURATION REQUIRED

f_IN= 2.2MHz

3.3V OR 5V

1.8V TO 2.5V

+

–

0

IN , IN

SNR = 77.1dB

V

GND

O

V

DD

THD = –85.7dB

SINAD = 76.2dB

SFDR = 90.3dB

ARBITRARY

DIFFERENTIAL

–20

–40

12-BIT

+SIGN

SAR ADC

+

V

DD

0V

DD

0V

A

IN1

CMOS/LVDS

SDR/DDR

REFBUFEN

S/H

–

A

IN1

12-BIT

+SIGN

SAR ADC

+

–

A

IN2

S/H

SDO1

SDO2

SDO3

SDO4

CLKOUT

SCK

–60

LTC2325-12

–80

12-BIT

+

–

A

BIPOLAR

UNIPOLAR

IN3

+SIGN

S/H

V

DD

–100

–120

–140

SAR ADC

CNV

SAMPLE

12-BIT

+SIGN

SAR ADC

+

–

CLOCK

A

IN4

S/H

0V

REF REFOUT1 REFOUT2 REFOUT3 REFOUT4

1µF 10µF 10µF 10µF 10µF

0

0.5

1

1.5

2

2.5

FOUR SIMULTANEOUS

SAMPLING CHANNELS

FREQUENCY (MHz)

232512 TA01b

232512 TA01a

232512f

1

For more information www.linear.com/LTC2325-12

LTC2325-12

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

Supply Voltage (V )..................................................6V

DD

Supply Voltage (OV )................................................3V

DD

Analog Input Voltage

52 51 50 49 48 47 46 45 44 43 42 41

–

A

, A (Note 3) ................... –±.3V to (V + ±.3V)

–

IN DD

+

–

IN

A

1

2

40 DNC/SDOD

IN4

+

REFOUT1,2,3,4........................ .–±.3V to (V + ±.3V)

39 SDO4/SDOD

IN4

DD

GND

–

GND

OV

3

38

37

CNV........................................ –±.3V to (OV + ±.3V)

A

4

IN3

DD

Digital Input Voltage

+

–

A

IN3

5

36 DNC/SDOC

SDO3/SDOC

35

(Note 3).......................... (GND – ±.3V) to (OV + ±.3V)

DD

REFOUT3

GND

6

–

7

34 CLKOUTEN/CLKOUT

Digital Output Voltage

53

GND

+

REF

8

33 CLKOUT/CLKOUT

(Note 3).......................... (GND – ±.3V) to (OV + ±.3V)

DD

REFOUT2

–

9

32 GND

Operating Temperature Range

A

10

11

31 OV

DD

IN2

+

–

LTC2325C................................................ ±°C to 7±°C

LTC2325I .............................................–4±°C to 85°C

LTC2325H.......................................... –4±°C to 125°C

Storage Temperature Range .................. –65°C to 15±°C

30 DNC/SDOB

IN2

+

GND 12

–

29 SDO2/SDOB

–

A

13

14

28 DNC/SDOA

IN1

+

27 SDO1/SDOA

IN1

15 16 17 18 19 20 21 22 23 24 25 26

UKG PACKAGE

52-LEAD (7mm × 8mm) PLASTIC QFN

T

JMAX

= 15±°C, θ = 31°C/W

JA

EXPOSED PAD (PIN 53) IS GND, MUST ꢀE SOLDERED TO PCꢀ

http://www.linear.com/product/LTC2325-12#orderinfo

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LTC2325UKG-12

PACKAGE DESCRIPTION

TEMPERATURE RANGE

±°C to 7±°C

LTC2325CUKG-12#PꢀF

LTC2325IUKG-12#PꢀF

LTC2325HUKG-12#PꢀF

LTC2325CUKG-12#TRPꢀF

LTC2325IUKG-12#TRPꢀF

LTC2325HUKG-12#TRPꢀF

52-Lead (7mm × 8mm) Plastic QFN

–4±°C to 85°C

–4±°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 5±± unit reels through

designated sales channels with #TRMPꢀF suffix.

232512f

2

For more information www.linear.com/LTC2325-12

LTC2325-12

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

Absolute Input Range (A to A

CONDITIONS

(Note 5)

MIN

TYP

MAX

UNITS

V

l

+

–

+

–

V

)

±

V

DD

V

DD

IN

+

Absolute Input Range (A to A

)

(Note 5)

±

V

IN

–

+

–

= V – V

IN

– V

Input Differential Voltage Range

Common Mode Input Range

V

–REFOUT1,2,3,4

REFOUT1,2,3,4

V

IN

+

–

= (V – V )/2

±

V

DD

V

CM

IN

I

IN

Analog Input DC Leakage Current

Analog Input Capacitance

–1

1

μA

pF

dꢀ

V

C

IN

1±

CMRR

Input Common Mode Rejection Ratio

CNV High Level Input Voltage

CNV Low Level Input Voltage

CNV Input Current

f

IN

= 2.2MHz

1±2

l

V

1.5

IHCNV

ILCNV

INCNV

±.5

1±

V

I

–1±

μA

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

ꢀits

l

Resolution

No Missing Codes

12

ꢀits

Transition Noise

±.3

±±.5

±±.4

±

LSꢀ

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

ꢀipolar Zero-Scale Error

ꢀipolar Zero-Scale Error Drift

ꢀipolar Full-Scale Error

ꢀipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–1

–±.99

–1

1

±.99

1

LSꢀ

DNL

ꢀZE

LSꢀ

±.±1

LSꢀ/°C

LSꢀ

l

FSE

V

= 4.±96V (REFꢀUFEN Grounded) (Note 7)

= 4.±96V (REFꢀUFEN Grounded)

–2

2

REFOUT1,2,3,4

15

ppm/°C

REFOUT1,2,3,4

232512f

3

For more information www.linear.com/LTC2325-12

LTC2325-12

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS (Notes 4, 8).

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

76

MAX

UNITS

dꢀ

l

SINAD

Signal-to-(Noise + Distortion) Ratio f = 2.2MHz, V

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

= 4.±96V, Internal Reference

= 5V, External Reference

74

IN

REFOUT1,2,3,4

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

f

IN

= 2.2MHz, V

76.5

77

dꢀ

SNR

Signal-to-Noise Ratio

75

76

dꢀ

77.6

–86

–85

93

dꢀ

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

–76

dꢀ

SFDR

dꢀ

93

dꢀ

–3dꢀ Input ꢀandwidth

Aperture Delay

95

MHz

ps

5±±

1

Aperture Delay Matching

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

3±

ns

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Internal Reference Output Voltage

4.75V < V < 5.25V

4.±78

2.±34

4.±96

2.±48

4.115

2.±64

V

REFOUT1,2,3,4

DD

3.13V < V < 3.47V

DD

l

V

Temperature Coefficient

(Note 14)

3

2±

ppm/°C

Ω

REF

REFOUT1,2,3,4 Output Impedance

Line Regulation

±.25

±.3

V

4.75V < V < 5.25V

mV/V

REFOUT1,2,3,4

DD

I

External Reference Current

REFꢀUFEN = ±V

REFOUT1,2,3,4

REFOUT1,2,3,4 = 4.±96V

REFOUT1,2,3,4 = 2.±48V

(Notes 9, 1±)

5±±

3±±

μA

232512f

4

For more information www.linear.com/LTC2325-12

LTC2325-12

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL PARAMETER

CONDITIONS

CMOS/LVDS = GND

MIN

±.8 • OV

–1±

TYP

MAX

UNITS

CMOS Digital Inputs and Outputs

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

IH

IL

DD

±.2 • OV

DD

I

IN

V

IN

= ±V to OV

DD

1±

μA

pF

C

IN

Digital Input Capacitance

5

l

V

High Level Output Voltage

Low Level Output Voltage

I = –5±±μA

OV – ±.2

V

OH

O

DD

I = 5±±μA

O

±.2

1±

OL

l

I

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

V

OUT

V

OUT

V

OUT

= ±V to OV

DD

–1±

μA

mA

OZ

= ±V

= OV

–1±

1±

SOURCE

SINK

DD

LVDS Digital Inputs and Outputs

CMOS/LVDS = OV

DD

l

V

LVDS Differential Input Voltage

LVDS Common Mode Input Voltage

LVDS Differential Output Voltage

LVDS Common Mode Output Voltage

1±±Ω Differential Termination

DD

24±

1

6±±

1.45

6±±

1.4

mV

V

ID

OV = 2.5V

1±±Ω Differential Termination

OV = 2.5V

DD

IS

1±±Ω Differential Termination

OV = 2.5V

DD

22±

±.85

1±±

±.85

35±

1.2

2±±

1.2

mV

V

OD

1±±Ω Differential Termination

OV = 2.5V

DD

OS

Low Power LVDS Differential Output

Voltage

1±±Ω Differential Termination

OV = 2.5V

DD

35±

1.4

mV

V

OD_LP

OS_LP

Low Power LVDS Common Mode Output 1±±Ω Differential Termination

Voltage

OV = 2.5V

DD

232512f

5

For more information www.linear.com/LTC2325-12

LTC2325-12

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

5V Operation

3.3V Operation

4.75

3.13

5.25

3.47

V

DD

+

–

l

IV

DD

Supply Current

5Msps Sample Rate (IN = IN = ±V)

31

44.5

mA

CMOS I/O Mode: CMOS/LVDS = GND

l

OV

Supply Voltage

1.71

2.63

15.5

6.4

V

mA

µA

DD

OVDD

NAP

I

Supply Current

5Msps Sample Rate (C = 5pF)

4.4

5.3

2±

L

Nap Mode Current

Sleep Mode Current

Power Dissipation

Conversion Done (I

)

VDD

Sleep Mode (I + I

)

9±

SLEEP

VDD OVDD

l

P

V

= 3.3V, 5Msps Sample Rate

DD

1±2

18

2±

181

21.1

288

mW

µW

D_3.3V

Nap Mode

Sleep Mode

l

P

D_5V

Power Dissipation

V

= 5V, 5Msps Sample Rate

162

27

3±

261

32

424

mW

µW

DD

Nap Mode

Sleep Mode

LVDS I/O Mode: CMOS/LVDS = OV , OV = 2.5V

DD

l

OV

Supply Voltage

2.37

2.63

32

V

mA

µA

DD

OVDD

NAP

I

Supply Current

5Msps Sample Rate (C = 5pF, R = 1±±Ω)

26

5.3

2±

L

Nap Mode Current

Conversion Done (I

)

6.4

9±

VDD

Sleep Mode Current

Power Dissipation

Sleep Mode (I

+ I

)

OVDD

SLEEP

VDD

l

P

V

= 3.3V, 5Msps Sample Rate

DD

151

52

8±

218

58.6

288

mW

µW

D_3.3V

Nap Mode

Sleep Mode

l

P

D_5V

Power Dissipation

V

= 5V, 5Msps Sample Rate

214

5±

4±

3±3

69.2

424

mW

µW

DD

Nap Mode

Sleep Mode

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

MIN

±.2

3±

TYP

MAX

5

UNITS

Msps

µs

l

f

t

Maximum Sampling Frequency

Time ꢀetween Conversions

Conversion Time

SMPL

(Note 11) t

= t

+ t

CONV

1±±±

17±

CYC

CNVH

ns

CONV

CNV High Time

ns

CNVH

Sampling Aperture

(Note 11) t

= t

– t

CONV

28

5±

ns

ACQUISITION

WAKE

ACQUISITION

CYC

REFOUT1,2,3,4 Wake-Up Time

C

= 1±µF

ms

REFOUT1,2,3,4

CMOS I/O Mode: SDR, CMOS/LVDS = GND, SDR/ DDR = GND

l

t

SCK Period

(Note 13)

9.1

4.1

±

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4.5

HSDO_SDR

DSCKCLKOUT

L

SCK to CLKOUT Delay

(Note 12)

2.5

232512f

6

For more information www.linear.com/LTC2325-12

LTC2325-12

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4).

SYMBOL

PARAMETER

CONDITIONS

(Note 11)

MIN

TYP

MAX

UNITS

ns

l

t

ꢀus Relinquish Time After CNV↑

SDO Valid Delay from CNV↓

SCK Delay Time to CNV↑

3

DCNVSDOZ

DCNVSDOV

DSCKHCNVH

ns

±

ns

CMOS I/O Mode: DDR, CMOS/LVDS = GND, SDR/ DDR = OV

DD

l

t

SCK Period

18.2

8.2

±

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4.5

3

HSDO_DDR

DSCKCLKOUT

DCNVSDOZ

DCNVSDOV

DSCKHCNVH

L

SCK to CLKOUT Delay

(Note 12)

(Note 11)

2

ꢀus Relinquish Time After CNV↑

SDO Valid Delay from CNV↓

SCK Delay Time to CNV↑

3

±

LVDS I/O Mode: SDR, CMOS/LVDS = OV , SDR/DDR = GND

DD

l

t

SCK Period

9.1

4.1

±

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4

HSDO_SDR

DSCKCLKOUT

DSCKHCNVH

L

SCK to CLKOUT Delay

(Note 12)

(Note 11)

2

SCK Delay Time to CNV↑

±

LVDS I/O Mode: DDR, CMOS/LVDS = OV , SDR/DDR = OV = 2.5V

DD

l

t

SCK Period

18.2

8.2

±

ns

SCK

SCK High Time

SCK Low Time

SCKH

SCKL

SDO Data Remains Valid Delay from CLKOUT↓ C = 5pF (Note 12)

1.5

4

HSDO_DDR

DSCKCLKOUT

DSCKHCNVH

L

SCK to CLKOUT Delay

(Note 12)

(Note 11)

2

SCK Delay Time to CNV↑

±

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 8: All specifications in dꢀ are referred to a full-scale ±4.±96V input

with REF = 4.±96V.

Note 2: All voltage values are with respect to ground.

Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer

Note 3: When these pin voltages are taken below ground, or above V or

must be turned off by setting REFꢀUFEN = ±V.

DD

OV , they will be clamped by internal diodes. This product can handle input

DD

Note 10: f

= 5MHz, I

varies proportionally with sample rate.

SMPL

REFOUT1,2,3,4

currents up to 1±±mA below ground, or above V or OV , without latch-up.

DD

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V.

Note 13: t

rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: CNV is driven from a low jitter digital source, typically at OV

logic levels.

Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.±96V, f = 5MHz.

SMPL

DD

Note 5: Recommended operating conditions.

of 9.1ns allows a shift clock frequency up to 1±5MHz for

SCK

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: ꢀipolar zero error is the offset voltage measured from –±.5LSꢀ

when the output code flickers between ± ±±±± ±±±± ±±±± and 1 1111

1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

DD

232512f

7

For more information www.linear.com/LTC2325-12

LTC2325-12

aDc TiMing characTerisTics

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

232512 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 1. Voltage Levels for Timing Specifications

232512f

8

For more information www.linear.com/LTC2325-12

LTC2325-12

Typical perForMance characTerisTics

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT1,2,3,4

= 4.096V, f_SMPL= 5Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

1.0

0.5

1.0

0.5

200000

σ = 0.3

160000

120000

80000

40000

0

–0.5

–1.0

–4096

–2048

0

2048

4096

–4096

–2048

0

2048

4096

–3

–2

–1

0

1

2

3

OUTPUT CODE

CODE

232512 G02

232512 G01

232512 G03

THD, Harmonics vs Input

32k Point FFT, f_SMPL= 5Msps,

f_IN= 2.2MHz

SNR, SINAD vs Input Frequency

(1kHz to 2.2MHz)

Frequency (1kHz to 2.2MHz)

0

–20

78.0

77.7

77.4

77.1

76.8

76.5

76.2

75.9

75.6

75.3

75.0

–80

–84

SNR = 77.1dB

THD = –85.7dB

SINAD = 76.2dB

SFDR = 90.3dB

THD

–88

SNR

–40

–92

–96

SINAD

–60

HD3

–100

–104

–108

–112

–116

–120

–80

HD2

–100

–120

–140

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

FREQUENCY (MHz)

232512 G04

232512 G05

232512 G06

THD, Harmonics vs Input Common

Mode

SNR, SINAD vs Reference Voltage,

f_IN= 2.2MHz

32k Point FFT, IMD, f_SMPL= 5Msps,

A_IN⁺= 1.2MHz, A_IN^–= 2.2MHz

–80

–83

78

77

76

75

74

73

72

71

70

0

–20

THD = 85dB

f = 2.2MHz

SNR

V

= 1MHz, 4V

CM

P-P

–86

THD

SINAD

–40

–89

–92

–60

HD3

–95

–80

–98

–101

–104

–107

–110

–100

–120

–140

HD2

1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.5

1

1.5

2

2.5

INPUT COMMON MODE (V)

V

(V)

REFOUT

FREQUENCY (MHz)

232512 G07

232512 G08

232512 G09

232512f

9

For more information www.linear.com/LTC2325-12

LTC2325-12

Typical perForMance characTerisTics

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, REFOUT1,2,3,4

= 4.096V, f_SMPL= 5Msps, unless otherwise noted.

Step Response

(Large Signal Settling)

4096

CMRR vs Input Frequency

Crosstalk vs Input Frequency

–105

–107

–109

–111

–113

–115

–117

–119

–121

–123

–125

120

112

104

96

V

= 4V

P-P

CM

3072

2048

4.096V RANGE

1024

88

0

+

IN = 5MHz SQUARE WAVE

–

IN = 0V

80

–1024

0

0.5

1

1.5

2

2.5

0

500

1000

1500

2000

2500

–20 –10

0

10 20 30 40 50 60 70 80 90

FREQUENCY (MHz)

FREQUENCY (kHz)

SETTLING TIME (ns)

232512 G11

232512 G10

232512 G12

Step Response

(Fine Settling)

External Reference Supply

Current vs Sample Frequency

REF Output vs Temperature

20

10

700

600

500

400

300

200

100

0

1.00

0.50

REFBUFEN = 0V

4.096V RANGE

+

(EXT REF BUF

IN = 5MHz

OVERDRIVING REF BUF)

SQUARE WAVE

V

= 3.3V

DD

–

IN = 0V

0

–0.50

–1.00

–1.50

–2.00

–2.50

–3.00

V

= 4.096V

0

REFOUT1,2,3,4

V

= 5V

DD

–10

V

= 2.048V

REFOUT1,2,3,4

–20

–20 –10

0

10 20 30 40 50 60 70 80 90

0

1

2

3

4

5

–55 –35 –15

5

25 45 65 85 105 125

SETTLING TIME (ns)

SAMPLE FREQUENCY (Msps)

TEMPERATURE (°C)

232512 G13

232512 G14

232512 G15

Supply Current

vs Sample Frequency

OV_DDCurrent vs SCK Frequency,

C_LOAD= 10pF

Offset Error vs Temperature

8

7

6

5

4

3

2

1

0

32

30

28

26

24

22

20

18

16

14

12

1.0

0.5

40

35

30

25

20

15

FULL SCALE SINUSOIDAL INPUT

LVDS

V

DD

= 5V

CMOS(2.5V)

0

V

= 3.3V

DD

CMOS(1.8V)

–0.5

LOW POWER LVDS

–1.0

0

22

44

66

88

110

–55 –35 –15

5

25 45 65 85 105 125

0

1

2

3

4

5

SCK FREQUENCY (MHz)

TEMPERATURE (°C)

SAMPLE FREQUENCY (Msps)

232512 G18

232512 G16

232512 G17

232512f

10

For more information www.linear.com/LTC2325-12

LTC2325-12

pin FuncTions

PINS THAT ARE THE SAME FOR ALL DIGITAL I/O MODES

REFOUT1(Pin22):ReferenceBuffer1Output.Anonboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

+

–

AIN4 , AIN4 (Pins 2, 1): Analog Differential Input Pins.

+

–

Full-scale range (AIN4 – AIN4 ) is ±REFOUT4 voltage.

These pins can be driven from V to GND.

DD

GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.

These pins and exposed pad (Pin 53) must be tied directly

to a solid ground plane.

SDR/DDR (Pin 23): Double Data Rate Input. Controls the

frequency of SCK and CLKOUT. Tie to GND for the falling

edge of SCK to shift each serial data output (Single Data

+

–

AIN3 , AIN3 (Pins 5, 4): Analog Differential Input Pins.

+

–

Full-scale range (AIN3 – AIN3 ) is ±REFOUT3 voltage.

These pins can be driven from V to GND.

Rate, SDR). Tie to OV to shift serial data output on each

DD

edge of SCK (Double Data Rate, DDR). CLKOUT will be a

REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

delayed version of SCK for both pin states.

CNV (Pin 24): Convert Input. This pin, when high, defines

the acquisition phase. When this pin is driven low, the

conversion phase is initiated and output data is clocked

out. This input must be driven at OV levels with a low

DD

jitter pulse. This pin is unaffected by the CMOS/LVDS pin.

REF (Pin 8): Common 4.096V reference output. Decouple

to GND with a 1μF low ESR ceramic capacitor. May be

overdriven with a single external reference to establish a

common reference for ADC cores 1 through 4.

CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin

to enable CMOS mode, tie to OV to enable LVDS mode.

DD

Float this pin to enable low power LVDS mode.

OV (Pins 31, 37): I/O Interface Digital Power. The range

DD

REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

of OV is 1.71V to 2.63V. This supply is nominally set

DD

to the same supply as the host interface (CMOS: 1.8V or

2.5V, LVDS: 2.5V). Bypass OV to GND (Pins 32 and 38)

DD

with 0.1µF capacitors.

REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie

to V when using the internal reference. Tie to ground

DD

to disable the internal REFOUT1–4 buffers for use with

+

–

AIN2 ,AIN2 (Pins11,10):AnalogDifferentialInputPins.

external voltage references. This pin has a 500k internal

+

–

Full-scale range (AIN2 – AIN2 ) is ±REFOUT2 voltage.

These pins can be driven from V to GND.

pull-up to V .

DD

REFOUT4 (Pin45):ReferenceBuffer4Output.Anonboard

buffer nominally outputs 4.096V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a 10µF (X5R, 0805 size) ceramic capacitor. The

internal buffer driving this pin may be disabled by ground-

ing the REFBUFEN pin. If the buffer is disabled, an external

reference may drive this pin in the range of 1.25V to 5V.

+

–

AIN1 ,AIN1 (Pins14,13):AnalogDifferentialInputPins.

+

–

Full-scale range (AIN1 – AIN1 ) is ±REFOUT1 voltage.

These pins can be driven from V to GND.

DD

V

(Pins 15, 21, 44, 52): Power Supply. Bypass V to

DD

GND with a 10µF ceramic capacitor and a 0.1µF ceramic

capacitorclosetothepart. TheV pinsshouldbeshorted

together and driven from the same supply.

DD

Exposed Pad (Pin 53): Ground. Solder this pad to ground.

232512f

11

For more information www.linear.com/LTC2325-12

LTC2325-12

pin FuncTions

CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)

LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR

FLOAT)

SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel

1. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 13-bit conversion

data to be read from SDO1 in SDR mode, 8 SCK edges

in DDR mode.

+

–

SDOA , SDOA (Pins 27, 28): LVDS Serial Data Output

for ADC Channel 1. The conversion result is shifted CH1

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 13-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

SDO2 (Pin 29): CMOS Serial Data Output for ADC Channel

2. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 13-bit conversion

data to be read from SDO2 in SDR mode, 8 SCK edges

in DDR mode.

+

–

SDOB , SDOB (Pins 29, 30): LVDS Serial Data Output

for ADC Channel 2. The conversion result is shifted CH2

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 13-bit conversion data to be read from SDOB in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

SDO3 (Pin 35): CMOS Serial Data Output for ADC Channel

3. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 13-bit conversion

data to be read from SDO3 in SDR mode, 8 SCK edges

in DDR mode.

+

–

CLKOUT ,CLKOUT (Pins33,34):SerialDataClockOutput.

CLKOUT provides a skew-matched clock to latch the SDO

outputatthereceiver.ThesepinsechotheinputatSCKwith

a small delay. These pins must be differentially terminated

by an external 100Ω resistor at the receiver (FPGA).

SDO4 (Pin 39): CMOS Serial Data Output for ADC Channel

4. The conversion result is shifted MSB first on each fall-

ing edge of SCK in SDR mode and each SCK edge in DDR

mode. 16 SCK edges are required for 13-bit conversion

data to be read from SDO4 in SDR mode, 8 SCK edges

in DDR mode.

+

–

SDOC , SDOC (Pins 35, 36): LVDS Serial Data Output

for ADC channel 3. The conversion result is shifted CH3

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 13-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver (FPGA). The logic level is determined by

+

–

OV . This pin echoes the input at SCK with a small delay.

SDOD , SDOD (Pins 39, 40): LVDS Serial Data Output

for ADC Channel 4. The conversion result is shifted CH4

MSB first on each falling edge of SCK in SDR mode and

each SCK edge in DDR mode. 16 SCK edges are required

for 13-bit conversion data to be read from SDOA in SDR

mode, 8 SCK edges in DDR mode. Terminate with a 100Ω

resistor at the receiver (FPGA).

DD

CLKOUTEN (Pin 34): CLKOUT can be disabled by tying

Pin 34 to OV for a small power savings. If CLKOUT is

DD

used, ground this pin.

SCK (Pin 41): Serial Data Clock Input. The falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins in SDR mode (DDR = LOW). In DDR mode

(SDR/DDR = HIGH) each edge of this clock shifts the

conversion result MSB first onto the SDO pins. The logic

+

–

SCK , SCK (Pins 41, 42): Serial Data Clock Input. The

falling edge of this clock shifts the conversion result MSB

first onto the SDO pins in SDR mode (SDR/DDR = LOW).

In DDR mode (SDR/DDR = HIGH) each edge of this clock

shifts the conversion result MSB first onto the SDO pins.

Thesepinsmustbedifferentiallyterminatedbyanexternal

level is determined by OV .

DD

DNC (Pins 28, 30, 36, 40, 42): In CMOS mode, do not

connect this pin.

100Ω resistor at the receiver (ADC).

232512f

12

For more information www.linear.com/LTC2325-12

LTC2325-12

FuncTional block DiagraM

CMOS IO Mode

V

GND

DD

24

CNV

(15, 21, 44, 52)

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

A

+

–

SDO1

DNC

IN1

+

–

27

28

14

13

12-BIT+SIGN

SAR ADC

CMOS

I/O

S/H

A

IN1

REFOUT1

×1

REF

22

A

+

–

IN2

SDO2

DNC

+

–

11

10

29

30

12-BIT+SIGN

SAR ADC

CMOS

I/O

S/H

IN2

REFOUT2

×1

REF

9

CLKOUT

SCK

41

42

33

34

CMOS

RECEIVERS

OUTPUT

CLOCK DRIVER

CLKOUTEN

DNC

SDR/DDR

23

A

+

–

IN3

SDO3

DNC

+

5

4

35

36

12-BIT+SIGN

SAR ADC

CMOS

I/O

S/H

–

IN3

REFOUT3

×1

REF

6

A

+

–

IN4

SDO4

DNC

+

2

1

39

40

12-BIT+SIGN

SAR ADC

CMOS

I/O

S/H

–

IN4

REFOUT4

×1

REF

45

250μA

OV (31, 37)

DD

REF

×1.7

×3.4

8

1.2V INT REF

REFBUFEN

43

25

CMOS/LVDS

232512 BDa

232512f

13

For more information www.linear.com/LTC2325-12

LTC2325-12

FuncTional block DiagraM

LVDS IO Mode

V

GND

DD

24

CNV

(15, 21, 44, 52)

(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)

+

–

A

+

–

SDOA

IN1

+

–

27

28

14

13

LVDS

I/O

12-BIT+SIGN

SAR ADC

S/H

A

IN1

REFOUT1

×1

REF

22

+

A

+

–

SDOB

IN2

+

–

11

10

29

30

LVDS

I/O

12-BIT+SIGN

SAR ADC

–

S/H

SDOB

IN2

REFOUT2

×1

REF

9

+

–

CLKOUT

SCK

41

42

33

34

LVDS

RECEIVERS

OUTPUT

CLOCK DRIVER

–

CLKOUT

SDR/DDR

23

+

A

+

SDOC

IN3

+

5

4

35

36

LVDS

I/O

12-BIT+SIGN

SAR ADC

–

S/H

–

A

–

SDOC

IN3

REFOUT3

×1

REF

6

+

A

+

–

SDOD

IN4

+

2

1

39

40

LVDS

I/O

12-BIT+SIGN

SAR ADC

–

S/H

–

SDOD

IN4

REFOUT4

×1

REF

45

250μA

OV (31, 37)

DD

REF

×1.7

×3.4

8

1.2V INT REF

REFBUFEN

43

25

CMOS/LVDS

232512 BDb

232512f

14

For more information www.linear.com/LTC2325-12

LTC2325-12

TiMing DiagraM

SDR Mode, CMOS

SAMPLE N

SAMPLE N+1

CNV

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

Hi-Z

CLKOUT

Hi-Z

SDO1

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[12:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

Hi-Z

SDO4

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[12:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

ACQUIRE

CONVERSION AND READOUT

232512 TD01

DDR Mode, CMOS

SAMPLE N

SAMPLE N+1

CNV

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

Hi-Z

CLKOUT

Hi-Z

SDO1

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[12:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

Hi-Z

SDO4

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[12:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

232512 TD02

ACQUIRE

CONVERSION AND READOUT

232512f

15

For more information www.linear.com/LTC2325-12

LTC2325-12

TiMing DiagraM

SDR Mode, LVDS

SAMPLE N

SAMPLE N+1

CNV

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

CLKOUT

SDOA

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

SDOD

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

ACQUIRE

CONVERSION AND READOUT

232512 TD03

DDR Mode, LVDS

SAMPLE N

SAMPLE N+1

CNV

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

CLKOUT

SDOA

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1

SDOD

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4

232512 TD04

ACQUIRE

CONVERSION AND READOUT

232512f

16

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

OVERVIEW

TRANSFER FUNCTION

The LTC2325-12 is a low noise, high speed 12-bit succes-

sive approximation register (SAR) ADC with differential

inputs and a wide input common mode range. Operating

from a single 3.3V or 5V supply, the LTC2325-12 has a

The LTC2325-12 digitizes the full-scale voltage of 2 •

13

REFOUT1,2,3,4 into 2 levels, resulting in an LSꢀ size of

1mVwithREF=4.±96V.Theidealtransferfunctionisshown

in Figure 2. The output data is in 2’s complement format.

When driven by fully differential inputs, the transfer func-

4V or 8V differential input range, making it ideal for

P-P

13

applications which require a wide dynamic range. The

LTC2325-12 achieves ±±.5LSꢀ INL typical, no missing

codes at 12 bits and 77dꢀ SNR.

tion spans 2 codes. When driven by pseudo-differential

12

inputs, the transfer function spans 2 codes.

TheLTC2325-12hasanonboardreferencebufferandlow

drift(2±ppm/°Cmax)4.±96Vtemperature-compensated

reference. The LTC2325-12 also has a high speed SPI-

compatible serial interface that supports CMOS or LVDS.

The fast 5Msps per channel throughput with one-cycle

latency makes the LTC2325-12 ideally suited for a wide

variety of high speed applications. The LTC2325-12 dis-

sipates only 45mW per channel. Nap and sleep modes

are also provided to reduce the power consumption

of the LTC2325-12 during inactive periods for further

power savings.

0 1111 1111 1111

0 1111 1111 1110

0 0000 0000 0001

0 0000 0000 0000

1 1111 1111 1111

1LSB = 2 • REFOUT1,2

1 0000 0000 0001

8192

1 0000 0000 0000

–REFOUT

–1LSB 0 1LSB

REFOUT

–1LSB

INPUT VOLTAGE (V)

232512 F02

Figure 2. LTC2325-12 Transfer Function

CONVERTER OPERATION

The LTC2325-12 operates in two phases. During the ac-

quisition phase, the sample capacitor is connected to the

V

DD

C

IN

R

15Ω

ON

10pF

analog input pins A and A to sample the differential

+

–

IN

A

+

IN

analoginputvoltage,asshowninFigure3.Afallingedgeon

the CNV pin initiates a conversion. During the conversion

phase,the13-bitCDACissequencedthroughasuccessive

approximationalgorithmeffectivelycomparingthesampled

input with binary-weighted fractions of the reference volt-

BIAS

VOLTAGE

V

DD

C

IN

R

15Ω

ON

10pF

232512 F03

age (e.g., V /2, V

REFOUT

/4 … V

REFOUT

/32768) using

REFOUT

–

IN

adifferentialcomparator. Attheendofconversion, aCDAC

output approximates the sampled analog input. The ADC

control logic then prepares the 13-bit digital output code

for serial transfer.

Figure 3. The Equivalent Circuit for the Differential

Analog Input of the LTC2325-12

Table 1. Code Ranges for the Analog Input Operational Modes

+

–

MODE

SPAN (V – V

)

IN

MIN CODE

MAX CODE

IN

Fully Differential

–REFOUT to +REFOUT

–REFOUT/2 to +REFOUT/2

± to REFOUT

1 ±±±± ±±±± ±±±±

1 1±±± ±±±± ±±±±

± ±±±± ±±±± ±±±±

± 1111 1111 1111

± ±111 1111 1111

± 1111 1111 1111

Pseudo-Differential ꢀipolar

Pseudo-Differential Unipolar

232512f

17

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Analog Input

is connected to the input. Any unwanted signal that is

common to both inputs will be reduced by the common

mode rejection of the ADC sampler. The inputs of the

ADC core draw a small current spike while charging the

The differential inputs of the LTC2325-12 provide great

flexibility to convert a wide variety of analog signals with

no configuration required. The LTC2325-12 digitizes the

C capacitors during acquisition.

IN

difference voltage between the A and A pins while

+

–

IN

supporting a wide common mode input range. The analog

Single-Ended Signals

input signals can have an arbitrary relationship to each

Single-ended signals can be directly digitized by the

LTC2325-12. These signals should be sensed pseudo-

differentially for improved common mode rejection. ꢀy

connecting the reference signal (e.g., ground sense) of

other, provided that they remain between V and GND.

DD

The LTC2325-12 can also digitize more limited classes of

analog input signals such as pseudo-differential unipolar/

bipolarandfullydifferentialwithnoconfigurationrequired.

the main analog signal to the other A pin, any noise or

IN

The analog inputs of the LTC2325-12 can be modeled

by the equivalent circuit shown in Figure 3. The back-

to-back diodes at the inputs form clamps that provide

disturbance common to the two signals will be rejected

by the high CMRR of the ADC. The LTC2325-12 flexibility

handles both pseudo-differential unipolar and bipolar

signals,withnoconfigurationrequired.Thewidecommon

mode input range relaxes the accuracy requirements of

anysignalconditioningcircuitspriortotheanaloginputs.

ESD protection. In the acquisition phase, 1±pF (C )

IN

from the sampling capacitor in series with approximately

15Ω(R )fromtheon-resistanceofthesamplingswitch

ON

V

REF

V

REF

LT1819

LTC2325-12

25Ω

+

–

0V

A

+

REFOUT1

REF

IN1

10µF

1µF

V

REF

220pF

10k

V

/2

REF

+

–

V

/2

REF

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

A

SDO1

CLKOUT

SCK

IN1

10k

1µF

ONLY CHANNEL 1 SHOWN FOR CLARITY

232512 F04

Figure 4. Pseudo-Differential Bipolar Application Circuit

ADC CODE

(2’s COMPLEMENT)

4095

2047

A

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

DOTTED REGIONS AVAILABLE

–2048

–4096

232512 F05

Figure 5. Pseudo-Differential Bipolar Transfer Function

232512f

18

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Pseudo-Differential Bipolar Input Range

Pseudo-Differential Unipolar Input Range

The pseudo-differential bipolar configuration represents

driving one of the analog inputs at a fixed voltage, typically

The pseudo-differential unipolar configuration represents

driving one of the analog inputs at ground and applying a

V

/2, and applying a signal to the other A pin. In this

signal to the other A pin. In this case, the analog input

REF

IN

case the analog input swings symmetrically around the

fixedinputyieldingbipolartwo’scomplementoutputcodes

with an ADC span of half of full-scale. This configuration

is illustrated in Figure 4, and the corresponding transfer

function in Figure 5. The fixed analog input pin need not

be set at V /2, but at some point within the V rails

swings between ground and V yielding unipolar two’s

REF

complement output codes with an ADC span of half of

full-scale. This configuration is illustrated in Figure 6, and

thecorrespondingtransferfunctioninFigure7.Iftheinput

signal (A – A ) swings negative, valid codes will be

+

–

IN

generated by the ADC and must be clamped by the user,

if necessary.

REF

DD

allowingthealternateinputtoswingsymmetricallyaround

thisvoltage.Iftheinputsignal(A –A )swingsbeyond

+

–

IN

±REFOUT1,2,3,4/2, valid codes will be generated by the

ADC and must be clamped by the user, if necessary.

V

REF

LT1818

LTC2325-12

V

REF

25Ω

+

–

0V

A

+

REFOUT1

IN1

0V

10µF

1µF

REF

220pF

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

SDO1

CLKOUT

SCK

IN1

232512 F06

Figure 6. Pseudo-Differential Unipolar Application Circuit

ADC CODE

(2’s COMPLEMENT)

4095

2047

A

IN

(A + – A –)

IN IN

–V

–V /2

REF

0

V

REF

/2

V

REF

DOTTED REGIONS AVAILABLE

–2048

–4096

232512 F07

Figure 7. Pseudo-Differential Unipolar Transfer Function

232512f

19

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Single-Ended-to-Differential Conversion

signal can span the maximum full-scale of the ADC, up to

±REFOUT1,2,3,4. The common mode input voltage can

Whilesingle-endedsignalscanbedirectlydigitizedaspre-

viously discussed, single-ended to differential conversion

circuits may also be used when higher dynamic range is

desired. ꢀy producing a differential signal at the inputs of

the LTC2325-12, the signal swing presented to the ADC is

maximized, thus increasing the achievable SNR.

The LT^®1819 high speed dual operational amplifier is

recommendedforperformingsingle-ended-to-differential

conversions, as shown in Figure 8. In this case, the first

amplifier is configured as a unity-gain buffer and the

single-ended input signal directly drives the high imped-

ance input of this amplifier.

span the entire supply range up to V , limited by the

DD

input signal swing. The fully-differential configuration is

illustrated in Figure 1±, with the corresponding transfer

function illustrated in Figure 11.

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high im-

pedance inputs of the LTC2325-12 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC inputs

draw a current spike when during acquisition.

Fully-Differential Inputs

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2325-12. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC inputs, which draw a small

current spike during acquisition.

To achieve the best distortion performance of the

LTC2325-12, we recommend driving a fully-differential

signal through LT1819 amplifiers configured as two

unity-gain buffers, as shown in Figure 9. This circuit

achieves the full data sheet THD specification of –88dꢀ at

input frequencies up to 5±±kHz. A fully-differential input

V

REF

0V

LT1819

V

REF

+

–

+

–

0V

V

REF

0V

V

REF

V

REF

/2

+

–

+

–

200Ω

0V

200Ω

232512 F09

232512 F08

Figure 8. Single-Ended to Differential Driver

Figure 9. LT1819 Buffering a Fully-Differential Signal Source

232512f

20

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Input Filtering

the input bandwidth to the ADC core to 11±MHz. A buffer

amplifier with a low noise density must be selected to

minimize the degradation of the SNR over this bandwidth.

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter

to minimize noise. The simple 1-pole RC lowpass filter

shown in Figure 12 is sufficient for many applications.

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

The sampling switch on-resistance (R ) and the sample

ON

capacitor (C ) form a second lowpass filter that limits

IN

V

REF

0V

LT1819

LTC2325-12

25Ω

+

–

0V

A

+

REFOUT1

REF

IN1

10µF

1µF

220pF

V

REF

0V

REF

+

–

0V

TO CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

–

A

SDO1

CLKOUT

SCK

IN1

ONLY CHANNEL 1 SHOWN FOR CLARITY

232512 F10

Figure 10. Fully-Differential Application Circuit

ADC CODE

(2’s COMPLEMENT)

4095

2047

A

IN

(A + – A –)

INn

–V

–V /2

REF

0

V

REF

/2

V

REF

–2048

–4096

232512 F11

Figure 11. Fully-Differential Transfer Function

232512f

21

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

ADC REFERENCE

the four internal reference buffers with a current limited

output (25±μA) so it may be easily overdriven with an

external reference in the range of 1.25V to 5V. ꢀypass

REF to GND with a 1μF (X5R, ±8±5 size) ceramic capacitor

to compensate the reference buffer and minimize noise.

The 1μF capacitor should be as close as possible to the

LTC2325-12 package to minimize wiring inductance. The

voltage on the REF pin must be externally buffered if used

for external circuitry.

Internal Reference

The LTC2325-12 has an on-chip, low noise, low

drift (2±ppm/°C max), temperature compensated band-

gap reference. It is internally buffered and is available

at REF (Pin 8). The reference buffer gains the internal

reference voltage to 4.±96V for supply voltages V = 5V

DD

and to 2.±48V for V = 3.3V. The REF pin also drives

DD

SINGLE-ENDED

INPUT SIGNAL

50Ω

+

IN

LTC2325

–

IN

3.3nF

SINGLE-ENDED

TO DIFFERENTIAL

232512 F12

DRIVER

BW = 1MHz

Figure 12. Input Signal Chain

Table 2. Reference Configurations and Ranges

REFOUT1,2,3,4

DIFFERENTIAL

INPUT RANGE

REFERENCE CONFIGURATION

V

REFBUFEN

5V

REF PIN

4.±96V

DD

Internal Reference with Internal ꢀuffers

5V

3.3V

5V

4.±96V

±4.±96V

3.3V

5V

2.±48V

±2.±48V

Common External Reference with Internal ꢀuffer (REF Pin

Externally Overdriven)

1.25V to 5V

4.±96V

1.25V to 3.3V

1.25V to 5V

1.25V to 3.3V

±1.25V to ±5V

±1.25V to ±3.3V

±1.25V to ±5V

±1.25V to ±3.3V

3.3V

5V

3.3V

±V

External Reference with REF ꢀuffers Disabled

3.3V

±V

2.±48V

232512f

22

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

External Reference

recommendedwhenoverdrivingREFOUT. TheLTC6655-5

offers the same small size, accuracy, drift and extended

temperature range as the LTC6655-4.±96. ꢀy using a 5V

reference, a higher SNR can be achieved. We recommend

bypassing the LTC6655-5 with a 1±μF ceramic capacitor

(X5R, ±8±5 size) close to each of the REFOUT1,2,3,4

pins. If the REF pin voltage is used as a REFOUT refer-

ence when REFꢀUFEN is connected to GND, it should be

buffered externally.

The internal REFOUT1,2,3,4 buffers can also be over-

driven from 1.25V to 5V with an external reference at

REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,

REFꢀUFEN must be grounded to disable the REF buffers.

A 55k internal resistance loads the REFOUT1,2,3,4 pins

when the REF buffers are disabled. To maximize the input

signal swing and corresponding SNR, the LTC6655-5 is

V

3.3V TO 5V

DD

V

+5V

DD

5V TO

13.2V

REFBUFEN

REF

REFBUFEN

REF

LTC6655-4.096

V

IN

OUT_F

V

OUT_S

1µF

LTC2325-12

SHDN

LTC2325-12

10µF

0.1µF

REFOUT1

REFOUT2

REFOUT3

REFOUT4

REFOUT1

REFOUT2

REFOUT3

REFOUT4

10µF

GND

232512 F13a

232512 F13b

(13a) LTC2325-12 Internal Reference Circuit

(13b) LTC2325-12 with a Shared External Reference Circuit

V

+5V

DD

REFBUFEN

REF

1µF

5V TO 13.2V

LTC6655-4.096

V

IN

OUT_F

V

OUT_S

REFOUT1

SHDN

10µF

0.1µF

LTC2325-12

LTC6655-2.048

V

REFOUT2

REFOUT3

IN

OUT_F

V

OUT_S

SHDN

LTC6655-2.5

V

IN

OUT_F

SHDN

V

OUT_S

LTC6655-3

V

IN

OUT_F

V

OUT_S

REFOUT4

SHDN

GND

232512 F13c

(13c) LTC2325-12 with Different External Reference Voltages

Figure 13. Reference Connections

232512f

23

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Internal Reference Buffer Transient Response

The REFOUT1,2,3,4 pins of the LTC2325-12 draw charge

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2325-12 provides

guaranteed tested limits for both AC distortion and noise

measurements.

(Q

) from the external bypass capacitors during

CONV

each conversion cycle. If the internal reference buffer is

overdriven, the external reference must provide all of this

charge with a DC current equivalent to I = Q

/t

.

REF

CONV CYC

Thus, the DC current draw of I

depends

REFOUT1,2,3,4

on the sampling rate and output code. In applications

where a burst of samples is taken after idling for long

periods, as shown in Figure 14 , I

quickly goes

REFꢀUF

Signal-to-Noise and Distortion Ratio (SINAD)

from approximately ~75µA to a maximum of 5±±µA for

REFOUT = 5V at 5Msps. This step in DC current draw

triggers a transient response in the external reference that

must be considered since any deviation in the voltage at

REFOUT will affect the accuracy of the output code. Due

to the one-cycle conversion latency, the first conversion

result at the beginning of a burst sampling period will

be invalid. If an external reference is used to overdrive

REFOUT1,2,3,4, the fast settling LTC6655 reference is

recommended.

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is bandlimited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure16showsthattheLTC2325-12achieves

a typical SINAD of 76dꢀ at a 5MHz sampling rate with a

2.2MHz input.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 16 shows

that the LTC2325-12 achieves a typical SNR of 77dꢀ at a

5MHz sampling rate with a 2.2MHz input.

CNV

IDLE

PERIOD

232512 F14

Figure 14. CNV Waveform Showing Burst Sampling

0

16384

SNR = 77.1dB

THD = –87.2dB

–20

SINAD = 76.2dB

SFDR = 90.3dB

12288

–40

8192

–60

–80

4.096V RANGE

4096

–100

–120

–140

0

+

IN = 5MHz SQUARE WAVE

–

IN = 0V

–4096

0

0.5

1

1.5

2

2.5

–20 –10

0

10 20 30 40 50 60 70 80 90

FREQUENCY (MHz)

SETTLING TIME (ns)

232512 F16

232512 F15

Figure 15. Transient Response of the LTC2325-12

Figure 16. 32k Point FFT of the LTC2325-12

232512f

24

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

Total Harmonic Distortion (THD)

allows the LTC2325-12 to communicate with any digital

logic operating between 1.8V and 2.5V. When using LVDS

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

I/O, the OV supply must be set to 2.5V.

DD

Power Supply Sequencing

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

The LTC2325-12 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2325-12

has a power-on-reset (POR) circuit that will reset the

LTC2325-12 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 1±ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

V2²+V3²+V4²+…+V_N²

THD=2±log

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through V are the amplitudes of the

N

second through Nth harmonics.

POWER CONSIDERATIONS

The LTC2325-12 requires two power supplies: the 3.3V

to 5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

40

35

30

25

20

15

V

DD

= 5V

V

= 3.3V

DD

0

1

2

3

4

5

SAMPLE FREQUENCY (Msps)

232516 F17

Figure 17. Power Supply Current of the LTC2325-12 Versus Sampling Rate

232512f

25

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

TIMING AND CONTROL

capture the SDO output eases timing requirements at the

receiver. For low throughput speed applications, CLKOUT

CNV Timing

can be disabled by tying Pin 34 to OV .

DD

The LTC2325-12 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

fallingedgestartstheconversionandreadoutprocess.The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source. Note the low jitter input clock times the falling

edge of the CNV signal. The rising edge jitter of CNV is

much less critical to performance. The typical pulse width

of the CNV signal is 3±ns with < 1.5ns rise and fall times

at a 5Msps conversion rate.

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-updelaysforsubsequentconversions. Sleepmode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2325-12,

the SCK signal must be held high or low and a series of

two CNV pulses must be applied. This is the case for both

CMOS and LVDS modes. The second rising edge of CNV

initiates the nap state. The nap state will persist until either

asinglerisingedgeofSCKisapplied,orfurtherCNVpulses

are applied. The SCK rising edge will put the LTC2325-12

back into the operational (full-power) state. When in nap

mode, two additional pulses will put the LTC2325-12 in

sleep mode. When configured for CMOS I/O operation, a

single rising edge of SCK can return the LTC2325-12 into

operational mode. A 1±ms delay is necessary after exiting

sleep mode to allow the reference buffer to recharge the

external filter capacitor. In LVDS mode, exit sleep mode

by supplying a fifth CNV pulse. The fifth pulse will return

the LTC2325-12 to operational mode, and further SCK

pulses will keep the part from re-entering nap and sleep

modes. The fifth SCK pulse also works in CMOS mode

as a method to exit sleep. In the absence of SCK pulses,

repetitive CNV pulses will cycle the LTC2325-12 between

operational, nap and sleep modes indefinitely.

SCK Serial Data Clock Input

In SDR mode (SDR/DDR Pin 23 = GND), the falling edge

of this clock shifts the conversion result MSꢀ first onto

the SDO pins. A 1±±MHz external clock must be applied

at the SCK pin to achieve 5Msps throughput using all four

SDO outputs. In DDR mode (SDR/DDR Pin 23 = OV ),

DD

each input edge of SCK shifts the conversion result MSꢀ

first onto the SDO pins. A 5±MHz external clock must be

applied at the SCK pin to achieve 5Msps throughput using

all five SDO1 through SDO4 outputs.

CLKOUT Serial Data Clock Output

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK to

RefertothetimingdiagramsinFigure18,Figure19,Figure2±

and Figure 21 for more detailed timing information about

sleep and nap modes.

CNV

1

2

NAP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

Z

WAKE ON 1ST SCK EDGE

SDO1 – 4

Z

232512 F18

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

232512f

26

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

REFOUT

RECOVERY

REFOUT1 – 4

4.096V

t

WAKE

CNV

1

2

3

4

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

WAKE ON 1ST SCK EDGE

SDO1 – 4

Z

232512 F19

Figure 19. CMOS Mode SLEEP and WAKE Using SCK

REFOUT

RECOVERY

REFOUT1 – 4

4.096V

t

WAKE

WAKE ON 5TH

CNV EDGE

CNV

1

2

3

4

5

NAP MODE

SLEEP MODE

FULL POWER MODE

SCK

HOLD STATIC HIGH OR LOW

SDO1 – 4

Z

232512 F20

Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV

SDR MODE TIMING

DDR MODE TIMING

t

CYC

t

READOUT

CNVH

CONV

t

CNVH

CONV

READOUT

t

DSCKCNVH

t

DSCKCNVH

CNV

t

SCKH

t

SCK

SCKH

t

SCK

1

2

3

14

15

16

1

2

3

14

15

16

t

SCKL

t

SCKL

CLKOUT

1

2

3

14

15

16

1

2

3

14

15

16

t

DSCKCLKOUT

t

DSCKCLKOUT

t

DCNVSDOV

DCNVSDOZ

t

HSDO

DCNVSDOV

HI-Z

SDO

D12

D11

D10

X

D12

SDO

D12

D11

D10

X

D12

232512 F21

Figure 21. LTC2325-12 Timing Diagram

232512f

27

For more information www.linear.com/LTC2325-12

LTC2325-12

applicaTions inForMaTion

DIGITAL INTERFACE

SDR/DDR Modes

The LTC2325-12 features a serial digital interface that

The LTC2325-12 has an SDR (single data rate) and DDR

(double data rate) mode for reading conversion data from

theSDOpins. Inbothmodes, CLKOUTisadelayedversion

of SCK. In SDR mode, each negative edge of SCK shifts

the conversion data out the SDO pins. In DDR mode,

each edge of the SCK input shifts the conversion data

out. In DDR mode, the required SCK frequency is half of

what is required in SDR mode. Tie SDR/DDR to ground

to configure for SDR mode and to OVDD for DDR mode.

The CLKOUT signal is a delayed version of the SCK input

and is phase aligned with the SDO data. In SDR mode, the

SDO transitions on the falling edge of CLKOUT as illus-

trated in Figure 21. We recommend using the rising edge

of CLKOUT to latch the SDO data into the FPGA register

in SDR mode. In DDR mode, the SDO transitions on each

input edge of SCK. We recommend using the CLKOUT ris-

ing and falling edges to latch the SDO data into the FPGA

registers in DDR mode. Since the CLKOUT and SDO data

are phase aligned, we recommend digitally delaying the

SDO data in the FPGA to provide adequate setup and hold

timing margins in DDR mode.

is simple and straightforward to use. The flexible OV

DD

supply allows the LTC2325-12 to communicate with any

digital logic operating between 1.8V and 2.5V. In addi-

tion to a standard CMOS SPI interface, the LTC2325-12

provides an optional LVDS SPI interface to support low

noise digital design. The CMOS /LVDS pin is used to select

the digital interface mode. The SCK input clock shifts the

conversion result MSB first on the SDO pins. CLKOUT

provides a skew-matched clock to latch the SDO output

at the receiver. The timing skew of the CLKOUT and SDO

outputs are matched. For high throughput applications,

using CLKOUT instead of SCK to capture the SDO output

eases timing requirements at the receiver. In CMOS mode,

use the SDO1 – SDO4, and CLKOUT pins as outputs. Use

+

the SCK pin as an input. In LVDS mode, use the SDOA /

–

+

–

+

–

SDOA through SDOD /SDOD and CLKOUT /CLKOUT

pins as differential outputs. Each LVDS lane yields one

channel worth of data: SDOA yields CH1 data, SDOB

yields CH2 data, SDOC yields CH3 data and SDOD yields

CH4 data. These pins must be differentially terminated

by an external 100Ω resistor at the receiver (FPGA).

+

–

The SCK /SCK pins are differential inputs and must be

terminated differentially by an external 100Ω resistor at

the receiver(ADC).

BOARD LAYOUT

To obtain the best performance from the LTC2325-12,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

2.5V

LTC2325-12

FPGA OR DSP

OV

DD

+

–

+

–

SCK

100Ω

+

–

+

–

SDOD

+

–

+

–

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common re-

turns for these bypass capacitors are essential to the low

noise operation of the ADC. A single solid ground plane

is recommended for this purpose. When possible, screen

the analog input traces using ground.

SDOC

100Ω

2.5V

CMOS/LVDS

+

–

+

–

CLKOUT

+

–

+

–

SDOB

+

–

+

–

SDOA

Recommended Layout

RETIMING

FLIP-FLOP

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2395A, the evaluation kit for the LTC2325-12.

CNV

232512 F22

Figure 22. LTC2325-12 Using the LVDS Interface

232512f

28

For more information www.linear.com/LTC2325-12

LTC2325-12

package DescripTion

Please refer to http://www.linear.com/product/LTC2325-12#packaging for the most recent package drawings.

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

7.50 ±0.05

6.10 ±0.05

5.50 REF

(2 SIDES)

0.70 ±0.05

6.45 ±0.05

6.50 REF

(2 SIDES)

7.10 ±0.05 8.50 ±0.05

5.41 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.50 REF

(2 SIDES)

0.75 ±0.05

7.00 ±0.10

(2 SIDES)

R = 0.115

TYP

0.00 – 0.05

51

52

0.40 ±0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45°C

CHAMFER

6.45 ±0.10

8.00 ±0.10

(2 SIDES)

6.50 REF

(2 SIDES)

5.41 ±0.10

(UKG52) QFN REV

Ø 0306

R = 0.10

TYP

0.25 ±0.05

0.50 BSC

TOP VIEW

SIDE VIEW

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

0.75 ±0.05

NOTE:

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

3. ALL DIMENSIONS ARE IN MILLIMETERS

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

232512f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

29

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2325-12

LTC2325-12

Typical applicaTion

Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop

V

CC

NC7SVUO4P5X

0.1µF

1k

MASTER_CLOCK

V

CC

50Ω

1k

D

PRE

NC7SV74K8X

CONV

Q

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

CLR

CONV ENABLE

CNV

LTC2325-12

SCK

10Ω

CLKOUT

GND

CMOS/LVDS

SDR/DDR

SDO1 – 4

232512 TA02

NC7SVU04P5X (× 5)

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC2311-16/LTC2311-14/ 16-/14-/12-Bit, 5Msps Simultaneous Sampling ADC 3.3V Supply, 1-Channel 40mW, 20ppm/°C Internal Reference, Flexible

LTC2311-12

Inputs, 16-Lead MSOP Package

LTC2323-16/LTC2323-14/ 16-14-/12-Bit Dual Simultaneous Sampling ADC

LTC2323-12

3V/5V Supply, 40mW/Ch, 20ppm/°C Max Internal Reference, Flexible

Inputs, 4mm × 5mm QFN-28 Package

LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, Dual 2Msps, Simultaneous

3.3V/5V Supply, 33mW/Ch, 20ppm°C Max Internal Reference,

Flexible Inputs, 4mm × 5mm QFN-28 Package

LTC2321-12

Sampling ADCs

LTC2320-16/LTC2320-14/ 16-/14-12-Bit Octal, 1.5Msps/Ch Simultaneous

LTC2320-12 Sampling ADC

3.3V/5V Supply, 20mW/Ch, 20ppm/°C Internal Reference,

Flexible Inputs, 7mm × 8mm QFN-52 Package

LTC2324-16/LTC2324-14/ 16-/14-12-Bit Quad, 2Msps/Ch Simultaneous

3.3V/5V Supply, 40mW/Ch, 20ppm/°C Internal Reference,

Flexible Inputs, 7mm × 8mm QFN-52 Package

LTC2324-12

Sampling ADC

DACs

LTC2632

Dual 12-/10-/8-Bit, SPI V

Reference

DACs with Internal

DACs with External

2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, 8-Pin ThinSOT™ Package

OUT

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit SPI V

Reference

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead

MSOP Package

OUT

References

LTC6655

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm

Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm

Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT1818/LT1819

400MHz, 2500V/µs, 9mA Single/Dual Operational

Amplifiers

–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply

Current, Unity-Gain Stable

LT1806

LT6200

325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,

Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable

165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable

Low Noise, Op Amp Family

232512f

LT 0417 • PRINTED IN USA

www.linear.com/LTC2325-12

30

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTC2325-12


型号：	LTC2325CUKG-12#PBF
厂家：	Linear
描述：	LTC2325-12 - Quad, 12-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: 0°C to 70°C 转换器
文件：	总30页 (文件大小：1341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2325CUKG-12#PBF [Linear]

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