LTC2377-18_技术文档

LTC2369-18

18-Bit, 1.6Msps, Pseudo-

Differential Unipolar SAR

ADC with 96.5dB SNR

FEATURES

DESCRIPTION

The LTC^®2369-18 is a low noise, low power, high speed

18-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2369-18 has a 0V

n

1.6Msps Throughput Rate

n

2.ꢀ5Sꢁ IN5 ꢂMaꢃx

n

Guaranteed 18-ꢁit No Missing Codes

n

5ow Power: 18mW at 1.6Msps, 18μW at 1.6ksps

to V pseudo-differential unipolar input range with V

REF

n

96.ꢀdꢁ SNR ꢂTypx at f = 2kHz

rangingfrom2.5Vto5.1V.TheLTC2369-18consumesonly

18mW and achieves 2.5LSꢀ ꢁIL maximum, no missing

codes at 18 bits with 96.5dꢀ SIR.

IN

n

–120dꢁ THD ꢂTypx at f = 2kHz

n

Guaranteed Operation to 125°C

n

2.5V Supply

The LTC2369-18 has a high speed SPꢁ-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic while

also featuring a daisy-chain mode. The fast 1.6Msps

throughput with no cycle latency makes the LTC2369-18

ideally suited for a wide variety of high speed applications.

Aninternaloscillatorsetstheconversiontime,easingexter-

nal timing considerations. The LTC2369-18 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

n

Pseudo-Differential Unipolar ꢁnput Range: 0V to V

REF

n

V

ꢁnput Range from 2.5V to 5.1V

REF

Io Pipeline Delay, Io Cycle Latency

1.8V to 5V ꢁ/O Voltages

SPꢁ-Compatible Serial ꢁ/O with Daisy-Chain Mode

ꢁnternal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFI Packages

APPLICATIONS

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents including 7705765.

n

Medical ꢁmaging

n

High Speed Data Acquisition

n

Portable or Compact ꢁnstrumentation

ꢁndustrial Process Control

Low Power ꢀattery-Operated ꢁnstrumentation

ATE

n

TYPICAL APPLICATION

32k Point FFT f_S= 1.6Msps, f_IN= 2kHz

0

2.5V 1.8V TO 5V

10μF

SIR = 96.5dꢀ

–20

–40

THD = –127dꢀ

SꢁIAD = 96.5dꢀ

SFDR = 134dꢀ

0.1μF

V

REF

–60

+

–

V

OV

DD

5.1Ω

CHAꢁI

RDL/SDꢁ

SDO

SCK

ꢀUSY

CIV

0V

+

–

–80

LT^®6202

ꢁI

–100

–120

–140

–160

–180

10nF

LTC2369-18

ꢁI

SAMPLE CLOCK

REF

GID

236918 TA01a

2.5V TO 5.1V

47μF

(X5R, 0805 SꢁZE)

0

100 200 300 400 500 600 700 800

FREQUEICY (kHz)

236918 TA01b

236918fa

1

LTC2369-18

ABSOLUTE MAXIMUM RATINGS ^{ꢂNotes 1, 2x}

Supply Voltage (V )...............................................2.8V

Power Dissipation.............................................. 500mW

DD

Supply Voltage (OV )................................................6V

Operating Temperature Range

DD

Reference ꢁnput (REF).................................................6V

LTC2369C................................................ 0°C to 70°C

LTC2369ꢁ .............................................–40°C to 85°C

LTC2369H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Analog ꢁnput Voltage (Iote 3)

+

–

ꢁI , ꢁI .........................(GID – 0.3V) to (REF + 0.3V)

Digital ꢁnput Voltage

(Iote 3).......................... (GID – 0.3V) to (OV + 0.3V)

DD

Digital Output Voltage

(Iote 3).......................... (GID – 0.3V) to (OV + 0.3V)

DD

PIN CONFIGURATION

TOP VꢁEW

CHAꢁI

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GID

OV

TOP VꢁEW

V

DD

CHAꢁI 1

16 GID

GID

SDO

V

2

15 OV

DD

+

GID 3

14 SDO

13 SCK

17

GID

ꢁI

SCK

+

–

ꢁI

4

5

–

ꢁI

RDL/SDꢁ

ꢀUSY

GID

12 RDL/SDꢁ

11 ꢀUSY

10 GID

GID

REF

GID 6

REF 7

REF 8

9

CIV

MS PACKAGE

16-LEAD PLASTꢁC MSOP

DE PACKAGE

T

JMAX

= 150°C, θ = 110°C/W

16-LEAD (4mm w 3mm) PLASTꢁC DFI

JA

T

= 150°C, θ = 40°C/W

JMAX

JA

EXPOSED PAD (PꢁI 17) ꢁS GID, MUST ꢀE SOLDERED TO PCꢀ

ORDER INFORMATION

5EAD FREE FINISH

LTC2369CMS-18#PꢀF

LTC2369ꢁMS-18#PꢀF

LTC2369HMS-18#PꢀF

LTC2369CDE-18#PꢀF

LTC2369ꢁDE-18#PꢀF

TAPE AND REE5

PART MARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC2369CMS-18#TRPꢀF 236918

LTC2369ꢁMS-18#TRPꢀF 236918

LTC2369HMS-18#TRPꢀF 236918

LTC2369CDE-18#TRPꢀF 23698

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

16-Lead (4mm × 3mm) Plastic DFI

LTC2369ꢁDE-18#TRPꢀF

23698

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

236918fa

2

LTC2369-18

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5

V +

PARAMETER

CONDITIONS

(Iote 5)

MIN

–0.1

0

TYP

MAX

+ 0.1

REF

UNITS

+

l

Absolute ꢁnput Range (ꢁI )

V

ꢁI

–

V

–

Absolute ꢁnput Range (ꢁI )

(Iote 5)

0.1

ꢁI

V + – V – ꢁnput Differential Voltage Range

V

ꢁI

= V + – V –

V

REF

V

ꢁI

ꢁ

Analog ꢁnput Leakage Current

Analog ꢁnput Capacitance

1

μA

ꢁI

C

Sample Mode

Hold Mode

45

5

pF

CMRR

ꢁnput Common Mode Rejection Ratio

f

ꢁI

= 800kHz

80

dꢀ

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5 PARAMETER

CONDITIONS

MIN

18

TYP

MAX

UNITS

ꢀits

l

Resolution

Io Missing Codes

18

ꢀits

Transition Ioise

1.3

0.5

0.1

0

LSꢀ

RMS

l

ꢁIL

ꢁntegral Linearity Error

Differential Linearity Error

Zero-Scale Error

(Iote 6)

(Iote 7)

–2.5

–0.5

–11

2.5

0.5

11

LSꢀ

DIL

ZSE

LSꢀ

Zero-Scale Error Drift

Full-Scale Error

0.04

5

LSꢀ/°C

LSꢀ

l

FSE

–50

50

Full-Scale Error Drift

0.15

ppm/°C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 2ꢀ°C and A_IN= –1dꢁFS. ꢂNotes 4, 8x

SYMꢁO5 PARAMETER

CONDITIONS

MIN

92.2

91.7

TYP

96.5

MAX

UNITS

dꢀ

l

SꢁIAD

SIR

Signal-to-(Ioise + Distortion) Ratio

f

ꢁI

f

ꢁI

= 2kHz, V = 5V

REF

= 2kHz, V = 5V, (H-Grade)

dꢀ

REF

l

Signal-to-Ioise Ratio

f

ꢁI

f

ꢁI

= 2kHz, V = 5V

92.6

87

96.5

90.7

dꢀ

REF

= 2kHz, V = 2.5V

REF

l

f

ꢁI

f

ꢁI

= 2kHz, V = 5V, (H-Grade)

92

86.4

96.5

90.7

dꢀ

REF

= 2kHz, V = 2.5V, (H-Grade)

REF

l

THD

Total Harmonic Distortion

f

ꢁI

f

ꢁI

= 2kHz, V = 5V

–120

–107

–103

dꢀ

REF

= 2kHz, V = 2.5V

REF

l

SFDR

Spurious Free Dynamic Range

–3dꢀ ꢁnput ꢀandwidth

Aperture Delay

f

ꢁI

= 2kHz, V = 5V

103

122

34

dꢀ

MHz

ps

REF

500

4

Aperture Jitter

ps

Transient Response

Full-Scale Step

200

ns

236918fa

3

LTC2369-18

REFERENCE INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5

PARAMETER

CONDITIONS

(Iote 5)

MIN

TYP

MAX

5.1

UNITS

V

l

V

Reference Voltage

Reference ꢁnput Current

2.5

REF

ꢁ

(Iote 9)

0.85

1.1

mA

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5 PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level ꢁnput Voltage

Low Level ꢁnput Voltage

Digital ꢁnput Current

0.8 • OV

ꢁH

ꢁL

DD

0.2 • OV

10

V

DD

ꢁ

V

ꢁI

= 0V to OV

DD

–10

μA

pF

ꢁI

C

V

Digital ꢁnput Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

ꢁI

l

ꢁ = –500μA

O

OV – 0.2

DD

V

OH

OL

ꢁ = 500μA

O

0.2

10

V

ꢁ

V

OUT

V

OUT

V

OUT

= 0V to OV

DD

–10

μA

mA

OZ

= 0V

= OV

–10

10

SOURCE

SꢁIK

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.375

1.71

TYP

MAX

2.625

5.25

8.6

UNITS

l

V

DD

2.5

V

OV

DD

ꢁ

Supply Current

Power Down Mode

1.6Msps Sample Rate

7.2

0.7

0.9

mA

μA

VDD

OVDD

PD

1.6Msps Sample Rate (C = 20pF)

L

+ ꢁ

l

Conversion Done (ꢁ

+ ꢁ , V > 2V)

REF REF

90

140

VDD

OVDD

REF REF

+ ꢁ , V > 2V, H-Grade)

μA

PD

P

Power Dissipation

Power Down Mode

1.6Msps Sample Rate

18

2.25

21.5

225

315

mW

μW

D

Conversion Done (ꢁ

+ ꢁ

OVDD

+ ꢁ

OVDD

+ ꢁ , V > 2V)

REF REF

VDD

REF REF

+ ꢁ , V > 2V, H-Grade)

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5

PARAMETER

CONDITIONS

MIN

TYP

MAX

1.6

UNITS

Msps

ns

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

COIV

ACQ

360

200

625

20

412

Acquisition Time

t

= t

– t

– t (Iote 10)

ꢀUSYLH

ns

ACQ

CYC

COIV

Time ꢀetween Conversions

CIV High Time

ns

CYC

ns

CIVH

ꢀUSYLH

CIVL

QUꢁET

SCK

C = 20pF

L

13

ns

CIV↑ to ꢀUSY Delay

Minimum Low Time for CIV

SCK Quiet Time from CIV↑

SCK Period

(Iote 11)

(Iote 10)

20

10

4

ns

(Iotes 11, 12)

ns

SCK High Time

ns

SCKH

236918fa

4

LTC2369-18

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2ꢀ°C. ꢂNote 4x

SYMꢁO5

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SCK Low Time

SCKL

(Iote 11)

4

ns

SDꢁ Setup Time From SCK↑

SDꢁ Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from ꢀUSY↓

ꢀus Enable Time After RDL↓

ꢀus Relinquish Time After RDL↑

SSDꢁSCK

HSDꢁSCK

SCKCH

DSDO

1

ns

t

= t

+ t (Iote 11)

DSDO

13.5

ns

SCKCH

SSDꢁSCK

C = 20pF (Iote 11)

L

9.5

ns

C = 20pF (Iote 10)

L

1

ns

HSDO

C = 20pF (Iote 10)

L

5

ns

DSDOꢀUSYL

EI

(Iote 11)

16

13

ns

DꢁS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may effect device

reliability and lifetime.

Note 7: Zero-scale error is the offset voltage measured from 0.5LSꢀ

when the output code flickers between 00 0000 0000 0000 0000 and

00 0000 0000 0000 0001. Full-scale error is the deviation of the last code

transition from ideal and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above REFor

Note 8: All specifications in dꢀ are referred to a full-scale 5V input with a

5V reference voltage.

OV , they will be clamped by internal diodes. This product can handle

DD

Note 9: f

= 1.6MHz, ꢁ varies proportionately with sample rate.

SMPL REF

input currents up to 100mA below ground or above REFor OV without

latch-up.

DD

Note 10: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

DD

Note 4: V = 2.5V, OV = 2.5V, REF = 5V, f = 1.6MHz.

SMPL

DD

and OV = 5.25V.

DD

Note ꢀ: Recommended operating conditions.

Note 12: t

of 10ns maximum allows a shift clock frequency up to

SCK

Note 6: ꢁntegral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

100MHz for rising capture.

0.8*OV

DD

t

WꢁDTH

0.2*OV

DD

50%

t

DELAY

236918 F01

0.8*OV

0.2*OV

DD

0.2*OV

Figure 1. Voltage 5evels for Timing Specifications

236918fa

5

LTC2369-18

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 2ꢀ°C, V}_DD= 2.ꢀV, OV_DD= 2.ꢀV, REF = ꢀV,

f_SMP5= 1.6Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

2.0

Differential Nonlinearity

vs Output Code

DC Histogram

0.5

0.4

40000

35000

30000

25000

20000

15000

10000

5000

X = 1.3

1.5

1.0

0.3

0.2

0.5

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

65536

131072

196608

262144

131067 131069 131071 131073 131075 131077

CODE

0

65536

131072

196608

262144

OUTPUT CODE

236918 G02

236918 G01

236918 G03

THD, Harmonics

32k Point FFT f_S= 1.6Msps,

f_IN= 2kHz

vs Input Frequency

SNR, SINAD vs Input Frequency

0

–20

–60

–70

100

95

90

85

80

75

70

SIR = 96.5dꢀ

THD = –127dꢀ

SꢁIAD = 96.5dꢀ

SFDR = 134dꢀ

–80

–40

SIR

THD

3RD

–90

–60

2ID

–100

–110

–120

–130

–140

–150

–160

SꢁIAD

–80

–100

–120

–140

–160

–180

0

100 200 300 400 500 600 700 800

125 150

175 200

0

25 50 75 100

0

175

200

25 50 75 100 125 150

FREQUEICY (kHz)

236918 G04

236918 G05

236918 G06

SNR, SINAD vs Input level,

f_IN= 2kHz

SNR, SINAD vs Reference

Voltage, f_IN= 2kHz

THD, Harmonics vs Reference

Voltage, f_IN= 2kHz

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

97

96

98.0

97.5

SIR

95

94

93

92

91

90

SꢁIAD

97.0

96.5

THD

2ID

SIR

SꢁIAD

3RD

96.0

95.5

95.0

3

3.5

4

5

2.5

4.5

2.5

3

4

4.5

5

3.5

–40

–30

–20

–10

0

REFEREICE VOLTAGE (V)

ꢁIPUT LEVEL (dꢀ)

236918 G08

236918 G09

236918 G07

236918fa

6

LTC2369-18

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 2ꢀ°C, V}_DD= 2.ꢀV, OV_DD= 2.ꢀV, REF = ꢀV,

f_SMP5= 1.6Msps, unless otherwise noted.

SNR, SINAD vs Temperature,

f_IN= 2kHz

THD, Harmonics vs Temperature,

f_IN= 2kHz

IN5/DN5 vs Temperature

1.0

0.5

0

98.0

97.5

97.0

96.5

96.0

95.5

95.0

94.5

94.0

–110

–115

MAX ꢁIL

MAX DIL

–120

SIR

THD

SꢁIAD

–125

–130

–135

–140

MꢁI DIL

MꢁI ꢁIL

2ID

3RD

–0.5

–1.0

–145

–55 –35 –15

5

25 45 65 85 105 125

25 45

TEMPERATURE (°C)

–55

5

45 65 85 105 125

–55 –35 –15

5

65 85 105 125

–35 –15

25

TEMPERATURE (°C)

236918 G12

236918 G11

236918 G10

Full-Scale Error vs Temperature

Offset Error vs Temperature

Supply Current vs Temperature

10

8

7

6

5

4

3

2

1

0

20

15

ꢁ

VDD

6

10

4

5

2

0

–2

–4

–6

–8

–10

–5

–10

–15

–20

ꢁ

REF

ꢁ

OVDD

25 45

TEMPERATURE (°C)

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

236918 G14

236918 G15

236918 G13

Reference Current

vs Reference Voltage

Shutdown Current vs Temperature

CMRR vs Input Frequency

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

ꢁ

+ ꢁ

VDD OVDD REF

0

100 200 300 400 500 600 700 800

–55 –35 –15

5

25 45 65 85 105 125

2.5

4.5

5

3

3.5

4

FREQUEICY (kHz)

TEMPERATURE (°C)

REFEREICE VOLTAGE (V)

236918 G16

236918 G17

236918 G18

236918fa

7

LTC2369-18

PIN FUNCTIONS

CHAIN ꢂPin 1x: Chain Mode Selector Pin. When low, the

LTC2369-18 operates in normal mode and the RDL/SDꢁ

input pin functions to enable or disable SDO. When high,

the LTC2369-18 operates in chain mode and the RDL/SDꢁ

pin functions as SDꢁ, the daisy-chain serial data input.

ꢁUSY ꢂPin 11x: ꢀUSY ꢁndicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished. Logic levels are determined by OV .

DD

RD5/SDI ꢂPin 12x: When CHAꢁI is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAꢁI is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

Logic levels are determined by OV .

DD

V

ꢂPin 2x: 2.5V Power Supply. The range of V is

DD

2.375Vto2.625V. ꢀypassV toGIDwitha10μFceramic

DD

capacitor.

determined by OV .

DD

GND ꢂPins 3, 6, 10 and 16x: Ground.

SCKꢂPin13x:SerialDataClockꢁnput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSꢀ

+

–

IN ꢂPin 4x: Analog ꢁnput. ꢁI operates differential with

–

+

respect to ꢁI with an ꢁI -ꢁI range of 0V to V

.

REF

first. Logic levels are determined by OV .

DD

–

IN ꢂPin ꢀx: Analog Ground Sense. ꢁI has an input range

of 100mV with respect to GID and must be tied to the

ground plane or a remote ground sense.

SDO ꢂPin 14x: Serial Data Output. The conversion result

or daisy-chain data is output on this pin on each rising

edgeofSCKMSꢀfirst. Theoutputdataisinstraightbinary

REFꢂPins7,8x:Referenceꢁnputs.TherangeofREFis2.5V

to 5.1V. This pin is referred to the GID pin and should be

decoupledcloselytothepinwitha47μFceramiccapacitor

(X5R, 0805 size).

format. Logic levels are determined by OV .

DD

OV ꢂPin 1ꢀx: ꢁ/O ꢁnterface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.8V, 2.5V, 3.3V,

CNV ꢂPin 9x: Convert ꢁnput. A rising edge on this input

or 5V). ꢀypass OV to GID with a 0.1μF capacitor.

DD

powers up the part and initiates a new conversion. Logic

GND ꢂEꢃposed Pad Pin 17, DFN Package Onlyx: Ground.

Exposedpadmustbesoldereddirectlytothegroundplane.

levels are determined by OV .

DD

236918fa

8

LTC2369-18

FUNCTIONAL BLOCK DIAGRAM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 5V

CHAꢁI

SDO

RDL/SDꢁ

SCK

+

ꢁI

+

SPꢁ

PORT

18-ꢀꢁT SAMPLꢁIG ADC

–

ꢁI

–

CIV

COITROL LOGꢁC

ꢀUSY

GID

236918 ꢀD

TIMING DIAGRAM

Conversion Timing Using the Serial Interface

CHAꢁI, RDL/SDꢁ = 0

CIV

COIVERT

POWER-DOWI AID ACQUꢁRE

ꢀUSY

SCK

SDO

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

236918 TD01

236918fa

9

LTC2369-18

APPLICATIONS INFORMATION

OVERVIEW

1LSB = FS/262144

111...111

111...110

111...101

111...100

TheLTC2369-18isalownoise,lowpower,highspeed18-bit

successive approximation register (SAR) ADC. Operating

from a single 2.5V supply, the LTC2369-18 supports a

0V to V

REF

pseudo-differential unipolar input range with

REF

V

ranging from 2.5V to 5.1V, making it ideal for high

UNIPOLAR

ZERO

performance applications which require a wide dynamic

range. The LTC2369-18 achieves 2.5LSꢀ ꢁIL max, no

missing codes at 18 bits and 96.5dꢀ SIR.

000...011

000...010

000...001

000...000

0V

1

FS – 1LSB

Fast 1.6Msps throughput with no cycle latency makes

the LTC2369-18 ideally suited for a wide variety of high

speed applications. An internal oscillator sets the con-

version time, easing external timing considerations. The

LTC2369-18 dissipates only 18mW at 1.6Msps, while an

auto power-down feature is provided to further reduce

power dissipation during inactive periods.

LSB

INPUT VOLTAGE (V)

236918 F02

Figure 2. 5TC2369-18 Transfer Function

ANA5OG INPUT

TheanaloginputsoftheLTC2369-18arepseudo-differential

in order to reduce any unwanted signal that is common

to both inputs. The analog inputs can be modeled by the

equivalentcircuitshowninFigure3.Thediodesattheinput

provide ESD protection. ꢁn the acquisition phase, each

CONVERTER OPERATION

The LTC2369-18 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

input sees approximately 45pF (C ) from the sampling

ꢁI

CDAC in series with 40Ω (R ) from the on-resistance

OI

+

–

+

converter (CDAC) is connected to the ꢁI and ꢁI pins to

sample the pseudo-differential analog input voltage. A ris-

ing edge on the CIV pin initiates a conversion. During the

conversionphase,the18-bitCDACissequencedthrougha

successiveapproximationalgorithm,effectivelycomparing

the sampled input with binary-weighted fractions of the

of the sampling switch. The ꢁI input draws a current

spike while charging the C capacitor during acquisition.

ꢁI

During conversion, the analog inputs draw only a small

leakage current.

REF

C

ꢁI

R

40Ω

OI

45pF

reference voltage (e.g. V /2, V /4 … V /262144)

REF

+

ꢁI

using the differential comparator. At the end of conver-

sion, the CDAC output approximates the sampled analog

input. The ADC control logic then prepares the 18-bit

digital output code for serial transfer.

ꢀꢁAS

VOLTAGE

REF

C

ꢁI

R

40Ω

OI

45pF

–

236918 F03

TRANSFER FUNCTION

The LTC2369-18 digitizes the full-scale voltage of REF

18

into 2 levels, resulting in an LSꢀ size of 19μV with

Figure 3. The Equivalent Circuit for the

Differential Analog Input of the 5TC2369-18

REF = 5V. The ideal transfer function is shown in Figure 2.

The output data is in straight binary format.

236918fa

10

LTC2369-18

APPLICATIONS INFORMATION

INPUT DRIVE CIRCUITS

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.IPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

A low impedance source can directly drive the high im-

pedance input of the LTC2369-18 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC input

draws a current spike when entering acquisition.

Pseudo-Differential Unipolar Inputs

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2369-18. The ampli-

fier provides low output impedance, which produces fast

settling of the analog signal during the acquisition phase.

ꢁt also provides isolation between the signal source and

the current spike the ADC input draws.

For most applications, we recommend the low power

LT6202 ADC driver to drive the LTC2369-18. With a low

noise density of 1.9nV/√Hz and a low supply current of

3mA, the LT6202 is flexible and may be configured to

convertsignals of variousamplitudes to the 0Vto5V input

range of the LTC2369-18.

To achieve the full distortion performance of the

LTC2369-18, a low distortion single-ended signal source

driven through the LT6202 configured as a unity-gain buf-

fer as shown in Figure 4 can be used to get the full data

sheet THD specification of –120dꢀ.

Input Filtering

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Ioisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

The LT6202 can also be used to buffer and convert large

true bipolar signals which swing below ground to the 0V

to 5V input range of the LTC2369-18. Figure 5a shows the

LT6202 being used to convert a 10V true bipolar signal

for use by the LTC2369-18. ꢁn this case, the LT6202 is

configured as an inverting amplifier stage, which acts to

attenuateandlevelshifttheinputsignaltothe0Vto5Vinput

rangeoftheLTC2369-18.ꢁntheinvertingconfiguration,the

single-ended input signal source no longer directly drives

a high impedance input. The input impedance is instead

LPF1

50Ω

LPF2

V

REF

+

–

5.1Ω

10nF

0V

+

–

66nF

ꢀW = 48kHz

ꢁI

LT6202

LTC2369-18

236918 F04

ꢀW = 3.2MHz

Figure 4. Input Signal Chain

. R must be chosen carefully based on

set by resistor R

ꢁI ꢁI

the source impedance of the signal source. Higher values

Another filter network consisting of LPF2 should be used

between the buffer and ADC input to both minimize the

noisecontributionofthebufferandtohelpminimizedistur-

bances reflected into the buffer from sampling transients.

Long RC time constants at the analog inputs will slow

down the settling of the analog inputs. Therefore, LPF2

requires a wider bandwidth than LPF1. A buffer amplifier

with a low noise density must be selected to minimize

degradation of the SIR.

of R tend to degrade both the noise and distortion of

ꢁI

the LT6202 and LTC2369-18 as a system. Table 1 shows

the resulting SIR and THD for several values of R , R1,

ꢁI

R2, R3 and R4 in this configuration. Figure 5b shows the

resultingFFTwhenusingtheLT6202asshowninFigure5a.

236918fa

11

LTC2369-18

APPLICATIONS INFORMATION

V

= V /2

REF

200pF

ADC REFERENCE

CM

The LTC2369-18 requires an external reference to define

its input range. A low noise, low temperature drift refer-

ence is critical to achieving the full datasheet performance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

many applications. With its small size, low power and

highaccuracy, theLTC6655-5isparticularlywellsuitedfor

use with the LTC2369-18. The LTC6655-5 offers 0.025%

(max) initial accuracy and 2ppm/°C (max) temperature

coefficient for high precision applications. The LTC6655-5

is fully specified over the H-grade temperature range and

complements the extended temperature operation of the

LTC2369-18 up to 125°C. We recommend bypassing the

LTC6655-5witha47μFceramiccapacitor(X5R,0805size)

close to the REF pin.

R2

R4

499Ω

402Ω

3

4

+

–

5V

0V

R3

2k

10μF

LT6202

R1

1

R

ꢁI

2k

10V

0V

–10V

499Ω

200pF

236918 F05a

Figure ꢀa. 5T6202 Converting a 10V ꢁipolar Signal

to a 0V to ꢀV Input Signal

0

SIR = 96.1dꢀ

–20

–40

THD = –97.3dꢀ

SꢁIAD = 92.7dꢀ

SFDR = 97.5dꢀ

–60

–80

TheREFpinoftheLTC2369-18drawscharge(Q

)from

COIV

the 47μF bypass capacitor during each conversion cycle.

The reference replenishes this charge with a DC current,

–100

–120

–140

–160

ꢁ

= Q

/t . The DC current draw of the REF pin,

REF

COIV CYC

, depends on the sampling rate and output code. ꢁf

400 500

the LTC2369-18 is used to continuously sample a signal

at a constant rate, the LTC6655-5 will keep the deviation

of the reference voltage over the entire code span to less

than 0.5LSꢀs.

1

100 200 300

600 700 800

FREQUEICY (kHz)

236918 F05b

Figure ꢀb. 32k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure ꢀa

When idling, the REF pin on the LTC2369-18 draws only

a small leakage current (< 1μA). ꢁn applications where a

burst of samples is taken after idling for long periods as

Table 1. SNR, THD vs R_INfor 10V Input Signal

R

R1

ꢂΩx

R2

ꢂΩx

R3

ꢂΩx

R4

ꢂΩx

SNR

ꢂdꢁx

THD

ꢂdꢁx

IN

shown in Figure 6, ꢁ quickly goes from approximately

REF

ꢂΩx

0μA to a maximum of 1.1mA at 1.6Msps. This step in DC

current draw triggers a transient response in the reference

that must be considered since any deviation in the refer-

ence output voltage will affect the accuracy of the output

2k

499

2k

402

2k

96.1

96

–97.3

–92

10k

100k

2.49k

24.9k

2.49k

24.9k

10k

100k

20k

93.8

–93.5

CIV

236918 F06

ꢁDLE

PERꢁOD

ꢁDLE

PERꢁOD

Figure 6. CNV Waveform Showing ꢁurst Sampling

236918fa

12

LTC2369-18

APPLICATIONS INFORMATION

code. ꢁn applications where the transient response of the

reference is important, the fast settling LTC6655-5 refer-

ence is also recommended.

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 8 shows

that the LTC2369-18 achieves a typical SIR of 96.5dꢀ at

a 1.6MHz sampling rate with a 2kHz input.

ꢁn applications where power management is critical and

the external reference may be powered down, it is rec-

ommended that REF is kept greater than 2V in order to

guaranteeamaximumshutdowncurrentof140μA.ꢁnsuch

applications, a Schottky diode can be placed between REF

0

SIR = 96.5dꢀ

–20

–40

THD = –127dꢀ

SꢁIAD = 96.5dꢀ

SFDR = 134dꢀ

–60

and V , as shown in Figure 7.

DD

–80

–100

–120

–140

–160

–180

REF

V

DD

LTC2369-18

0

100 200 300 400 500 600 700 800

FREQUEICY (kHz)

236918 F07

236918 F08

Figure 7. A Schottky Diode ꢁetween REF and V_DDMaintains

REF > 2V for Applications Where the Reference May ꢁe

Powered Down

Figure 8. 32k Point FFT with f_IN= 2kHz of the 5TC2369-18

Total Harmonic Distortion ꢂTHDx

DYNAMIC PERFORMANCE

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2369-18 provides

guaranteed tested limits for both AC distortion and noise

measurements.

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

V2²+ V3²+ V4²+…+ V_I²

THD=20log

V1

where V1 is the RMS amplitude of the fundamental fre-

quencyandV2throughV aretheamplitudesofthesecond

I

Signal-to-Noise and Distortion Ratio ꢂSINADx

through Ith harmonics.

The signal-to-noise and distortion ratio (SꢁIAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 8 shows that the LTC2369-18 achieves

a typical SꢁIAD of 96.5dꢀ at a 1.6MHz sampling rate with

a 2kHz input.

POWER CONSIDERATIONS

The LTC2369-18 provides two power supply pins: the

2.5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2369-18 to communicate with any digital

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems.

Signal-to-Noise Ratio ꢂSNRx

The signal-to-noise ratio (SIR) is the ratio between the

RMS amplitude of the fundamental input frequency and

236918fa

13

LTC2369-18

APPLICATIONS INFORMATION

Power Supply Sequencing

power down, disable SDO and turn off SCK. The auto

power-down feature will reduce the power dissipation of

the LTC2369-18 as the sampling frequency is reduced.

Since power is consumed only during a conversion, the

LTC2369-18remainspowereddownforalargerfractionof

The LTC2369-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2369-18

has a power-on-reset (POR) circuit that will reset the

LTC2369-18 at initial power-up or whenever the power

supply voltage drops below 1V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. Io conversions should be initiated

until 20μs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 9.

DIGITA5 INTERFACE

The LTC2369-18 has a serial digital interface. The flexible

OV supply allows the LTC2369-18 to communicate with

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

TIMING AND CONTRO5

CNV Timing

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

100MHz,a1.6Mspsthroughputisstillachieved.Theserial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D17 remains valid till the first rising edge of SCK.

The LTC2369-18 conversion is controlled by CIV. A ris-

ing edge on CIV will start a conversion and power up the

LTC2369-18.Onceaconversionhasbeeninitiated,itcannot

berestarteduntiltheconversioniscomplete.Foroptimum

performance, CIV should be driven by a clean low jitter

signal. Converter status is indicated by the ꢀUSY output

which remains high while the conversion is in progress.

To ensure that no errors occur in the digitized results, any

additional transitions on CIV should occur within 40ns

from the start of the conversion or after the conversion

has been completed. Once the conversion has completed,

the LTC2369-18 powers down and begins acquiring the

input signal.

The serial interface on the LTC2369-18 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operation of the LTC2369-18. Several modes are provided

depending on whether a single or multiple ADCs share the

SPꢁ bus or are daisy chained.

8

7

6

5

Internal Conversion Clock

ꢁ

VDD

The LTC2369-18 has an internal clock that is trimmed to

achieveamaximumconversiontimeof412ns.Withamin-

imum acquisition time of 200ns, throughput performance

of1.6Mspsisguaranteedwithoutanyexternaladjustments.

4

3

2

1

0

ꢁ

OVDD

ꢁ

REF

Auto Power-Down

800 1000

1200 1400 1600

0

200 400 600

SAMPLꢁIG RATE (kHz)

The LTC2369-18 automatically powers down after a

conversion has been completed and powers up once a

new conversion is initiated on the rising edge of CIV.

During power down, data from the last conversion can

be clocked out. To minimize power dissipation during

236918 F09

Figure 9. Power Supply Current of the 5TC2369-18

Versus Sampling Rate

236918fa

14

LTC2369-18

TIMING DIAGRAMS

Normal Mode, Single Device

Figure 10 shows a single LTC2369-18 operated in normal

mode with CHAꢁI and RDL/SDꢁ tied to ground. With

RDL/SDꢁ grounded, SDO is enabled and the MSꢀ(D17) of

the new conversion data is available at the falling edge of

ꢀUSY. ThisisthesimplestwaytooperatetheLTC2369-18.

When CHAꢁI = 0, the LTC2369-18 operates in normal

mode. ꢁn normal mode, RDL/SDꢁ enables or disables the

serial data output pin SDO. ꢁf RDL/SDꢁ is high, SDO is in

high impedance. ꢁf RDL/SDꢁ is low, SDO is driven.

COIVERT

DꢁGꢁTAL HOST

ꢁRQ

CIV

CHAꢁI

ꢀUSY

LTC2369-18

RDL/SDꢁ

SDO

DATA ꢁI

CLK

SCK

POWER-DOWI

AID ACQUꢁRE

COIVERT

POWER-DOWI AID ACQUꢁRE

COIVERT

CHAꢁI = 0

RDL/SDꢁ = 0

t

CYC

t

CIVH

t

CIVL

CIV

t

= t

– t

ACQ CYC COIV ꢀUSYLH

t

COIV

ACQ

ꢀUSY

t

SCK

t

ꢀUSYLH

t

QUꢁET

SCKH

1

2

3

16

17

18

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOꢀUSYL

D17

D16

D15

D1

D0

236918 F10

Figure 10. Using a Single 5TC2369-18 in Normal Mode

236918fa

15

LTC2369-18

TIMING DIAGRAMS

Normal Mode, Multiple Devices

be used to allow only one LTC2369-18 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure11,

the RDL/SDꢁ inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDꢁ is brought low, the MSꢀ of the selected

device is output onto SDO.

Figure 11 shows multiple LTC2369-18 devices operating

in normal mode (CHAꢁI = 0) sharing CIV, SCK and SDO.

ꢀy sharing CIV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDꢁ input of each ADC must

RDL

ꢀ

A

COIVERT

CIV

CHAꢁI

ꢀUSY

SDO

ꢁRQ

CHAꢁI

LTC2369-18

ꢀ

LTC2369-18

A

DꢁGꢁTAL HOST

SDO

RDL/SDꢁ

SCK

DATA ꢁI

CLK

POWER-DOWI

AID ACQUꢁRE

COIVERT

POWER-DOWI AID ACQUꢁRE

CHAꢁI = 0

t

CIVL

CIV

t

COIV

ꢀUSY

t

ꢀUSYLH

RDL/SDꢁ

A

ꢀ

RDL/SDꢁ

t

SCK

t

QUꢁET

SCKH

19

SCK

SDO

1

2

3

16

17

18

20

21

34

35

36

t

HSDO

SCKL

D17

t

DSDO

DꢁS

D0

t

EI

Hi-Z

D17

D16

D15

D1

A

D16

D15

D1

ꢀ

D0

ꢀ

A

ꢀ

236918 F11

Figure 11. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO

236918fa

16

LTC2369-18

TIMING DIAGRAMS

Chain Mode, Multiple Devices

number of converters. Figure 12 shows an example with

two daisy-chained devices. The MSꢀ of converter A will

appear at SDO of converter ꢀ after 18 SCK cycles. The

MSꢀ of converter A is clocked in at the SDꢁ/RDL pin of

converter ꢀ on the rising edge of the first SCK.

When CHAꢁI = OV , the LTC2369-18 operates in

DD

chain mode. ꢁn chain mode, SDO is always enabled and

RDL/SDꢁ serves as the serial data input pin (SDꢁ) where

daisy-chain data output from another ADC can be input.

This is useful for applications where hardware constraints

maylimitthenumberoflinesneededtointerfacetoalarge

COIVERT

OV

DD

OV

DD

CIV

DꢁGꢁTAL HOST

CHAꢁI

LTC2369-18

RDL/SDꢁ

SDO

RDL/SDꢁ

ꢀUSY

SDO

ꢁRQ

A

ꢀ

DATA ꢁI

SCK

CLK

POWER-DOWI

AID ACQUꢁRE

COIVERT

POWER-DOWI AID ACQUꢁRE

COIVERT

CHAꢁI = OV

DD

RDL/SDꢁ = 0

A

t

CYC

t

CIVL

CIV

ꢀUSY

t

COIV

t

ꢀUSYLH

t

SCKCH

t

SCKH

QUꢁET

SCK

1

2

3

16

17

18

19

20

34

35

36

t

SCKL

t

SSDꢁSCK

HSDO

t

DSDO

HSDꢁSCK

SDO = RDL/SDꢁ

A

ꢀ

D17

D16

D15

D1

D0

A

ꢀ

A

ꢀ

t

DSDOꢀUSYL

D15

D1

ꢀ

D0

D17

D16

D1

D0

A

SDO

ꢀ

A

ꢀ

236918 F12

Figure 12. Chain Mode Timing Diagram

236918fa

17

LTC2369-18

BOARD LAYOUT

To obtain the best performance from the LTC2369-18

a printed circuit board is recommended. Layout for the

printed circuit board (PCꢀ) should ensure the digital and

analog signal lines are separated as much as possible. ꢁn

particular,careshouldbetakennottorunanydigitalclocks

orsignalsalongsideanalogsignalsorunderneaththeADC.

Recommended 5ayout

ThefollowingisanexampleofarecommendedPCꢀlayout.

A single solid ground plane is used. ꢀypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1813A, the

evaluation kit for the LTC2369-18.

Partial Top Silkscreen

236918fa

18

LTC2369-18

BOARD LAYOUT

Partial 5ayer 1 Component Side

Partial 5ayer 2 Ground Plane

236918fa

19

LTC2369-18

BOARD LAYOUT

Partial 5ayer 3 PWR Plane

Partial 5ayer 4 ꢁottom 5ayer

236918fa

20

LTC2369-18

BOARD LAYOUT

Partial Schematic of Demoboard

R E F

8

R E F

1

G I D

7

1 5

2

D D

G I D 1 6

O V

G I D

1 0

V

G I D

6

3

2

1

3

2

1

236918fa

21

LTC2369-18

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DE Package

16-5ead Plastic DFN ꢂ4mm × 3mmx

(Reference LTC DWG # 05-08-1732 Rev Ø)

R = 0.115

TYP

0.40 0.10

4.00 0.10

(2 SꢁDES)

9

16

R = 0.05

0.70 0.05

TYP

3.30 0.05

1.70 0.05

3.30 0.10

3.60 0.05

2.20 0.05

3.00 0.10

(2 SꢁDES)

1.70 0.10

PꢁI 1 IOTCH

R = 0.20 OR

PꢁI 1

TOP MARK

(SEE IOTE 6)

0.35 × 45°

PACKAGE

OUTLꢁIE

CHAMFER

(DE16) DFI 0806 REV Ø

8

1

0.23 0.05

0.45 ꢀSC

0.75 0.05

0.200 REF

0.25 0.05

0.45 ꢀSC

3.15 REF

0.00 – 0.05

ꢀOTTOM VꢁEW—EXPOSED PAD

RECOMMEIDED SOLDER PAD PꢁTCH AID DꢁMEISꢁOIS

APPLY SOLDER MASK TO AREAS THAT ARE IOT SOLDERED

IOTE:

1. DRAWꢁIG PROPOSED TO ꢀE MADE VARꢁATꢁOI OF VERSꢁOI (WGED-3) ꢁI JEDEC

PACKAGE OUTLꢁIE MO-229

2. DRAWꢁIG IOT TO SCALE

3. ALL DꢁMEISꢁOIS ARE ꢁI MꢁLLꢁMETERS

4. DꢁMEISꢁOIS OF EXPOSED PAD OI ꢀOTTOM OF PACKAGE DO IOT ꢁICLUDE

MOLD FLASH. MOLD FLASH, ꢁF PRESEIT, SHALL IOT EXCEED 0.15mm OI AIY SꢁDE

5. EXPOSED PAD SHALL ꢀE SOLDER PLATED

6. SHADED AREA ꢁS OILY A REFEREICE FOR PꢁI 1 LOCATꢁOI OI THE

TOP AID ꢀOTTOM OF PACKAGE

MS Package

16-5ead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev Ø)

0.889 0.127

(.035 .005)

5.23

(.206)

MꢁI

3.20 – 3.45

(.126 – .136)

4.039 0.102

(.159 .004)

(IOTE 3)

0.50

0.305 0.038

(.0120 .0015)

TYP

(.0197)

0.280 0.076

(.011 .003)

REF

ꢀSC

16151413121110

9

RECOMMEIDED SOLDER PAD LAYOUT

3.00 0.102

(.118 .004)

(IOTE 4)

DETAꢁL “A”

0° – 6° TYP

4.90 0.152

(.193 .006)

0.254

(.010)

GAUGE PLAIE

0.53 0.152

(.021 .006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAꢁL “A”

0.18

(.007)

SEATꢁIG

PLAIE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 0.0508

(.004 .002)

0.50

(.0197)

ꢀSC

MSOP (MS16) 1107 REV Ø

IOTE:

1. DꢁMEISꢁOIS ꢁI MꢁLLꢁMETER/(ꢁICH)

2. DRAWꢁIG IOT TO SCALE

4. DꢁMEISꢁOI DOES IOT ꢁICLUDE ꢁITERLEAD FLASH OR PROTRUSꢁOIS.

ꢁITERLEAD FLASH OR PROTRUSꢁOIS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE

5. LEAD COPLAIARꢁTY (ꢀOTTOM OF LEADS AFTER FORMꢁIG) SHALL ꢀE 0.102mm (.004") MAX

3. DꢁMEISꢁOI DOES IOT ꢁICLUDE MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS.

MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE

236918fa

22

LTC2369-18

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMꢁER

A

03/12 Updated conditions for ꢁ and P in Power Requirements section

4

PD

D

Added Figure 7 and associated text

13

236918fa

ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2369-18

TYPICAL APPLICATION

5T6202 Converting a 10V ꢁipolar Signal to a 0V to ꢀV Input Signal Into the 5TC2369-18

LTC6655-5

V

8V

ꢁI

OUT_F

OUT_S

5V

200pF

47μF

R2

3k

5

R4

402Ω

LT6202

+

2.5V

V

5V

0V

3

4

+

REF

V

5.1Ω

DD

R3

2k

+

–

10μF

1

ꢁI

LTC2369-18

10nF

–

V

2

236918 TA02

R

ꢁI

2k

R1

–3V

10V

499Ω

0V

–10V

220pF

RELATED PARTS

PART NUMꢁER

DESCRIPTION

COMMENTS

ADCs

LTC2379-18/LTC2378-18 18-ꢀit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential ꢁnput, 101.2dꢀ SIR, 5V ꢁnput Range, DGC,

LTC2377-18/LTC2376-18 Power ADC Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC2380-16/LTC2378-16 16-ꢀit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential ꢁnput, 96.2dꢀ SIR, 5V ꢁnput Range, DGC,

LTC2377-16/LTC2376-16 Power ADC

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC2383-16/LTC2382-16/ 16-ꢀit, 1Msps/500ksps/250ksps Serial, Low Power

2.5V Supply, Differential ꢁnput, 92dꢀ SIR, 2.5V ꢁnput Range, Pin-

Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC2381-16

ADC

LTC2393-16/LTC2392-16/ 16-ꢀit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, Pin-

LTC2391-16

Compatible Family in 7mm × 7mm LQFP-48 and QFI-48 Packages

3.3V Supply, 1-Channel, Unipolar/ꢀipolar, 18mW, MSOP-10 Package

2.35V to 3.6V Supply 6- and 8-Lead TSOT-23 Packages

LTC2355-14/LTC2356-14 14-ꢀit, 3.5Msps Serial ADC

LTC2366

DACS

12-ꢀit, 3Msps Serial ADC

LTC2757

18-ꢀit, Single Parallel ꢁ

SoftSpan™ DAC

1LSꢀ ꢁIL/DIL, Software-Selectable Ranges, 7mm × 7mm

LQFP-48 Package

OUT

LTC2641

16-ꢀit/14-ꢀit/12-ꢀit Single Serial V

DACs

1LSꢀ ꢁIL/DIL, MSOP-8 Package, 0V to 5V Output

OUT

LTC2630

12-ꢀit/10-ꢀit/8-ꢀit Single V

DACs

SC70 6-Pin Package, ꢁnternal Reference, 1LSꢀ ꢁIL (12 ꢀits)

OUT

References

LTC6655

Precision Low Drift Low Ioise ꢀuffered Reference

5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Ioise, MSOP-8 Package

5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Ioise, MSOP-8 Package

LTC6652

Amplifiers

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail ꢁnput/Output Ioise 1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢀandwidth

Low Power Amplifiers

LT6200/LT6200-5/

LT6200-10

165MHz/800MHz/1.6GHz Op Amp with

Unity Gain/AV = 5/AV = 10

Low Ioise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dꢀ at

1MHz, TSOT23-6 Package

LTC1992

Low Power, Fully Differential ꢁnput/Output Amplifier/ 1mA Supply Current

Driver Family

LT6360

Low Ioise SAR ADC Driver with True Zero Output

Low Ioise ꢁntegrated Charge Pump

236918fa

LT 0312 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2377-18
厂家：	Linear
描述：	18-Bit, 1.6Msps, Pseudo-Differential Unipolar SAR 18位， 1.6Msps伪差分SAR单极
文件：	总24页 (文件大小：879K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2377-18 [Linear]

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