LTC2381CMS-16#PBF_技术文档

LTC2381-16

16-Bit, 250ksps, Low Power

SAR ADC with Serial Interface

FEATURES

DESCRIPTION

The LTC^®2381-16 is a low noise, low power, high speed

16-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2381-16 has a

2.5V fully differential input range. The LTC2381-16

consumes only 3.25mW and achieves 2LSB INL max,

no missing codes at 16-bits and 92dB SNR.

n

250ksps Throughput Rate

n

2LSB INL (Max)

n

Guaranteed 16-Bit No Missing Codes

n

Low Power: 3.25mW at 250ksps, 13µW at 1ksps

n

92dB SNR (Typ) at f = 20kHz

IN

n

Extended Acquisition Time of 3.25µs Allows Use of

Lower Power Drivers

The LTC2381-16 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 250ksps

throughput with no cycle latency makes the LTC2381-16

ideally suited for a wide variety of high speed applications.

Aninternaloscillatorsetstheconversiontime,easingexter-

nal timing considerations. The LTC2381-16 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

n

Guaranteed Operation to 125°C

n

2.5V Supply

n

Fully Differential Input Range 2.5V

n

External 2.5V Reference Input

n

No Pipeline Delay, No Cycle Latency

n

1.8V to 5V I/O Voltages

n

SPI-Compatible Serial I/O with Daisy-Chain Mode

n

Internal Conversion Clock

n

16-Pin MSOP and 4mm × 3mm DFN Packages

The LTC2381-16 features a proprietary sampling archi-

tecture that enables the ADC to begin acquiring the next

sample during the current conversion. The resulting

extended acquisition time of 3.25µs allows the use of

extremely low power ADC drivers.

APPLICATIONS

n

Medical Imaging

n

High Speed Data Acquisition

n

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

ATE

TYPICAL APPLICATION

32k Point FFT f_S= 250ksps, f_IN= 20kHz

0

2.5V 1.8V TO 5V

SNR = 91.8dB

–20

–40

THD = –106dB

SINAD = 91.6dB

SFDR = 107dB

10µF

0.1µF

ANALOG INPUT

0V TO 2.5V

–60

V

OV

DD

50Ω

100Ω

3300pF

100Ω

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

DD

+

–

IN

–80

LT6350

LTC2381-16

–100

–120

–140

–160

–180

IN

SAMPLE CLOCK

REF

GND

238116 TA01

2.5V

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

47µF

(X5R, 0805 SIZE)

0

25

50

75

100

125

FREQUENCY (kHz)

238116 TA02a

238116fa

1

For more information www.linear.com/LTC2381-16

LTC2381-16

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Digital Output Voltage

Supply Voltage (V )...............................................2.8V

DD

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

Supply Voltage (OV )................................................6V

DD

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC2381C ................................................ 0°C to 70°C

LTC2381I .............................................–40°C to 85°C

LTC2381H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Reference Input (REF)..............................................2.8V

Analog Input Voltage (Note 3)

+

–

IN , IN ......................... (GND –0.3V) to (REF + 0.3V)

Digital Input Voltage

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

PIN CONFIGURATION

TOP VIEW

CHAIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

OV

TOP VIEW

V

DD

CHAIN 1

16 GND

GND

SDO

V

2

15 OV

DD

+

GND 3

14 SDO

13 SCK

17

GND

IN

SCK

+

–

IN

4

5

–

IN

RDL/SDI

BUSY

GND

12 RDL/SDI

11 BUSY

10 GND

GND

REF

GND 6

REF 7

REF 8

9

CNV

MS PACKAGE

16-LEAD (4mm × 5mm) PLASTIC MSOP

DE PACKAGE

16-LEAD (4mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 110°C/W

JA

JMAX

T

JMAX

= 150°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC2381-16#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2381CMS-16#PBF

LTC2381IMS-16#PBF

LTC2381HMS-16#PBF

LTC2381CDE-16#PBF

LTC2381IDE-16#PBF

LTC2381CMS-16#TRPBF 238116

LTC2381IMS-16#TRPBF 238116

LTC2381HMS-16#TRPBF 238116

LTC2381CDE-16#TRPBF 23816

16-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

16-Lead Plastic MSOP

16-Lead (4mm × 3mm) Plastic DFN

LTC2381IDE-16#TRPBF

23816

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

238116fa

2

For more information www.linear.com/LTC2381-16

LTC2381-16

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

V +

PARAMETER

CONDITIONS

(Note 5)

MIN

–0.05

TYP

MAX

UNITS

+

l

Absolute Input Range (IN )

V

REF

V

REF

V

IN

–

V

IN

–

Absolute Input Range (IN )

(Note 5)

V + – V – Input Differential Voltage range

V

IN

= V + – V –

–V

+V

REF

IN

REF

V

CM

Common-Mode Input Range

V

/2–

V /2

REF

V

/2+

REF

0.05

1

l

I

Analog Input Leakage Current

Analog Input Capacitance

µA

IN

C

Sample Mode

Hold Mode

45

5

pF

IN

CMRR

Input Common Mode Rejection Ratio

70

dB

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

16

Bits

Transition Noise

0.6

0.9

0.5

0.25

3

LSB

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

Bipolar Zero-Scale Error

Bipolar Zero-Scale Error Drift

Bipolar Full-Scale Error

Bipolar Full-Scale Error Drift

(Note 6)

(Note 7)

–2

–1

–6

2

1

6

LSB

DNL

BZE

LSB

mLSB/°C

LSB

l

FSE

–14

3

14

0.1

ppm/°C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS. (Notes 4, 8)

SYMBOL PARAMETER

CONDITIONS

MIN

88.5

89

TYP

92

MAX

UNITS

dB

l

SINAD

SNR

Signal-to-(Noise + Distortion) Ratio

f

= 20kHz

IN

Signal-to-Noise Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

–3dB Input Bandwidth

Aperture Delay

= 20kHz

92

dB

THD

= 20kHz, First 5 Harmonics

= 20kHz

–106

107

30

–99

dB

SFDR

dB

MHz

ns

2

Aperture Jitter

30

ps

Transient Response

Full-Scale Step

250

ns

238116fa

3

For more information www.linear.com/LTC2381-16

LTC2381-16

REFERENCE INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

MAX

2.6

UNITS

V

l

V

Reference Voltage

Load Current

2.4

REF

I

(Note 9)

285

µA

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OV

IH

IL

DD

0.2 • OV

10

V

DD

I

V

= 0V to OV

DD

–10

µA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –500 µA

O

OV – 0.2

DD

V

OH

OL

I = 500 µA

O

0.2

10

V

I

V

= 0V to OV

DD

–10

µA

mA

OZ

OUT

= 0V

= OV

–10

10

SOURCE

SINK

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.375

1.71

TYP

MAX

2.625

5.25

UNITS

l

V

DD

2.5

V

OV

DD

l

I

DD

Supply Current

Power Down Mode

250ksps Sample Rate

Conversion Done

Conversion Done (H-Grade)

1.3

0.5

1.7

40

110

mA

µA

P

Power Dissipation

Power Down Mode

250ksps Sample Rate

Conversion Done

Conversion Done (H-Grade)

3.25

1.25

4.25

100

275

mW

µW

D

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

250

3

UNITS

ksps

µs

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

2

Acquisition Time

t

= t

– t (Note 10)

HOLD

3.25

µs

ACQ

CYC

Maximum Time Between Acquisitions

Time Between Conversions

CNV High Time

750

20

ns

HOLD

CYC

4

us

20

ns

CNVH

BUSYLH

CNVL

SCK

CNV ↑ to BUSY Delay

Minimum Low Time for CNV

SCK Period

C = 20pF (Note 11)

L

ns

(Note 11)

200

10

ns

(Notes 11, 12)

ns

238116fa

4

For more information www.linear.com/LTC2381-16

LTC2381-16

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SCK High Time

SCKH

SCK Low Time

4

ns

SCKL

SDI Setup Time From SCK ↑

SDI Hold Time From SCK ↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK ↑

SDO Data Remains Valid Delay from SCK ↑

SDO Data Valid Delay from BUSY ↓

Bus Enable Time After RDL ↓

Bus Relinquish Time After RDL ↑

SCK Setup Time from RDL/SDI ↓

SCK Hold Time from RDL/SDI ↓

(Note 11)

4

ns

SSDISCK

HSDISCK

SCKCH

DSDO

1

ns

t

= t

+ t (Note 11)

DSDO

13.5

ns

SCKCH

SSDISCK

C = 20pF (Note 11)

L

9.5

ns

C = 20pF (Note 10)

L

1

ns

HSDO

C = 20pF (Note 10)

L

5

ns

DSDOBUSYL

EN

(Note 11)

(Note 10)

16

13

ns

DIS

1

ns

SSCKRDL

HSCKRDL

16

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Bipolar zero-scale error is the offset voltage measured from

–0.5LSB when the output code flickers between 0000 0000 0000 0000

and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of

–FS or +FS untrimmed deviation from ideal first and last code transitions

and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 8: All specifications in dB are referred to a full-scale 2.5V input with

a 2.5V reference voltage.

Note 3: When these pin voltages are taken below ground or above REF

or OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 100mA below ground or above REFor OV without

latch-up.

Note 9: f

= 250kHz, I varies proportionately with sample rate.

DD

SMPL REF

Note 10: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

Note 4: V = 2.5V, OV = 2.5V, REF = 2.5V, f = 250kHz.

SMPL

DD

Note 5: Recommended operating conditions.

and OV = 5.25V.

DD

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 12: t

100MHz for rising capture.

of 10ns maximum allows a shift clock frequency up to

SCK

0.8*OV

DD

t

WIDTH

0.2*OV

DD

t

50%

DELAY

238216 F01

0.8*OV

0.2*OV

0.8*OV

0.2*OV

DD

Figure 1. Voltage Levels for Timing Specifications

238116fa

5

For more information www.linear.com/LTC2381-16

LTC2381-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 2.5V, OV_DD= 2.5V, REF = 2.5V,

f_SMPL= 250ksps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

2.0

1.5

1.0

1600000

1400000

1200000

1000000

1.0

0.5

0.0

0.5

0.0

800000

600000

400000

200000

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–32768

–16384

0

16384

32768

–32768

–16384

0

16384

32768

–2

–1

0

1

2

OUTPUT CODE

CODE

238116 G01

238116 G02

238116 G03

32k Point FFT f_S= 250ksps,

f_IN= 20kHz

THD, Harmonics

vs Input Frequency

SNR, SINAD vs Input Frequency

0

–20

93

92.5

92

–90

–95

SNR = 91.8dB

THD = –106dB

SINAD = 91.6dB

SFDR = 107dB

–40

–100

–105

–110

–115

–120

–125

–130

–60

SNR

3RD

2ND

THD

–80

91.5

91

–100

–120

–140

–160

–180

SINAD

90.5

90

0

25

50

75

100

125

0

25

50

75

100

0

25

50

FREQUENCY (kHz)

75

100

FREQUENCY (kHz)

238116 G05

238116 G06

238116 G04

SNR, SINAD vs Input level,

f_IN= 20kHz

SNR, SINAD vs Temperature

THD, Harmonics vs Temperature

93.0

92.5

92.0

91.5

91.0

93.00

92.50

92.00

91.50

91.00

–100

–105

–110

–115

–120

SNR

SINAD

SNR

THD

2ND

SINAD

3RD

–55 –35 –15

5

25 45 65 85 105 125

–40

–30

–20

–10

0

–55 –35 –15

5

25 45 65 85 105 125

INPUT LEVEL (dB)

TEMPERATURE (ºC)

TEMPERATURE (°C)

238116 G07

238116 G08

238116fa

6

For more information www.linear.com/LTC2381-16

LTC2381-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 2.5V, OV_DD= 2.5V, REF = 2.5V,

f_SMPL= 250ksps, unless otherwise noted.

INL/DNL vs Temperature

Full-Scale Error vs Temperature

Offset Error vs Temperature

1

0.5

0

–0.5

–1

0

–0.25

–0.5

–0.75

–1

–FS

MAX INL

MAX DNL

MIN DNL

MIN INL

+FS

–0.5

–1

–1.5

–2

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

238116 G10

238116 G11

238116 G12

Supply Current vs Temperature

Shutdown Current vs Temperature

Supply Current vs Sampling Rate

1.5

1

1.4

1.2

1

30

25

20

15

10

5

I

+ I

VDD OVDD REF

I

VDD

0.8

0.6

0.4

0.2

0

0.5

0

I

REF

I

OVDD

0

50

100

150

200

250

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

SAMPLING RATE (kHz)

TEMPERATURE (°C)

238116 G13

238116 G14

238116 G15

238116fa

7

For more information www.linear.com/LTC2381-16

LTC2381-16

PIN FUNCTIONS

CHAIN (Pin 1): Chain Mode Selector Pin. When low, the

LTC2381-16 operates in Normal Mode and the RDL/SDI

input pin functions to enable or disable SDO. When high,

the LTC2381-16 operates in Chain Mode and the RDL/

SDI pin functions as SDI, the daisy chain serial data input.

RDL/SDI (Pin 12): When CHAIN is low, the part is in Nor-

mal Mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input.

V

(Pin 2): 2.5V Digital Power Supply. The range of

SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,

theconversionresultordaisychaindatafromanotherADC

is shifted out on the rising edges of this clock MSB first.

DD

V

DD

is 2.375V to 2.625V. Bypass V to GND with a 10µF

DD

ceramic capacitor.

GND (Pins 3, 6, 10 and 16): Ground.

SDO(Pin14):SerialDataOutput. Theconversionresultor

daisy chain data is output on this pin on each rising edge

of SCK MSB first. The output data is in 2’s complement

format.

+

–

IN , IN (Pins 4, 5): Positive and Negative Differential

Analog Inputs.

REF (Pins 7, 8): Reference Input. The range of REF is 2.4V

to 2.6V. This pin is referred to the GND pin and should be

decoupledcloselytothepinwitha 47µFceramiccapacitor

(X5R, 0805 size).

OV (Pin 15): I/O Interface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.8V, 2.5V, 3.3V,

or 5V). Bypass OV to GND with a 0.1µF capacitor.

DD

CNV (Pin 9): Convert Input. A rising edge on this input

initiates a new conversion. When the conversion is done,

the part powers down as long as CNV is held high. When

CNV is returned low, the part powers up in preparation

for the next conversion.

GND (Exposed Pad Pin 17 – DFN Package Only): Ground.

Exposedpadmustbesoldereddirectlytothegroundplane.

BUSY (Pin 11): BUSY indicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished.

FUNCTIONAL BLOCK DIAGRAM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 2.5V

LTC2381-16

+

CHAIN

SDO

RDL/SDI

SCK

+

–

IN

SPI

PORT

16-BIT SAMPLING ADC

–

IN

CNV

CONTROL LOGIC

BUSY

GND

238116 BD01

238116fa

8

For more information www.linear.com/LTC2381-16

LTC2381-16

TIMING DIAGRAM

Conversion Timing Using the Serial Interface

CHAIN, RDL/SDI = 0

CNV

POWER-UP

POWER-DOWN

CONVERT

BUSY

HOLD

ACQUIRE

SCK

SDO

D15 D14 D13 D2 D1 D0

238116 TD01

APPLICATIONS INFORMATION

OVERVIEW

CONVERTER OPERATION

TheLTC2381-16isalownoise,lowpower,highspeed16-bit

successive approximation register (SAR) ADC. Operating

from a single 2.5V supply, the LTC2381-16 supports a

large 2.5V fully differential input range, making it ideal

for high performance applications which require a wide

dynamicrange.TheLTC2381-16achieves 2LSBINLmax,

no missing codes at 16-bits and 92dB SNR.

A rising edge on the CNV pin initiates a conversion. During

the conversion phase, the 16-bit CDAC is sequenced

through a successive approximation algorithm, effec-

tively comparing the sampled input with binary-weighted

fractions of the reference voltage (e.g. V /2, V /4 …

REF

V

REF

/65536) using the differential comparator. At the end

ofconversion,theCDACoutputapproximatesthesampled

analog input. The ADC control logic then prepares the 16-

bit digital output code for serial transfer.

Fast 250ksps throughput with no cycle latency makes the

LTC2381-16 ideally suited for a wide variety of high speed

applications.Aninternaloscillatorsetstheconversiontime,

easing external timing considerations. The LTC2381-16

dissipates only 3.25mW at 250ksps, while an auto

power-down feature is provided to further reduce power

dissipation during inactive periods.

TRANSFER FUNCTION

The LTC2381-16 digitizes the full-scale voltage of 2 × REF

16

into 2 levels, resulting in an LSB size of 76µV with

REF=2.5V.TheidealtransferfunctionisshowninFigure2.

The output data is in 2’s complement format.

The LTC2381-16 features a proprietary sampling archi-

tecture that enables the ADC to begin acquiring the next

sample during the current conversion. The resulting

extended acquisition time of 3.25µs allows the use of

extremely low power ADC drivers.

ANALOG INPUT

The analog inputs of the LTC2381-16 are fully differential

in order to maximize the signal swing that can be digitized.

Theanaloginputscanbemodeledbytheequivalentcircuit

238116fa

9

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

shown in Figure 3. The diodes at the input provide ESD

is important even for DC inputs, because the ADC inputs

draw a current spike when entering acquisition.

protection. In the acquisition phase, each input sees ap-

proximately 45pF (C ) from the sampling CDAC in series

IN

For best performance, a buffer amplifier should be used

to drive the analog inputs of the LTC2381-16. The ampli-

fier provides low output impedance which produces fast

settling of the analog signal during the acquisition phase.

It also provides isolation between the signal source and

the current spike the ADC inputs draw.

with 40Ω (R ) from the on-resistance of the sampling

ON

switch. Any unwanted signal that is common to both in-

puts will be reduced by the common mode rejection of the

ADC. The inputs draw a current spike while charging the

C capacitors during acquisition. When the LTC2381-16

IN

is not acquiring the input, the analog inputs draw only a

small leakage current.

Input Filtering

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

011...111

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

Another filter network consisting of LPF2 and the 100Ω

series input resistors should be used between the buffer

and ADC inputs to both minimize the noise contribution

of the buffer and to help minimize disturbances reflected

into the buffer from sampling transients. Long RC time

constants at the analog inputs will slow down the settling

of the analog inputs. Therefore, LPF2 requires a wider

bandwidth than LPF1. A buffer amplifier with a low noise

density must be selected to minimize degradation of the

SNR. With the 482kHz lowpass filter shown in Figure 4,

the LT6350 provides the full data sheet performance of

the LTC2381-16.

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/65536

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

INPUT VOLTAGE (V)

238116 F02

Figure 2. LTC2381-16 Transfer Function

REF

C

IN

R

ON

+

IN

BIAS

VOLTAGE

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

REF

C

IN

ON

–

238116 F03

Figure 3. The Equivalent Circuit for the

Differential Analog Input of the LTC2381-16

LPF2

50Ω

SINGLE-ENDED-

INPUT SIGNAL

100Ω

LPF1

+

IN

INPUT DRIVE CIRCUITS

500Ω

3300pF

LTC2381-16

LT6350

A low impedance source can directly drive the high im-

pedance inputs of the LTC2381-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

–

6600pF

50Ω

100Ω

BW = 482kHz

238116 F04

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

BW = 48kHz

Figure 4. Input Signal Chain

238116fa

10

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

Single-Ended-to-Differential Conversion

The LT6350 can also be used to buffer and convert large,

true bipolar signals which swing below ground to the

2.5V differential input range of the LTC2381-16. Figure

7 shows the LT6350 being used to convert a 10V true

bipolar signal for use by the LTC2381-16. The input im-

Forsingle-endedinputsignals,asingle-endedtodifferential

conversion circuit must be used to produce a differential

signal at the inputs of the LTC2381-16. The LT6350 ADC

driverisrecommendedforperformingsingle-ended-to-dif-

ferential conversions. The LT6350 is flexible and may be

configured to convert single-ended signals of various

amplitudes to the 2.5V differential input range of the

LTC2381-16. The LT6350 is also available in H-grade to

complement the extended temperature operation of the

LTC2381-16 up to 125°C.

pedance is again set by resistor R . Table 2 shows the

IN

resulting SNR and THD for several values of R . Figure

IN

LT6350

OUT1

OUT2

0V to

2.5V

4

5

R

INT

8

1

+

–

INT

0V to 2.5V

Figure 5 shows the LT6350 being used to convert a 0V

to 2.5V single-ended input signal. In this case, the first

amplifier is configured as a unity gain buffer and the sin-

gle-ended input signal directly drives the high-impedance

input of the amplifier. As shown in the FFT of Figure 5a,

the LT6350 drives the LTC2381-16 to full data sheet per-

formance without degrading the SNR or THD .

–

+

2.5V to

0V

2

+

–

V

= V /2

REF

CM

238116 F05

Figure 5. LT6350 Converting a 0V-2.5V Single-Ended Signal

to a 2.5V Differential Input Signal

The LT6350 can also be used to buffer and convert

single-ended signals larger than the input range of the

LTC2381-16 in order to maximize the signal swing that

can be digitized. Figure 6 shows the LT6350 converting a

0V-5V single-ended input signal to the 2.5V differential

input range of the LTC2381-16. In this case, the first am-

plifierintheLT6350isconfiguredasaninvertingamplifier

stage, which acts to attenuate the input signal down to the

0V-2.5V input range of the LTC2381-16. In the inverting

amplifier configuration, the single-ended input signal

source no longer directly drives a high impedance input

of the first amplifier. The input impedance is instead set

0

SNR = 91.8dB

–20

–40

THD = –106dB

SINAD = 91.6dB

SFDR = 107dB

–60

–80

–100

–120

–140

–160

–180

0

25

50

75

100

125

FREQUENCY (kHz)

by resistor R . R must be chosen carefully based on

IN IN

238116 F05a

the source impedance of the signal source. Higher values

Figure 5a. 32k Point FFT Plot for Circuit Shown in Figure 5

of R tend to degrade both the noise and distortion of

IN

the LT6350 and LTC2381-16 as a system. R1, R2 and R3

must be selected in relation to R to achieve the desired

IN

attenuation and to maintain a balanced input impedance

in the first amplifier. Table 1 shows the resulting SNR

and THD for several values of R , R1, R2 and R3 in this

IN

configuration. Figure 6a shows the resulting FFT when

using the LT6350 as shown in Figure 6.

238116fa

11

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

V

CM

REF

R2 = 1.24k

200pF

R2 = 1k

150pF

LT6350

OUT1

OUT2

2.5V to

0V

4

5

OUT1

OUT2

2.5V to

0V

4

5

R

INT

R

V

8

+

–

INT

R

INT

8

+

–

INT

10µF

R4 = 1.1k

R3 = 10k

10µF

R4 = 680Ω

R3 = 2k

–

+

–

+

0V to

2.5V

0V to

2.5V

1

2

1

2

R

= 2k

R1 = 1k

R = 10k

IN

R1 = 1.24k

+

–

+

–

V

= V /2

REF

= V /2

REF

CM

75pF

0V to 5V

10V

238116 F06

220pF

238116 F07

Figure 6. LT6350 Converting a 0V-5V Single-Ended Signal

to a 2.5V Differential Input Signal

Figure 7. LT6350 Converting a 10V Single-Ended Signal to

a 2.5V Differential Input Signal

0

SNR = 91.7dB

SNR = 91.8dB

–20

–40

THD = –100dB

SINAD = 91.2dB

SFDR = 103.5dB

–20

–40

THD = –95.5dB

SINAD = 91.4dB

SFDR = 96.9dB

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

25

50

75

100

125

0

25

50

75

100

125

FREQUENCY (kHz)

238116 F06a

238116 F07a

Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6

Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7

7a shows the resulting FFT when using the LT6350 as

shown in Figure 7.

10k

50k

5k

10k

50k

3.3k

16k

91

–100

–97

25k

Table 1. SNR, THD vs R_INfor 0-5V Single-Ended Input Signal

Table 2. SNR, THD vs R_INfor 10V Single-Ended Input Signal

R

R1

(Ω)

R2

(Ω)

R3

(Ω)

R4

(Ω)

SNR

(dB)

THD

(dB)

IN

R

IN

R1

(Ω)

R2

(Ω)

R3

(Ω)

R4

(Ω)

SNR

(dB)

THD

(dB)

(Ω)

2k

1k

2k

680

92

–100

is critical to achieving the full data sheet performance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications. Withitssmallsize, lowpowerandhigh

accuracy, the LTC6652-2.5 is particularly well suited for

use with the LTC2381-16. The LTC6652-2.5 offers 0.05%

(max)initialaccuracyand5ppm/°C(max)temperatureco-

efficient for high precision applications. The LTC6652-2.5

10k

50k

1.24k

6.19k

12.4k

1.24k

6.19k

12.4k

10k

50k

1.1k

5.49k

11k

92

91

–96

–97

100k

ADC REFERENCE

TheLTC2381-16requiresanexternalreferencetodefineits

input range. A low noise, low temperature drift reference

is fully specified over the H-grade temperature range and

238116fa

12

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

complements the extended temperature operation of the

LTC2381-16 up to 125°C. We recommend bypassing the

LTC6652-2.5 with a 47µF ceramic capacitor (X5R, 0805

size) close to the REF pin. All performance curves shown

in this data sheet were obtained using the LTC6652-2.5.

V

OUT_S

OUT_F

LTC6655-2.5

V

1Ω

47µF

REF

The REF pin of the LTC2381-16 draws charge (Q

)

CONV

LTC2381-16

from the 47µF bypass capacitor during each conversion

cycle. The reference replenishes this charge with a DC

238116 F09

current, I

= Q

/t . The DC current draw of the

REF

CONV CYC

Figure 9. LTC6655-2.5 Driving REF of LTC2381-16

REF pin, I , depends on the sampling rate and output

REF

code. If the LTC2381-16 is used to continuously sample

a signal at a constant rate, the LTC6652-2.5 will keep the

deviation of the reference voltage over the entire code

span to less than 0.5LSBs.

0

SNR = 91.8dB

–20

–40

THD = –106dB

SINAD = 91.6dB

SFDR = 107dB

–60

When idling, the REF pin on the LTC2381-16 draws only a

smallleakagecurrent(<1µA).Inapplicationswhereaburst

of samples is taken after idling for long periods as shown

–80

–100

–120

–140

–160

–180

in Figure 8, I quickly goes from approximately 0µA to

REF

a maximum of 285µA at 250ksps. This step in DC current

draw triggers a transient response in the reference that

must be considered since any deviation in the reference

output voltage will affect the accuracy of the output code.

In applications where the transient response of the refer-

ence is important, the fast settling LTC6655-2.5 reference

is recommended. Inserting a 1Ω resistor between the

47µF bypass capacitor and reference output as shown in

Figure 9 helps to improve the transient settling time and

minimize the reference voltage deviation.

0

25

50

75

100

125

FREQUENCY (kHz)

238116 F10

Figure 10. 32k Point FFT of the LTC2381-16

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2381-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

CNV

IDLE

PERIOD

IDLE

PERIOD

238116 F08

Figure 8. CNV Waveform Showing Burst Sampling

238116fa

13

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure10showsthattheLTC2381-16achieves

a typical SINAD of 92dB at a 250kHz sampling rate with

a 20kHz input.

supply voltage drops below 1V. Once the supply voltage

reenters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 20µs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

Signal-to-Noise Ratio (SNR)

TIMING AND CONTROL

CNV Timing

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 10 shows

that the LTC2381-16 achieves a typical SNR of 92dB at a

250kHz sampling rate with a 20kHz input.

The LTC2381-16 conversion is controlled by CNV. A rising

edge on CNV will start a conversion. Once a conversion

has been initiated, it cannot be restarted until the conver-

sion is complete. For optimum performance, CNV should

be driven by a clean low jitter signal. Converter status is

indicated by the BUSY output which remains high while

the conversion is in progress. To ensure that no errors

occur in the digitized results, any additional transitions

on CNV should occur within 40ns from the start of the

conversion or after the conversion has been completed.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency (f

SM-

/2). THD is expressed as:

PL

2

V2²+ V3²+ V4²+…+ V_N

1.4

1.2

1

THD=20log

V1

where V1 is the RMS amplitude of the fundamental fre-

0.8

0.6

0.4

0.2

0

quencyandV2throughV aretheamplitudesofthesecond

N

through Nth harmonics.

POWER CONSIDERATIONS

TheLTC2381-16providestwopowersupplypins:the2.5V

0

50

100

150

200

250

power supply (V ), and the digital input/output interface

DD

SAMPLING RATE (kHz)

power supply (OV ). The flexible OV supply allows the

DD

238116 F11

LTC2381-16tocommunicatewithanydigitallogicoperating

Figure 11. Power Supply Current of the LTC2381-16

Versus Sampling Rate

between 1.8V and 5V, including 2.5V and 3.3V systems.

Power Supply Sequencing

ACQUISITION

The LTC2381-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2381-16

has a power-on-reset (POR) circuit that will reset the

LTC2381-16 at initial power-up or whenever the power

AproprietarysamplingarchitectureallowstheLTC2381-16

to begin acquiring the input signal for the next conversion

750nsafterthestartofthecurrentconversion.Thisextends

238116fa

14

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

theacquisitiontimeto3.25µs,easingsettlingrequirements

and allowing the use of extremely low power ADC drivers.

(Refer to the Timing Diagram.)

initiation of the next conversion. The auto power-down

feature will reduce the power dissipation of the LTC2381-

16 as the sampling frequency is reduced. Since the time

required to power up the part does not change at lower

sample rates, the LTC2381-16 can remain powered-down

Internal Conversion Clock

for a larger fraction of the conversion cycle (t ), there-

CYC

The LTC2381-16 has an internal clock that is trimmed to

achieve a maximum conversion time of 2.5µs.

by reducing the average power dissipation which scales

linearly with sampling rate as shown in Figure 11.

Auto Power-Down

The LTC2381-16 automatically powers down after a con-

version has been completed as long as CNV remains high.

During power-down, the data from the last conversion

can be clocked out. To minimize power dissipation during

power-down, disable SDO and turn off SCK. To power up

DIGITAL INTERFACE

The LTC2381-16 has a serial digital interface. The flexible

OV supplyallowstheLTC2381-16tocommunicatewith

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

the part, bring CNV low at least 200ns (t

) before the

CONVL

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

15MHz, a 250ksps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D15 remains valid till the first rising edge of SCK.

The serial interface on the LTC2381-16 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2381-16. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy-chained.

238116fa

15

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

Normal Mode, Single Device

Figure 12 shows a single LTC2381-16 operated in Normal

Mode with CHAIN and RDL/SDI tied to ground. With RDL/

SDI grounded, SDO is enabled and the MSB(D15) of the

new conversion data is available at the falling edge of

BUSY.ThisisthesimplestwaytooperatetheLTC2381-16.

When CHAIN = 0, the LTC2381-16 operates in Normal

mode. In Normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

high-impedance. If RDL/SDI is low, SDO is driven.

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

LTC2381-16

SCK

RDL/SDI

SDO

DATA IN

CLK

238116 F10

CONVERT

POWER-DOWN

POWER-UP

CONVERT

ACQUIRE

CHAIN = 0

ACQUIRE

t

CYC

t

CNVH

t

CNV

CNVL

t

ACQ

HOLD

t

= t

– t

ACQ CYC HOLD

BUSY

SCK

t

CONV

t

SCK

t

BUSYLH

t

SCKH

1

2

3

14

15

16

t

SCKL

t

HSDO

t

DSDOBUSYL

t

DSDO

SDO

D15

D14

D13

D1

D0

238116 F10a

(RDL/SDI = 0)

Figure 12. Using a Single LTC2381-16 in Normal Mode

238116fa

16

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

Normal Mode, Multiple Devices

timeinordertoavoidbusconflicts. AsshowninFigure13,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSB of the selected

device is output onto SDO. To ensure the MSB is properly

output and captured, SCK must be held low at least 1ns

before and 16ns after bringing RDL/SDI low.

Figure 13 shows multiple LTC2381-16 devices operating

in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO.

By sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDI input of each ADC must

be used to allow only one LTC2381-16 to drive SDO at a

RDL2

RDL1

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2381-16

B

LTC2381-16

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

238116 F11

CONVERT

POWER-DOWN

CONVERT

POWER-UP

ACQUIRE

CHAIN = 0

CNV

ACQUIRE

t

CNVL

t

HOLD

BUSY

t

CONV

t

BUSYLH

RDL/SDI

A

RDL/SDI

B

t

SCK

t

SCKH

HSCKRDL

SCK

SDO

1

2

3

14

15

16

17

18

19

30

31

32

t

SCKL

SSCKRDL

HSDO

t

DIS

t

DSDO

t

EN

Hi-Z

D15

D14

D13

D1

A

D0

A

D15

D14

D13

D1

B

D0

B

A

B

238116 F11a

Figure 13. Normal Mode with Multiple Devices Sharing CNV, SCK and SDO

238116fa

17

For more information www.linear.com/LTC2381-16

LTC2381-16

APPLICATIONS INFORMATION

When CHAIN = OV , the LTC2381-16 operates in Chain

This is useful for applications where hardware constraints

may limit the numberoflines needed to interface toa large

number of converters. Figure 14 shows an example with

two daisy chained devices. The MSB of converter A will

appear at SDO of converter B after 16 SCK cycles. The

MSB of converter A is clocked in at the SDI/RDL pin of

converter B on the rising edge of the first SCK.

DD

Mode. In Chain Mode, SDO is always enabled and RDL/

SDI serves as the serial data input pin (SDI) where daisy

chain data output from another ADC can be input.

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2381-16

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

238116 F12

CONVERT

POWER-DOWN

POWER-UP

CONVERT

ACQUIRE

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

t

SCKCH

t

SCKH

SCK

1

2

3

14

15

16

17

18

30

31

32

t

SSDISCK

SCKL

t

HSDO

t

HSDISCK

t

DSDO

SDO = RDL/SDI

A

B

D15

D14

D13

D1

D0

A

t

DSDOBUSYL

D15

D14

D13

D1

D15

D14

D1

A

D0

A

B

A

SDO

B

238116 F14

Figure 14. Chain Mode Timing Diagram

238116fa

18

For more information www.linear.com/LTC2381-16

LTC2381-16

BOARD LAYOUT

To obtain the best performance from the LTC2381-16

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible. In

particular,careshouldbetakennottorunanydigitalclocks

orsignalsalongsideanalogsignalsorunderneaththeADC.

Recommended Layout

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1571A, the

evaluation kit for the LTC2381-16.

Partial Top Silkscreen

238116 F13

238116fa

19

For more information www.linear.com/LTC2381-16

LTC2381-16

BOARD LAYOUT

Partial Layer 1 Component Side

238116 BL01

Partial Layer 2 Ground Plane

238116 BL02

238116fa

20

For more information www.linear.com/LTC2381-16

LTC2381-16

BOARD LAYOUT

Partial Layer 3 PWR Plane

238116 BL03

Partial Layer 4 Bottom Layer

238116 BL04

238116fa

21

For more information www.linear.com/LTC2381-16

LTC2381-16

BOARD LAYOUT

Partial Schematic of Demoboard

R E F 1

8

R E F

1

G N D

7

1 5

D D

G N D 1 6

O V

G N D

1 0

D D

V

2

G N D

6

3

2

1

3

2

1

238116fa

22

For more information www.linear.com/LTC2381-16

LTC2381-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2381-16#packaging for the most recent package drawings.

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)

0.70 0.05

3.30 0.05

ꢀ.70 0.05

3.60 0.05

2.20 0.05

PACKAGE

OUTLINE

0.25 0.05

0.45 BSC

3.ꢀ5 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.ꢀꢀ5

TYP

0.40 0.ꢀ0

4.00 0.ꢀ0

(2 SIDES)

9

ꢀ6

R = 0.05

TYP

3.30 0.ꢀ0

3.00 0.ꢀ0

(2 SIDES)

ꢀ.70 0.ꢀ0

PIN ꢀ NOTCH

R = 0.20 OR

0.35 × 45°

PIN ꢀ

TOP MARK

(SEE NOTE 6)

CHAMFER

(DEꢀ6) DFN 0806 REV Ø

8

ꢀ

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

3.ꢀ5 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

238116fa

23

For more information www.linear.com/LTC2381-16

LTC2381-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2381-16#packaging for the most recent package drawings.

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

238116fa

24

For more information www.linear.com/LTC2381-16

LTC2381-16

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

07/16 Updated graphs G01, G02 and G03

6

238116fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation

that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

For more information www.linear.com/LTC2381-16

LTC2381-16

TYPICAL APPLICATION

ADC Driver: Single-Ended Input to Differential Output with Filter

0

–20

SNR = 91.8dB

THD = –106dB

SINAD = 91.6dB

SFDR = 107dB

LPF2

50Ω

SINGLE-ENDED

INPUT SIGNAL

–40

LT6350

LPF1

500Ω

100Ω

+

–

4

5

IN

–60

R

INT

3300pF

8

1

+

–

INT

LTC2381-16

–80

6600pF

IN

–100

–120

–140

–160

–180

50Ω

BW = 482kHz

+

–

238116 TA03

2

BW = 48kHz

+

–

V

= V /2

REF

CM

0

25

50

75

100

125

FREQUENCY (kHz)

238116 TA04

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC2383-16/LTC2382-16 16-Bit, 1Msps/500ksps Serial ADC

2.5V Supply, Differential Input, 92dB SNR, 2.5V Input Range,16-Pin MSOP

and 4mmx3mm16-Pin DFN Packages,Pin Compatible with the LTC2382-16

LTC2393-16

LTC2392-16

LTC2391-16

16-Bit, 1Msps Parallel/Serial ADC

16-Bit, 500ksps Parallel/Serial ADC

16-Bit, 250ksps Parallel/Serial ADC

5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2392-16, LTC2391-16

5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2393-16, LTC2391-16

5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2393-16, LTC2392-16

LTC1864/LTC1864L

LTC1865/LTC1865L

LTC2302/LTC2306

16-Bit, 250ksps/150ksps 1-Channel µPower, ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package

16-Bit, 250ksps 2-Channel µPower ADC

5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package

5V Supply, 14mW at 500ksps, 10-Pin DFN Package

12-Bit, 500ksps, 1-/2-Channel, Low Noise, ADC

LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC

3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package

DACs

LTC2641

16-Bit Single Serial V

DACs

1LSB INL, 1LSB DNL, MSOP-8 Package, 0V to 5V Output

SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)

OUT

LTC2630

12-/10-/8-Bit Single V

OUT

REFERENCES

LTC6652

Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 2.1ppm Peak-to-Peak Noise, MSOP-8

Package

LTC6655

AMPLIFIERS

LT6350

Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

Low Noise Single-Ended-To-Differential ADC Driver Rai-to-Rail Input and Outputs, 240ns 0.01% Settling Time, DFN-8 or

MSOP-8 Packages

LT6200/LT6200-5/

LT6200-10

165MHz/800MHz/1.6GHz Op Amp with Unity

Gain/AV = 5/AV = 10

Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz,

TSOT23-6 Package

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail Input/Output

Noise Low Power Amplifiers

1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth

LTC1992

Low Power, Fully Differential Input/Output

Amplifier/Driver Family

1mA Supply Current

238116fa

LT 0716 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

26

For more information www.linear.com/LTC2381-16

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2381-16

●

 LINEAR TECHNOLOGY CORPORATION 2010


型号：	LTC2381CMS-16#PBF
厂家：	Linear
描述：	LTC2381-16 - 16-Bit, 250ksps, Low Power SAR ADC with Serial Interface; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总26页 (文件大小：1941K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2381CMS-16#PBF [Linear]

相关型号：

LTC2381CMS-16#TRPBF

LTC2381CMS-16PBF

LTC2381HMS-16PBF

LTC2381IDE-16PBF

LTC2381IMS-16PBF

LTC2382-16

LTC2382CDE-16#PBF

LTC2382CDE-16#TRPBF

LTC2382CDE-16PBF

LTC2382CMS-16#PBF

LTC2382CMS-16#TRPBF

LTC2382CMS-16PBF