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LTC2389-18 [Linear]

16-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog; 16位， 2.5Msps SAR ADC ，具有引脚可配置模拟
LTC2389-18
型号： LTC2389-18
厂家： Linear    Linear
描述：

16-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog
16位， 2.5Msps SAR ADC ，具有引脚可配置模拟
文件： 总40页 (文件大小：1048K)
中文：  中文翻译
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LTC2389-16  
16-Bit, 2.5Msps SAR ADC  
with Pin-Configurable Analog  
Input Range and 96dB SNR  
Features  
Description  
The LTC®2389-16 is a low noise, high speed 16-bit  
successiveapproximationregister(SAR)ADC. Operating  
from a single 5V supply, the LTC2389-16 supports pin-  
configurable fully differential (±±.ꢀ96V), pseudo-differ-  
ential unipolar (ꢀV to ±.ꢀ96V), and pseudo-differential  
bipolar (±2.ꢀ±8V) analog input ranges, allowing it to  
interface with multiple signal chain formats without re-  
quiring additional level translation or signal conditioning.  
The LTC2389-16 achieves ±1LSB INL (maximum), no  
missing codes at 16-bits, and 96.ꢀdB (fully differential)/  
93.5dB (pseudo differential) SNR (typical).  
n
2.5Msps Throughput Rate  
n
±±LSB INL (Max)  
n
Guaranteed ±6-Bit, No Missing Codes  
n
Pin-Configurable Analog Input Range:  
±ꢀ.ꢁ06ꢂ ꢃullꢄ ꢅifferential  
ꢁꢂ to ꢀ.ꢁ06ꢂ Pseudo-ꢅifferential Unipolar  
±2.ꢁꢀ4ꢂ Pseudo-ꢅifferential Bipolar  
n
06.ꢁdB (ꢃullꢄ ꢅifferential)/03.5dB (Pseudo  
ꢅifferential) SNR (Tꢄp) at f = 2kHz  
IN  
n
–116dB (Fully Differential)/–112dB (Pseudo  
Differential) THD (Typ) at f = 2kHz  
IN  
n
Guaranteed Operation to 125ꢁC  
The LTC2389-16 includes a precision internal ±.ꢀ96V  
reference, with a guaranteed ꢀ.5% initial accuracy and a  
±2ꢀppm/ꢁC (maximum) temperature coefficient, as well  
as an internal reference buffer. Fast 2.5Msps throughput  
with no cycle latency in the parallel interface modes  
makes the LTC2389-16 ideally suited for a wide variety  
of high speed applications. An internal oscillator sets  
the conversion time, easing external timing considera-  
tions. The LTC2389-16 dissipates only 162.5mW at  
2.5Msps, while both nap and sleep power-down modes  
areprovidedtofurtherreducepowerconsumptionduring  
inactive periods.  
n
Single 5V Supply  
n
Internal 2ꢀppm/ꢁC (Max) Reference  
n
Internal Reference Buffer  
n
162.5mW Power Dissipation at 2.5Msps  
n
No Pipeline Delay, No Cycle Latency  
n
1.8V to 5V I/O Voltages  
n
Parallel and Serial I/O Interface  
n
±8-pin 7mm × 7mm LQFP and QFN Packages  
applications  
n
Medical Imaging  
n
High Speed, Wide Dynamic Range Data Acquisition  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and  
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property  
of their respective owners. Protected by U.S. Patents, including 77ꢀ5765.  
n
Industrial Process Control  
Instrumentation  
ATE  
n
n
typical application  
32k Point ꢃꢃT fSMPL = 2.5Msps, fIN = 2kHz  
5V 1.8V TO 5V  
0
10µF  
0.1µF  
V
0.1µF  
10µF  
SNR = 96.0dB  
THD = –116dB  
SINAD = 96.0dB  
4.096V  
–20  
0V  
0V  
OV  
PARALLEL OR  
SERIAL INTERFACE  
DD  
DD  
–40 SFDR = 117dB  
16 BIT  
A0  
–60  
–80  
10Ω  
49.9Ω  
1nF  
+
A1  
IN  
IN  
4.096V  
MODE0  
MODE1  
RESET  
PD  
+
–
0V  
4.096V  
LTC2389-16  
–100  
–120  
–140  
–160  
–180  
CS  
1nF  
49.9Ω  
10Ω  
0V  
–
OB/2C  
PD/FD  
BUSY  
4.096V  
CNVST  
SAMPLE  
CLOCK  
VCM REFOUT REFIN REFSENSE GND  
0V  
238916 TA01a  
0
250  
500  
750  
1000  
1250  
10µF  
2.048V  
FREQUENCY (kHz)  
238916 TA01b  
1µF  
238916f  
1
LTC2389-16  
absolute maximum ratings (Notes ±, 2)  
Supply Voltage (V , OV ) .......................................6V  
Operating Temperature Range  
DD  
DD  
Analog Input Voltage (Note 3)  
LTC2389C................................................ ꢀꢁC to 7ꢀꢁC  
LTC2389I .............................................–±ꢀꢁC to 85ꢁC  
LTC2389H.......................................... –±ꢀꢁC to 125ꢁC  
Storage Temperature Range .................. –65ꢁC to 15ꢀꢁC  
Lead Temperature (Soldering, 1ꢀ sec)  
+
–
IN , IN , REFIN, CNVST.....(GND – ꢀ.3V) to (V + ꢀ.3V)  
DD  
Digital Input Voltage  
(Note 3).......................... (GND – ꢀ.3V) to (OV + ꢀ.3V)  
DD  
Digital Output Voltage  
(Note 3).......................... (GND – ꢀ.3V) to (OV + ꢀ.3V)  
LX Package.......................................................3ꢀꢀꢁC  
DD  
Power Dissipation.............................................. 5ꢀꢀmW  
pin conFiguration  
TOP VIEW  
TOP VIEW  
GND  
1
2
3
4
5
6
7
8
9
36 VCM  
35 GND  
GND  
1
2
3
4
5
6
7
8
9
36 VCM  
35 GND  
34 CNVST  
33 PD  
32 RESET  
31 CS  
30 PD/FD  
29 BUSY  
28 D15  
27 D14  
26 D13  
25 D12  
V
V
DD  
V
DD  
V
DD  
34  
CNVST  
DD  
MODE0  
MODE1  
OB/2C  
A0  
33 PD  
32 RESET  
31 CS  
30 PD/FD  
29 BUSY  
28 D15  
27 D14  
26 D13  
25 D12  
MODE0  
MODE1  
OB/2C  
A0  
49  
GND  
A1  
D0  
A1  
D0  
D1 10  
D2 11  
D3 12  
D1 10  
D2 11  
D3 12  
UK PACKAGE  
48-LEAD (7mm × 7mm) PLASTIC QFN  
LX PACKAGE  
T
JMAX  
= 125ꢁC, θ = 29ꢁC/W  
JA  
48-LEAD (7mm × 7mm) PLASTIC LQFP  
EXPOSED PAD (PIN ±9) IS GND, MUST BE SOLDERED TO PCB  
T
JMAX  
= 15ꢀꢁC, θ = 5ꢀꢁC/W  
JA  
orDer inFormation  
LEAꢅ ꢃREE ꢃINISH  
LTC2389CUK-16#PBF  
LTC2389IUK-16#PBF  
LEAꢅ ꢃREE ꢃINISH  
LTC2389CLX-16#PBF  
LTC2389ILX-16#PBF  
LTC2389HLX-16#PBF  
TAPE ANꢅ REEL  
PART MARKING*  
PACKAGE ꢅESCRIPTION  
TEMPERATURE RANGE  
LTC2389CUK-16#TRPBF LTC2389UK-16  
ꢀꢁC to 7ꢀꢁC  
±8-Lead 7mm × 7mm Plastic QFN  
±8-Lead 7mm × 7mm Plastic QFN  
PACKAGE ꢅESCRIPTION  
LTC2389IUK-16#TRPBF  
TRAY  
LTC2389UK-16  
PART MARKING*  
LTC2389LX-16  
LTC2389LX-16  
LTC2389LX-16  
–±ꢀꢁC to 85ꢁC  
TEMPERATURE RANGE  
ꢀꢁC to 7ꢀꢁC  
LTC2389CLX-16#PBF  
LTC2389ILX-16#PBF  
LTC2389HLX-16#PBF  
±8-Lead 7mm × 7mm Plastic LQFP  
±8-Lead 7mm × 7mm Plastic LQFP  
±8-Lead 7mm × 7mm Plastic LQFP  
–±ꢀꢁC to 85ꢁC  
–±ꢀꢁC to 125ꢁC  
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
238916f  
2
LTC2389-16  
analog input The l denotes the specifications which applꢄ over the full operating temperature range, otherwise  
specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
TYP  
MAX  
UNITS  
+
l
+
–
V
V
Absolute Input Range (IN )  
(Note 5)  
–ꢀ.1  
V
V
+ ꢀ.1  
V
IN  
IN  
REF  
–
l
l
l
Absolute Input Range (IN )  
Fully Differential (Note 5)  
Pseudo-Differential Unipolar (Note 5)  
Pseudo-Differential Bipolar (Note 5)  
–ꢀ.1  
–ꢀ.1  
+ ꢀ.1  
ꢀ.1  
/2 + ꢀ.1  
V
V
V
REF  
ꢀ
REF  
V
V
/2 – ꢀ.1  
V
V
/2  
V
REF  
REF  
–
l
l
l
+
V
– V  
Input Differential Voltage Range  
Fully Differential  
Pseudo-Differential Unipolar  
Pseudo-Differential Bipolar  
–V  
V
V
V
V
V
V
IN  
IN  
REF  
REF  
REF  
ꢀ
–V /2  
REF  
/2  
REF  
l
V
Input Common Mode Voltage Range Fully Differential  
/2 – ꢀ.1  
/2  
V
/2 + ꢀ.1  
V
CM  
IN  
REF  
REF  
REF  
l
l
I
Analog Input Leakage Current  
C- and I-Grades  
H-Grade  
–1  
–2  
1
2
µA  
µA  
IN  
C
Analog Input Capacitance  
Sample Mode  
Hold Mode  
±5  
5
pF  
pF  
CMRR  
Input Common Mode Rejection Ratio  
CNVST High Level Input Voltage  
CNVST Low Level Input Voltage  
CNVST Input Current  
7ꢀ  
dB  
V
l
l
l
V
V
1.5  
IHCNVST  
ꢀ.5  
V
ILCNVST  
INCNVST  
I
V
IN  
= ꢀV to V  
–25  
–6ꢀ  
µA  
DD  
converter characteristics The l denotes the specifications which applꢄ over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
16  
TYP  
MAX  
UNITS  
Bits  
l
l
Resolution  
No Missing Codes  
Transition Noise  
16  
Bits  
Fully Differential  
Pseudo-Differential Unipolar  
Pseudo-Differential Bipolar  
ꢀ.19  
ꢀ.38  
ꢀ.38  
LSB  
RMS  
RMS  
RMS  
LSB  
LSB  
l
l
l
INL  
Integral Linearity Error  
Differential Linearity Error  
Zero-Scale Error  
Fully Differential (Note 6)  
–1  
–1  
–1  
±ꢀ.3  
±ꢀ.3  
±ꢀ.3  
1
1
1
LSB  
LSB  
LSB  
Pseudo-Differential Unipolar (Note 6)  
Pseudo-Differential Bipolar (Note 6)  
l
l
l
DNL  
ZSE  
Fully Differential  
Pseudo-Differential Unipolar  
Pseudo-Differential Bipolar  
–ꢀ.6  
–ꢀ.7  
–ꢀ.7  
±ꢀ.1  
±ꢀ.1  
±ꢀ.1  
ꢀ.6  
ꢀ.7  
ꢀ.7  
LSB  
LSB  
LSB  
l
l
l
Fully Differential (Note 7)  
Pseudo-Differential Unipolar (Note 7)  
Pseudo-Differential Bipolar (Note 7)  
–3  
–±  
–±  
ꢀ
ꢀ
ꢀ
3
±
±
LSB  
LSB  
LSB  
Zero-Scale Error Drift  
Full-Scale Error  
±ꢀ.ꢀ5  
ppm/ꢁC  
l
FSE  
External Reference (Note 7)  
Internal Reference (Note 7)  
ꢀ.15  
ꢀ.15  
%
%
Full-Scale Error Drift  
±5  
ppm/ꢁC  
238916f  
3
LTC2389-16  
Dynamic accuracy The l denotes the specifications which applꢄ over the full operating temperature range,  
otherwise specifications are at TA = 25°C. AIN = –±dBꢃS (Notes ꢀ, 4)  
SYMBOL PARAMETER  
CONꢅITIONS  
Fully Differential, f = 2kHz  
MIN  
TYP  
MAX  
UNITS  
l
l
l
SINAD  
Signal-to-(Noise +  
Distortion) Ratio  
9±.±  
91.2  
91.7  
96.ꢀ  
93.2  
93.5  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz  
IN  
Pseudo-Differential Bipolar, f = 2kHz  
IN  
l
l
l
Fully Differential, f = 2kHz (H-Grade)  
9±.3  
91.ꢀ  
91.5  
96.ꢀ  
93.2  
93.5  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz (H-Grade)  
IN  
Pseudo-Differential Bipolar, f = 2kHz (H-Grade)  
IN  
l
l
l
SNR  
Signal-to-Noise Ratio Fully Differential, f = 2kHz  
95.1  
91.7  
92.1  
96.ꢀ  
93.2  
93.5  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz  
IN  
Pseudo-Differential Bipolar, f = 2kHz  
IN  
l
l
l
Fully Differential, f = 2kHz (H-Grade)  
9±.9  
91.5  
91.9  
96.ꢀ  
93.2  
93.5  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz (H-Grade)  
IN  
Pseudo-Differential Bipolar, f = 2kHz (H-Grade)  
IN  
l
l
l
THD  
Total Harmonic  
Distortion  
Fully Differential, f = 2kHz, First 5 Harmonics  
–116  
–112  
–111  
–1ꢀ3  
–1ꢀ1  
–1ꢀ2  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz, First 5 Harmonics  
IN  
Pseudo-Differential Bipolar, f = 2kHz, First 5 Harmonics  
IN  
l
l
l
Fully Differential, f = 2kHz, First 5 Harmonics (H-Grade)  
–116  
–112  
–111  
–1ꢀ3  
–1ꢀ1  
–1ꢀ2  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz, First 5 Harmonics (H-Grade)  
IN  
Pseudo-Differential Bipolar, f = 2kHz, First 5 Harmonics (H-Grade)  
IN  
l
l
l
SFDR  
Spurious-Free  
Dynamic Range  
Fully Differential, f = 2kHz  
1ꢀ±  
1ꢀ2  
1ꢀ2  
117  
113  
112  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz  
IN  
Pseudo-Differential Bipolar, f = 2kHz  
IN  
l
l
l
Fully Differential, f = 2kHz (H-Grade)  
1ꢀ3  
1ꢀ2  
1ꢀ2  
117  
113  
112  
dB  
dB  
dB  
IN  
Pseudo-Differential Unipolar, f = 2kHz (H-Grade)  
IN  
Pseudo-Differential Bipolar, f = 2kHz (H-Grade)  
IN  
–3dB Input Bandwidth  
Aperture Delay  
5ꢀ  
ꢀ.5  
1
MHz  
ns  
Aperture Jitter  
ps  
RMS  
Transient Response  
Full-Scale Step  
7ꢀ  
ns  
reFerence characteristics The l denotes the specifications which applꢄ over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
TYP  
±.ꢀ96  
±1ꢀ  
2.3  
MAX  
±.116  
±2ꢀ  
UNITS  
V
V
Internal Reference Voltage  
REFOUT Tied to REFIN, I  
= ꢀµA  
±.ꢀ76  
REFOUT  
OUT  
l
V
Tempco  
I
= ꢀµA (Note 9)  
OUT  
ppm/ꢁC  
kΩ  
REFOUT  
REFOUT Output Impedance  
REFOUT Line Regulation  
Converter REFIN Voltage  
REFIN Input Impedance  
VCM Output Voltage  
–ꢀ.1mA ≤ I  
≤ ꢀ.1mA  
OUT  
V
DD  
= ±.75V to 5.25V  
ꢀ.3  
mV/V  
V
V
REF  
±.ꢀ76  
±.ꢀ96  
7±  
±.116  
kΩ  
I
= ꢀµA  
2.ꢀ8  
V
OUT  
238916f  
4
LTC2389-16  
Digital inputs anD Digital outputs The l denotes the specifications which applꢄ over the full  
operating temperature range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
TYP  
MAX  
UNITS  
V
l
l
l
V
IH  
V
IL  
High Level Input Voltage  
Low Level Input Voltage  
Digital Input Current  
0.8 • OV  
DD  
0.2 • OV  
V
DD  
I
V
= ꢀV to OV  
DD  
–1ꢀ  
1ꢀ  
µA  
pF  
IN  
IN  
C
V
V
Digital Input Capacitance  
High Level Output Voltage  
Low Level Output Voltage  
Hi-Z Output Leakage Current  
Output Source Current  
Output Sink Current  
5
IN  
l
l
l
I
I
= –5ꢀꢀµA  
= 5ꢀꢀµA  
OV – ꢀ.2  
DD  
V
OH  
OL  
OUT  
OUT  
ꢀ.2  
1ꢀ  
V
I
I
I
V
V
V
= ꢀV to OV  
= ꢀV  
–1ꢀ  
µA  
mA  
mA  
OZ  
OUT  
OUT  
OUT  
DD  
–1ꢀ  
1ꢀ  
SOURCE  
SINK  
= OV  
DD  
power requirements The l denotes the specifications which applꢄ over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
±.75  
1.71  
TYP  
MAX  
5.25  
5.25  
36  
UNITS  
l
l
l
V
Supply Voltage  
Supply Voltage  
Core Supply Current  
5
V
V
DD  
OV  
DD  
I
2.5Msps Sample Rate  
2.5Msps Sample Rate, Internal Reference Enabled  
32.5  
3±.1  
mA  
mA  
VDD  
I
I
I/O Supply Current  
2.5Msps Sample Rate (C = 15pF)  
1.6  
15  
mA  
µA  
OVDD  
L
l
Power Down Current  
Conversion Done, P = OV , Other Digital Inputs  
25ꢀ  
PD  
D
DD  
(I  
VDD  
+ I  
)
Tied to OV or GND  
OVDD  
DD  
P
D
Power Dissipation  
2.5Msps Sample Rate  
162.5  
75  
18ꢀ  
125ꢀ  
mW  
µW  
Conversion Done, P = OV , Other Digital Inputs  
D
DD  
Tied to OV or GND  
DD  
timing characteristics The l denotes the specifications which applꢄ over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
SYMBOL  
PARAMETER  
CONꢅITIONS  
MIN  
TYP  
MAX  
UNITS  
l
l
f
Sampling Frequency  
Parallel Output Modes  
Serial Output Mode  
2.5  
2.ꢀ  
Msps  
Msps  
SMPL  
l
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
t
Conversion Time  
2±5  
77  
28ꢀ  
11ꢀ  
31ꢀ  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CONV  
ACQ  
Acquisition Time  
t
= t  
– t  
– t  
(Note 1ꢀ)  
BUSYLH  
ACQ  
CYC  
CONV  
±ꢀꢀ  
2ꢀ  
Time Between CNVST↓  
CNVST Low Time  
CNVST High Time  
CNVST↓ to BUSY Delay  
RESET Pulse Width  
SCK Period  
CYC  
CNVSTL  
CNVSTH  
BUSYLH  
RESETH  
SCK  
2ꢀꢀ  
C = 15pF  
13  
L
2ꢀꢀ  
1ꢀ  
±
(Notes 5, 11)  
SCK High Time  
SCKH  
SCKL  
SCK Low Time  
±
1ꢀ  
2
SCK↓ Delay From CS↓  
SDI Setup Time From SCK↓  
DSCK  
SSDI  
238916f  
5
LTC2389-16  
timing characteristics The l denotes the specifications which applꢄ over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Note ꢀ)  
l
t
t
t
t
t
t
t
1
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SDI Hold Time From SCK↓  
HSDI  
DSDO  
HSDO  
DDBUSYL  
EN  
l
l
l
l
l
l
C = 15pF  
9
SDO Data Valid Delay From SCK↑  
SDO Data Remains Valid Delay From SCK↑  
Data Valid to BUSY↓  
L
C = 15pF  
L
1
1
C = 15pF  
L
11  
8
Bus Enable Time After CS↓  
Data Valid Delay From A1 Transition  
Bus Relinquish Time After CS↑  
C = 15pF  
L
DDA1  
DIS  
11  
Note ±: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 2: All voltage values are with respect to ground.  
Note 3: When these pin voltages are taken below ground or above  
zero-scale error is the offset voltage measured from ꢀ.5LSB when the  
output code flickers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and ꢀꢀꢀꢀ ꢀꢀꢀꢀ  
ꢀꢀꢀꢀ ꢀꢀꢀ1. Bipolar zero-scale error is the offset voltage measured from  
–ꢀ.5LSB when the output code flickers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and  
1111 1111 1111 1111. Fully differential full-scale error is the worst-case  
deviation of the first and last code transitions from ideal and includes the  
effect of offset error. Unipolar full-scale error is the deviation of the last  
code transition from ideal and includes the effect of offset error. Bipolar  
full-scale error is the worst-case deviation of the first and last code  
transitions from ideal and includes the effect of offset error.  
Note 4: All specifications in dB are referred to a full-scale ±±.ꢀ96V (fully  
differential), ꢀV to ±.ꢀ96V (pseudo-differential unipolar), or ±2.ꢀ±8V  
(pseudo-differential bipolar) input with a ±.ꢀ96V reference voltage.  
Note 0: Temperature coefficient is calculated by dividing the maximum  
change in output voltage by the specified temperature range.  
V
or OV , they will be clamped by internal diodes. This product can  
DD  
DD  
handle input currents up to 1ꢀꢀmA below ground, or above V or OV  
,
DD  
DD  
without latchup.  
Note ꢀ: V = 5V, OV = 5V, V = ±.ꢀ96V external reference,  
DD  
DD  
REF  
f
= 2.5MHz, unless otherwise noted.  
SMPL  
Note 5: Recommended operating conditions.  
Note 6: Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual endpoints of the transfer curve.  
The deviation is measured from the center of the quantization band.  
Note 7: Fully differential zero-scale error is the offset voltage measured  
from –ꢀ.5LSB when the output code flickers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ  
ꢀꢀꢀꢀ and 1111 1111 1111 1111 in two’s complement format. Unipolar  
Note ±ꢁ: Guaranteed by design, not subject to test.  
Note ±±: A t  
period of 1ꢀns minimum allows a shift clock frequency of  
SCK  
up to 1ꢀꢀMHz for rising capture.  
0.8 • OV  
DD  
t
WIDTH  
0.2 • OV  
DD  
50%  
50%  
t
t
DELAY  
DELAY  
238916 F01  
0.8 • OV  
0.8 • OV  
0.2 • OV  
DD  
DD  
DD  
DD  
0.2 • OV  
ꢃigure ±. ꢂoltage Levels for Timing Specifications  
238916f  
6
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, ꢃullꢄ ꢅifferential Range (Pꢅ/FD = ꢁꢂ), ꢂCM = 2.ꢁꢀ4ꢂ, fSMPL = 2.5Msps, unless otherwise noted.  
Integral Nonlinearitꢄ  
vs Output Code  
ꢅifferential Nonlinearitꢄ  
vs Output Code  
ꢅC Histogram (Zero-Scale)  
1.0  
0.8  
280000  
240000  
200000  
160000  
120000  
80000  
40000  
0
0.5  
0.4  
INTERNAL REF  
EXTERNAL REF  
INTERNAL REF  
EXTERNAL REF  
0.6  
0.3  
0.4  
0.2  
0.2  
0.1  
0
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
0
16384  
32768  
49152  
65536  
0
16384  
32768  
49152  
65536  
–2  
–1  
0
1
2
OUTPUT CODE  
CODE  
OUTPUT CODE  
238916 G01  
238916 G02  
238916 G03  
Internal Reference Output  
vs Temperature  
32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz  
ꢅC Histogram (Near ꢃull-Scale)  
280000  
240000  
200000  
160000  
120000  
80000  
40000  
0
4.097  
4.096  
4.095  
4.094  
4.093  
4.092  
4.091  
4.090  
4.089  
0
SNR = 96.0dB  
THD = –116dB  
SINAD = 96.0dB  
T
C
= 8ppm/°C  
–20  
–40 SFDR = 117dB  
–60  
–80  
–100  
–120  
–140  
–160  
–180  
32762 32763 32764 32765 32766  
CODE  
0
250  
500  
750  
1000  
1250  
–55 –35 –15  
5
25 45 65 85 105 125  
TEMPERATURE (°C)  
FREQUENCY (kHz)  
238916 G04  
238916 G05  
238916 G06  
SNR, SINAꢅ vs Input Level,  
fIN = 2kHz  
SNR, SINAꢅ vs Input ꢃrequencꢄ  
THꢅ, Harmonics vs Input ꢃrequencꢄ  
–85  
–90  
97.0  
96.5  
96.0  
95.5  
95.0  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
–95  
SNR  
SNR  
–100  
–105  
–110  
–115  
–120  
–125  
–130  
SINAD  
SINAD  
THD  
3RD  
2ND  
0
12.5  
37.5 50 62.5 75 87.5 100  
25  
–10  
0
12.5  
37.5 50 62.5 75 87.5 100  
–40  
–30  
–20  
INPUT LEVEL (dB)  
0
25  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 G08  
238916 G07  
238916 G09  
238916f  
7
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, ꢃullꢄ ꢅifferential Range (Pꢅ/FD = ꢁꢂ), ꢂCM = 2.ꢁꢀ4ꢂ, fSMPL = 2.5Msps, unless otherwise noted.  
SNR, SINAꢅ vs Temperature,  
fIN = 2kHz  
THꢅ, Harmonics vs Temperature,  
f
IN = 2kHz  
INL/ꢅNL vs Temperature  
98  
97  
96  
95  
94  
93  
–110  
–115  
–120  
–125  
–130  
–135  
1.0  
0.5  
0
THD  
MAX INL  
MAX DNL  
3RD  
SNR  
SINAD  
MIN DNL  
MIN INL  
2ND  
–0.5  
–1.0  
85 105  
125  
–55 –35 –15  
5
45  
85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65  
25  
65  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
238916 G10  
238916 G11  
238916 G12  
Offset Error vs Temperature  
ꢃull-Scale Error vs Temperature  
Supplꢄ Current vs Temperature  
1.0  
0.5  
25  
20  
35  
30  
25  
20  
15  
10  
5
I
VDD  
15  
+FS  
10  
5
0
0
–5  
–FS  
–10  
–15  
–20  
–25  
–0.5  
I
OVDD  
–1.0  
0
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
238916 G13  
238916 G15  
238916 G14  
Power-ꢅown Current  
vs Temperature  
Supplꢄ Current  
vs Sampling ꢃrequencꢄ  
CMRR vs Input ꢃrequencꢄ  
35  
30  
25  
20  
15  
10  
5
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
75  
70  
65  
60  
55  
50  
I
+ I  
VDD OVDD  
I
VDD  
I
OVDD  
0
1
10  
100  
1000  
10000  
500  
750  
1000  
1250  
0
250  
–55 –35 –15  
5
25 45 65 85 105 125  
SAMPLING FREQUENCY (kHz)  
TEMPERATURE (°C)  
FREQUENCY (kHz)  
238916 G17  
238916 G16  
238916 G18  
238916f  
8
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, Pseudo-ꢅifferential Unipolar Range (Pꢅ/FD = Oꢂꢅꢅ, OB/2C = Oꢂꢅꢅ), fSMPL = 2.5Msps, unless otherwise noted.  
ꢅifferential Nonlinearitꢄ  
vs Output Code  
Integral Nonlinearitꢄ vs Output Code  
ꢅC Histogram (Near Zero-Scale)  
1.0  
0.8  
240000  
200000  
160000  
120000  
80000  
40000  
0
0.5  
0.4  
INTERNAL REF  
EXTERNAL REF  
INTERNAL REF  
EXTERNAL REF  
0.6  
0.3  
0.4  
0.2  
0.2  
0.1  
0
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
0
16384  
32768  
49152  
65536  
0
16384  
32768  
49152  
65536  
2
3
4
5
6
OUTPUT CODE  
CODE  
OUTPUT CODE  
238916 G19  
238916 G20  
238916 G21  
32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz  
ꢅC Histogram (Near ꢃull-Scale)  
SNR, SINAꢅ vs Input ꢃrequencꢄ  
96  
94  
92  
90  
88  
86  
84  
82  
80  
240000  
200000  
160000  
120000  
80000  
40000  
0
0
SNR = 93.2dB  
THD = –112dB  
SINAD = 93.2dB  
–20  
–40 SFDR = 113dB  
SNR  
–60  
–80  
SINAD  
–100  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
65530 65531 65532 65533 65534  
CODE  
0
12.5 25 37.5 50 62.5 75 87.5 100  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 G24  
238916 G23  
238916 G22  
SNR, SINAꢅ vs Input Level,  
fIN = 2kHz  
SNR, SINAꢅ vs Temperature,  
fIN = 2kHz  
THꢅ, Harmonics vs Input ꢃrequencꢄ  
–75  
–80  
94.0  
93.5  
93.0  
92.5  
92.0  
95  
94  
93  
92  
91  
90  
SNR  
–85  
SNR  
–90  
–95  
THD  
SINAD  
3RD  
2ND  
–100  
–105  
–110  
–115  
–120  
–125  
–130  
SINAD  
0
12.5  
37.5 50 62.5 75 87.5 100  
–10  
25  
–40  
–30  
–20  
0
–55 –35 –15  
5
45  
85 105 125  
25  
65  
FREQUENCY (kHz)  
INPUT LEVEL (dB)  
TEMPERATURE (°C)  
238916 G25  
238916 G26  
238916 G27  
238916f  
9
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, Pseudo-ꢅifferential Unipolar Range (Pꢅ/FD = Oꢂꢅꢅ, OB/2C = Oꢂꢅꢅ), fSMPL = 2.5Msps, unless otherwise noted.  
THꢅ, Harmonics vs Temperature,  
f
IN = 2kHz  
INL/ꢅNL vs Temperature  
Offset Error vs Temperature  
1.0  
1.0  
0.5  
–105  
–110  
–115  
–120  
–125  
–130  
–135  
THD  
0.5  
MAX INL  
MAX DNL  
2ND  
0
0
MIN DNL  
MIN INL  
3RD  
–0.5  
–0.5  
–1.0  
–1.0  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
238916 G29  
238916 G30  
238916 G28  
ꢃull-Scale Error vs Temperature  
CMRR vs Input ꢃrequencꢄ  
35  
30  
25  
20  
15  
10  
5
0
–5  
–10  
–15  
–20  
–25  
–30  
–35  
80  
75  
70  
65  
60  
55  
50  
–55 –35 –15  
5
25 45 65 85 105 125  
500  
750  
1000  
1250  
0
250  
TEMPERATURE (°C)  
FREQUENCY (kHz)  
238916 G31  
238916 G32  
238916f  
10  
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, Pseudo-ꢅifferential Bipolar Range (Pꢅ/FD = Oꢂꢅꢅ, OB/2C = Oꢂ), fSMPL = 2.5Msps, unless otherwise noted.  
Integral Nonlinearitꢄ  
vs Output Code  
ꢅifferential Nonlinearitꢄ  
vs Output Code  
ꢅC Histogram (Zero-Scale)  
240000  
200000  
160000  
120000  
80000  
40000  
0
0.5  
0.4  
1.0  
0.8  
0.6  
0.4  
0.2  
0
INTERNAL REF  
EXTERNAL REF  
INTERNAL REF  
EXTERNAL REF  
0.3  
0.2  
0.1  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
0
16384  
32768  
49152  
65536  
0
16384  
32768  
49152  
65536  
–2  
–1  
0
1
2
CODE  
OUTPUT CODE  
OUTPUT CODE  
238916 G34  
238916 G33  
238916 G35  
32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz  
ꢅC Histogram (Near ꢃull-Scale)  
SNR, SINAꢅ vs Input ꢃrequencꢄ  
240000  
200000  
160000  
120000  
80000  
40000  
0
0
96  
94  
92  
90  
88  
86  
84  
82  
80  
SNR = 93.5dB  
THD = –111dB  
SINAD = 93.5dB  
–20  
SNR  
–40 SFDR = 112dB  
–60  
–80  
SINAD  
–100  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
32762 32763 32764 32765 32766  
CODE  
0
12.5  
37.5 50 62.5 75 87.5 100  
25  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 G36  
238916 G37  
238916 G38  
SNR, SINAꢅ vs Input Level,  
fIN = 2kHz  
SNR, SINAꢅ vs Temperature,  
fIN = 2kHz  
THꢅ, Harmonics vs Input ꢃrequencꢄ  
–75  
–80  
94.5  
94.0  
93.5  
93.0  
92.5  
95  
94  
93  
92  
91  
90  
SNR  
–85  
THD  
2ND  
–90  
SINAD  
SNR  
–95  
–100  
–105  
–110  
–115  
–120  
–125  
–130  
3RD  
SINAD  
0
12.5  
37.5 50 62.5 75 87.5 100  
25  
–40  
–30  
–20  
–10  
0
–55 –35 –15  
5
45  
85 105 125  
25  
65  
FREQUENCY (kHz)  
INPUT LEVEL (dB)  
TEMPERATURE (°C)  
238916 G39  
238916 G40  
238916 G41  
238916f  
11  
LTC2389-16  
typical perFormance characteristics TA = 25°C, ꢂꢅꢅ = 5ꢂ, Oꢂꢅꢅ = 2.5ꢂ, ꢂREꢃ = ꢀ.ꢁ06ꢂ  
External Reference, Pseudo-ꢅifferential Bipolar Range (Pꢅ/FD = Oꢂꢅꢅ, OB/2C = Oꢂ), fSMPL = 2.5Msps, unless otherwise noted.  
THꢅ, Harmonics vs Temperature,  
f
IN = 2kHz  
INL/ꢅNL vs Temperature  
Offset Error vs Temperature  
–105  
–110  
–115  
–120  
–125  
–130  
–135  
1.0  
1.0  
0.5  
THD  
0.5  
0
MAX INL  
MAX DNL  
2ND  
0
MIN DNL  
MIN INL  
–0.5  
–0.5  
3RD  
–1.0  
–1.0  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
–55 –35 –15  
5
25 45 65 85 105 125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
238916 G42  
238916 G43  
238916 G44  
CMRR vs Input ꢃrequencꢄ  
ꢃull-Scale Error vs Temperature  
25  
20  
80  
75  
70  
65  
60  
55  
50  
15  
+FS  
10  
5
0
–5  
–FS  
–10  
–15  
–20  
–25  
500  
750  
1000  
1250  
0
250  
–55 –35 –15  
5
25 45 65 85 105 125  
FREQUENCY (kHz)  
TEMPERATURE (°C)  
238916 G46  
238916 G45  
238916f  
12  
LTC2389-16  
pin Functions  
GNꢅ (Pins ±, ±7, 2ꢁ, 35, ꢀ±, ꢀꢀ, ꢀ4, Exposed Pad  
Pin ꢀ0 (QꢃN Onlꢄ)): Ground. Solder all GND pins and  
exposed pad to the ground plane.  
and lower bytes of the bus, as described in Table 1. When  
MODEꢀ = 1, the output data bus is configured to provide  
serial data, and the logic input A1 has no effect on the  
parsing or presentation of the serial data. Logic levels  
ꢂ
(Pins 2, 3, ±0, ꢀꢁ, ꢀ5, ꢀ6, ꢀ7): 5V Power Supply.  
ꢅꢅ  
are determined by OV . For information regarding pin  
DD  
The range of V is ±.75V to 5.25V. Bypass V network  
DD  
DD  
compatibility with 18-bit versions of the LTC2389 family,  
refer to the Pin Compatibility with LTC2389-18 section.  
to GND with a ꢀ.1μF ceramic capacitor close to each pin  
and a 1ꢀμF ceramic capacitor in parallel.  
ꢅꢁ (Pin 0): Data Bit ꢀ. When MODEꢀ = ꢀ, this pin is bit ꢀ  
MOꢅEꢁ (Pin ꢀ): Data Bus Configuration Input. This pin,  
in conjunction with Pin 8 (A1), controls the parsing and  
presentation of conversion results on the output data bus.  
Based on the state of MODEꢀ, the bus is configured to  
provide either 16-bit/8-bit parallel (MODEꢀ = ꢀ), or serial  
(MODEꢀ = 1) data, as described in Table 1. Digital outputs  
that are not active in a particular mode become Hi-Z. Logic  
of the parallel data output bus, as described in Table 1.  
Logic levels are determined by OV .  
DD  
ꢅ± (Pin ±ꢁ): Data Bit 1. When MODEꢀ = ꢀ, this pin is bit 1  
of the parallel data output bus, as described in Table 1.  
Logic levels are determined by OV .  
DD  
ꢅ2 (Pin ±±): Data Bit 2. When MODEꢀ = ꢀ, this pin is bit 2  
levels are determined by OV . For information regarding  
DD  
of the parallel data output bus, as described in Table 1.  
pincompatibilitywith18-bitversionsoftheLTC2389family,  
Logic levels are determined by OV .  
DD  
refer to the Pin Compatibility with LTC2389-18 section.  
ꢅ3 (Pin ±2): Data Bit 3. When MODEꢀ = ꢀ, this pin is bit 3  
MOꢅE± (Pin 5): Data Bus Configuration Input. This pin is  
reserved for use in 18-bit versions of the LTC2389 family,  
and for 16-bit versions of the family it should be driven to  
of the parallel data output bus, as described in Table 1.  
Logic levels are determined by OV .  
DD  
ꢅꢀ (Pin ±3): Data Bit ±. When MODEꢀ = ꢀ, this pin is bit ±  
a logic low level. Logic levels are determined by OV . For  
DD  
of the parallel data output bus, as described in Table 1.  
informationregardingpincompatibilitywith18-bitversions  
of the LTC2389 family, refer to the Pin Compatibility with  
LTC2389-18 section.  
Logic levels are determined by OV .  
DD  
ꢅ5 (Pin ±ꢀ): Data Bit 5. When MODEꢀ = ꢀ, this pin is bit 5  
of the parallel data output bus, as described in Table 1.  
OB/2C (Pin 6): Offset Binary/ Two’s Complement Input.  
This pin, in conjunction with Pin 3ꢀ (PD/FD), controls the  
analog input range of the converter and the binary format  
of the conversion result, as described in Table 2. Logic  
Logic levels are determined by OV .  
DD  
ꢅ6 (Pin ±5): Data Bit 6. When MODEꢀ = ꢀ, this pin is bit 6  
of the parallel data output bus, as described in Table 1.  
levels are determined by OV .  
DD  
Logic levels are determined by OV .  
DD  
Aꢁ (Pin 7): Address Bit ꢀ Input. This pin is reserved  
for use in 18-bit versions of the LTC2389 family, and  
for 16-bit versions of the family it should be driven to a  
ꢅ7 (Pin ±6): Data Bit 7. When MODEꢀ = ꢀ, this pin is bit 7  
of the parallel data output bus, as described in Table 1.  
Logic levels are determined by OV .  
DD  
logic low level. Logic levels are determined by OV . For  
DD  
Oꢂ (Pin ±4): I/O Interface Power Supply. The range of  
ꢅꢅ  
informationregardingpincompatibilitywith18-bitversions  
of the LTC2389 family, refer to the Pin Compatibility with  
LTC2389-18 section.  
OV is 1.71V to 5.25V. Bypass OV to GND close to the  
DD  
DD  
pin with a ꢀ.1μF and a 1ꢀμF ceramic capacitor in parallel.  
ꢅ4 (Pin 2±): Data Bit 8. When MODEꢀ = ꢀ, this pin is bit 8  
A± (Pin 4): Address Bit 1 Input. This pin, in conjunction  
withPin±(MODEꢀ),controlstheparsingandpresentation  
ofconversionresultsontheparalleloutputdatabus.When  
MODEꢀ = ꢀ, the bus is configured to provide 16-bit/8-bit  
parallel data, and the logic input A1 determines which  
segment of the conversion result is driven on the upper  
of the parallel data output bus, as described in Table 1.  
Logic levels are determined by OV .  
DD  
ꢅ0/SꢅI (Pin 22): Data Bit 9/Serial Data Input. When  
MODEꢀ = ꢀ, this pin is bit 9 of the parallel data output  
bus, as described in Table 1. When MODEꢀ = 1, this pin  
238916f  
13  
LTC2389-16  
pin Functions  
is the serial data input, which can be used to daisy chain  
two or more converters on a single SDO line. The digital  
data level on SDI is output on SDO with a delay of 16 SCK  
periods after the start of the read sequence. Logic levels  
ꢅ±2 (Pin 25): Data Bit 12. When MODEꢀ = ꢀ, this pin  
is bit 12 of the parallel data output bus, as described in  
Table 1. Logic levels are determined by OV .  
DD  
ꢅ±3 (Pin 26): Data Bit 13. When MODEꢀ = ꢀ, this pin  
are determined by OV .  
DD  
is bit 13 of the parallel data output bus, as described in  
ꢅ±ꢁ/SꢅO (Pin 23): Data Bit 1ꢀ/Serial Data Output. When  
MODEꢀ = ꢀ, this pin is bit 1ꢀ of the parallel data output  
bus, as described in Table 1. When MODEꢀ = 1, this pin  
is the serial data output line, which serially outputs the  
result of the most recent conversion clocked by SCK. The  
data is output MSB first on the rising edge of SCK. The  
dataformatisdeterminedby thelogic levelsofpins PD/FD  
and OB/2C, as described in Table 2. Logic levels are  
Table 1. Logic levels are determined by OV .  
DD  
ꢅ±ꢀ (Pin 27): Data Bit 1±. When MODEꢀ = ꢀ, this pin  
is bit 1± of the parallel data output bus, as described in  
Table 1. Logic levels are determined by OV .  
DD  
ꢅ±5 (Pin 24): Data Bit 15. When MODEꢀ = ꢀ, this pin  
is bit 15 of the parallel data output bus, as described in  
Table 1. Logic levels are determined by OV .  
DD  
determined by OV .  
DD  
BUSY (Pin 20): Busy Output. This pin transitions low to  
high at the start of each conversion and stays high until  
the conversion is complete. The falling edge of BUSY can  
be used as the data-ready clock signal. Logic levels are  
ꢅ±±/SCK (Pin 2ꢀ): Data Bit 11/Serial Clock Input. When  
MODEꢀ = ꢀ, this pin is bit 11 of the parallel data output  
bus, as described in Table 1. When MODEꢀ = 1, this pin  
this is the serial clock input. Logic levels are determined  
determined by OV .  
DD  
by OV .  
DD  
Table ±. ꢅata Bus Configuration Table. Use Input MOꢅEꢁ to Select Bus Configuration Based on Application Bus Width.  
In the ±6-Bit/4-Bit Parallel Configuration, Input A± Controls Mapping of Upper and Lower Bꢄtes of Conversion Result R[±5:ꢁ] Onto  
ꢅata Bus Pins ꢅ[±5:ꢁ]. Shaded Cells ꢅenote Bidirectional Pins Configured as Inputs.  
BUS CONꢃIGURATION  
16-Bit/8-Bit Parallel  
Serial  
MOꢅEꢁ  
A±  
ꢀ
ꢅ[±5:±2]  
ꢅ±±  
R[15:8]  
R[7:ꢀ]  
SCK  
ꢅ±ꢁ  
ꢅ0  
ꢅ4  
ꢅ[7:ꢁ]  
R[7:ꢀ]  
ꢀ
ꢀ
1
1
R[15:8]  
X
All Hi-Z  
SDO  
SDI  
All Hi-Z  
238916f  
14  
LTC2389-16  
pin Functions  
Pꢅ/FD (Pin 3ꢁ): Pseudo-Differential/Fully-Differential  
Input. Thispin, inconjunctionwithPin6(OB/2C), controls  
the analog input range of the converter and the binary  
format of the conversion result, as described in Table 2.  
ꢂCM (Pin 36): Common Mode Analog Output. Typically  
the output voltage on this pin is 2.ꢀ8V. Bypass to GND  
with a 1ꢀμF capacitor.  
REꢃOUT (Pin 37): Internal Reference Output. Connect  
this pin to REFIN if using the internal reference, giving  
a nominal reference voltage of ±.ꢀ96V. If an external  
reference is used, connect REFOUT to ground to power  
down the internal reference.  
Logic levels are determined by OV .  
DD  
CS (Pin 3±): Chip Select Input. The data I/O bus is enabled  
when CS is low and goes Hi-Z when CS is high. CS also  
gates the external shift clock. Logic levels are determined  
by OV .  
DD  
REꢃIN (Pin 34): Reference Input. Connect this pin to  
REFOUT if using the internal reference, giving a nominal  
reference voltage of ±.ꢀ96V. An external reference can be  
applied to REFIN if a more accurate reference is required.  
If an external reference is used tie REFOUT to ground to  
power down the internal reference. For increased filtering  
of reference noise, bypass this pin to REFSENSE using a  
1μF, or larger, ceramic capacitor.  
RESET(Pin32):ResetInput.Whenthispinisbroughthigh,  
theLTC2389-16isreset.Ifthisoccursduringaconversion,  
the conversion is halted and the data bus becomes Hi-Z.  
Logic levels are determined by OV .  
DD  
Pꢅ (Pin 33): Power-Down Input. When this pin is brought  
high, the LTC2389-16 is powered down and subse-  
quent conversion requests are ignored. Before enabling  
power-down,theresultofthelastconversionresultshould  
REꢃSENSE(Pin30):ReferenceInputSense.Donotconnect  
REFSENSE to ground when using the internal reference. If  
an external reference is used, connect REFSENSE to the  
ground pin of the external reference.  
be read. Logic levels are determined by OV .  
DD  
CNVST (Pin 3ꢀ): Conversion Start Input. A falling edge on  
this pin puts the internal sample-and-hold into the hold  
mode and starts a conversion. CNVST is independent of  
–
+
IN , IN (Pin ꢀ2, Pin ꢀ3): Negative and Positive Analog  
Inputs. The analog input range depends on the levels  
applied to Pin 3ꢀ (PD/FD) and Pin 6 (OB/2C), as described  
in Table 2.  
CS. Logic levels are determined by V .  
DD  
Table 2. Analog Input Range and Output Binarꢄ ꢃormat Configuration Table. Use Inputs Pꢅ/FD and OB/2C to Select Converter Analog  
Input Range and Binarꢄ ꢃormat of Conversion Result.  
Pꢅ/FD  
OB/2C  
ANALOG INPUT RANGE  
Fully-Differential  
BINARY ꢃORMAT Oꢃ CONꢂERSION RESULT  
Two’s Complement  
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
1
Fully-Differential  
Offset Binary  
Pseudo-Differential Bipolar  
Pseudo-Differential Unipolar  
Two’s Complement  
Straight Binary  
238916f  
15  
LTC2389-16  
Functional block Diagram  
V
OV  
DD  
DD  
LTC2389-16  
16-BIT OR 8-BIT BUS  
SDI  
SDO  
+
–
IN  
IN  
PARALLEL/  
SERIAL  
INTERFACE  
SCK  
16-BIT SAMPLING ADC 16 BITS  
CS  
MODE1  
MODE0  
A1  
1x BUFFER  
REFIN  
A0  
REFOUT  
VCM  
BUSY  
4.096V  
REFERENCE  
CONTROL LOGIC  
REFSENSE CNVST  
PD/FD  
OB/2C  
RESET  
PD GND  
238916 BD  
238916f  
16  
LTC2389-16  
timing Diagrams  
Conversion Timing Using the Parallel Interface  
CS = RESET = 0  
CNVST  
CONVERT  
ACQUIRE  
BUSY  
D[15:0]  
PREVIOUS CONVERSION  
CURRENT CONVERSION  
Conversion Timing Using the Serial Interface  
CS = RESET = 0  
CNVST  
CONVERT  
ACQUIRE  
BUSY  
SCK  
SDO  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
DON’T CARE  
238916 TD01  
238916f  
17  
LTC2389-16  
applications inFormation  
OꢂERꢂIEW  
TRANSꢃER ꢃUNCTION  
The LTC2389-16 digitizes the full-scale voltage of 2 • V  
The LTC2389-16 is a low noise, high speed 16-bit succes-  
sive approximation register (SAR) ADC. Operating from  
a single 5V supply, the LTC2389-16 supports pin-con-  
figurable fully differential (±±.ꢀ96V), pseudo-differential  
unipolar (ꢀV to ±.ꢀ96V) and pseudo-differential bipolar  
(±2.ꢀ±8V)analoginputranges,allowingittointerfacewith  
multiple signal chain formats without requiring additional  
level translation or signal conditioning. The LTC2389-16  
achieves ±1LSB INL (maximum), no missing codes at  
16-bits, and 96.ꢀdB (fully differential)/93.5dB (pseudo  
differential) SNR (typical).  
REF  
in fully-differential mode and V  
in pseudo-differential  
REF  
16  
mode, into 2 levels. With V  
= ±.ꢀ96V, the resulting  
REF  
LSBsizesinfully-differentialandpseudo-differentialmode  
are 125μV and 62.5μV, respectively. The binary format of  
the conversion result depends on the logic levels on pins  
PD/FD and OB/2C, as described in Table 2. The ideal two’s  
complementtransferfunctionisshowninFigure2,whilethe  
idealstraightbinarytransferfunctionisshowninFigure 3.  
The ideal offset binary transfer function can be obtained  
from the two’s complement transfer function by inverting  
the most significant bit (MSB) of each output code.  
The LTC2389-16 includes a precision internal ±.ꢀ96V  
reference, with a guaranteed ꢀ.5% initial accuracy and a  
±2ꢀppm/ꢁC(maximum)temperaturecoefficient,aswellas  
aninternalreferencebuffer.Fast2.5Mspsthroughputwith  
no cycle latency in the parallel interface modes makes the  
LTC2389-16 ideally suited for a wide variety of high speed  
applications.Aninternaloscillatorsetstheconversiontime,  
easing external timing considerations. The LTC2389-16  
dissipates only 162.5mW at 2.5Msps, while both nap and  
sleep power-down modes are provided to further reduce  
power consumption during inactive periods.  
011...111  
BIPOLAR  
ZERO  
011...110  
000...001  
000...000  
111...111  
111...110  
100...001  
100...000  
FSR = +FS – –FS  
1LSB = FSR/65536  
–1 0V  
LSB  
1
–FSR/2  
FSR/2 – 1LSB  
LSB  
INPUT VOLTAGE (V)  
238916 F02  
CONꢂERTER OPERATION  
ꢃigure 2. LTC2340-±6 Two’s Complement Transfer ꢃunction.  
Offset Binarꢄ Transfer ꢃunction Can Be Obtained bꢄ Inverting  
the Most Significant Bit (MSB) of Each Output Code  
The LTC2389-16 operates in two phases. During the ac-  
quisition phase, the charge redistribution capacitor D/A  
+
–
converter (CDAC) is connected to the IN and IN pins  
to sample the differential analog input voltage. A falling  
edge on the CNVST pin initiates a conversion. During the  
conversionphase,the16-bitCDACissequencedthrougha  
successiveapproximationalgorithm,effectivelycomparing  
the sampled input with binary-weighted fractions of the  
111...111  
111...110  
100...001  
100...000  
reference voltage (e.g., V /2, V /± … V /65536)  
REF  
REF  
REF  
UNIPOLAR  
ZERO  
011...111  
011...110  
using a differential comparator. At the end of conversion,  
the CDAC output approximates the sampled analog input.  
The ADC control logic then prepares the 16-bit digital  
output code for parallel or serial transfer.  
000...001  
000...000  
FSR = +FS  
1LSB = FSR/65536  
0V  
FSR – 1LSB  
INPUT VOLTAGE (V)  
238916 F03  
ꢃigure 3. LTC2340-±6 Straight Binarꢄ Transfer ꢃunction  
238916f  
18  
LTC2389-16  
applications inFormation  
ANALOG INPUT  
Pseudo-ꢅifferential Unipolar Input Range  
In the pseudo-differential unipolar input range, the ADC  
TheanaloginputsoftheLTC2389-16canbepinconfigured  
toacceptoneofthreeinputvoltageranges:fullydifferential  
(±±.ꢀ96V),pseudo-differentialunipolar(ꢀVto±.ꢀ96V),and  
pseudo-differential bipolar (±2.ꢀ±8V). In all three ranges,  
the ADC samples and digitizes the voltage difference  
+
–
digitizes the differential analog input voltage (IN – IN )  
over a span of (ꢀV to V ). In this range, a single-ended  
REF  
+
unipolar input signal, driven on the IN pin, is measured  
with respect to the signal ground reference level, driven  
+
–
–
+
between the two analog input pins (IN – IN ), and any  
unwanted signal that is common to both inputs is reduced  
by the common mode rejection ratio (CMRR) of the ADC.  
Independent of the selected range, the analog inputs can  
be modeled by the equivalent circuit shown in Figure ±.  
The diodes at the input provide ESD protection. In the  
acquisition phase, each input sees approximately ±ꢀpF  
on the IN pin. The IN pin is allowed to swing from (GND  
–
– ꢀ.1V) to (V + ꢀ.1V), while the IN pin is restricted to  
REF  
(GND ± ꢀ.1V). Unwanted signals common to both inputs  
are reduced by the CMRR of the ADC.  
Pseudo-ꢅifferential Bipolar Input Range  
In the pseudo-differential bipolar input range, the ADC  
(C ) from the sampling CDAC in series with ±ꢀΩ (R )  
IN  
IN  
+
–
digitizes the differential analog input voltage (IN – IN )  
from the on-resistance of the sampling switch. The inputs  
over a span of (±V /2). In this range, a single-ended  
REF  
drawasmallcurrentspikewhilechargingtheC capacitors  
IN  
+
bipolar input signal, driven on the IN pin, is measured  
during acquisition. During conversion, the analog inputs  
draw only a small leakage current.  
with respect to the signal mid-scale reference level, driven  
–
+
on the IN pin. The IN pin is allowed to swing from (GND  
–
V
V
DD  
DD  
– ꢀ.1V) to (V  
+ ꢀ.1V), while the IN pin is restricted  
C
REF  
IN  
R
IN  
40pF  
to (V /2 ± ꢀ.1V). Unwanted signals common to both  
40Ω  
REF  
+
–
IN  
IN  
inputs are reduced by the CMRR of the ADC.  
BIAS  
VOLTAGE  
INPUT ꢅRIꢂE CIRCUITS  
C
40pF  
IN  
R
40Ω  
IN  
A low impedance source can directly drive the high im-  
pedance inputs of the LTC2389-16 without gain error. A  
high impedance source should be buffered to minimize  
settling time during acquisition and to optimize the dis-  
tortion performance of the ADC. Minimizing settling time  
is important even for DC signals because the ADC inputs  
draw a current spike when entering acquisition.  
238916 F04  
ꢃigure ꢀ. Equivalent Circuit for the ꢅifferential  
Analog Input of the LTC2340-±6  
ꢃullꢄ ꢅifferential Input Range  
For best performance, a buffer amplifier should be used  
to drive the analog inputs of the LTC2389-16. The ampli-  
fier provides low output impedance enabling fast settling  
of the analog signal during the acquisition phase. It also  
providesisolationbetweenthesignalsourceandthecurrent  
spike drawn by the ADC inputs when entering acquisition.  
The fully differential input range provides the widest  
input signal swing, configuring the ADC to digitize the  
+
–
–
differential analog input voltage (IN – IN ) over a span  
+
of (±V ). In this range, the IN and IN pins should  
REF  
be driven 18ꢀ degrees out-of-phase with respect to  
each other, centered around a common mode voltage  
+
–
(IN +IN )/2 that is restricted to (V /2 ± ꢀ.1V). Both the  
REF  
+
–
IN and IN pins are allowed to swing from (GND – ꢀ.1V)  
to(V +ꢀ.1V).Unwantedsignalscommontobothinputs  
REF  
are reduced by the CMRR of the ADC.  
238916f  
19  
LTC2389-16  
applications inFormation  
Input ꢃiltering  
lowpass filter also directly affects settling of the analog  
inputs during acquisition and must be kept fast. In many  
applications ±9.9Ω series resistors allow for sufficient  
transientsettlingduringacquisitionwhileprovidinguseful  
additional filtering of wideband driver noise.  
The noise and distortion of the buffer amplifier and other  
supporting circuitry must be considered since they add  
to the ADC noise and distortion. A buffer amplifier with  
low noise density must be selected to minimize SNR  
degradation. A filter network should be placed between  
the buffer output and ADC input to both minimize the  
noise contribution of the buffer and reduce disturbances  
reflected into the buffer from ADC sampling transients. A  
simple one-pole lowpass RC filter is sufficient for many  
applications. It is important that the RC time constants  
of this filter be small enough to allow the analog inputs  
to completely settle to 16-bit resolution within the ADC  
Highqualitycapacitorsandresistorsshouldbeusedinthe  
RCfilterssincethesecomponentscanadddistortion.NPO  
and silver mica type dielectric capacitors have excellent  
linearity. Carbon surface mount resistors can generate  
distortion from self heating and from damage that may  
occurduringsoldering.Metalfilmsurfacemountresistors  
are much less susceptible to both problems.  
ꢃullꢄ ꢅifferential Inputs  
acquisition time (t ), as insufficient settling can limit  
ACQ  
The LTC2389-16 accepts fully differential input signals  
directly. For most fully differential applications, it is  
recommended that the LTC2389-16 be driven using the  
LT62ꢀ1 ADC driver configured as two unity-gain buffers,  
as shown in Figure 5a. The LT62ꢀ1 combines fast settling  
and good DC linearity with a ꢀ.95nV/√Hz input-referred  
noise density, enabling it to achieve the full ADC data  
sheet SNR and THD specifications, as shown in the FFT  
plot in Figure 5b. This topology may also be used to buf-  
fer single-ended signals and achieves full ADC data sheet  
SNR and THD specifications in both pseudo-differential  
input modes, as shown in the FFT plots in Figures 5c  
and 5d.  
INL and THD performance. In many applications an RC  
time constant of 1ꢀns is fast enough to allow for sufficient  
transient settling during acquisition while simultaneously  
filtering driver wideband noise.  
Often it is also beneficial to add small series resistors  
betweentheprimarylowpassRCfilterandtheADCinputs.  
These resistors, in conjunction with the ADC sampling  
capacitance C and sampling switch resistance R ,  
IN  
IN  
form a second lowpass RC filter which further limits high-  
frequency driver noise as well as reduces the magnitude  
of the current spike drawn by the analog inputs when  
entering acquisition. The time constant of this secondary  
238916f  
20  
LTC2389-16  
applications inFormation  
4.096V  
0V  
0V  
LOWPASS FILTERS  
10Ω  
1/2 LT6201  
–
+
49.9Ω  
49.9Ω  
4.096V  
+
–
IN  
1nF  
0V  
4.096V  
LTC2389-16  
1nF  
IN  
0V  
10Ω  
+
–
238916 F05a  
4.096V  
1/2 LT6201  
0V  
2.048V  
ꢃigure 5a. LT62ꢁ± Buffering a ꢃullꢄ-ꢅifferential or Single-Ended Signal Source  
0
0
0
SNR = 96.0dB  
THD = –116dB  
SINAD = 96.0dB  
SNR = 93.2dB  
THD = –112dB  
SINAD = 93.2dB  
SNR = 93.5dB  
THD = –111dB  
–20  
–20  
–20  
SINAD = 93.5dB  
–40 SFDR = 117dB  
–40 SFDR = 113dB  
–40 SFDR = 112dB  
–60  
–80  
–60  
–80  
–60  
–80  
–100  
–100  
–100  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 F05b  
238916 F05c  
238916 F05d  
ꢃigure 5b. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 5a;  
ꢅriven with ꢃullꢄ ꢅifferential Inputs  
ꢃigure 5c. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 5a;  
ꢅriven with Unipolar Inputs  
ꢃigure 5d. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 5a;  
ꢅriven with Bipolar Inputs  
238916f  
21  
LTC2389-16  
applications inFormation  
In applications where slightly degraded SNR and  
THD performance is acceptable, it is possible to drive  
the LTC2389-16 using the lower power LT6231 ADC  
driver configured as two unity-gain buffers, as shown in  
Figure 6a. The RC time constant of the output lowpass  
filter is larger in this topology to limit the high frequency  
noise contribution of the LT6231. As shown in the FFT  
plots in Figures 6b-6d, this circuit achieves 95.7dB SNR  
and –115dB THD in fully differential input mode, 92.±dB  
SNR and –112dB THD in unipolar input mode, and 92.7dB  
SNR and –11ꢀdB THD in bipolar input mode.  
4.096V  
0V  
LOWPASS FILTERS  
1/2 LT6231  
–
0V  
15Ω  
49.9Ω  
49.9Ω  
+
4.096V  
+
–
IN  
1nF  
1nF  
0V  
4.096V  
LTC2389-16  
IN  
0V  
15Ω  
+
238916 F06a  
–
4.096V  
1/2 LT6231  
0V  
2.048V  
ꢃigure 6a. LT623± Buffering a ꢃullꢄ-ꢅifferential or Single-Ended Signal Source  
0
0
0
SNR = 95.7dB  
THD = –115dB  
SINAD = 95.6dB  
SNR = 92.4dB  
THD = –112dB  
SINAD = 92.3dB  
SNR = 92.7dB  
THD = –110dB  
SINAD = 92.6dB  
–20  
–20  
–20  
–40 SFDR = 116dB  
–40 SFDR = 113dB  
–40 SFDR = 111dB  
–60  
–80  
–60  
–80  
–60  
–80  
–100  
–100  
–100  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 F06b  
238916 F06c  
238916 F06d  
ꢃigure 6b. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 6a;  
ꢅriven with ꢃullꢄ ꢅifferential Inputs  
ꢃigure 6c. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 6a;  
ꢅriven with Unipolar Inputs  
ꢃigure 6d. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 6a;  
ꢅriven with Bipolar Inputs  
238916f  
22  
LTC2389-16  
applications inFormation  
Single-Ended to ꢅifferential Conversion  
±±.ꢀ96V output signal. The RC time constant of the  
output lowpass filters is chosen to allow for sufficient  
transient settling of the LTC2389-16 analog inputs dur-  
ing acquisition. This wide filter bandwidth, coupled with  
the relatively high wideband noise of the single-ended  
to differential conversion circuit, limits the achievable  
SNR of this topology to 95.6dB, as shown in the FFT  
plot in Figure 7b.  
In some applications it may be desirable to convert a  
single-endedunipolarorbipolarsignaltoafully-differential  
signal prior to driving the LTC2389-16 to take advantage  
of the higher SNR of the LTC2389-16 in fully differential  
input mode. The LT62ꢀ1 ADC driver configured in the  
topology shown in Figure 7a can be used to convert a ꢀV  
to ±.ꢀ96V single-ended input signal to a fully-differential  
4.096V  
0V  
LOWPASS FILTERS  
4.096V  
0V  
1/2 LT6201  
10Ω  
49.9Ω  
+
–
330pF  
330pF  
+
–
1nF  
1nF  
IN  
LTC2389-16  
402Ω  
402Ω  
1/2 LT6201  
IN  
49.9Ω  
10Ω  
–
238916 F07a  
+
4.096V  
0V  
+
–
V
= 2.048V  
CM  
ꢃigure 7a. LT62ꢁ± Converting a ꢁꢂ to ꢀ.ꢁ06ꢂ Single-Ended Signal to a ±ꢀ.ꢁ06ꢂ ꢃullꢄ-ꢅifferential Signal  
0
SNR = 95.6dB  
THD = –112dB  
–20  
SINAD = 95.6dB  
–40 SFDR = 114dB  
–60  
–80  
–100  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
238916 F07b  
ꢃigure 7b. 32k Point ꢃꢃT fSMPL = 2.5Msps, fIN = 2kHz,  
for Circuit Shown in ꢃigure 7a  
238916f  
23  
LTC2389-16  
applications inFormation  
An alternate single-ended to differential topology em-  
ploying the LT6231 followed by the LT62ꢀ1 is shown in  
Figure 8a. This topology enables additional band-limiting  
of the wideband noise of the single-ended to differential  
conversion circuit using lowpass filters A without affect-  
ing the settling at the inputs of the LTC2389-16 during  
acquisition. This circuit achieves the full ADC data sheet  
SNR specifications, as shown in the FFT plot in Figure 8b.  
4.096V  
0V  
LOWPASS FILTERS A  
LOWPASS FILTERS B  
10Ω  
1/2 LT6201  
–
+
4.096V  
0V  
49.9Ω  
49.9Ω  
1/2 LT6231  
50Ω  
+
–
+
–
1nF  
IN  
10nF  
10nF  
1k  
1k  
1/2 LT6231  
LTC2389-16  
IN  
1nF  
50Ω  
–
+
+
–
10Ω  
238916 F08a  
4.096V  
0V  
+
V
CM  
= 2.048V  
–
1/2 LT6201  
ꢃigure 4a. LT623± Converting a ꢁꢂ to ꢀ.ꢁ06ꢂ Single-Ended Signal to a ±ꢀ.ꢁ06ꢂ  
ꢃullꢄ-ꢅifferential Signal ꢃollowed bꢄ LT62ꢁ± Buffering ꢃullꢄ-ꢅifferential Signal  
0
SNR = 96.0dB  
THD = –116dB  
–20  
SINAD = 96.0dB  
–40 SFDR = 117dB  
–60  
–80  
–100  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
238916 F08b  
ꢃigure 4b. 32k Point ꢃꢃT fSMPL = 2.5Msps, fIN = 2kHz,  
for Circuit Shown in ꢃigure 4a  
238916f  
24  
LTC2389-16  
applications inFormation  
Single-Ended Unipolar and Bipolar Inputs  
LT62ꢀꢀ combines fast settling and good DC linearity with  
a ꢀ.95nV/√Hz input-referred noise density, enabling it to  
achieve the full ADC data sheet SNR and THD specifica-  
tions in both pseudo-differential input modes, as shown  
in the FFT plots in Figures 9b and 9c.  
The LTC2389-16 accepts both single-ended unipolar  
and single-ended bipolar input signals directly. For most  
single-ended applications, it is recommended that the  
LTC2389-16 be driven using the LT62ꢀꢀ ADC driver con-  
figured as a unity-gain buffer, as shown in Figure 9a. The  
4.096V  
0V  
LOWPASS FILTER  
10Ω  
0V  
49.9Ω  
49.9Ω  
+
+
–
IN  
–
LT6200  
1nF  
LTC2389-16  
4.096V  
IN  
0V  
238916 F09a  
2.048V  
ꢃigure 0a. LT62ꢁꢁ Buffering a Single-Ended Signal Source  
0
0
SNR = 93.2dB  
THD = –112dB  
SINAD = 93.2dB  
SNR = 93.5dB  
THD = –111dB  
–20  
–20  
SINAD = 93.5dB  
–40 SFDR = 113dB  
–40 SFDR = 112dB  
–60  
–80  
–60  
–80  
–100  
–100  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 F09b  
238916 F09c  
ꢃigure 0b. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 0a;  
ꢅriven with Unipolar Inputs  
ꢃigure 0c. 32k Point ꢃꢃT fSMPL = 2.5Msps,  
fIN = 2kHz, for Circuit Shown in ꢃigure 0a;  
ꢅriven with Bipolar Inputs  
238916f  
25  
LTC2389-16  
applications inFormation  
In applications where slightly degraded SNR and THD  
performance is acceptable, it is possible to drive the  
LTC2389-16 using the lower power LT623ꢀ ADC driver  
configured as a unity-gain buffer, as shown in Figure 1ꢀa.  
The RC time constant of the output lowpass filter is  
larger in this topology to limit the high frequency noise  
contribution of the LT623ꢀ. As shown in the FFT plots in  
Figures 1ꢀb and 1ꢀc, this circuit achieves 92.5dB SNR  
and –112dB THD in unipolar input mode and 92.8dB SNR  
and –111dB THD in bipolar input mode.  
Note that in the circuits of Figures 9a and 1ꢀa, the source  
impedanceofthesignalappliedtoIN–directlyaffectsinput  
settling time during signal acquisition. In single-ended  
applicationswhere the impedanceofthis referencesignal  
is intrinsically high, the dual-buffer approach shown in  
Figures 5a and 6a will provide for faster acquisition time  
and better distortion performance from the ADC.  
4.096V  
0V  
LOWPASS FILTER  
15Ω  
49.9Ω  
49.9Ω  
+
0V  
+
–
IN  
–
LT6230  
1nF  
LTC2389-16  
4.096V  
IN  
0V  
238916 F10a  
2.048V  
ꢃigure ±ꢁa. The LT623ꢁ Buffering a Single-Ended Signal Source  
0
0
SNR = 92.5dB  
THD = –112dB  
SINAD = 92.5dB  
SNR = 92.8dB  
THD = –111dB  
–20  
–20  
SINAD = 92.7dB  
–40 SFDR = 112dB  
–40 SFDR = 112dB  
–60  
–80  
–60  
–80  
–100  
–100  
–120  
–140  
–160  
–180  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
238916 F10b  
238916 F10c  
ꢃigure ±ꢁb. 32k Point ꢃꢃT fSMPL = 2.5Msps, fIN = 2kHz, for  
Circuit Shown in ꢃigure ±ꢁa; ꢅriven with Unipolar Inputs  
ꢃigure ±ꢁc. 32k Point ꢃꢃT fSMPL = 2.5Msps, fIN = 2kHz, for  
Circuit Shown in ꢃigure ±ꢁa; ꢅriven with Bipolar Inputs  
238916f  
26  
LTC2389-16  
applications inFormation  
AꢅC REꢃERENCE  
ꢅYNAMIC PERꢃORMANCE  
Fast fourier transform (FFT) techniques are used to test the  
ADC’s frequency response, distortion and noise at the rated  
throughput. By applying a low distortion sine wave and ana-  
lyzing the digital output using an FFT algorithm, the ADC’s  
spectralcontentcanbeexaminedforfrequenciesoutsidethe  
fundamental. The LTC2389-16 provides guaranteed tested  
limits for both AC distortion and noise measurements.  
A low noise, low temperature drift reference is critical  
to achieving the full data sheet performance of the ADC.  
The LTC2389-16 provides an excellent internal refer-  
ence with a ±2ꢀppm/ꢁC (maximum) temperature coef-  
ficient. If even better accuracy is required, an external  
reference can be used. In both cases, the high speed, low  
noise internal reference buffer is employed and cannot be  
bypassed.Thebuffercontributesasignal-dependentnoise  
term to the converter with a typical standard deviation of:  
Signal-to-Noise and ꢅistortion Ratio (SINAꢅ)  
The signal-to-noise and distortion ratio (SINAD) is the  
ratiobetweentheRMSamplitudeofthefundamentalinput  
frequency and the RMS amplitude of all other frequency  
components at the A/D output. The output is band-limited  
tofrequenciesfromaboveDCandbelowhalfthesampling  
frequency. Figure11showsthattheLTC2389-16achieves  
a typical SINAD of 96.ꢀdB (fully differential) at a 2.5MHz  
sampling rate with a 2kHz input.  
+
–
(VIN − V  
)
IN  
• 16µVRMS  
,
VREF  
whichaccountsfortheincreaseintransitionnoisebetween  
zero-scale and full-scale inputs. The reference voltage  
applied to REFIN adds a similar signal-dependent noise  
term, but its magnitude is limited by a ±kHz (typical)  
lowpass filter in the internal buffer, making this term  
negligible in most cases.  
Signal-to-Noise Ratio (SNR)  
Internal Reference  
The signal-to-noise ratio (SNR) is the ratio between the  
RMS amplitude of the fundamental input frequency and  
the RMS amplitude of all other frequency components  
except the first five harmonics and DC. Figure 11 shows  
that the LTC2389-16 achieves a typical SNR of 96.ꢀdB  
(fully differential) at a 2.5MHz sampling rate with a  
2kHz input.  
To use the internal reference, simply tie the REFOUT and  
REFIN pins together. This connects the ±.ꢀ96V output of  
the internal reference to the input of the internal reference  
buffer. The output impedance of the internal reference  
is approximately 2.3kΩ and the input impedance of the  
internalreferencebufferisabout7±kΩ.Itisrecommended  
REFIN be bypassed to REFSENSE with a 1μF, or larger,  
capacitor to filter the output noise of the internal refer-  
ence. Do not ground the REFSENSE pin when using the  
internal reference.  
0
SNR = 96.0dB  
THD = –116dB  
–20  
SINAD = 96.0dB  
–40 SFDR = 117dB  
–60  
–80  
External Reference  
An external reference can be used with the LTC2389-16  
when even higher performance is required. The  
LTC6655 offers ꢀ.ꢀ25% (maximum) initial accuracy  
and 2ppm/ꢁC (maximum) temperature coefficient for  
high precision applications. The LTC6655 is fully speci-  
fiedovertheH-gradetemperaturerangeandcomplements  
the extended temperature operation of the LTC2389-16  
up to 125ꢁC. When using an external reference, connect  
the reference output to the REFIN pin and connect the  
REFOUT pin to ground. The REFSENSE pin should be  
connected to the ground of the external reference.  
–100  
–120  
–140  
–160  
–180  
0
250  
500  
750  
1000  
1250  
FREQUENCY (kHz)  
238916 F11  
ꢃigure ±±. 32k Point ꢃꢃT of LTC2340-±6,  
fSMPL = 2.5Msps, fIN = 2kHz  
238916f  
27  
LTC2389-16  
applications inFormation  
Total Harmonic ꢅistortion (THꢅ)  
Power Supplꢄ Sequencing  
Totalharmonicdistortion(THD)istheratiooftheRMSsum  
ofallharmonicsoftheinputsignaltothefundamentalitself.  
The out-of-band harmonics alias into the frequency band  
The LTC2389-16 does not have any specific power supply  
sequencing requirements. Care should be taken to adhere  
to the maximum voltage relationships described in the  
Absolute Maximum Ratings section. The LTC2389-16  
has an internal power-on reset (POR) circuit which resets  
the converter on initial power-up or whenever the power  
supply voltage drops below 2.5V. Once the supply volt-  
age re-enters the nominal supply voltage range, the POR  
reinitializes the ADC. With the POR, the result of the first  
conversionisvalidafterpower-upaslongasthereference  
has been given sufficient time to settle.  
between DC and half the sampling frequency (f  
THD is expressed as:  
/2).  
SMPL  
V22 + V32 + V±2 + …+ VN2  
THD= 2ꢀlog  
V1  
where V1 is the RMS amplitude of the fundamen-  
tal frequency and V2 through V are the amplitudes  
N
of the second through Nth harmonics, respectively.  
Figure 11 shows that the LTC2389-16 achieves a typical  
THD of –116dB (fully differential) at a 2.5MHz sampling  
rate with a 2kHz input.  
Nap Mode  
The LTC2389-16 can be put into nap mode after a conver-  
sionhasbeencompletedtoreducethepowerconsumption  
betweenconversions.Inthismodesomeofthecircuitryon  
the device is turned off. Nap mode is enabled by keeping  
CNVST low between conversions, as shown in Figure 12.  
To initiateanewconversionafterenteringnapmode,bring  
CNVST high and hold for at least 2ꢀꢀns before bringing  
it low again.  
POWER CONSIꢅERATIONS  
The LTC2389-16 provides two sets of power supply pins:  
the 5V core power supply (V ) and the digital input/  
DD  
output interface power supply (OV ). The flexible OV  
DD  
DD  
supply allows the LTC2389-16 to communicate with any  
digital logic operating between 1.8V and 5V, including  
2.5V and 3.3V systems. Both the V and OV supply  
DD  
DD  
networksshouldbebypassedtoGNDwithaꢀ.1μFceramic  
capacitor close to each pin and a 1ꢀμF ceramic capacitor  
in parallel.  
t
CNVSTH  
CNVST  
BUSY  
NAP  
t
t
ACQ  
CONV  
NAP MODE  
238916 F12  
ꢃigure ±2. Nap Mode Timing for the LTC2340-±6  
238916f  
28  
LTC2389-16  
applications inFormation  
Power Shutdown Mode  
mode and the fraction of the conversion cycle (t ) spent  
CYC  
napping increases as the sampling frequency (f  
decreased.  
) is  
SMPL  
When PD is tied high, the LTC2389-16 enters power  
shutdown. In this state, all internal functions, including  
the reference, are turned off and subsequent conversion  
requestsareignored.Beforeenteringpowershutdown,the  
digital output data should be read. If a request for power  
shutdown occurs during a conversion, the conversion will  
finishandthenthedevicewillpowerdown,butthedatafrom  
thatconversionshouldbereadonlyafterpowershutdown  
mode has ended. In this mode, power consumption drops  
to a typical value of 75μW from 162.5mW. This mode can  
be used if the LTC2389-16 is inactive for a long period of  
time and the user wants to minimize power dissipation.  
TIMING ANꢅ CONTROL  
CNVST Timing  
The LTC2389-16 conversion is controlled by CNVST. A  
falling edge on CNVST initiates the conversion process,  
which once begun, cannot be restarted until the con-  
version is complete. For optimum performance, CNVST  
should be driven by a clean, low jitter signal and transi-  
tions on data I/O lines should be avoided leading up to the  
falling edge of CNVST. Converter status is indicated by the  
BUSY output, which remains high while the conversion  
is in progress. Once CNVST is brought low to begin a  
conversion, it should be returned high either within 40ns  
from the start of the conversion or after the conversion  
is complete to ensure no errors occur in the digitized  
results. The CNVST timing required to take advantage of  
the reduced power nap mode of operation is described in  
the Nap Mode section.  
Recoverꢄ ꢃrom Power Shutdown Mode  
To end the power shutdown and begin powering up the  
internal circuitry, return the PD pin to a low level. If the  
internal reference is used, the 2.3kΩ output impedance  
with the 1μF bypass capacitor on the REFIN/REFOUT pins  
will be the main time constant for the power-on recovery  
time. If an external reference is used, typically allow 5ms  
for recovery before initiating a new conversion.  
Internal Conversion Clock  
Power ꢅissipation vs Sampling ꢃrequencꢄ  
The LTC2389-16 has an internal clock that is trimmed to  
achieveamaximumconversiontimeof310ns.Noexternal  
adjustments are required and with a minimum acquisition  
time of 77ns, a throughput performance of 2.5Msps is  
guaranteed in the parallel output modes.  
When nap mode is employed, the power dissipation of  
the LTC2389-16 will decrease as the sampling frequency  
is reduced, as shown in Figure 13. This decrease in  
average power dissipation occurs because a portion of  
the circuitry on the LTC2389-16 is turned off during nap  
35  
30  
25  
20  
15  
10  
5
I
VDD  
I
OVDD  
0
1
10  
100  
1000  
10000  
SAMPLING FREQUENCY (kHz)  
238916 F13  
ꢃigure ±3. Supplꢄ Current vs Sampling ꢃrequencꢄ. Power ꢅissipation  
of the LTC2340-±6 ꢅecreases with ꢅecreasing Sampling ꢃrequencꢄ  
238916f  
29  
LTC2389-16  
applications inFormation  
ꢅIGITAL INTERꢃACE  
4-Bit Parallel Bus Configuration  
To accommodate a variety of application-specific proces-  
sor and FPGA data bus widths, the LTC2389-16 output  
bus may be configured to operate in either 16-bit parallel,  
8-bit parallel or serial modes, as described in Table 1. The  
In applications such as 8-bit microcontroller based solu-  
tions where an 8-bit wide parallel data bus is available, the  
LTC2389-16iscapableofprovidingeachconversionresult  
R[15:0] in two 8-bit words on pins D[15:8]. To select this  
busconfiguration, pinMODE0shouldbedriventoMODE0  
= 0, as described in Table 1. In this configuration, address  
input pin A1 controls whether the upper byte R[15:8] or  
the lower byte R[7:0] of the conversion result is driven  
on D[15:8], as shown in Figure 17. Note that, as shown in  
Table 1, D[7:0] also functions as an 8-bit wide parallel bus  
withA1providingcontroloftheoppositepolarityasitdoes  
on D[15:8]. Use of D[7:0] as an 8-bit parallel bus should  
beavoidedinapplicationswhereitisimportanttomaintain  
compatibility with 18-bit versions of the LTC2389 family,  
as described in the Pin Compatibility with LTC2389-18  
section. The chip select pin, CS, enables the 8-bit paral-  
lel bus to be shared between multiple devices. See the  
16-BitParallelBusConfigurationsectionforfurtherdetails.  
flexible OV supply allows the LTC2389-16 to commu-  
DD  
nicate with any digital logic operating between 1.8V and  
5V, including 2.5V and 3.3V systems.  
±6-Bit Parallel Bus Configuration  
In applications such as FPGA and CPLD based solutions  
or 16-bit microcontroller based solutions where a full  
16-bit wide parallel data bus is available, the LTC2389-16  
is capable of providing each conversion result R[15:0]  
as one 16-bit word on pins D[15:0]. To select this bus  
configuration, pin MODE0 should be driven to MODE0  
= 0 and pin A1 should be driven to A1 = 0, as described  
in Table 1. If the application does not require the bus to  
be shared, drive the chip select pin CS = 0 to enable the  
LTC2389-16 to drive the bus continuously, as shown in  
Figure 14. In applications where the bus must be shared,  
drive CS = 1 when other devices are using the bus to Hi-Z  
the LTC2389-16 bus pins and drive CS = 0 to allow the  
LTC2389-16todrivethebus,asshowninFigures15and16.  
238916f  
30  
LTC2389-16  
applications inFormation  
MODE0 = 0, A1 = 0, MODE1 = A0 = 0  
t
CS = 0, MODE0 = 0, A1 = 0, MODE1 = A0 = 0  
CNVSTL  
CNVST, CS  
t
CNVST  
CNVSTL  
BUSY  
BUSY  
t
CONV  
t
CONV  
t
BUSYLH  
t
t
DDBUSYL  
BUSYLH  
DATA BUS  
D[15:0]  
Hi-Z  
Hi-Z  
DATA BUS  
D[15:0]  
CURRENT  
CONVERSION  
PREVIOUS CONVERSION  
PREVIOUS CONVERSION  
238916 F16  
238916 F14  
t
t
DIS  
EN  
Figure 14. Read the Parallel Data Continuously.  
The Data Bus Is Always Driven and Cannot Be Shared  
Figure 16. Read the Parallel Data During  
the Following Conversion  
MODE0 = 0, MODE1 = A0 = 0  
MODE0 = 0, A1 = 0, MODE1 = A0 = 0  
8-BIT INTERFACE  
CS  
CS  
A1  
BUSY  
Hi-Z  
Hi-Z  
238916 F17  
Hi-Z  
Hi-Z  
t
CURRENT  
CONVERSION  
DATA BUS  
D[15:0]  
D[15:8]  
HIGH 8 BITS  
LOW 8 BITS  
238916 F15  
t
EN  
t
DDA1  
t
DIS  
t
EN  
DIS  
Figure 15. Read the Parallel Data After the Conversion  
Figure 17. 8-Bit Parallel Interface Using A1 Pin  
238916f  
31  
LTC2389-16  
applications inFormation  
SCK STARTS LOW  
MODE0 = 1, A1 = X, MODE1 = A0 = 0  
t
DSCK  
CS  
BUSY  
t
SCK  
t
SCKL  
t
SCKH  
SCK  
1
2
3
4
15  
16  
17  
18  
t
t
DSDO, HSDO  
SDO  
(ADC 2)  
Hi-Z  
D15  
D14  
D13  
D1  
D0  
X15  
X14  
t
t
EN  
HSDI  
t
SSDI  
SDI  
(ADC 2)  
Hi-Z  
X15  
X14  
X13  
X1  
X0  
SCK STARTS HIGH  
MODE0 = 1, A1 = X, MODE1 = A0 = 0  
t
DSCK  
CS  
BUSY  
t
SCK  
t
SCKL  
t
SCKH  
SCK  
1
2
3
4
15  
16  
17  
18  
t
t
DSDO, HSDO  
SDO  
(ADC 2)  
Hi-Z  
D15  
D14  
D13  
D1  
D0  
X15  
X14  
t
t
EN  
HSDI  
t
SSDI  
SDI  
(ADC 2)  
Hi-Z  
X15  
X14  
X13  
X1  
X0  
CNVST IN  
CS IN  
SCK IN  
LTC2389-16  
LTC2389-16  
CNVST  
CS  
CNVST  
CS  
SCK  
SDI  
SCK  
SDI  
SDO  
SDO  
ADC 2  
DATA OUT  
ADC 1  
238916 F18  
Figure 18. Serial Interface with External Clock. Read After the Conversion. Daisy Chain Multiple Converters  
238916f  
32  
LTC2389-16  
applications inFormation  
Serial Bus Configuration  
SCK cycle delay. The serial output of ADC1 is clocked  
into ADC2 on the falling edges of SCK. This is useful in  
applications where hardware constraints limit the number  
ofdatalinesavailabletointerfacewithmultipleconverters.  
In applications where a serial bus is required to minimize  
the data bus width, the LTC2389-16 is capable of provid-  
ing each conversion result R[15:0] serially on pin D10/  
SDO. To select this bus configuration, pin MODE0 should  
be driven to MODE0 = 1, as described in Table 1. Address  
input pin A1 has no effect on the parsing or presentation  
of serial conversion data. As shown in Figure 18, the serial  
output data is presented on the SDO pin in response to an  
external shift clock input applied to the SCK pin. The data  
on SDO changes state following rising edges of SCK. The  
one exception to this behavior is that D15 remains valid  
untilthefirstSCKrisingedgefollowingthefirstSCKfalling  
edge. If CS is used to gate the serial output data, the full  
conversion result should be read before CS is returned to  
a high level. For best performance, do not clock serial data  
out when BUSY is high. The SDI input pin can be used to  
daisy chain multiple converters, as shown in Figure 18.  
In this figure, two devices are cascaded with the MSB of  
ADC1 appearing at the serial output of ADC2 after a 16  
Data Format  
The binary format of the conversion result depends on the  
state of pins PD/FD and OB/2C, as described in Table 2.  
These pins are active in both the parallel and serial modes  
of operation.  
Reset  
As shown in Figure 19, when the RESET pin is high, the  
LTC2389-16 is reset and the data bus is put into a high  
impedance mode. If this occurs during a conversion, the  
conversion is immediately halted. In reset, requests for  
new conversions are ignored. Once RESET returns low,  
the LTC2389-16 is ready to start a new conversion after  
the acquisition time has been met.  
t
RESETH  
RESET  
t
ACQ  
CVNST  
Hi-Z  
DATA BUS D[15:0]  
238916 F19  
Figure 19. RESET Pin Timing  
238916f  
33  
LTC2389-16  
applications inFormation  
BOARD LAYOUT  
and 8 (A1). Additionally, if the 8-bit parallel bus configur-  
ation is used, the upper byte Pins 28 through 21 (D[15:8])  
of the output data bus should be used to read the conver-  
sion results. Simplifications to these constraints are  
possible based on the specific application. For further  
details on the operation of the LTC2389-18, please refer  
to the associated data sheet.  
To obtain the best performance from the LTC2389-16, a  
printed circuit board (PCB) is recommended. Layout for  
the printed circuit board should ensure the digital and  
analog signal lines are separated as much as possible. In  
particular,careshouldbetakennottorunanydigitalclocks  
orsignalsalongsideanalogsignalsorunderneaththeADC.  
Recommended Layout  
Pin Compatibility with LTC2389-18  
ThefollowingisanexampleofarecommendedPCBlayout.  
A single solid ground plane is used. Bypass capacitors to  
the supplies are placed as close as possible to the supply  
pins. Low impedance common returns for these bypass  
capacitors are essential to the low noise operation of the  
ADC. The analog input traces are shielded by ground. For  
more details and information refer to DC1826A-E, the  
evaluation kit for the LTC2389-16.  
To ensure a board layout intended for use with the  
LTC2389-16 is also compatible with 18-bit versions of  
the LTC2389 family, the design should maintain the ability  
to drive Pins 4 (MODE0) and 5 (MODE1) to both logic high  
andlogiclowlevels, todynamicallydrivePins7(A0)and8  
(A1) to both logic high and logic low levels, and to read  
dynamic data driven by the LTC2389-18 on Pins 7 (A0)  
238916 F20  
Partial Top Silkscreen  
238916f  
34  
LTC2389-16  
applications inFormation  
238916 F21  
Partial Layer 1 Component Side  
238916 F22  
Partial Layer 2 Ground Plane  
238916f  
35  
LTC2389-16  
applications inFormation  
238916 F23  
Partial Layer 3 Power Plane  
238916 F24  
Partial Layer 4 Bottom Layer  
238916 F25  
Bottom Silk Partial  
238916f  
36  
LTC2389-16  
applications inFormation  
D F L D P /  
S L C  
3 0  
3 1  
3 3  
3 2  
T
O U E F R  
3 7  
3 8  
3 9  
N I E F R  
P D  
E S R E  
S E E N S E F R  
T
E 0 O D M  
E 1 O D M  
4
5
6
L C 2 O B /  
L T S C N V  
3 4  
M
V C  
3 6  
O N  
P R  
L R C  
7
8
6
4
C
V C  
D G N  
3
VDD  
VDD  
19  
17  
1
GND  
GND  
GND  
GND  
GND  
GND  
GND  
2
40  
45  
46  
47  
20  
35  
41  
44  
48  
VDD  
VDD  
VDD  
VDD  
VDD  
3
2
1
3
2
1
238916f  
37  
LTC2389-16  
package Description  
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.  
LX Package  
48-Lead Plastic LQFP (7mm × 7mm)  
(Reference LTC DWG # 05-08-1760 Rev Ø)  
7.15 – 7.25  
5.50 REF  
9.00 BSC  
7.00 BSC  
48  
48  
SEE NOTE: 4  
1
2
1
2
0.50 BSC  
9.00 BSC  
7.00 BSC  
5.50 REF  
7.15 – 7.25  
0.20 – 0.30  
A
A
PACKAGE OUTLINE  
C0.30 – 0.50  
1.30 MIN  
RECOMMENDED SOLDER PAD LAYOUT  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
1.60  
11° – 13°  
1.35 – 1.45 MAX  
R0.08 – 0.20  
GAUGE PLANE  
0.25  
0° – 7°  
11° – 13°  
1.00 REF  
0.50  
BSC  
0.09 – 0.20  
0.17 – 0.27  
0.05 – 0.15  
LX48 LQFP 0907 REVØ  
0.45 – 0.75  
SECTION A – A  
NOTE:  
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE  
2. DIMENSIONS ARE IN MILLIMETERS  
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER  
5. DRAWING IS NOT TO SCALE  
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT  
238916f  
38  
LTC2389-16  
package Description  
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.  
UK Package  
48-Lead Plastic QFN (7mm × 7mm)  
(Reference LTC DWG # 05-08-1704)  
0.70 ±0.05  
5.15 ± 0.05  
5.50 REF  
6.10 ±0.05 7.50 ±0.05  
(4 SIDES)  
5.15 ± 0.05  
PACKAGE OUTLINE  
0.25 ±0.05  
0.50 BSC  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
0.75 ± 0.05  
R = 0.115  
TYP  
7.00 ± 0.10  
(4 SIDES)  
R = 0.10  
TYP  
47 48  
0.40 ± 0.10  
PIN 1 TOP MARK  
(SEE NOTE 6)  
1
2
PIN 1  
CHAMFER  
C = 0.35  
5.15 ± 0.10  
5.50 REF  
(4-SIDES)  
5.15 ± 0.10  
(UK48) QFN 0406 REV C  
0.200 REF  
0.25 ± 0.05  
0.50 BSC  
BOTTOM VIEW—EXPOSED PAD  
0.00 – 0.05  
NOTE:  
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE  
238916f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
39  
LTC2389-16  
typical application  
ADC Driver: Single-Ended Input to Differential Output  
4.096V  
LOWPASS FILTERS  
4.096V  
1/2 LT6201  
0V  
10Ω  
49.9Ω  
+
–
0V  
330pF  
330pF  
+
–
1nF  
1nF  
IN  
LTC2389-16  
402Ω  
402Ω  
1/2 LT6201  
IN  
49.9Ω  
10Ω  
–
238916 TA02  
+
4.096V  
0V  
+
V
= 2.048V  
CM  
–
relateD parts  
PART NUMBER  
DESCRIPTION  
COMMENTS  
ADCs  
LTC2389-18  
18-Bit, 2.5Msps, All-In-One ADC  
5V Supply, Pin-Configurable Input, 99.8dB SNR, ±4.096V, 0V to  
4.096V, and ±2.048V Input Ranges, Internal 4.096V Reference, Internal  
Reference Buffer, 7mm × 7mm LQFP-48 and QFN-48 Packages  
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial,  
LTC2377-18/LTC2376-18 Low Power ADC  
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,  
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages  
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,  
LTC2377-16/LTC2376-16 Power ADC  
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages  
LTC2369-18/LTC2368-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial,  
LTC2367-18/LTC2364-18 Low Power ADC  
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 5V Input  
Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm  
DFN-16 Packages  
LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input  
LTC2367-16/LTC2364-16 Power ADC  
Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm  
DFN-16 Packages  
LTC2393-16/LTC2392-16/ 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range,  
LTC2391-16  
Pin-Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages  
LTC2383-16/LTC2382-16/ 16-Bit, 1Msps/500ksps/250ksps Serial, Low  
2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range,  
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages  
LTC2381-16  
Power ADC  
DACs  
LTC2756/LTC2757  
LTC2641  
18-Bit, Single Serial/Parallel I  
SoftSpan™ DAC  
±1LSB INL/DNL, SSOP-28/7mm × 7mm LQFP-48 Package  
±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output  
OUT  
16-Bit/14-Bit/12-Bit Single Serial V  
DACs  
OUT  
LTC2751  
16-Bit/14-Bit/12-Bit Single Parallel I  
SoftSpan DAC  
±1LSB INL/DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package  
OUT  
References  
LTC6655  
Precision Low Drift Low Noise Buffered Reference  
Precision Low Drift Low Noise Buffered Reference  
5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package  
5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package  
LTC6652  
Amplifiers  
LT6200/LT6201  
Single/Dual 165MHz Op Amp with Unity Gain Stability  
0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz, TSOT23-6 Package  
1.1nV/√Hz (100kHz), 3.5mA Maximum, 350μV Maximum Offset  
LT6230/LT6231/LT6232 Single/Dual/Quad 215MHz Rail-to-Rail Output Low  
Noise Low Power Amplifiers  
LT6202/LT6203  
Single/Dual 100MHz Rail-to-Rail Input/Output Low  
Noise Low Power Amplifiers  
1.9nV√Hz (100kHz), 3mA Maximum, 100MHz Gain Bandwidth  
LT6350  
Low Noise Single-Ended-to-Differential ADC Driver  
Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time  
LTC1992  
Low Power, Fully Differential Input/Output Amplifier/ 1mA Supply Current  
Driver Family  
238916f  
LT 0512 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
40  
●
●
LINEAR TECHNOLOGY CORPORATION 2012  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  

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