LTC2392CUK-16#PBF_技术文档

LTC2392-16

16-Bit, 500ksps SAR ADC

with 94dB SNR

Features

Description

The LTC^®2392-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2392-16 supports a large

±±.ꢀ96V fully differential input range, making it ideal for

high performance applications which require maximum

dynamic range. The LTC2392-16 achieves ±2LSB INL

max, no missing codes at 16-bits and 9±dB SNR (typ).

n

500ksps Throughput Rate

n

±±LSB INL (Max)

n

Guaranteed 16-Bit No Missing Codes

n

94dB SNR (Typ) at f = ±0kHz

IN

n

Guaranteed Operation to 125°C

Single 5V Supply

1.8V to 5V I/O Voltages

11ꢀmW Power Dissipation

The LTC2392-16 includes a precision internal reference

with a guaranteed ꢀ.5% initial accuracy and a ±2ꢀppm/°C

(max) temperature coefficient. Fast 5ꢀꢀksps throughput

with no cycle latency in both parallel and serial interface

modes makes the LTC2392-16 ideally suited for a wide

variety of high speed applications. An internal oscillator

sets the conversion time, easing external timing con-

siderations. The LTC2392-16 dissipates only 11ꢀmW at

5ꢀꢀksps,whilebothnapandsleeppower-downmodesare

provided to further reduce power during inactive periods.

±±.ꢀ96V Differential Input Range

Internal Reference (2ꢀppm/°C Max)

No Pipeline Delay, No Cycle Latency

Parallel and Serial Interface

Internal Conversion Clock

±8-Lead 7mm × 7mm LQFP and QFN Packages

applications

n

Medical Imaging

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

High Speed Data Acquisition

n

Digital Signal Processing

Industrial Process Control

Instrumentation

ATE

n

typical application

16k Point FFT f_S= 500ksps,

f_IN= ±0kHz

5V

0.1µF

5V

0.1µF

1.8V TO 5V

4.7µF

0

–20

SNR = 94dB

10µF

THD = –103dB

SINAD = 93.5dB

SFDR = 104dB

–40

ANALOG INPUT

0V TO 4.096V

AVP

DVP

OVP

PARALLEL

OR

SERIAL

INTERFACE

–60

249Ω

16 BIT

+

IN

–80

–100

–120

–140

–160

LT6350

2200pF

249Ω

LTC2392-16

SER/PAR

BYTESWAP

OB/2C

CS

–

IN

RD

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

BUSY

VCM REFIN REFOUT CNVST PD RESET GND OGND

10µF 1µF

239216 TA01

–180

0

100

150

200

250

50

SAMPLE CLOCK

FREQUENCY (kHz)

239216 G08

239216fa

1

LTC2392-16

absolute maximum ratings ^{(Notes 1, ±)}

Supply Voltage (V , V , V )..........................6.ꢀV

Operating Temperature Range

AVP DVP OVP

Analog Input Voltage (Note 3)

LTC2392C................................................ ꢀ°C to 7ꢀ°C

LTC2392I .............................................–±ꢀ°C to 85°C

LTC2392H.......................................... –±ꢀ°C to 125°C

Storage Temperature Range .................. –65°C to 15ꢀ°C

+

–

IN , IN , REFIN, CNVST... (GND – ꢀ.3V) to (V

+ ꢀ.3V)

AVP

OVP

Digital Input Voltage........(GND – ꢀ.3V) to (V

Digital Output Voltage.....(GND – ꢀ.3V) to (V

Power Dissipation.............................................. 5ꢀꢀmW

pin conFiguration

TOP VIEW

GND 1

AVP 2

DVP 3

36 VCM

35 GND

34 CNVST

33 PD

32 RESET

31 CS

GND

AVP

1

2

3

4

5

6

7

8

9

36 VCM

35 GND

34 CNVST

33 PD

32 RESET

31 CS

30 RD

29 BUSY

28 D15

27 D14

26 D13

25 D12

DVP

SER/PAR 4

GND 5

OB/2C 6

GND 7

BYTESWAP 8

D0 9

SER/PAR

GND

OB/2C

GND

BYTESWAP

D0

49

GND

30 RD

29 BUSY

28 D15

27 D14

26 D13

25 D12

D1 10

D2 11

D3 12

D1 10

D2 11

D3 12

UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

LX PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

T

= 125°C, θ = 29°C/W

JA

JMAX

EXPOSED PAD (PIN ±9) IS GND, MUST BE SOLDERED TO PCB

T

= 15ꢀ°C, θ = 55°C/W

JA

JMAX

orDer inFormation

LEAD FREE FINISH

LTC2392CUK-16#PBF

LTC2392IUK-16#PBF

LEAD FREE FINISH

LTC2392CLX-16#PBF

LTC2392ILX-16#PBF

LTC2392HLX-16#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

ꢀ°C to 7ꢀ°C

LTC2392CUK-16#TRPBF LTC2392UK-16

±8-Lead 7mm × 7mm Plastic QFN

PACKAGE DESCRIPTION

LTC2392IUK-16#TRPBF

TRAY

LTC2392UK-16

PART MARKING*

LTC2392LX-16

–±ꢀ°C to 85°C

TEMPERATURE RANGE

ꢀ°C to 7ꢀ°C

LTC2392CLX-16#PBF

LTC2392ILX-16#PBF

LTC2392HLX-16#PBF

±8-Lead 7mm × 7mm Plastic LQFP

–±ꢀ°C to 85°C

–±ꢀ°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

239216fa

2

LTC2392-16

analog input ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= ±5°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

–ꢀ.ꢀ5

TYP

MAX

AVP

UNITS

+

l

V

Absolute Input Range (IN )

(Note 5)

V

IN

–

+

–

Absolute Input Range (IN )

(Note 5)

–

+

–

– V

Input Differential Voltage Range

Common Mode Input Range

Analog Input Leakage Current

Analog Input Capacitance

V

= V – V

–V

V

REF

V

IN

REF

V

/2 – ꢀ.ꢀ5

REF

V

/2

REF

V

/2 + ꢀ.ꢀ5

±1

V

CM

REF

I

IN

µA

C

Sample Mode

Hold Mode

±5

5

pF

IN

CMRR

Input Common Mode Rejection Ratio

7ꢀ

dB

converter characteristics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= ±5°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

Transition Noise

16

Bits

ꢀ.3

±1

LSB

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

Bipolar Zero Error

Bipolar Zero Error Drift

Bipolar Full-Scale Error

(Note 6)

(Note 7)

–2

–1

–7

2

1

7

LSB

DNL

BZE

LSB

1

ppm/°C

l

FSE

External Reference

Internal Reference (Note 7)

ꢀ.13

ꢀ.1

%

Bipolar Full-Scale Error Drift

±1ꢀ

ppm/°C

Dynamic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= ±5°C. A_IN= –1dBFS (Notes 4, 8)

SYMBOL

SINAD

SNR

PARAMETER

CONDITIONS

MIN

91

TYP

93.5

9±

MAX

UNITS

dB

l

Signal-to-(Noise + Distortion) Ratio

Signal-to-Noise Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range

–3dB Input Bandwidth

Aperture Delay

f

= 2ꢀkHz

IN

= 2ꢀkHz

92

dB

THD

= 2ꢀkHz, First 5 Harmonics

= 2ꢀkHz

–1ꢀ3

1ꢀ±

5ꢀ

–95

dB

SFDR

dB

MHz

ns

ꢀ.5

7

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

6ꢀ

ns

239216fa

3

LTC2392-16

internal reFerence characteristics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= ±5°C. (Note 4)

PARAMETER

CONDITIONS

MIN

TYP

±.ꢀ96

±1ꢀ

2.6

MAX

±.116

±2ꢀ

UNITS

V

REF

V

REF

V

REF

Output Voltage

Output Tempco

Output Impedance

I

= ꢀ

±.ꢀ76

OUT

l

= ꢀ (I-, H-Grades) (Note 11)

ppm/°C

kΩ

–ꢀ.1mA ≤ I

≤ ꢀ.1mA

OUT

External Reference Voltage

REFIN Input Impedance

2.5

±.ꢀ96

85

AVP – ꢀ.5

V

kΩ

V

Line Regulation

AVP = ±.75V to 5.25V

= ꢀ

ꢀ.3

mV/V

V

REF

VCM Output Voltage

I

2.ꢀ8

OUT

Digital inputs anD Digital outputs ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= ±5°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OVP

IH

IL

ꢀ.5

1ꢀ

V

I

IN

V

= ꢀV to OVP

IN

–1ꢀ

OVP – ꢀ.2

–1ꢀ

µA

pF

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –5ꢀꢀµA

O

V

OH

OL

I = 5ꢀꢀµA

O

ꢀ.2

1ꢀ

V

I

V

= ꢀV to OVP

= ꢀV

µA

mA

OZ

OUT

–1ꢀ

1ꢀ

SOURCE

SINK

= OVP

power requirements ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= ±5°C. (Note 4)

SYMBOL

PARAMETER

Supply Voltage

CONDITIONS

MIN

±.75

1.71

TYP

MAX

5.25

UNITS

l

V

, V

5

V

AVP DVP

OVP

l

I

DD

Supply Current

Power Down Mode

5ꢀꢀksps Sample Rate with Nap Mode

Conversion Done and All Digital Inputs Tied to OVP

22

35

27

25ꢀ

mA

µA

P

D

Power Dissipation

Power Down Mode

5ꢀꢀksps Sample Rate with Nap Mode

Conversion Done and All Digital Inputs Tied to OVP

11ꢀ

175

135

125ꢀ

mW

µW

239216fa

4

LTC2392-16

timing characteristics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= ±5°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5ꢀꢀ

UNITS

ksps

ns

l

f

t

Sampling Frequency

Conversion Time

SMPL

13ꢀꢀ

685

CONV

Acquisition Time

ns

ACQ

±

CNVST Low Time

2ꢀ

ns

CNVST High Time

25ꢀ

ns

5

C = 15pF

L

15

ns

CNVST↓ to BUSY Delay

RESET Pulse Width

SCLK Period

6

5

12.5

±

ns

7

(Note 9)

ns

8

SCLK High Time

ns

9

SCLK Low Time

±

ns

1ꢀ

t , t

SCLK Rise and Fall Times

SDIN Setup Time

(Note 1ꢀ)

1

µs

r

f

l

t

2

1

2

ns

11

12

13

1±

15

16

17

18

SDIN Hold Time

ns

C = 15pF

L

8

ns

SDOUT Delay After SCLK↑

SDOUT Delay After CS↓

CS↓ to SCLK Setup Time

Data Valid to BUSY↓

Data Access Time after RD↓ or BYTESWAP↑

Bus Relinquish Time

ns

2ꢀ

1

ns

1ꢀ

ns

1ꢀ

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Bipolar zero error is the offset voltage measured from –ꢀ.5LSB

when the output code flickers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 1111

1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note ±: All voltage values are with respect to ground.

Note 8: All specifications in dB are referred to a full-scale ±±.ꢀ96V input

with a ±.ꢀ96V reference voltage.

Note 3: When these pin voltages are taken below ground or above

AVP, DVP or OVP, they will be clamped by internal diodes. This product

can handle input currents up to 1ꢀꢀmA below ground or above AVP, DVP

or OVP without latchup.

Note 9: t of 8ns maximum allows a shift clock frequency up to

13

2 • (t + t

) for falling edge capture with 5ꢀ% duty cycle and up to

SETUP

13

8ꢀMHz for rising capture. t

is the set-up time of the receiving logic.

SETUP

Note 4: AVP = DVP = OVP = 5V, f

= 5ꢀꢀksps, external reference equal

SMPL

to ±.ꢀ96V unless otherwise noted.

Note 10: Guaranteed by design.

Note 5: Recommended operating conditions.

Note 11: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

4V

t

WIDTH

0.5V

50%

t

DELAY

239216 F01

4V

0.5V

Figure 1. Voltage Levels for Timing Specifications

239216fa

5

LTC2392-16

typical perFormance characteristics ^T_A^{= ±5°C, f}_SMPL= 500ksps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

(External Reference)

2000000

1800000

1600000

1400000

1200000

1000000

800000

600000

400000

200000

0

1.5

1.0

2.0

1.5

1.0

0.5

0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

32764 32766 32768 32770 32772

0

16384

32768

49152

65536

32768

0

16384

49152

65536

CODE

OUTPUT CODE

239216 G03

239216 G02

239216 G01

DC Histogram

(Internal Reference)

Internal Reference Output

vs Temperature

Offset Error vs Temperature

2000000

1800000

1600000

1400000

1200000

1000000

800000

600000

400000

200000

0

4.0975

4.0970

4.0965

4.0960

4.0955

4.0950

4.0945

4.0940

4.0935

4.0930

4.0925

1.0

0.8

TC = 4ppm/°C

0.6

0.4

0.2

0

32764 32766 32768 32770 32772

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

CODE

TEMPERATURE (°C)

239216 G04

239216 G06

239216 G05

16k Point FFT f_S= 500ksps,

f_IN= ±0kHz

16k Point FFT f_S= 500ksps,

f_IN= 100kHz

Full-Scale Error vs Temperature

10

8

0

–20

0

–20

SNR = 94dB

THD = –103dB

SINAD = 93.5dB

SFDR = 104dB

THD = –97.3dB

SINAD = 92.3dB

SFDR = 101.7dB

6

–40

4

–60

2

–80

0

–100

–120

–140

–160

–100

–120

–140

–160

–2

–4

–6

–8

–10

–180

–55 –35 –15

5

25 45 65 85 105 125

0

100

150

200

250

50

0

100

150

200

250

50

TEMPERATURE (°C)

FREQUENCY (kHz)

239216 G07

239216 G08

239216 G09

239216fa

6

LTC2392-16

typical perFormance characteristics ^T_A^{= ±5°C, f}_SMPL= 500ksps, unless otherwise noted.

THD, Harmonics

vs Input Frequency

SNR, SINAD at f_IN= ±0kHz

vs Temperature

SNR, SINAD vs Input Frequency

96

94

92

90

88

86

84

82

80

–70

–75

96

95

94

93

92

SNR

–80

SINAD

–85

SNR

–90

–95

SINAD

THD

3RD

–100

–105

–110

–115

–120

2ND

100 125

0

25

50

75

150

175

200

85

105 125

100 125

–55 –35 –15

5

45

0

25 50 75

150 175 200

25

65

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

239216 G11

239216 G12

239216 G10

THD, Harmonics at f_IN= ±0kHz

vs Temperature

Supply Current vs Sampling

Frequency

SNR, SINAD vs Input Level

95.0

94.5

94.0

93.5

93.0

30

–95

–100

–105

–110

–115

–120

SNR

25

20

SINAD

THD

2ND

3RD

15

10

5

0

–55 –35 –15

5

25 45 65 85 105 125

–20

–10

–40

0

–30

0.1

1

10

100

1000

TEMPERATURE (°C)

SAMPLING FREQUENCY (kHz)

INPUT LEVEL (dB)

239216 G15

239216 G13

239216 G14

Power-Down Current

vs Temperature

Supply Current vs Temperature

25

20

15

10

5

90

80

70

60

50

40

30

20

10

0

AVP

DVP

OVP

AVP

OVP

0

–35

–15

5

25 45

65 85 105

125

–55 –35 –15

5

25 45 65 85 105 125

–55

TEMPERATURE (°C)

239216 G17

239216 G16

239216fa

7

LTC2392-16

pin Functions

GND (Pins 1, 5, 7, ±0, 35, 41, 44, 48, Exposed Pad Pin

49): Ground. All GND pins must be connected to a solid

ground plane. Exposed pad must be soldered directly to

the ground plane.

D6 (Pin 15): Data Bit 6. When SER/PAR = ꢀ this pin is

Bit 6 of the parallel port data output bus.

D7 (Pin 16): Data Bit 7. When SER/PAR = ꢀ this pin is

Bit 7 of the parallel port data output bus.

AVP (Pins ±, 40, 45, 46, 47): 5V Analog Power Supply.

The range of AVP is ±.75V to 5.25V. Bypass AVP to GND

with a good quality ꢀ.1µF and a 1ꢀµF ceramic capacitor

in parallel.

OGND (Pin 17): Digital Ground for the Input/Output

Interface.

OVP (Pin 18): Digital Power Supply for the Input/Output

Interface. The range for OVP is 1.8V to 5V. Bypass OVP

to OGND with a good quality ±.7µF ceramic capacitor

close to the pin.

DVP (Pins 3, 19): 5V Digital Power Supply. The range of

DVP is ±.75V to 5.25V. Bypass DVP to GND with a good

quality ꢀ.1µF and a 1ꢀµF ceramic capacitor in parallel.

D8 (Pin ±1): Data Bit 8. When SER/PAR = ꢀ this pin is

Bit 8 of the parallel port data output bus.

SER/PAR (Pin 4): Serial/Parallel Selection Input. This pin

controls the digital interface. A logic high on this pin se-

lects the serial interface and a logic low selects the parallel

interface. In the serial mode the non-active digital outputs

are high impedance.

D9/SDIN(Pin±±):DataBit9/SerialDataInput. WhenSER/

PAR = ꢀ this pin is Bit 9 of the parallel port data output bus.

When SER/PAR = 1, (serial mode) this is the serial data

input. SDIN can be used as a data input to daisy chain two

or more conversion results into a single SDOUT line. The

digital data level on SDIN is output on SDOUT with a delay

of 16 SCLK periods after the start of the read sequence.

OB/2C (Pin 6): Offset Binary/Two’s Complement Input.

When OB/2C is high, the digital output is offset binary.

When low, the MSB is inverted resulting in two’s comple-

ment output.

D10/SDOUT(Pin±3):DataBit1ꢀ/SerialDataOutput.When

SER/PAR = ꢀ this pin is Bit 1ꢀ of the parallel port data

output bus. When SER/PAR = 1, (serial mode) this is the

serial data output. The conversion result can be clocked

out serially on this pin synchronized to SCLK. The data

is clocked out MSB first on the rising edge of SCLK and

is valid on the falling edge of SCLK. The data format is

determined by the logic level of OB/2C.

BYTESWAP (Pin 8): BYTESWAP Input. With BYTESWAP

low, data will be output with Pin 28 (D15) being the MSB

and Pin 9 (Dꢀ) being the LSB. With BYTESWAP high, the

upper eight bits and the lower eight bits will be switched.

The MSB is output on Pin 16 and Bit 8 is output on Pin 9.

Bit 7 is output on Pin 28 and the LSB is output on Pin 21.

D0 (Pin 9): Data Bit ꢀ. When SER/PAR = ꢀ this pin is Bit ꢀ

of the parallel port data output bus.

D11/SCLK (Pin ±4): Data Bit 11/Serial Clock Input. When

SER/PAR = ꢀ this pin is Bit 11 of the parallel port data

output bus. When SER/PAR = 1, (serial mode) this is the

serial clock input.

D1 (Pin 10): Data Bit 1. When SER/PAR = ꢀ this pin is

Bit 1 of the parallel port data output bus.

D± (Pin 11): Data Bit 2. When SER/PAR = ꢀ this pin is

Bit 2 of the parallel port data output bus.

D1± (Pin ±5): Data Bit 12. When SER/PAR = ꢀ this pin is

Bit 12 of the parallel port data output bus.

D3 (Pin 1±): Data Bit 3. When SER/PAR = ꢀ this pin is

Bit 3 of the parallel port data output bus.

D13 (Pin ±6): Data Bit 13. When SER/PAR = ꢀ this pin is

Bit 13 of the parallel port data output bus.

D4 (Pin 13): Data Bit ±. When SER/PAR = ꢀ this pin is

Bit ± of the parallel port data output bus.

D14 (Pin ±7): Data Bit 1±. When SER/PAR = ꢀ this pin is

Bit 1± of the parallel port data output bus.

D5 (Pin 14): Data Bit 5. When SER/PAR = ꢀ this pin is

Bit 5 of the parallel port data output bus.

239216fa

8

LTC2392-16

pin Functions

D15 (Pin ±8): Data Bit 15. When SER/PAR = ꢀ this pin is

Bit 15 of the parallel port data output bus. The data format

is determined by the logic level of OB/2C.

VCM (Pin 36): Common Mode Analog Output. Typically

the output voltage is 2.ꢀ±8V. Bypass to GND with a 1ꢀµF

capacitor.

BUSY (Pin ±9): Busy Output. A low-to-high transition oc-

curs when a conversion is started. It stays high until the

conversion is complete. The falling edge of BUSY can be

used as the data-ready clock signal.

REFOUT (Pin 37): Internal Reference Output. Nominal

output voltage is ±.ꢀ96V. Connect this pin to REFIN if

using the internal reference. If an external reference is

used connect REFOUT to ground.

RD (Pin 30): Read Data Input. When CS and RD are both

REFIN (Pin 38): Reference Input. An external reference

can be applied to REFIN if a more accurate reference is

required. If an external reference is used tie REFOUT to

ground.

low, the parallel and serial output bus is enabled.

CS (Pin 31): Chip Select. When CS and RD are both low,

the parallel and serial output bus is enabled. CS is also

used to gate the external shift clock.

REFSENSE (Pin 39): Reference Input Sense. Leave

REFSENSE open when using the internal reference. If

an external reference is used connect REFSENSE to the

ground pin of the external reference.

RESET (Pin 3±): Reset Input. When high the LTC2392-16

is reset, and if this occurs during a conversion, the con-

version is halted and the data bus is put into Hi-Z mode.

–

+

IN , IN (Pin 4±, Pin 43): Differential Analog Inputs.

PD (Pin 33): Power-Down Input. When high, the

LTC2392-16ispowereddownandsubsequentconversion

requests are ignored. Before entering power shutdown,

the digital output data should be read.

–

IN – (IN ) can range up to ±V

.

REF

CNVST (Pin 34): Conversion Start Input. A falling edge

on CNVST puts the internal sample-and-hold into the hold

modeandstartsaconversion.CNVSTisindependentofCS.

239216fa

9

LTC2392-16

Functional block Diagram

AVP DVP OVP

LTC2392-16

16-BIT OR

TWO BYTE

SDIN

SDOUT

SCLK

+

IN

PARALLEL/

SERIAL

INTERFACE

16-BIT SAMPLING ADC

16-BIT

–

IN

CS

1x BUFFER

RD

REFIN

SER/PAR

BYTESWAP

OB/2C

REFOUT

VCM

4.096V

BUSY

CONTROL LOGIC

CNVST PD

REFERENCE

REFSENSE

RESET

GND OGND

239216BD

239216fa

10

LTC2392-16

timing Diagrams

Conversion Timing Using the Parallel Interface

CS, RD = 0

CNVST

ACQUIRE

BUSY

CONVERT

D[15:0]

PREVIOUS CONVERSION

CURRENT CONVERSION

239216 TD01

Conversion Timing Using the Serial Interface

CS, RD = 0

CNVST

ACQUIRE

BUSY

CONVERT

SCLK

D14 D12 D10 D8 D6 D4 D2 D0

D15 D13 D11 D9 D7 D5 D3 D1

SDOUT

239216 TD02

239216fa

11

LTC2392-16

applications inFormation

OVERVIEW

011...111

011...110

BIPOLAR

ZERO

The LTC2392-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2392-16 supports a

large ±±.ꢀ96V fully differential input range, making it ideal

for high performance applications which require a wide

dynamic range. The LTC2392-16 achieves ±2LSB INL

max, no missing codes at 16 bits and 9±dB SNR (typ).

000...001

000...000

111...111

111...110

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/65536

The LTC2392-16 includes a precision internal reference

with a guaranteed ꢀ.5% initial accuracy and a ±2ꢀppm/°C

(max) temperature coefficient. Fast 5ꢀꢀksps throughput

with no cycle latency in both parallel and serial interface

modes makes the LTC2392-16 ideally suited for a wide

varietyofhighspeedapplications.Aninternaloscillatorsets

theconversiontime,easingexternaltimingconsiderations.

TheLTC2392-16dissipatesonly11ꢀmWat5ꢀꢀksps,while

both nap and sleep power-down modes are provided to

further reduce power during inactive periods.

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

INPUT VOLTAGE (V)

239216 F02

Figure ±. LTC±39±-16 Two’s Complement Transfer Function

ANALOG INPUT

The analog inputs of the LTC2392-16 are fully differential

in order to maximize the signal swing that can be digitized.

Theanaloginputscanbemodeledbytheequivalentcircuit

showninFigure3.ThediodesattheinputprovideESDpro-

tection. The analog inputs should not exceed the supply or

gobelowground.Intheacquisitionphase,eachinputsees

approximately±ꢀpF(C )fromthesamplingCDACinseries

with 5ꢀΩ (R ) from the on-resistance of the sampling

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw only one small current spike

CONVERTER OPERATION

The LTC2392-16 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

IN

+

–

IN

converter (CDAC) is connected to the IN and IN pins

to sample the differential analog input voltage. A falling

edge on the CNVST pin initiates a conversion. During the

conversion phase, the 16-bit CDAC is sequenced through

asuccessiveapproximationalgorithm,effectivelycompar-

ing the sampled input with binary-weighted fractions of

while charging the C capacitors during acquisition.

During conversion, the analog inputs draw only a small

IN

leakage current.

thereferencevoltage(e.g., V /2, V /±…V /65536)

REF

usingthedifferentialcomparator.Attheendofconversion,

the CDAC output approximates the sampled analog input.

The ADC control logic then prepares the 16-bit digital

output code for parallel or serial transfer.

AVP

C

IN

R

IN

+

–

IN

BIAS

AVP

VOLTAGE

TRANSFER FUNCTION

C

239216 F03

The LTC2392-16 digitizes the full-scale voltage of 2 • V

REF

16

into2 levels,resultinginanLSBsizeof125µVwhenV

=±.ꢀ96V.Theidealtransferfunctionfortwo’scomplement

is shown in Figure 2. The OB/2C pin selects either offset

binary or two’s complement format.

Figure 3. The Equivalent Circuit for the

Differential Analog Input of the LTC±39±-16

239216fa

12

LTC2392-16

applications inFormation

INPUT DRIVE CIRCUITS

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

Alowimpedancesourcecandirectlydrivethehighimped-

ance inputs of the LTC2392-16 without gain error. A high

impedance source should be buffered to minimize settling

time during acquisition and to optimize the distortion

performance of the ADC.

Single-to-Differential Conversion

For single-ended input signals, a single-ended-to-differ-

ential conversion circuit must be used to produce a differ-

ential signal at the ADC inputs. The LT^®635ꢀ ADC driver is

recommendedforperformingasingle-ended-to-differential

conversion, as shown in Figure ±a. Its low noise and good

DC linearity allows the LTC2392-16 to meet full data sheet

specifications. An alternative solution using two op amps

is shown in Figure ±b. Using two LT18ꢀ6 op amps, the

circuit achieves 9±dB signal-to-noise ratio (SNR). For a

2ꢀkHz input signal, the input of the LTC2392-16 has been

bandwidth limited to about 25kHz.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2392-16. The amplifier

provides low output impedance to allow for fast settling

of the analog signal during the acquisition phase. It also

provides isolation between the signal source and the ADC

inputswhichdrawasmallcurrentspikeduringacquisition.

Input Filtering

The noise and distortion of the buffer amplifier and other

circuitry must be considered since they add to the ADC

noiseanddistortion.Noisyinputcircuitryshouldbefiltered

prior to the analog inputs to minimize noise. A simple

1-pole RC filter is sufficient for many applications.

ADC REFERENCE

A low noise, low temperature drift reference is critical to

achieving the full data sheet performance of the ADC. The

LTC2392-16 provides an excellent internal reference with

a ±2ꢀppm/°C (max) temperature coefficient. For better

accuracy, an external reference can be used.

Large filter RC time constants slow down the settling at

the analog inputs. It is important that the overall RC time

constants be short enough to allow the analog inputs to

completely settle to 16-bit resolution within the acquisi-

The high speed, low noise internal reference buffer is used

for both internal and external reference applications. It

cannot be bypassed.

tion time (t ).

ACQ

Highqualitycapacitorsandresistorsshouldbeusedinthe

RC filter since these components can add distortion. NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

ANALOG

INPUT

+

0V TO 4.096V

LT1806

–

249Ω

+

IN

301Ω

0.013µF

249Ω

LTC2392-16

+

IN

301Ω

249Ω

–

IN

ANALOG INPUT

0V TO 4.096V

2200pF

LT6350

LTC2392-16

239216 F04b

249Ω

–

+

IN

LT1806

239216 F04a

COMMON

MODE

VOLTAGE

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

Figure 4a. Recommended Single-Ended-to-Differential

Conversion Circuit Using the LT6350 ADC Driver

Figure 4b. Alternative Single-Ended-to-Differential

Conversion Circuit Using Two LT1806 Op Amps

239216fa

13

LTC2392-16

applications inFormation

Internal Reference

DYNAMIC PERFORMANCE

To use the internal reference, simply tie the REFOUT and

REFIN pins together. This connects the ±.ꢀ96V output of

the internal reference to the input of the internal reference

buffer. The output impedance of the internal reference

is approximately 2.6kΩ and the input impedance of the

internalreferencebufferisabout85kΩ.Itisrecommended

that this node be bypassed to ground with a 1µF or larger

capacitortofiltertheoutputnoiseoftheinternalreference.

The REFSENSE pin should be left floating when using the

internal reference.

Fast fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2392-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 5 shows that the LTC2392-16 achieves

a typical SINAD of 93.5dB at a 5ꢀꢀkHz sampling rate with

a 2ꢀkHz input.

External Reference

An external reference can be used with the LTC2392-16

when even higher performance is required. The

LT179ꢀ-±.ꢀ96 offers ꢀ.ꢀ5% (max) initial accuracy and

1ꢀppm/°C (max) temperature coefficient. When using an

external reference, connect the reference output to the

REFIN pin and connect the REFOUT pin to ground. The

REFSENSE pin should be connected to the ground of the

external reference.

0

–20

SNR = 94dB

THD = –103dB

SINAD = 93.5dB

SFDR = 104dB

–40

–60

–80

–100

–120

–140

–160

–180

0

100

150

200

250

50

FREQUENCY (kHz)

239216 G08

Figure 5. 16k Point FFT of the LTC±39±-16, f_S= 500ksps, f_IN= ±0kHz

239216fa

14

LTC2392-16

applications inFormation

Signal-to-Noise Ratio (SNR)

Power Supply Sequencing

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 5 shows

that the LTC2392-16 achieves a typical SNR of 9±dB at a

5ꢀꢀkHz sampling rate with a 2ꢀkHz input.

The LTC2392-16 does not have any specific power supply

sequencingrequirements.Careshouldbetakentoobserve

the maximum voltage relationships described in the Ab-

solute Maximum Ratings section. The LTC2392-16 has a

power-on-reset (POR) circuit. With the POR, the result of

the first conversion is valid after power has been applied

to the ADC. The LTC2392-16 will reset itself if the power

supply voltage drops below 2.5V. Once the supply voltage

is brought back to its nominal value, the POR will reinitial-

ize the ADC and it will be ready to start a new conversion.

Total Harmonic Distortion (THD)

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

Nap Mode

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

The LTC2392-16 can be put into the nap mode after a

conversion has been completed to reduce the power

consumption between conversions. In this mode some

of the circuitry on the device is turned off. Nap mode is

enabledbykeepingCNVSTlowbetweenconversions.When

the next conversion is requested, bring CNVST high and

hold for at least 25ꢀns, then start the next conversion by

bringing CNVST low. See Figure 6.

2

V₂+ V₃+ V₄...V_N

THD= 20log

V₁

where V is the RMS amplitude of the fundamental fre-

1

quencyandV throughV aretheamplitudesofthesecond

2

N

through Nth harmonics.

Power Shutdown Mode

POWER CONSIDERATIONS

When PD is tied high, the LTC2392-16 enters power

shutdown and subsequent requests for conversion are

ignored. Before entering power shutdown, the digital

output data needs to be read. However, if a request for

power shutdown (PD = high) occurs during a conversion,

the conversion will finish and then the device will power

The LTC2392-16 provides three sets of power supply

pins: the analog 5V power supply (AVP), the digital 5V

power supply (DVP) and the digital input/output interface

power supply (OVP). The flexible OVP supply allows the

LTC2392-16tocommunicatewithanydigitallogicoperat-

ingbetween1.8Vand5V,including2.5Vand3.3Vsystems.

t

5

CNVST

BUSY

NAP

t

ACQ

CONV

NAP MODE

239216 F06

Figure 6. Nap Mode Timing for the LTC±39±-16

239216fa

15

LTC2392-16

applications inFormation

down. The data from that conversion can be read after PD

= low is applied. In this mode power consumption drops

to a typical value of 175µW from 11ꢀmW. This mode can

be used if the LTC2392-16 is inactive for a long period of

timeandtheuserwantstominimizethepowerdissipation.

TIMING AND CONTROL

The LTC2392-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. CS and RD

control the digital interface on the LTC2392-16. When

either CS or RD is high, the digital outputs are high

impedance.

Recovery from Power Shutdown Mode

Once the PD pin is returned to a low level, ending the

power shutdown request, the internal circuitry will begin

to power up. If the internal reference is used, the 2.6kΩ

output impedance with the 1µF bypass capacitor on the

REFIN/REFOUT pins will be the main time constant for

the power-on recovery time. If an external reference is

used, typically allow 5ms for recovery before initiating a

new conversion.

CNVST Timing

The LTC2392-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. Once a

conversion has been initiated, it cannot be restarted until

the conversion is complete. For optimum performance

CNVSTshouldbeacleanlowjittersignal. Converterstatus

is indicated by the BUSY output which remains high while

the conversion is in progress. To ensure no errors occur

in the digitized results return the rising edge either within

±ꢀns from the start of the conversion or wait until after

the conversion has been completed. The CNVST timing

needed to take advantage of the reduced power mode of

operation is described in the Nap Mode section.

Power Dissipation vs Sampling Frequency

The power dissipation of the LTC2392-16 will decrease

as the sampling frequency is reduced when nap mode is

activated. See Figure 7. In nap mode, a portion of the cir-

cuitry on the LTC2392-16 is turned off after a conversion

has been completed. Increasing the time allowed between

conversions lowers the average power.

Internal Conversion Clock

The LTC2392-16 has an internal clock that is trimmed

to achieve a maximum conversion time of 13ꢀꢀns. No

external adjustments are required and with a maximum

acquisition time of 685ns, a throughput performance of

5ꢀꢀksps is guaranteed.

30

25

20

DIGITAL INTERFACE

15

10

The LTC2392-16 allows both parallel and serial digital

interfaces.TheflexibleOVPsupplyallowstheLTC2392-16

to communicate with any digital logic operating between

1.8V and 5V, including 2.5V and 3.3V systems.

5

0

0.1

1

10

100

1000

SAMPLING FREQUENCY (kHz)

239216 G15

Figure 7. Power Dissipation of the LTC±39±-16

Decreases with Decreasing Sampling Frequency

239216fa

16

LTC2392-16

applications inFormation

Parallel Modes

If CS and RD are used to gate the serial output data, the

full conversion result should be read before CS and RD

are returned to a high level.

The parallel output data interface is active when the

SER/PAR pinistiedlowandwhenbothCSandRDarelow.

The output data can be read as a 16-bit word as shown

in Figures 8, 9 and 1ꢀ or it can be read as two 8-bit bytes

by using the BYTESWAP pin. As shown in Figure 11, with

the BYTESWAP pin low, the first eight MSBs are output

on the D15 to D8 pins and the eight LSBs are output on

the D7 to DO pins. When BYTESWAP is taken high, the

eight LSBs now are output on the D15 to D8 pins and the

eight MSBs are output on the D7 to Dꢀ pins.

The SDIN input pin is used to daisychain multiple con-

verters. This is useful for applications where hardware

constraints may limit the number of lines needed to

interface to a large number of converters. For example,

if two devices are cascaded, the MSB of the first device

will appear at the output after 17 SCLK cycles. The first

MSB is clocked in on the falling edge of the first SCLK.

See Figure 12.

Serial Modes

Data Format

The serial output data interface is active when the

SER/PAR pin is tied high and when both CS and RD are

low. The serial output data will be clocked out on the

SDOUT pin when an external clock is applied to the SCLK

pin. Clocking out the data after the conversion will yield

the best performance. With a shift clock frequency of at

least25MHz, a5ꢀꢀkspsthroughputisachieved. Theserial

output data changes state on the rising edge of SCLK and

can be captured on the falling edge of SCLK. D15 remains

valid till the first rising edge of shift clock after the first

falling edge of shift clock. The non-active digital outputs

are high impedance when operating in the serial mode.

When OB/2C is high, the digital output is offset binary.

When low, the MSB is inverted resulting in two’s comple-

ment output. This pin is active in both the parallel and

serial modes of operation.

Reset

When the RESET pin is high, the LTC2392-16 is reset, and

ifthisoccursduringaconversion, theconversionishalted

and the data bus is put into Hi-Z mode. In reset, requests

fornewconversionsareignored.OnceRESETreturnslow,

the LTC2392-16 is ready to start a new conversion after

the acquisition time plus 1µs has been met. See Figure 13.

CS = RD = 0

t

4

CNVST

BUSY

t

CONV

t

16

6

PREVIOUS CONVERSION

NEW

DATA BUS D[15:0]

239216 F08

Figure 8. Read the Parallel Data Continuously.

The Data Bus is Always Driven and Can’t Be Shared

239216fa

17

LTC2392-16

applications inFormation

CS

RD

BUSY

Hi-Z

CURRENT

CONVERSION

DATA BUS D[15:0]

239216 F09

t

18

17

Figure 9. Read the Parallel Data After the Conversion

CS = 0

t

4

CNVST, RD

BUSY

t

CONV

t

6

Hi-Z

DATA BUS D[15:0]

239216 F09

t

17

t

18

Figure 10. Read the Parallel Data During the Conversion

8-BIT INTERFACE

CS, RD

BYTESWAP

D[15:8]

Hi-Z

HIGH BYTE

LOW BYTE

239216 F11

t

17

t

17

t

18

Figure 11. 8-Bit Parallel Interface Using the BYTESWAP Pin

239216fa

18

LTC2392-16

applications inFormation

SCLK STARTS LOW

RD = 0

t

15

CS

BUSY

t

8

t

10

t

9

SCLK

1

2

3

4

15

16

17

18

t

13

Hi-Z

SDOUT

(ADC 2)

D15

D14

D13

D1

D0

D15

D14

1

2

1

t

12

14

t

11

SDIN

(ADC 2)

D15

D14

D13

D1

D0

1

RD = 0

SCLK STARTS HIGH

CS

BUSY

t

8

t

10

t

9

SCLK

1

2

3

4

15

16

17

18

t

13

Hi-Z

SDOUT

(ADC 2)

D15

D14

D13

D1

D0

D15

D14

1

2

1

t

12

14

t

11

SDIN

(ADC 2)

D15

D14

D13

D1

D0

1

CNVST IN

CS IN

RD IN

SCLK IN

LTC2392-16

CNVST

CS

RD

SCLK

SDIN SDOUT

RD

SCLK

SDIN SDOUT

DATA OUT

239216 F12

ADC 1

ADC 2

Figure 1±. Serial Interface with External Clock. Read After

the Conversion. Daisy Chain Multiple Converters

239216fa

19

LTC2392-16

applications inFormation

t

7

RESET

t

+ 1µs

ACQ

CVNST

Hi-Z

DATA BUS D[15:0]

239216 F13

Figure 13. RESET Pin Timing

239216fa

20

LTC2392-16

applications inFormation

BOARD LAYOUT

Recommended Layout

To obtain the best performance from the LTC2392-16, a

printed circuit board (PCB) is recommended. Layout for

the printed circuit board should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals alongside analog signals or underneath

the ADC.

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC15ꢀꢀA, the

evaluation kit for the LTC2392-16.

Partial Schematic of Demo board

C36

1µF

CNVST

34

39

38

37

CNVST

REFSENSE

REFIN

REFOUT

R2

249Ω

1%

29

28

27

26

25

24

23

22

21

16

15

14

13

12

11

10

9

BUSY

D15

D14

D13

D12

BUSY

D15

43

D14

+

IN

D13

D12

C54

OPT

D11/SCLK

D10/SDOUT

D9/SDIN

D8

D10/SDOUT

D9/SDIN

D8

C2

D7

LTC2392-16

2200pF

1206 NPO

D6

D5

D4

R3

249Ω

1%

D3

D2

D1

D2

D1

44

–

IN

D0

8

C55

OPT

BYTESWAP

GND

7

VCM OB/2C GND SER/PAR RESET PD CS RD

36

6

5

4

32 33

31 30

C53

10µF

C31

0.1µF

C30

10µF

C29

0.1µF

C28

10µF

R24

1.0Ω

3.3V

5V

C40

4.7µF

47

46 45 40

2

19

3

18

AVP/AVL AVP AVP AVP AVP

DVP DVP/DVL OVP

LTC2392-16

GND GND GND GND GND GND OGND

48 44 41 35 20 17

239216 TA01

1

239216fa

21

LTC2392-16

applications inFormation

Partial Top Silkscreen

Partial Layer 1 Component Side

Partial Layer ± Ground Plane

239216fa

22

LTC2392-16

package Description

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # ꢀ5-ꢀ8-17ꢀ± Rev C)

0.70 0.05

5.ꢀ5 0.05

5.50 REF

6.ꢀ0 0.05 7.50 0.05

(4 SIDES)

5.ꢀ5 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

7.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

47 48

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ

CHAMFER

C = 0.35

5.ꢀ5 0.ꢀ0

5.50 REF

(4-SIDES)

5.ꢀ5 0.ꢀ0

(UK48) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

239216fa

23

LTC2392-16

package Description

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LX Package

48-Lead Plastic LQFP (7mm × 7mm)

(Reference LTC DWG # ꢀ5-ꢀ8-176ꢀ Rev Ø)

7.15 – 7.25

5.50 REF

9.00 BSC

7.00 BSC

48

SEE NOTE: 4

1

2

1

2

0.50 BSC

9.00 BSC

7.00 BSC

5.50 REF

7.15 – 7.25

0.20 – 0.30

A

PACKAGE OUTLINE

C0.30 – 0.50

1.30 MIN

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.60

11° – 13°

1.35 – 1.45 MAX

R0.08 – 0.20

GAUGE PLANE

0.25

0° – 7°

11° – 13°

1.00 REF

0.50

BSC

0.09 – 0.20

0.17 – 0.27

0.05 – 0.15

LX48 LQFP 0907 REVØ

0.45 – 0.75

SECTION A – A

NOTE:

1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE

2. DIMENSIONS ARE IN MILLIMETERS

4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

5. DRAWING IS NOT TO SCALE

3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

239216fa

24

LTC2392-16

revision history

REV

DATE

DESCRIPTION

PAGE NUMBER

A

ꢀ7/12 Increased T

to 15ꢀ°C on LQFP package.

2

17

JMAX

Added condition for reading conversion result under Serial Modes.

Added “plus 1µs” to acquisition time in Reset section and Figure 13.

Updated data bit numbering on Figure 12.

17, 2ꢀ

19

239216fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

LTC2392-16

typical application

ADC Driver: Single-Ended Input to Differential Output

5V

249Ω

0.1µF

V

IN

+

5V

+

^{0V to 4V}–

IN1

+

–

SHDN

V

OUT2

–

A

IN

2200pF

LTC2392-16

+

–

+

LT6350

A

IN

–

+

–

V

OUT1

249Ω

IN2

IN1

239216 TA03

0.1µF

–5V

0.1µF

499Ω

2V

relateD parts

PART NUMBER

DESCRIPTION

COMMENTS

LTC1±11

1±-Bit 2.5Msps Parallel ADC

5V Supply, 1-Channel, 8ꢀdB SNR, ±1.8V, ±1.27V, ±ꢀ.9V, ±ꢀ.6±V

Input Ranges, SSOP-36 Package

LTC16ꢀ9

16-Bit 2ꢀꢀksps Serial ADC

5V Supply, 1-Channel, 87dB SNR, Resistor-Selectable Inputs:

±1ꢀV, ±5V, ±3.3V, ꢀV to ±V, ꢀV to 5V, ꢀV to 1ꢀV

LTC186±

LTC186±L

LTC1865

LTC1865L

LTC1867

16-Bit 25ꢀksps Serial ADC

16-Bit 15ꢀksps Serial ADC

16-Bit 25ꢀksps Serial ADC

16-Bit 15ꢀksps Serial ADC

5V Supply, 1-Channel, ±.3mW, MSOP-8 Package

3V Supply, 1-Channel, 1.3mW, MSOP-8 Package

5V Supply, 2-Channel, ±.3mW, MSOP-8 Package

3V Supply, 2-Channel, 1.3mW, MSOP-8 Package

16-Bit, 2ꢀꢀksps 8-Channel ADC

5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible with

LTC1863, LTC1867L

LTC2355-1±/LTC2356-1±

LTC2391-16

1±-Bit, 3.5Msps Serial ADCs

3.3V Supply, 1-Channel, 18mW, MSOP-1ꢀ Package

16-Bit, 25ꢀksps Parallel/Serial ADC

16-Bit, 1Msps Parallel/Serial ADC

5V Supply, Differential Input, 9±dB SNR, ±±.ꢀ96V Input Range,

Pin Compatible with the LTC2393-16, LTC2392-16

LTC2393-16

5V Supply, Differential Input, 9±dB SNR, ±±.ꢀ96V Input Range,

Pin Compatible with the LTC2392-16, LTC2391-16

DACs

LTC26±1

LTC263ꢀ

References

LT1236

16-Bit Single Serial V

DACs

±1LSB INL, ±1LSB DNL, MSOP-8 Package, ꢀV to 5V Output

SC7ꢀ 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)

OUT

12-/1ꢀ-/8-Bit Single V

OUT

Precision Reference in SO-8 Package

ꢀ.25ppm Noise, Low Drift Precision Reference

5V, 1ꢀV; ꢀ.ꢀ5% Initial Accuracy (Max); 5ppm Tempco (Max)

ꢀ.ꢀ25% Initial Accuracy (Max), 2ppm Tempco (Max),

LTC6655

P-P

ꢀ.25ppm Noise (ꢀ.1Hz to 1ꢀHz) in MSOP-8 Package

P-P

Amplifiers

LT1±69

125µV (Max) Input Offset Voltage, Low Distortion: –96.5dB at

Dual 9ꢀMHz, 22V/µs Dual Op Amps in ±mm × ±mm

DFN-12 Package

1ꢀꢀkHz, 1ꢀV , Settling Time: 9ꢀꢀns

P-P

LT18ꢀ6/LT18ꢀ7

325MHz, Single/Dual Precision Op Amps in TSOT23-6,

MSOP-8 Packages

Rail-to-Rail Input and Output, Low Distortion, –8ꢀdBc at 5MHz,

Low Voltage Noise: 3.5nV/√Hz

LTC62ꢀꢀ/LTC62ꢀꢀ-5/

LTC62ꢀꢀ-1ꢀ

165MHz/8ꢀꢀMHz/1.6GHz Op Amps with

Unity Gain/AV = 5/AV = 1ꢀ

Low Noise Voltage: ꢀ.95nV/√Hz (1ꢀꢀkHz), Low Distortion:

–8ꢀdB at 1MHz, TSOT23-6 Package

LT635ꢀ

Low Noise Single-Ended-to-Differential ADC Driver

Rail-to-Rail Input and Outputs, 2±ꢀns ꢀ.ꢀ1% Settling Time

239216fa

LT 0712 REV A • PRINTED IN USA

LinearTechnology Corporation

163ꢀ McCarthy Blvd., Milpitas, CA 95ꢀ35-7±17

26

●

 LINEAR TECHNOLOGY CORPORATION 2010

(±ꢀ8) ±32-19ꢀꢀ FAX: (±ꢀ8) ±3±-ꢀ5ꢀ7 www.linear.com


型号：	LTC2392CUK-16#PBF
厂家：	Linear
描述：	LTC2392-16 - 16-Bit, 500ksps SAR ADC with 94dB SNR; Package: QFN; Pins: 48; Temperature Range: 0°C to 70°C 转换器
文件：	总26页 (文件大小：306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2392CUK-16#PBF [Linear]

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