LTC2393IUK-16#TRPBF_技术文档

LTC2393-16

16-Bit, 1Msps SAR ADC

With 94dB SNR

FEATURES

DESCRIPTION

The LTC^®2393-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2393-16 supports a large

±±.ꢀ96V fully differential input range, maꢁing it ideal for

high performance applications which require maximum

dynamic range. The LTC2393-16 achieves ±2LSꢂ ꢃIL

max, no missing codes at 16-bits and 9±.2dꢂ SIR (typ).

n

1Msps Throughput Rate

n

±±2LS ꢀI2 ꢁMaꢂx

n

Guaranteed 16-Sit Io Missing Codes

n

94.±dS LIR ꢁTypx at f = ±0kHz

ꢀI

n

Guaranteed Operation to 125/C

n

Single 5V Supply

n

1.8V to 5V ꢃꢄO Voltages

n

1±ꢀmW Power Dissipation

The LTC2393-16 includes a precision internal reference

with a guaranteed ꢀ.5% initial accuracy and a ±2ꢀppmꢄ/C

(max)temperaturecoefficient.Fast1Mspsthroughputwith

nocyclelatencyinbothparallelandserialinterfacemodes

maꢁes the LTC2393-16 ideally suited for a wide variety

of high speed applications. An internal oscillator sets the

conversion time, easing external timing considerations.

The LTC2393-16 dissipates only 1±ꢀmW at 1Msps, while

both nap and sleep power-down modes are provided to

further reduce power during inactive periods.

n

±±.ꢀ96V Differential ꢃnput Range

n

ꢃnternal Reference (2ꢀppmꢄ/C Max)

n

Io Pipeline Delay, Io Cycle Latency

n

Parallel and Serial ꢃnterface

ꢃnternal Conversion Clocꢁ

n

±8-Lead 7mm × 7mm LQFP and QFI Pacꢁages

APPLICATIONS

n

Medical ꢃmaging

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarꢁs of Linear

Technology Corporation. All other trademarꢁs are the property of their respective owners.

n

High Speed Data Acquisition

n

Digital Signal Processing

ꢃndustrial Process Control

ꢃnstrumentation

ATE

n

TYPICAL APPLICATION

16k Point FFT f_L= 1Msps,

5V

ꢀ.1μF

1.8V TO 5V

±.7μF

f_ꢀI= ±0kHz

1ꢀμF

ꢀ.1μF

1ꢀμF

ꢀ

–2ꢀ

SIR = 9±.2dꢂ

THD ꢀ –1ꢀ5dꢂ

SꢃIAD = 93.9dꢂ

SFDR = 1ꢀ8dꢂ

AIALOG ꢃIPUT

ꢀV TO ±.ꢀ96V

AVP

DVP

OVP

PARALLEL

OR

SERꢃAL

ꢃITERFACE

–±ꢀ

2±9Ω

16 ꢂꢃT

+

ꢃI

–6ꢀ

–8ꢀ

LT635ꢀ

22ꢀꢀpF

2±9Ω

LTC2393-16

SERꢄPAR

ꢂYTESWAP

Oꢂꢄ2C

CS

–1ꢀꢀ

–12ꢀ

–1±ꢀ

–16ꢀ

–

ꢃI

RD

SꢃIGLE-EIDED-

TO-DꢃFFEREITꢃAL

DRꢃVER

ꢂUSY

VCM REFꢃI REFOUT CNVST PD RESET GID OGID

1ꢀμF 1μF

239316 TAꢀ1

SAMPLE CLOCK

–18ꢀ

ꢀ

±ꢀꢀ

5ꢀꢀ

1ꢀꢀ

2ꢀꢀ

3ꢀꢀ

FREQUEICY (ꢁHz)

239316 Gꢀ8

239316fa

1

LTC2393-16

ABSOLUTE MAXIMUM RATINGS ^{ꢁIotes 1, ±x}

Supply Voltage (V , V , V )..........................6.ꢀV

Operating Temperature Range

AVP DVP OVP

Analog ꢃnput Voltage (Iote 3)

LTC2393C ................................................ ꢀ/C to 7ꢀ/C

LTC2393ꢃ.............................................. –±ꢀ/C to 85/C

LTC2393H .......................................... –±ꢀ/C to 125/C

Storage Temperature Range................... –65/C to 15ꢀ/C

+

–

ꢃI , ꢃI , REFꢃI, CNVST .. (GID – ꢀ.3V) to (V

+ ꢀ.3V)

AVP

OVP

Digital ꢃnput Voltage........(GID – ꢀ.3V) to (V

Digital Output Voltage .....(GID – ꢀ.3V) to (V

Power Dissipation...............................................5ꢀꢀmW

PIN CONFIGURATION

TOP VꢃEW

GID 1

AVP 2

DVP 3

36 VCM

35 GID

3± CNVST

33 PD

32 RESET

31 CS

GID

AVP

1

2

3

±

5

6

7

8

9

36 VCM

35 GID

3± CNVST

33 PD

32 RESET

31 CS

3ꢀ RD

29 ꢂUSY

28 D15

27 D1±

26 D13

25 D12

DVP

SERꢄPAR ±

GID 5

Oꢂꢄ2C 6

GID 7

ꢂYTESWAP 8

Dꢀ 9

SERꢄPAR

GID

Oꢂꢄ2C

GID

ꢂYTESWAP

Dꢀ

±9

GID

3ꢀ RD

29 ꢂUSY

28 D15

27 D1±

26 D13

25 D12

D1 1ꢀ

D2 11

D3 12

D1 1ꢀ

D2 11

D3 12

UK PACKAGE

±8-LEAD (7mm s 7mm) PLASTꢃC QFI

LX PACKAGE

T

= 125/C, θ = 29/CꢄW

JA

±8-LEAD (7mm s 7mm) PLASTꢃC LQFP

JMAX

EXPOSED PAD (PꢃI ±9) ꢃS GID, MUST ꢂE SOLDERED TO PCꢂ

T

= 15ꢀ/C, θ = 55/CꢄW

JA

JMAX

ORDER INFORMATION

2EAD FREE FꢀIꢀLH

LTC2393CUK-16#PꢂF

LTC2393ꢃUK-16#PꢂF

2EAD FREE FꢀIꢀLH

LTC2393CLX-16#PꢂF

LTC2393ꢃLX-16#PꢂF

LTC2393HLX-16#PꢂF

TAPE AID REE2

PART MARKꢀIG*

PACKAGE DELCRꢀPTꢀOI

TEMPERATURE RAIGE

ꢀ/C to 7ꢀ/C

LTC2393CUK-16#TRPꢂF LTC2393UK-16

±8-Lead 7mm × 7mm Plastic QFI

PACKAGE DELCRꢀPTꢀOI

LTC2393ꢃUK-16#TRPꢂF

TRAY

LTC2393UK-16

PART MARKꢀIG*

LTC2393LX-16

–±ꢀ/C to 85/C

TEMPERATURE RAIGE

ꢀ/C to 7ꢀ/C

LTC2393CLX-16#PꢂF

LTC2393ꢃLX-16#PꢂF

LTC2393HLX-16#PꢂF

±8-Lead 7mm × 7mm Plastic LQFP

–±ꢀ/C to 85/C

–±ꢀ/C to 125/C

Consult LTC Marꢁeting for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marꢁeting for information on non-standard lead based finish parts.

For more information on lead free part marꢁing, go to: http:ꢄꢄwww.linear.comꢄleadfreeꢄ

For more information on tape and reel specifications, go to: http:ꢄꢄwww.linear.comꢄtapeandreelꢄ

239316fa

2

LTC2393-16

ANALOG INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= ±5°C. ꢁIote 4x

LYMSO2

PARAMETER

COIDꢀTꢀOIL

MꢀI

–ꢀ.ꢀ5

TYP

MAX

AVP

UIꢀTL

+

l

V

Absolute ꢃnput Range (ꢃI )

(Iote 5)

V

ꢃI

–

+

–

Absolute ꢃnput Range (ꢃI )

(Iote 5)

–

+

–

– V

ꢃnput Differential Voltage Range

Common Mode ꢃnput Range

Analog ꢃnput Leaꢁage Current

Analog ꢃnput Capacitance

V

ꢃI

= V – V

–V

V

REF

V

ꢃI

REF

V

ꢄ2 – ꢀ.ꢀ5

REF

V

ꢄ2

REF

V

ꢄ2 + ꢀ.ꢀ5

±1

V

CM

REF

ꢃ

μA

ꢃI

C

Sample Mode

Hold Mode

±5

5

pF

ꢃI

CMRR

ꢃnput Common Mode Rejection Ratio

7ꢀ

dꢂ

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= ±5°C. ꢁIote 4x

LYMSO2

PARAMETER

COIDꢀTꢀOIL

MꢀI

16

TYP

MAX

UIꢀTL

ꢂits

l

Resolution

Io Missing Codes

Transition Ioise

16

ꢂits

ꢀ.3

±1

LSꢂ

RMS

l

ꢃIL

ꢃntegral Linearity Error

Differential Linearity Error

ꢂipolar Zero Error

ꢂipolar Zero Error Drift

ꢂipolar Full-Scale Error

(Iote 6)

(Iote 7)

–2

–1

–7

2

1

7

LSꢂ

DIL

ꢂZE

LSꢂ

1

ppmꢄ/C

l

FSE

External Reference

ꢃnternal Reference (Iote 7)

ꢀ.1

%

ꢂipolar Full-Scale Error Drift

±1ꢀ

ppmꢄ/C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= ±5°C. A_ꢀI= –1dSFL ꢁIotes 4, 8x

LYMSO2

SꢃIAD

SIR

PARAMETER

COIDꢀTꢀOIL

MꢀI

92

TYP

93.9

9±.2

MAX

UIꢀTL

dꢂ

l

Signal-to-(Ioise + Distortion) Ratio

Signal-to-Ioise Ratio

f

ꢃI

f

ꢃI

= 2ꢀꢁHz

92.5

dꢂ

THD

Total Harmonic Distortion

f

ꢃI

f

ꢃI

= 2ꢀꢁHz, First 5 Harmonics (C- and ꢃ-Grades)

= 2ꢀꢁHz, First 5 Harmonics (H-Grade)

–1ꢀ5

–1ꢀꢀ

–98

dꢂ

SFDR

Spurious-Free Dynamic Range

–3dꢂ ꢃnput ꢂandwidth

Aperture Delay

f

ꢃI

= 2ꢀꢁHz

1ꢀ8

5ꢀ

ꢀ.5

7

dꢂ

MHz

ns

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

6ꢀ

ns

239316fa

3

LTC2393-16

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= ±5°C. ꢁIote 4x

PARAMETER

COIDꢀTꢀOIL

MꢀI

TYP

±.ꢀ96

±1ꢀ

2.6

MAX

±.116

±2ꢀ

UIꢀTL

V

REF

V

REF

V

REF

Output Voltage

Output Tempco

Output ꢃmpedance

ꢃ

= ꢀ

±.ꢀ76

OUT

l

= ꢀ (ꢃ- and H-Grades) (Iote 11)

ppmꢄ/C

ꢁΩ

–ꢀ.1mA ≤ ꢃ

≤ ꢀ.1mA

OUT

External Reference Voltage

REFꢃI ꢃnput ꢃmpedance

2.5

±.ꢀ96

85

AVP – ꢀ.5

V

ꢁΩ

V

Line Regulation

AVP = ±.75V to 5.25V

= ꢀ

ꢀ.3

mVꢄV

V

REF

VCM Output Voltage

ꢃ

2.ꢀ8

OUT

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= ±5°C. ꢁIote 4x

LYMSO2

PARAMETER

COIDꢀTꢀOIL

MꢀI

TYP

MAX

UIꢀTL

V

l

V

ꢃH

V

ꢃL

High Level ꢃnput Voltage

Low Level ꢃnput Voltage

Digital ꢃnput Current

ꢀ.8 • OVP

ꢀ.5

1ꢀ

V

ꢃ

V

= ꢀV to OVP

ꢃI

–1ꢀ

OVP – ꢀ.2

–1ꢀ

μA

pF

ꢃI

C

V

Digital ꢃnput Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leaꢁage Current

Output Source Current

Output Sinꢁ Current

5

ꢃI

l

ꢃ = –5ꢀꢀμA

O

V

OH

OL

ꢃ = 5ꢀꢀμA

O

ꢀ.2

1ꢀ

V

ꢃ

V

OUT

V

OUT

V

OUT

= ꢀV to OVP

= ꢀV

μA

mA

OZ

–1ꢀ

1ꢀ

SOURCE

SꢃIK

= OVP

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= ±5°C. ꢁIote 4x

LYMSO2

PARAMETER

Supply Voltage

COIDꢀTꢀOIL

MꢀI

±.75

1.71

TYP

MAX

5.25

UIꢀTL

l

V

, V

5

V

AVP DVP

OVP

l

ꢃ

DD

Supply Current

Power Down Mode

1Msps Sample Rate with Iap Mode

Conversion Done and All Digital ꢃnputs Tied to OVP

28

35

25ꢀ

mA

μA

P

Power Dissipation

Power Down Mode

1Msps Sample Rate with Iap Mode

Conversion Done and All Digital ꢃnputs Tied to OVP

1±ꢀ

175

125ꢀ

mW

μW

D

239316fa

4

LTC2393-16

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= ±5°C. ꢁIote 4x

LYMSO2

PARAMETER

COIDꢀTꢀOIL

MꢀI

TYP

MAX

1

UIꢀTL

Msps

ns

l

f

t

Sampling Frequency

Conversion Time

SMPL

6ꢀꢀ

385

COIV

Acquisition Time

ns

ACQ

±

CNVST Low Time

2ꢀ

ns

CNVST High Time

25ꢀ

ns

5

CNVST↓ to ꢂUSY Delay

RESET Pulse Width

SCLK Period

C = 15pF

L

15

1

ns

6

5

12.5

±

ns

7

(Iote 9)

ns

8

SCLK High Time

ns

9

SCLK Low Time

±

ns

1ꢀ

t , t

SCLK Rise and Fall Times

SDꢃI Setup Time

(Iote 1ꢀ)

μs

r

f

l

t

11

t

12

t

13

t

1±

t

15

t

16

t

17

t

18

2

1

2

ns

SDꢃI Hold Time

ns

SDOUT Delay After SCLK↑

SDOUT Delay After CS↓

CS↓ to SCLK Setup Time

Data Valid to ꢂUSY↓

Data Access Time after RD↓ or ꢂYTESWAP↑

ꢂus Relinquish Time

C = 15pF

L

8

ns

2ꢀ

1

ns

1ꢀ

ns

1ꢀ

ns

Iote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Iote 7: ꢂipolar zero error is the offset voltage measured from –ꢀ.5LSꢂ

when the output code flicꢁers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 1111

1111 1111 1111. ꢂipolar full-scale error is the worst-case of –FS or +FS

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Iote ±: All voltage values are with respect to ground.

Iote 8: All specifications in dꢂ are referred to a full-scale ±±.ꢀ96V input

with a ±.ꢀ96V reference voltage.

Iote 3: When these pin voltages are taꢁen below ground or above

AVP, DVP or OVP, they will be clamped by internal diodes. This product can

handle input currents up to 1ꢀꢀmA below ground or above AVP, DVP or

OVP without latchup.

Iote 9: t of 8ns maximum allows a shift clocꢁ frequency up to

13

2 • (t + t

) for falling edge capture with 5ꢀ% duty cycle and up to

SETUP

13

8ꢀMHz for rising capture. t

is the set-up time of the receiving logic.

SETUP

Iote 4: AVP = DVP = OVP = 5V, f

= 1MHz, external reference equal to

SMPL

±.ꢀ96V unless otherwise noted.

Iote 10: Guaranteed by design.

Iote 5: Recommended operating conditions.

Iote 11: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Iote 6: ꢃntegral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

±V

t

WꢃDTH

ꢀ.5V

5ꢀ%

t

DELAY

239316Fꢀ1

±V

ꢀ.5V

Figure 1. Voltage 2evels for Timing Lpecifications

239316fa

5

LTC2393-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= ±5°C, f}_LMP2= 1Msps, unless otherwise noted.

ꢀntegral Ionlinearity

vs Output Code

Differential Ionlinearity

vs Output Code

DC Histogram

ꢁEꢂternal Referencex

1.5

1.ꢀ

2ꢀꢀꢀꢀꢀꢀ

18ꢀꢀꢀꢀꢀ

16ꢀꢀꢀꢀꢀ

1±ꢀꢀꢀꢀꢀ

12ꢀꢀꢀꢀꢀ

1ꢀꢀꢀꢀꢀꢀ

8ꢀꢀꢀꢀꢀ

6ꢀꢀꢀꢀꢀ

±ꢀꢀꢀꢀꢀ

2ꢀꢀꢀꢀꢀ

ꢀ

2.ꢀ

1.5

1.ꢀ

ꢀ.5

ꢀ

ꢀ.5

ꢀ

–ꢀ.5

–1.ꢀ

–1.5

–2.ꢀ

–ꢀ.5

–1.ꢀ

–1.5

3276±

32766 32768 3277ꢀ 32772

CODE

ꢀ

1638±

32768

±9152

65536

32768

ꢀ

1638±

±9152

65536

OUTPUT CODE

239316 Gꢀ2

239316 Gꢀ3

239316 Gꢀ1

DC Histogram

ꢁꢀnternal Referencex

ꢀnternal Reference Output

vs Temperature

Offset Error vs Temperature

2ꢀꢀꢀꢀꢀꢀ

18ꢀꢀꢀꢀꢀ

16ꢀꢀꢀꢀꢀ

1±ꢀꢀꢀꢀꢀ

12ꢀꢀꢀꢀꢀ

1ꢀꢀꢀꢀꢀꢀ

8ꢀꢀꢀꢀꢀ

6ꢀꢀꢀꢀꢀ

±ꢀꢀꢀꢀꢀ

2ꢀꢀꢀꢀꢀ

ꢀ

±.ꢀ975

±.ꢀ97ꢀ

±.ꢀ965

±.ꢀ96ꢀ

±.ꢀ955

±.ꢀ95ꢀ

±.ꢀ9±5

±.ꢀ9±ꢀ

±.ꢀ935

±.ꢀ93ꢀ

±.ꢀ925

1.ꢀ

ꢀ.8

TC = ±ppmꢄ/C

ꢀ.6

ꢀ.±

ꢀ.2

ꢀ

3276± 32766 32768 3277ꢀ 32772

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

TEMPERATURE (/C)

CODE

TEMPERATURE (/C)

239316 Gꢀ±

239316 Gꢀ6

239316 Gꢀ5

16k Point FFT f_L= 1Msps,

f_ꢀI= ±0kHz

16k Point FFT f_L= 1Msps,

f_ꢀI= 100kHz

Full-Lcale Error vs Temperature

1ꢀ

8

ꢀ

–2ꢀ

ꢀ

–2ꢀ

SIR = 9±.2dꢂ

THD ꢀ –1ꢀꢀ.6dꢂ

SꢃIAD = 93.3dꢂ

SFDR = 1ꢀ5.2dꢂ

THD ꢀ –1ꢀ5dꢂ

SꢃIAD = 93.9dꢂ

SFDR = 1ꢀ8dꢂ

6

–±ꢀ

±

–6ꢀ

2

–8ꢀ

ꢀ

–1ꢀꢀ

–12ꢀ

–1±ꢀ

–16ꢀ

–18ꢀ

–1ꢀꢀ

–12ꢀ

–1±ꢀ

–16ꢀ

–2

–±

–6

–8

–1ꢀ

–18ꢀ

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

ꢀ

±ꢀꢀ

5ꢀꢀ

ꢀ

±ꢀꢀ

5ꢀꢀ

1ꢀꢀ

2ꢀꢀ

3ꢀꢀ

1ꢀꢀ

2ꢀꢀ

3ꢀꢀ

TEMPERATURE (/C)

FREQUEICY (ꢁHz)

239316 Gꢀ7

239316 Gꢀ9

239316 Gꢀ8

239316fa

6

LTC2393-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= ±5°C, f}_LMP2= 1Msps, unless otherwise noted.

THD, Harmonics

LIR, LꢀIAD at f_ꢀI= ±0kHz

vs Temperature

LIR, LꢀIAD vs ꢀnput Frequency

vs ꢀnput Frequency

–7ꢀ

–75

96

9±

92

9ꢀ

88

86

8±

82

8ꢀ

95.ꢀ

9±.5

9±.ꢀ

93.5

93.ꢀ

SIR

–8ꢀ

SꢃIAD

SIR

–85

–9ꢀ

SꢃIAD

–95

THD

3RD

2ID

–1ꢀꢀ

–1ꢀ5

–11ꢀ

–115

–12ꢀ

1ꢀꢀ 125

ꢀ

25 5ꢀ 75

15ꢀ 175 2ꢀꢀ

ꢀ

25 5ꢀ 75

15ꢀ 175 2ꢀꢀ

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

FREQUEICY (ꢁHz)

TEMPERATURE (/C)

239316 G11

239316 G1ꢀ

239316 G12

THD, Harmonics at f_ꢀI= ±0kHz

vs Temperature

Lupply Current vs Lampling

Frequency

LIR, LꢀIAD vs ꢀnput 2evel

3ꢀ

95.ꢀ

9±.5

9±.ꢀ

93.5

93.ꢀ

–9ꢀ

–95

SIR

25

2ꢀ

SꢃIAD

–1ꢀꢀ

THD

3RD

–1ꢀ5

–11ꢀ

15

1ꢀ

2ID

–115

–12ꢀ

5

ꢀ

ꢀ.1

1

1ꢀ

1ꢀꢀ

1ꢀꢀꢀ

–2ꢀ

–1ꢀ

–±ꢀ

ꢀ

–3ꢀ

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

SAMPLꢃIG FREQUEICY (ꢁHz)

TEMPERATURE (/C)

ꢃIPUT LEVEL (dꢂ)

239316 G15

239316 G1±

239316 G13

Power-Down Current

vs Temperature

Lupply Current vs Temperature

3ꢀ

25

9ꢀ

8ꢀ

7ꢀ

6ꢀ

5ꢀ

±ꢀ

3ꢀ

2ꢀ

1ꢀ

ꢀ

AVP

2ꢀ

15

1ꢀ

DVP

OVP

5

ꢀ

AVP

OVP

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

–55 –35 –15

5

25 ±5 65 85 1ꢀ5 125

TEMPERATURE (/C)

239316 G16

239316 G17

239316fa

7

LTC2393-16

PIN FUNCTIONS

GID ꢁPins 1, 5, 7, ±0, 35, 41, 44, 48, Eꢂposed Pad

Pin 49 ꢁQFI Onlyxx: Ground. All GID pins must be con-

nected to a solid ground plane. Exposed pad must be

soldered directly to the ground plane.

D7 ꢁPin 16x: Data ꢂit 7. When SERꢄPAR = ꢀ this pin is

ꢂit 7 of the parallel port data output bus.

OGID ꢁPin 17x: Digital Ground for the ꢃnputꢄOutput

ꢃnterface.

AVP ꢁPins ±, 40, 45, 46, 47x: 5V Analog Power Supply.

The range of AVP is ±.75V to 5.25V. ꢂypass AVP to GID

with a good quality ꢀ.1μF and a 1ꢀμF ceramic capacitor

in parallel.

OVP ꢁPin 18x: Digital Power Supply for the ꢃnputꢄOutput

ꢃnterface. The range for OVP is 1.8V to 5V. ꢂypass OVP

to OGID with a good quality ±.7μF ceramic capacitor

close to the pin.

DVP ꢁPins 3, 19x: 5V Digital Power Supply. The range of

DVP is ±.75V to 5.25V. ꢂypass DVP to GID with a good

quality ꢀ.1μF and a 1ꢀμF ceramic capacitor in parallel.

D8 ꢁPin ±1x: Data ꢂit 8. When SERꢄPAR = ꢀ this pin is

ꢂit 8 of the parallel port data output bus.

D9/LDꢀIꢁPin±±x:Dataꢂit9ꢄSerialDataꢃnput. WhenSERꢄ

PAR = ꢀ this pin is ꢂit 9 of the parallel port data output bus.

When SERꢄPAR = 1, (serial mode) this is the serial data

input. SDꢃI can be used as a data input to daisy chain two

or more conversion results into a single SDOUT line. The

digital data level on SDꢃI is output on SDOUT with a delay

of 16 SCLK periods after the start of the read sequence.

LER/PAR ꢁPin 4x: SerialꢄParallel Selection ꢃnput. This pin

controls the digital interface. A logic high on this pin se-

lects the serial interface and a logic low selects the parallel

interface. ꢃn the serial mode the non-active digital outputs

are high impedance.

OS/2C ꢁPin 6x: Offset ꢂinaryꢄTwo’s Complement ꢃnput.

When Oꢂꢄ2C is high, the digital output is offset binary.

When low, the MSꢂ is inverted resulting in two’s comple-

ment output.

D10/LDOUTꢁPin±3x:Dataꢂit1ꢀꢄSerialDataOutput.When

SERꢄPAR = ꢀ this pin is ꢂit 1ꢀ of the parallel port data

output bus. When SERꢄPAR = 1, (serial mode) this is the

serial data output. The conversion result can be clocꢁed

out serially on this pin synchronized to SCLK. The data

is clocꢁed out MSꢂ first on the rising edge of SCLK and

is valid on the falling edge of SCLK. The data format is

determined by the logic level of Oꢂꢄ2C.

SYTELWAP ꢁPin 8x: ꢂYTESWAP ꢃnput. With ꢂYTESWAP

low, data will be output with Pin 28 (D15) being the MSꢂ

and Pin 9 (Dꢀ) being the LSꢂ. With ꢂYTESWAP high, the

upper eight bits and the lower eight bits will be switched.

The MSꢂ is output on Pin 16 and ꢂit 8 is output on Pin 9.

ꢂit 7 is output on Pin 28 and the LSꢂ is output on Pin 21.

D11/LC2K ꢁPin ±4x: Data ꢂit 11ꢄSerial Clocꢁ ꢃnput. When

SERꢄPAR = ꢀ this pin is ꢂit 11 of the parallel port data

output bus. When SERꢄPAR = 1, (serial mode) this is the

serial clocꢁ input.

D0 ꢁPin 9x: Data ꢂit ꢀ. When SERꢄPAR = ꢀ this pin is ꢂit ꢀ

of the parallel port data output bus.

D1 ꢁPin 10x: Data ꢂit 1. When SERꢄPAR = ꢀ this pin is

ꢂit 1 of the parallel port data output bus.

D1± ꢁPin ±5x: Data ꢂit 12. When SERꢄPAR = ꢀ this pin is

ꢂit 12 of the parallel port data output bus.

D± ꢁPin 11x: Data ꢂit 2. When SERꢄPAR = ꢀ this pin is

ꢂit 2 of the parallel port data output bus.

D13 ꢁPin ±6x: Data ꢂit 13. When SERꢄPAR = ꢀ this pin is

ꢂit 13 of the parallel port data output bus.

D3 ꢁPin 1±x: Data ꢂit 3. When SERꢄPAR = ꢀ this pin is

ꢂit 3 of the parallel port data output bus.

D14 ꢁPin ±7x: Data ꢂit 1±. When SERꢄPAR = ꢀ this pin is

ꢂit 1± of the parallel port data output bus.

D4 ꢁPin 13x: Data ꢂit ±. When SERꢄPAR = ꢀ this pin is

ꢂit ± of the parallel port data output bus.

D15 ꢁPin ±8x: Data ꢂit 15. When SERꢄPAR = ꢀ this pin is

ꢂit 15 of the parallel port data output bus. The data format

is determined by the logic level of Oꢂꢄ2C.

D5 ꢁPin 14x: Data ꢂit 5. When SERꢄPAR = ꢀ this pin is

ꢂit 5 of the parallel port data output bus.

D6 ꢁPin 15x: Data ꢂit 6. When SERꢄPAR = ꢀ this pin is

ꢂit 6 of the parallel port data output bus.

239316fa

8

LTC2393-16

PIN FUNCTIONS

SULY ꢁPin ±9x: ꢂusy Output. A low-to-high transition oc-

curs when a conversion is started. ꢃt stays high until the

conversion is complete. The falling edge of ꢂUSY can be

used as the data-ready clocꢁ signal.

VCM ꢁPin 36x: Common Mode Analog Output. Typically

the output voltage is 2.ꢀ±8V. ꢂypass to GID with a 1ꢀμF

capacitor.

REFOUT ꢁPin 37x: ꢃnternal Reference Output. Iominal

output voltage is ±.ꢀ96V. Connect this pin to REFꢃI if us-

ing the internal reference. ꢃf an external reference is used

connect REFOUT to ground.

RD ꢁPin 30x: Read Data ꢃnput. When CS and RD are both

low, the parallel and serial output bus is enabled.

CS ꢁPin 31x: Chip Select. When CS and RD are both low,

the parallel and serial output bus is enabled. CS is also

used to gate the external shift clocꢁ.

REFꢀI ꢁPin 38x: Reference ꢃnput. An external reference

can be applied to REFꢃI if a more accurate reference is

required. ꢃf an external reference is used tie REFOUT to

ground.

RELET ꢁPin 3±x: Reset ꢃnput. When high the LTC2393-16

is reset, and if this occurs during a conversion, the con-

version is halted and the data bus is put into Hi-Z mode.

REFLEILE ꢁPin 39x: Reference ꢃnput Sense. Leave

REFSEISE open when using the internal reference. ꢃf

an external reference is used connect REFSEISE to the

ground pin of the external reference.

PD ꢁPin 33x: Power-Down ꢃnput. When high, the

LTC2393-16ispowereddownandsubsequentconversion

requests are ignored. ꢂefore entering power shutdown,

the digital output data should be read.

–

+

ꢀI , ꢀI ꢁPin 4±, Pin 43x: Differential Analog ꢃnputs.

–

ꢃI – (ꢃI ) can range up to ±V

.

REF

CNVST ꢁPin 34x: Conversion Start ꢃnput. A falling edge

on CNVST puts the internal sample-and-hold into the hold

modeandstartsaconversion.CNVSTisindependentofCS.

239316fa

9

LTC2393-16

FUNCTIONAL BLOCK DIAGRAM

AVP DVP OVP

LTC2393-16

16-ꢂꢃT OR

TWO ꢂYTE

SDꢃI

SDOUT

SCLK

+

ꢃI

PARALLELꢄ

SERꢃAL

ꢃITERFACE

16-ꢂꢃT SAMPLꢃIG ADC

16-ꢂꢃT

–

ꢃI

CS

1x ꢂUFFER

RD

REFꢃI

SERꢄPAR

ꢂYTESWAP

Oꢂꢄ2C

REFOUT

VCM

±.ꢀ96V

ꢂUSY

COITROL LOGꢃC

CNVST PD

REFEREICE

REFSEISE

RESET

GID OGID

239316ꢂD

TIMING DIAGRAMS

Conversion Timing Using the Parallel ꢀnterface

CS, RD = ꢀ

CNVST

ACQUꢃRE

ꢂUSY

COIVERT

D[15:ꢀ]

PREVꢃOUS COIVERSꢃOI

CURREIT COIVERSꢃOI

239315 TDꢀ1

Conversion Timing Using the Lerial ꢀnterface

CS, RD = ꢀ

CNVST

ACQUꢃRE

ꢂUSY

COIVERT

SCLK

D1± D12 D1ꢀ D8 D6 D± D2 Dꢀ

D15 D13 D11 D9 D7 D5 D3 D1

SDOUT

239315 TDꢀ2

239316fa

10

LTC2393-16

APPLICATIONS INFORMATION

OVERVꢀEW

ꢀ11...111

ꢀ11...11ꢀ

ꢂꢃPOLAR

ZERO

The LTC2393-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2393-16 supports a large

±±.ꢀ96V fully differential input range, maꢁing it ideal

for high performance applications which require a wide

dynamic range. The LTC2393-16 achieves ±2LSꢂ ꢃIL

max, no missing codes at 16 bits and 9±.2dꢂ SIR (typ).

ꢀꢀꢀ...ꢀꢀ1

ꢀꢀꢀ...ꢀꢀꢀ

111...111

111...11ꢀ

1ꢀꢀ...ꢀꢀ1

1ꢀꢀ...ꢀꢀꢀ

FSR = +FS – –FS

1LSꢂ = FSRꢄ65536

The LTC2393-16 includes a precision internal reference

with a guaranteed ꢀ.5% initial accuracy and a ±2ꢀppmꢄ/C

(max)temperaturecoefficient.Fast1Mspsthroughputwith

no cycle latency in both parallel and serial interface modes

maꢁes the LTC2393-16 ideally suited for a wide variety

of high speed applications. An internal oscillator sets the

conversion time, easing external timing considerations.

The LTC2393-16 dissipates only 1±ꢀmW at 1Msps, while

both nap and sleep power-down modes are provided to

further reduce power during inactive periods.

–1 ꢀV

LSꢂ

ꢃIPUT VOLTAGE (V)

1

LSꢂ

–FSRꢄ2

FSRꢄ2 – 1LSꢂ

239316 Fꢀ2

Figure ±. 2TC±393-16 Two’s Complement Transfer Function

AIA2OG ꢀIPUT

The analog inputs of the LTC2393-16 are fully differential

in order to maximize the signal swing that can be digitized.

Theanaloginputscanbemodeledbytheequivalentcircuit

showninFigure3.ThediodesattheinputprovideESDpro-

tection. The analog inputs should not exceed the supply or

gobelowground.ꢃntheacquisitionphase,eachinputsees

approximately±ꢀpF(C )fromthesamplingCDACinseries

with 5ꢀΩ (R ) from the on-resistance of the sampling

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw only one small current spiꢁe

COIVERTER OPERATꢀOI

The LTC2393-16 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor DꢄA

ꢃI

+

–

ꢃI

converter (CDAC) is connected to the ꢃI and ꢃI pins

to sample the differential analog input voltage. A falling

edge on the CNVST pin initiates a conversion. During the

conversion phase, the 16-bit CDAC is sequenced through

asuccessiveapproximationalgorithm,effectivelycompar-

ing the sampled input with binary-weighted fractions of

while charging the C capacitors during acquisition.

During conversion, the analog inputs draw only a small

ꢃI

leaꢁage current.

thereferencevoltage(e.g., V ꢄ2, V ꢄ±…V ꢄ65536)

REF

usingthedifferentialcomparator.Attheendofconversion,

the CDAC output approximates the sampled analog input.

The ADC control logic then prepares the 16-bit digital

output code for parallel or serial transfer.

AVP

C

ꢃI

R

ꢃI

R

ꢃI

+

–

ꢃI

ꢂꢃAS

AVP

VOLTAGE

C

TRAILFER FUICTꢀOI

ꢃI

239316 Fꢀ3

ꢃI

The LTC2393-16 digitizes the full-scale voltage of 2 • V

REF

16

into2 levels,resultinginanLSꢂsizeof125μVwhenV

=±.ꢀ96V. Theidealtransferfunctionfortwo’scomplement

is shown in Figure 2. The Oꢂꢄ2C pin selects either offset

binary or two’s complement format.

Figure 3. The Equivalent Circuit for the

Differential Analog ꢀnput of the 2TC±393-16

239316fa

11

LTC2393-16

APPLICATIONS INFORMATION

ꢀIPUT DRꢀVE CꢀRCUꢀTL

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

Alowimpedancesourcecandirectlydrivethehighimped-

ance inputs of the LTC2393-16 without gain error. A high

impedance source should be buffered to minimize settling

time during acquisition and to optimize the distortion

performance of the ADC.

Lingle-to-Differential Conversion

For single-ended input signals, a single-ended-to-differ-

ential conversion circuit must be used to produce a dif-

ferentialsignalattheADCinputs.TheLT635ꢀADCdriveris

recommendedforperformingasingle-ended-to-differential

conversion, as shown in Figure ±a. ꢃts low noise and good

DC linearity allows the LTC2393-16 to meet full data sheet

specifications. An alternative solution using two op amps

is shown in Figure ±b. Using two LT18ꢀ6 op amps, the

circuit achieves 9±.1dꢂ signal-to-noise ratio (SIR). For a

2ꢀꢁHz input signal, the input of the LTC2393-16 has been

bandwidth limited to about 25ꢁHz.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2393-16. The amplifier

provides low output impedance to allow for fast settling

of the analog signal during the acquisition phase. ꢃt also

provides isolation between the signal source and the ADC

inputswhichdrawasmallcurrentspiꢁeduringacquisition.

ꢀnput Filtering

The noise and distortion of the buffer amplifier and other

circuitry must be considered since they add to the ADC

noiseanddistortion.Ioisyinputcircuitryshouldbefiltered

prior to the analog inputs to minimize noise. A simple

1-pole RC filter is sufficient for many applications.

ADC REFEREICE

A low noise, low temperature drift reference is critical to

achieving the full data sheet performance of the ADC. The

LTC2393-16 provides an excellent internal reference with

a ±2ꢀppmꢄ/C (max) temperature coefficient. For better

accuracy, an external reference can be used.

Large filter RC time constants slow down the settling at

the analog inputs. ꢃt is important that the overall RC time

constants be short enough to allow the analog inputs to

completely settle to 16-bit resolution within the acquisi-

The high speed, low noise internal reference buffer is used

for both internal and external reference applications. ꢃt

cannot be bypassed.

tion time (t ).

ACQ

Highqualitycapacitorsandresistorsshouldbeusedinthe

RC filter since these components can add distortion. IPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

AIALOG

ꢃIPUT

+

ꢀV TO ±.ꢀ96V

LT18ꢀ6

–

2±9Ω

+

ꢃI

3ꢀ1Ω

ꢀ.ꢀ13μF

2±9Ω

LTC2393-16

+

ꢃI

3ꢀ1Ω

2±9Ω

–

ꢃI

AIALOG ꢃIPUT

ꢀV TO ±.ꢀ96V

22ꢀꢀpF

LT635ꢀ

LTC2393-16

239316 Fꢀ±b

2±9Ω

–

+

ꢃI

LT18ꢀ6

239316 Fꢀ±a

COMMOI

MODE

VOLTAGE

SꢃIGLE-EIDED-

TO-DꢃFFEREITꢃAL

DRꢃVER

Figure 4a. Recommended Lingle-Ended-to-Differential

Conversion Circuit Using the 2T6350 ADC Driver

Figure 4b. Alternative Lingle-Ended-to-Differential Conversion

Circuit Using Two 2T1806 Op Amps

239316fa

12

LTC2393-16

APPLICATIONS INFORMATION

ꢀnternal Reference

DYIAMꢀC PERFORMAICE

To use the internal reference, simply tie the REFOUT and

REFꢃI pins together. This connects the ±.ꢀ96V output of

the internal reference to the input of the internal reference

buffer. The output impedance of the internal reference is

approximately 2.6ꢁΩ and the input impedance of the in-

ternal reference buffer is about 85ꢁΩ. ꢃt is recommended

that this node be bypassed to ground with a 1μF or larger

capacitortofiltertheoutputnoiseoftheinternalreference.

The REFSEISE pin should be left floating when using the

internal reference.

Fast fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢂy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2393-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Lignal-to-Ioise and Distortion Ratio ꢁLꢀIADx

The signal-to-noise and distortion ratio (SꢃIAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the AꢄD output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 5 shows that the LTC2393-16 achieves

a typical SꢃIAD of 93.9dꢂ at a 1MHz sampling rate with

a 2ꢀꢁHz input.

Eꢂternal Reference

An external reference can be used with the LTC2393-16

when even higher performance is required. The

LT179ꢀ-±.ꢀ96 offers ꢀ.ꢀ5% (max) initial accuracy and

1ꢀppmꢄ/C (max) temperature coefficient. When using an

external reference, connect the reference output to the

REFꢃI pin and connect the REFOUT pin to ground. The

REFSEISE pin should be connected to the ground of the

external reference.

ꢀ

–2ꢀ

SIR = 9±.2dꢂ

THD ꢀ –1ꢀ5dꢂ

SꢃIAD = 93.9dꢂ

SFDR = 1ꢀ8dꢂ

–±ꢀ

–6ꢀ

–8ꢀ

–1ꢀꢀ

–12ꢀ

–1±ꢀ

–16ꢀ

–18ꢀ

ꢀ

±ꢀꢀ

5ꢀꢀ

1ꢀꢀ

2ꢀꢀ

3ꢀꢀ

FREQUEICY (ꢁHz)

239316 Gꢀ8

Figure 5. 16k Point FFT of the 2TC±393-16, f_L= 1Msps, f_ꢀI= ±0kHz

239316fa

13

LTC2393-16

APPLICATIONS INFORMATION

Lignal-to-Ioise Ratio ꢁLIRx

Power Lupply Lequencing

The signal-to-noise ratio (SIR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 5 shows

that the LTC2393-16 achieves a typical SIR of 9±.2dꢂ at

a 1MHz sampling rate with a 2ꢀꢁHz input.

The LTC2393-16 does not have any specific power supply

sequencingrequirements.Careshouldbetaꢁentoobserve

the maximum voltage relationships described in the Ab-

solute Maximum Ratings section. The LTC2393-16 has a

power-on-reset (POR) circuit. With the POR, the result of

the first conversion is valid after power has been applied

to the ADC. The LTC2393-16 will reset itself if the power

supply voltage drops below 2.5V. Once the supply voltage

is brought bacꢁ to its nominal value, the POR will reinitial-

ize the ADC and it will be ready to start a new conversion.

Total Harmonic Distortion ꢁTHDx

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

Iap Mode

between DC and half the sampling frequency (f

THD is expressed as:

ꢄ2).

SMPL

The LTC2393-16 can be put into the nap mode after a

conversion has been completed to reduce the power

consumption between conversions. ꢃn this mode some

of the circuitry on the device is turned off. Iap mode is

enabledbyꢁeepingCNVSTlowbetweenconversions.When

the next conversion is requested, bring CNVST high and

hold for at least 25ꢀns, then start the next conversion by

bringing CNVST low. See Figure 6.

V₂²+ V₃²+ V_±²...V_I²

THD = 2ꢀ log

V₁

where V is the RMS amplitude of the fundamental fre-

1

quencyandV throughV aretheamplitudesofthesecond

2

I

through Ith harmonics.

Power Lhutdown Mode

POWER COILꢀDERATꢀOIL

When PD is tied high, the LTC2393-16 enters power shut-

downandsubsequentrequestsforconversionareignored.

ꢂefore entering power shutdown, the digital output data

needstoberead.However,ifarequestforpowershutdown

(PD = high) occurs during a conversion, the conversion

The LTC2393-16 provides three sets of power supply

pins: the analog 5V power supply (AVP), the digital 5V

power supply (DVP) and the digital inputꢄoutput interface

power supply (OVP). The flexible OVP supply allows the

LTC2393-16tocommunicatewithanydigitallogicoperating

between 1.8V and 5V, including 2.5V and 3.3V systems.

t

5

CNVST

ꢂUSY

IAP

t

ACQ

COIV

IAP MODE

239316 Fꢀ6

Figure 6. Iap Mode Timing for the 2TC±393-16

239316fa

14

LTC2393-16

APPLICATIONS INFORMATION

will finish and then the device will power down. The data

from that conversion can be read after PD = low is applied.

ꢃn this mode power consumption drops to a typical value

of 175μW from 1±ꢀmW. This mode can be used if the

LTC2393-16 is inactive for a long period of time and the

user wants to minimize the power dissipation.

TꢀMꢀIG AID COITRO2

The LTC2393-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. CS and RD

control the digital interface on the LTC2393-16. When

either CS or RD is high, the digital outputs are high

impedance.

Recovery from Power Lhutdown Mode

CNVST Timing

Once the PD pin is returned to a low level, ending the

power shutdown request, the internal circuitry will begin

to power up. ꢃf the internal reference is used, the 2.6ꢁΩ

output impedance with the 1μF bypass capacitor on the

REFꢃIꢄREFOUT pins will be the main time constant for

the power-on recovery time. ꢃf an external reference is

used, typically allow 5ms for recovery before initiating a

new conversion.

The LTC2393-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. Once a

conversion has been initiated, it cannot be restarted until

the conversion is complete. For optimum performance

CNVSTshouldbeacleanlowjittersignal. Converterstatus

is indicated by the ꢂUSY output which remains high while

the conversion is in progress. To ensure no errors occur

in the digitized results return the rising edge either within

±ꢀns from the start of the conversion or wait until after

the conversion has been completed. The CNVST timing

needed to taꢁe advantage of the reduced power mode of

operation is described in the Iap Mode section.

Power Dissipation vs Lampling Frequency

The power dissipation of the LTC2393-16 will decrease

as the sampling frequency is reduced when nap mode

is activated. See Figure 7. ꢃn nap mode, a portion of the

circuitryontheLTC2393-16isturnedoffafteraconversion

has been completed. ꢃncreasing the time allowed between

conversions lowers the average power.

ꢀnternal Conversion Clock

The LTC2393-16 has an internal clocꢁ that is trimmed

to achieve a maximum conversion time of 6ꢀꢀns. Io

external adjustments are required and with a maximum

acquisition time of 385ns, a throughput performance of

1Msps is guaranteed.

3ꢀ

25

2ꢀ

DꢀGꢀTA2 ꢀITERFACE

The LTC2393-16 allows both parallel and serial digital

interfaces. TheflexibleOVPsupplyallowstheLTC2393-16

to communicate with any digital logic operating between

1.8V and 5V, including 2.5V and 3.3V systems.

15

1ꢀ

5

ꢀ

ꢀ.1

1

1ꢀ

1ꢀꢀ

1ꢀꢀꢀ

SAMPLꢃIG FREQUEICY (ꢁHz)

239316 G15

Figure 7. Power Dissipation of the 2TC±393-16

Decreases with Decreasing Lampling Frequency

239316fa

15

LTC2393-16

APPLICATIONS INFORMATION

Parallel Modes

ꢃf CS and RD are used to gate the serial output data, the

full conversion result should be read before CS and RD

are returned to a high level.

The parallel output data interface is active when the

SERꢄPAR pin is tied low and when both CS and RD are low.

The output data can be read as a 16-bit word as shown

in Figures 8, 9 and 1ꢀ or it can be read as two 8-bit bytes

by using the ꢂYTESWAP pin. As shown in Figure 11, with

the ꢂYTESWAP pin low, the first eight MSꢂs are output on

the D15 to D8 pins and the eight LSꢂs are output on the

D7 to DO pins. When ꢂYTESWAP is taꢁen high, the eight

LSꢂs now are output on the D15 to D8 pins and the eight

MSꢂs are output on the D7 to Dꢀ pins.

The SDꢃI input pin is used to daisy chain multiple con-

verters. This is useful for applications where hardware

constraints may limit the number of lines needed to

interface to a large number of converters. For example,

if two devices are cascaded, the MSꢂ of the first device

will appear at the output after 17 SCLK cycles. The first

MSꢂ is clocꢁed in on the falling edge of the first SCLK.

See Figure 12.

Lerial Modes

Data Format

The serial output data interface is active when the

SERꢄPAR pinistiedhighandwhenbothCSandRDarelow.

The serial output data will be clocꢁed out on the SDOUT

pin when an external clocꢁ is applied to the SCLK pin.

Clocꢁing out the data after the conversion will yield the

best performance. With a shift clocꢁ frequency of at least

±ꢀMHz, a 1Msps throughput is still achieved. The serial

output data changes state on the rising edge of SCLK and

can be captured on the falling edge of SCLK. D15 remains

valid till the first rising edge of shift clocꢁ after the first

falling edge of shift clocꢁ. The non-active digital outputs

are high impedance when operating in the serial mode.

When Oꢂꢄ2C is high, the digital output is offset binary.

When low, the MSꢂ is inverted resulting in two’s comple-

ment output. This pin is active in both the parallel and

serial modes of operation.

Reset

When the RESET pin is high, the LTC2393-16 is reset, and

ifthisoccursduringaconversion, theconversionishalted

and the data bus is put into Hi-Z mode. ꢃn reset, requests

for new conversions are ignored. Once RESET returns

low, the LTC2393-16 is ready to start a new conversion

after the acquisition time has been met. See Figure 13.

CS = RD = ꢀ

t

±

CNVST

ꢂUSY

t

COIV

t

6

16

PREVꢃOUS COIVERSꢃOI

IEW

DATA ꢂUS D[15:ꢀ]

239316 Fꢀ8

Figure 8. Read the Parallel Data Continuously.

The Data Sus is Always Driven and Can’t Se Lhared

239316fa

16

LTC2393-16

APPLICATIONS INFORMATION

CS

RD

ꢂUSY

Hi-Z

CURREIT

COIVERSꢃOI

DATA ꢂUS D[15:ꢀ]

239316 Fꢀ9

t

17

t

18

Figure 9. Read the Parallel Data After the Conversion

CS = ꢀ

t

±

CNVST, RD

ꢂUSY

t

COIV

t

6

Hi-Z

PREVꢃOUS

COIVERSꢃOI

DATA ꢂUS D[15:ꢀ]

239316 Fꢀ9

t

18

17

Figure 10. Read the Parallel Data During the Conversion

8-ꢂꢃT ꢃITERFACE

CS, RD

ꢂYTESWAP

D[15:8]

Hi-Z

HꢃGH ꢂYTE

LOW ꢂYTE

239316 F11

t

17

t

18

17

Figure 11. 8-Sit Parallel ꢀnterface Using the SYTELWAP Pin

239316fa

17

LTC2393-16

APPLICATIONS INFORMATION

RD = ꢀ

SCLK STARTS LOW

t

15

CS

ꢂUSY

t

8

t

1ꢀ

t

9

SCLK

1

2

3

±

15

16

17

18

t

13

SDOUT

(ADC 2)

Hi-Z

D15

D1±

2

D13

2

D1

2

Dꢀ

2

D15

1

D1±

1

2

t

12

1±

t

11

SDꢃI

(ADC 2)

D15

1

D1±

1

D13

1

D1

1

Dꢀ

1

RD = ꢀ

SCLK STARTS HꢃGH

CS

ꢂUSY

t

8

t

1ꢀ

t

9

SCLK

1

2

3

±

15

16

17

18

t

13

Hi-Z

SDOUT

(ADC 2)

D15

D1±

2

D13

2

D1

2

Dꢀ

2

D15

1

D1±

1

2

t

12

1±

t

11

SDꢃI

(ADC 2)

D15

1

D1±

1

D13

1

D1

1

Dꢀ

1

CNVST ꢃI

CS ꢃI

RD ꢃI

SCLK ꢃI

LTC2393-16

CNVST

CS

RD

SCLK

SDꢃI SDOUT

RD

SCLK

SDꢃI SDOUT

DATA OUT

239316 F12

ADC 1

ADC 2

Figure 1±. Lerial ꢀnterface with Eꢂternal Clock. Read After the Conversion. Daisy Chain Multiple Converters

t

7

RESET

t

ACQ

CVNST

Hi-Z

DATA ꢂUS D[15:ꢀ]

239316 F13

Figure 13. RELET Pin Timing

239316fa

18

LTC2393-16

APPLICATIONS INFORMATION

SOARD 2AYOUT

Recommended 2ayout

To obtain the best performance from the LTC2393-16, a

printed circuit board (PCꢂ) is recommended. Layout for

the printed circuit board should ensure the digital and

analog signal lines are separated as much as possible.

ꢃn particular, care should be taꢁen not to run any digital

clocꢁs or signals alongside analog signals or underneath

the ADC.

ThefollowingisanexampleofarecommendedPCꢂlayout.

A single solid ground plane is used. ꢂypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC15ꢀꢀA, the

evaluation ꢁit for the LTC2393-16

Partial Lchematic of Demoboard

C36

1μF

CNVST

3±

39

REFSEISE

38

37

CNVST

REFꢃI

REFOUT

R2

2±9Ω

1%

29

28

27

26

25

2±

23

22

21

16

15

1±

13

12

11

1ꢀ

9

ꢂUSY

D15

D1±

D13

D12

ꢂUSY

D15

±3

D1±

+

ꢃI

D13

D12

C5±

OPT

D11ꢄSCLK

D1ꢀꢄSDOUT

D9ꢄSDꢃI

D8

D1ꢀꢄSDOUT

D9ꢄSDꢃI

D8

C2

D7

LTC2393-16

22ꢀꢀpF

12ꢀ6 IPO

D6

D5

D±

R3

2±9Ω

1%

D3

D2

D1

D2

D1

±±

–

ꢃI

Dꢀ

8

C55

OPT

ꢂYTESWAP

GID

7

VCM Oꢂꢄ2C GID SERꢄPAR RESET PD CS RD

36

6

5

±

32 33

31 3ꢀ

C53

1ꢀμF

C31

ꢀ.1μF

C3ꢀ

1ꢀμF

C29

ꢀ.1μF

C28

1ꢀμF

R2±

1.ꢀΩ

3.3V

5V

C±ꢀ

±.7μF

±7

±6 ±5 ±ꢀ

2

19

3

18

AVPꢄAVL AVP AVP AVP AVP

DVP DVPꢄDVL OVP

LTC2393-16

GID GID GID GID GID GID OGID

±8 ±± ±1 35 2ꢀ 17

239316 TAꢀ2

1

239316fa

19

LTC2393-16

APPLICATIONS INFORMATION

Partial Top Lilkscreen

Partial 2ayer 1 Component Lide

Partial 2ayer ± Ground Plane

239316fa

20

LTC2393-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UK Package

48-Lead Plastic QFN (7mm w 7mm)

(Reference LTC DWG # 05-08-ꢀ704 Rev C)

0.70 0.05

5.ꢀ5 0.05

5.50 REF

6.ꢀ0 0.05 7.50 0.05

(4 SIDES)

5.ꢀ5 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

7.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

47 48

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ

CHAMFER

C = 0.35

5.ꢀ5 0.ꢀ0

5.50 REF

(4-SIDES)

5.ꢀ5 0.ꢀ0

(UK48) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

239316fa

21

LTC2393-16

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

2X Package

48-2ead Plastic 2QFP ꢁ7mm × 7mmx

(Reference LTC DWG # ꢀ5-ꢀ8-176ꢀ Rev Ø)

7.15 – 7.25

5.5ꢀ REF

9.ꢀꢀ ꢂSC

7.ꢀꢀ ꢂSC

±8

SEE IOTE: ±

1

2

1

2

ꢀ.5ꢀ ꢂSC

9.ꢀꢀ ꢂSC

7.ꢀꢀ ꢂSC

5.5ꢀ REF

7.15 – 7.25

ꢀ.2ꢀ – ꢀ.3ꢀ

A

PACKAGE OUTLꢃIE

Cꢀ.3ꢀ – ꢀ.5ꢀ

1.3ꢀ MꢃI

RECOMMEIDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE IOT SOLDERED

1.6ꢀ

11/ – 13/

1.35 – 1.±5 MAX

Rꢀ.ꢀ8 – ꢀ.2ꢀ

GAUGE PLAIE

ꢀ.25

ꢀ/ – 7/

11/ – 13/

1.ꢀꢀ REF

ꢀ.5ꢀ

ꢂSC

ꢀ.ꢀ9 – ꢀ.2ꢀ

ꢀ.17 – ꢀ.27

ꢀ.ꢀ5 – ꢀ.15

LX±8 LQFP ꢀ9ꢀ7 REVØ

ꢀ.±5 – ꢀ.75

SECTꢃOI A – A

IOTE:

1. PACKAGE DꢃMEISꢃOIS COIFORM TO JEDEC #MS-ꢀ26 PACKAGE OUTLꢃIE

2. DꢃMEISꢃOIS ARE ꢃI MꢃLLꢃMETERS

±. PꢃI-1 ꢃIDEITꢃFꢃER ꢃS A MOLDED ꢃIDEITATꢃOI, ꢀ.5ꢀmm DꢃAMETER

5. DRAWꢃIG ꢃS IOT TO SCALE

3. DꢃMEISꢃOIS OF PACKAGE DO IOT ꢃICLUDE MOLD FLASH. MOLD FLASH

SHALL IOT EXCEED ꢀ.25mm OI AIY SꢃDE, ꢃF PRESEIT

239316fa

22

LTC2393-16

REVISION HISTORY

REV

DATE

DELCRꢀPTꢀOI

PAGE IUMSER

A

7ꢄ12

ꢃncreased T

to 15ꢀ/C on LQFP pacꢁage

2

3

JMAX

ꢃncreased SFDR specification under Dynamic Accuray to 1ꢀ8dꢂ

Updated SIR, SꢃIAD vs ꢃnput Frequency graph

7

Added condition for reading conversion result under Serial Modes

Updated data bit numbering on Figure 12

16

18

239316fa

ꢃnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation maꢁes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2393-16

TYPICAL APPLICATION

ADC Driver: Lingle-Ended ꢀnput to Differential Output

5V

2±9Ω

ꢀ.1μF

V

ꢃI

+

5V

+

ꢃI1

^{ꢀV to ±V}–

SHDN

V

OUT2

+

–

A

ꢃI

22ꢀꢀpF

LTC2393-16

+

–

+

LT635ꢀ

A

ꢃI

–

+

–

V

OUT1

2±9Ω

ꢃI2

ꢃI1

239316 TAꢀ3

ꢀ.1μF

–5V

ꢀ.1μF

±99Ω

2V

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239316fa

LT 0712 REV A • PRINTED IN USA

LinearTechnology Corporation

163ꢀ McCarthy ꢂlvd., Milpitas, CA 95ꢀ35-7±17

24

●

(±ꢀ8) ±32-19ꢀꢀ FAX: (±ꢀ8) ±3±-ꢀ5ꢀ7 www.linear.com


型号：	LTC2393IUK-16#TRPBF
厂家：	Linear
描述：	LTC2393-16 - 16-Bit, 1Msps SAR ADC With 94dB SNR; Package: QFN; Pins: 48; Temperature Range: -40°C to 85°C 转换器
文件：	总24页 (文件大小：230K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2393IUK-16#TRPBF [Linear]

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