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LTC2401CMS#PBF [Linear]

LTC2401 - 1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C;
LTC2401CMS#PBF
型号： LTC2401CMS#PBF
厂家： Linear    Linear
描述：

LTC2401 - 1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C

光电二极管 转换器
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中文：  中文翻译
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LTC2401/LTC2402  
1-/2-Channel 24-Bit µPower  
No Latency ∆ΣTMADCs in MSOP-10  
U
FEATURES  
DESCRIPTIO  
TheLTC®2401/LTC2402are1-and2-channel2.7Vto5.5V  
micropower 24-bit analog-to-digital converters with an  
integrated oscillator, 4ppm INL and 0.6ppm RMS noise.  
These ultrasmall devices use delta-sigma technology and  
anewdigitalfilterarchitecturethatsettlesinasinglecycle.  
This eliminates the latency found in conventional ∆Σ  
converters and simplifies multiplexed applications.  
■
24-Bit ADCs in Tiny MSOP-10 Packages  
■
4ppm INL, No Missing Codes  
■
4ppm Full-Scale Error  
0.5ppm Offset  
0.6ppm Noise  
Single Conversion Settling Time for  
Multiplexed Applications  
1- or 2-Channel Inputs  
Automatic Channel Selection (Ping-Pong) (LTC2402)  
Zero Scale and Full Scale Set for Reference  
and Ground Sensing  
Internal Oscillator—No External Components Required  
110dB Min, 50Hz/60Hz Notch Filter  
Reference Input Voltage: 0.1V to VCC  
Live Zero—Extended Input Range Accommodates  
12.5% Overrange and Underrange  
Single Supply 2.7V to 5.5V Operation  
■
■
■
■
Through a single pin, the LTC2401/LTC2402 can be  
■
configured for better than 110dB rejection at 50Hz or  
60Hz ±2%, or can be driven by an external oscillator for  
a user defined rejection frequency in the range 1Hz to  
120Hz. The internal oscillator requires no external fre-  
quency setting components.  
■
■
■
■
■
These converters accept an external reference voltage  
from 0.1V to VCC. With an extended input conversion  
range of –12.5% VREF to 112.5% VREF (VREF = FSSET –  
ZSSET), the LTC2401/LTC2402 smoothly resolve the off-  
set and overrange problems of preceding sensors or  
signal conditioning circuits.  
■
■
Low Supply CurrUent (200µA) and Auto Shutdown  
APPLICATIO S  
The LTC2401/LTC2402 communicate through a 2- or  
3-wire digital interface that is compatible with SPI and  
MICROWIRETM protocols.  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
No Latency ∆Σ is a trademark of Linear Technology Corporation.  
MICROWIRE is a trademark of National Semiconductor Corporation.  
■
Weight Scales  
Direct Temperature Measurement  
Gas Analyzers  
Strain Gauge Transducers  
Instrumentation  
Data Acquisition  
■
■
■
■
■
■
Industrial Process Control  
U
TYPICAL APPLICATIO  
Pseudo Differential Bridge Digitizer  
2.7V TO 5.5V  
2.7V TO 5.5V  
V
CC  
1µF  
1
2
4
3
5
= INTERNAL OSC/50Hz REJECTION  
V
1
10  
CC  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
LTC2402  
SET  
FS  
9
SCK  
SDO  
CS  
2
3
4
5
9
8
7
6
REFERENCE VOLTAGE  
ZS + 0.1V TO V  
FS  
SET  
SCK  
SDO  
CS  
SET  
CC  
8
3-WIRE  
SPI INTERFACE  
CH0  
CH1  
ZS  
3-WIRE  
SPI INTERFACE  
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
SET  
= FS  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
7
REF  
(V  
REF  
– ZS  
)
SET  
10  
F
O
SET  
INTERNAL OSCILLATOR  
60Hz REJECTION  
0V TO FS  
– 100mV  
GND  
SET  
SET  
GND  
6
24012 TA01  
24012TA02  
1
LTC2401/LTC2402  
W W  
U W  
ABSOLUTE MAXIMUM RATINGS  
(Notes 1, 2)  
Operating Temperature Range  
Supply Voltage (VCC) to GND.......................–0.3V to 7V  
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)  
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)  
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)  
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)  
LTC2401/LTC2402C ................................ 0°C to 70°C  
LTC2401/LTC2402I ............................ –40°C to 85°C  
Storage Temperature Range ................. –65°C to 150°C  
Lead Temperature (Soldering, 10 sec).................. 300°C  
U
W
U
PACKAGE/ORDER INFORMATION  
ORDER PART NUMBER  
ORDER PART NUMBER  
TOP VIEW  
TOP VIEW  
LTC2401CMS  
LTC2401IMS  
V
CC  
10 F  
1
2
3
4
5
10 F  
O
LTC2402CMS  
LTC2402IMS  
V
SET  
V
1
2
3
CC  
O
FS  
FS  
9
8
7
6
SCK  
SDO  
CS  
9
8
7
6
SCK  
SDO  
CS  
SET  
CH1  
CH0  
IN  
NC 4  
SET  
ZS  
SET  
ZS  
5
GND  
GND  
MS10 PART MARKING  
MS10 PART MARKING  
MS10 PACKAGE  
10-LEAD PLASTIC MSOP  
MS10 PACKAGE  
10-LEAD PLASTIC MSOP  
LTMB  
LTMC  
LTMD  
LTME  
TJMAX = 125°C, θJA = 130°C/W  
TJMAX = 125°C, θJA = 130°C/W  
Consult factory for Military grade parts.  
U
CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Notes 3, 4)  
PARAMETER  
CONDITIONS  
MIN  
24  
TYP  
MAX  
UNITS  
Bits  
Resolution  
●
●
No Missing Codes Resolution  
Integral Nonlinearity  
0.1V ≤ FS  
≤ V , ZS = 0V (Note 5)  
SET  
24  
Bits  
SET  
CC  
FS = 2.5V, ZS = 0V (Note 6)  
●
●
2
4
10  
15  
ppm of V  
ppm of V  
SET  
SET  
REF  
REF  
FS = 5V, ZS = 0V (Note 6)  
SET  
SET  
Offset Error  
2.5V ≤ FS  
≤ V , ZS = 0V  
●
0.5  
0.01  
4
2
ppm of V  
SET  
SET  
SET  
SET  
CC  
SET  
REF  
Offset Error Drift  
Full-Scale Error  
2.5V ≤ FS  
2.5V ≤ FS  
2.5V ≤ FS  
≤ V , ZS = 0V  
ppm of V /°C  
REF  
CC  
SET  
≤ V , ZS = 0V  
●
10  
ppm of V  
REF  
CC  
SET  
Full-Scale Error Drift  
Total Unadjusted Error  
≤ V , ZS = 0V  
0.04  
ppm of V /°C  
REF  
CC  
SET  
FS = 2.5V, ZS = 0V  
5
10  
ppm of V  
ppm of V  
SET  
SET  
REF  
REF  
FS = 5V, ZS = 0V  
SET  
SET  
Output Noise  
V
IN  
= 0V (Note 13)  
3
µV  
RMS  
Normal Mode Rejection 60Hz ±2%  
Normal Mode Rejection 50Hz ±2%  
Power Supply Rejection, DC  
(Note 7)  
(Note 8)  
●
●
110  
110  
130  
130  
100  
110  
110  
dB  
dB  
dB  
dB  
dB  
FS = 2.5V, ZS = 0V, V = 0V  
SET  
SET  
IN  
Power Supply Rejection, 60Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Notes 7, 15)  
SET  
SET  
IN  
Power Supply Rejection, 50Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Notes 8, 15)  
SET  
SET  
IN  
2
LTC2401/LTC2402  
U
U
U
U
A ALOG I PUT A D REFERE CE  
The ● denotes specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
ZS – 0.12V  
TYP  
MAX  
FS + 0.12V  
REF  
UNITS  
V
V
Input Voltage Range  
(Note 14)  
●
●
●
IN  
SET  
REF  
SET  
SET  
FS  
SET  
Full-Scale Set Range  
Zero-Scale Set Range  
Input Sampling Capacitance  
Reference Sampling Capacitance  
Input Leakage Current  
0.1 + ZS  
0
V
V
CC  
ZS  
FS – 0.1  
SET  
V
SET  
C
C
10  
15  
1
pF  
pF  
nA  
nA  
S(IN)  
S(REF)  
I
I
CS = V  
●
●
–10  
–12  
10  
12  
IN(LEAK)  
REF(LEAK)  
CC  
V
= 2.5V, CS = V  
1
Reference Leakage CurreU nt  
REF  
CC  
U
The ● denotes specifications which apply over the full  
DIGITAL I PUTS A D DIGITAL OUTPUTS  
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
2.7V ≤ V ≤ 5.5V  
MIN  
TYP  
MAX  
UNITS  
V
V
V
V
High Level Input Voltage  
●
●
●
●
●
●
2.5  
2.0  
V
V
IH  
IL  
IH  
IL  
CC  
CS, F  
2.7V ≤ V ≤ 3.3V  
O
CC  
Low Level Input Voltage  
CS, F  
4.5V ≤ V ≤ 5.5V  
0.8  
0.6  
V
V
CC  
2.7V ≤ V ≤ 5.5V  
O
CC  
High Level Input Voltage  
SCK  
2.7V ≤ V ≤ 5.5V (Note 9)  
2.5  
2.0  
V
V
CC  
2.7V ≤ V ≤ 3.3V (Note 9)  
CC  
Low Level Input Voltage  
SCK  
4.5V ≤ V ≤ 5.5V (Note 9)  
0.8  
0.6  
V
V
CC  
2.7V ≤ V ≤ 5.5V (Note 9)  
CC  
I
I
Digital Input Current  
0V ≤ V ≤ V  
CC  
–10  
–10  
10  
µA  
µA  
pF  
pF  
V
IN  
IN  
CS, F  
O
Digital Input Current  
SCK  
0V ≤ V ≤ V (Note 9)  
10  
IN  
IN  
CC  
C
C
V
V
V
V
Digital Input Capacitance  
10  
10  
IN  
CS, F  
O
Digital Input Capacitance  
SCK  
(Note 9)  
IN  
High Level Output Voltage  
SDO  
I = –800µA  
O
●
●
●
●
●
V
V
– 0.5  
OH  
OL  
OH  
OL  
CC  
Low Level Output Voltage  
SDO  
I = 1.6mA  
O
0.4  
V
High Level Output Voltage  
SCK  
I = –800µA (Note 10)  
O
– 0.5  
V
CC  
Low Level Output Voltage  
SCK  
I = 1.6mA (Note 10)  
O
0.4  
10  
V
I
High-Z Output Leakage  
SDO  
–10  
µA  
OZ  
W U  
POWER REQUIRE E TS  
The ● denotes specifications which apply over the full operating temperature range,  
otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
Supply Voltage  
Supply Current  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
●
2.7  
5.5  
V
CC  
I
CC  
Conversion Mode  
Sleep Mode  
CS = 0V (Note 12)  
●
●
200  
20  
300  
30  
µA  
µA  
CS = V (Note 12)  
CC  
3
LTC2401/LTC2402  
W U  
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Note 3)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
2.56  
0.5  
TYP  
MAX  
307.2  
390  
UNITS  
kHz  
µs  
f
t
t
t
External Oscillator Frequency Range  
External Oscillator High Period  
External Oscillator Low Period  
Conversion Time  
●
●
●
EOSC  
HEO  
0.5  
390  
µs  
LEO  
F
= 0V  
O
●
●
●
130.86  
157.03  
133.53  
160.23  
EOSC  
136.20  
163.44  
(in kHz)  
ms  
ms  
ms  
CONV  
F = V  
O
CC  
External Oscillator (Note 11)  
20510/f  
f
Internal SCK Frequency  
Internal Oscillator (Note 10)  
External Oscillator (Notes 10, 11)  
19.2  
kHz  
kHz  
ISCK  
f
/8  
EOSC  
D
Internal SCK Duty Cycle  
(Note 10)  
(Note 9)  
(Note 9)  
(Note 9)  
45  
55  
%
kHz  
ns  
ISCK  
f
t
t
t
External SCK Frequency Range  
External SCK Low Period  
●
●
●
2000  
ESCK  
250  
250  
1.64  
LESCK  
External SCK High Period  
ns  
HESCK  
DOUT_ISCK  
Internal SCK 32-Bit Data Output Time  
Internal Oscillator (Notes 10, 12)  
External Oscillator (Notes 10, 11)  
●
●
1.67  
1.70  
ms  
ms  
256/f  
(in kHz)  
EOSC  
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time  
CS ↓ to SDO Low Z  
CS ↑ to SDO High Z  
CS ↓ to SCK ↓  
(Note 9)  
●
●
●
●
●
●
●
●
●
32/f  
(in kHz)  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DOUT_ESCK  
ESCK  
0
0
150  
150  
150  
1
2
(Note 10)  
(Note 9)  
0
3
CS ↓ to SCK ↑  
50  
4
SCK ↓ to SDO Valid  
SDO Hold After SCK ↓  
SCK Set-Up Before CS ↓  
SCK Hold After CS ↓  
200  
KQMAX  
KQMIN  
(Note 5)  
15  
50  
t
t
5
6
50  
Note 1: Absolute Maximum Ratings are those values beyond which the  
life of the device may be impaired.  
Note 2: All voltage values are with respect to GND.  
Note 9: The converter is in external SCK mode of operation such that  
the SCK pin is used as digital input. The frequency of the clock signal  
driving SCK during the data output is fESCK and is expressed in kHz.  
Note 10: The converter is in internal SCK mode of operation such that  
the SCK pin is used as digital output. In this mode of operation, the  
SCK pin has a total equivalent load capacitance CLOAD = 20pF.  
Note 11: The external oscillator is connected to the FO pin. The external  
oscillator frequency, fEOSC, is expressed in kHz.  
Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Input source  
resistance = 0Ω.  
Note 4: Internal Conversion Clock source with the FO pin tied  
to GND or to VCC or to external conversion clock source with  
f
EOSC = 153600Hz unless otherwise specified.  
Note 12: The converter uses the internal oscillator.  
Note 5: Guaranteed by design, not subject to test.  
FO = 0V or FO = VCC  
.
Note 6: Integral nonlinearity is defined as the deviation of a code from  
a straight line passing through the actual endpoints of the transfer  
curve. The deviation is measured from the center of the quantization  
band.  
Note 13: The output noise includes the contribution of the internal  
calibration operations.  
Note 14: VREF = FSSET – ZSSET. The minimum input voltage is limited  
to –0.3V and the maximum to VCC + 0.3V.  
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%  
(external oscillator).  
Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P.  
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%  
(external oscillator).  
4
LTC2401/LTC2402  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Negative Extended Input Range  
Total Unadjusted Error (3V Supply)  
Total Unadjusted Error (3V Supply)  
INL (3V Supply)  
10  
5
10  
5
10  
V
V
= 3V  
REF  
CC  
T
= 25°C  
A
= 2.5V  
T
= 90°C  
A
5
0
T
= 125°C  
A
T
= –55°C, –45°C, 25°C, 90°C  
A
T
A
= –45°C  
0
0
125°C  
T
= –55°C  
A
–5  
–5  
–10  
–5  
–10  
125°C  
V
V
= 3V  
= 2.5V  
CC  
REF  
–10  
–0.3 –0.25 –0.2 –0.15 –0.1 –0.05  
INPUT VOLTAGE (V)  
0
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
24012 G03  
24012 G01  
24012 G02  
Positive Extended Input Range  
Total Unadjusted Error (3V Supply)  
Total Unadjusted Error (5V Supply)  
INL (5V Supply)  
10  
5
10  
5
10  
5
V
V
= 3V  
REF  
V
V
= 5V  
= 5V  
CC  
CC  
REF  
= 2.5V  
T
= –55°C, –45°C, 25°C, 90°C, 125°C  
A
T
= –55°C, –45°C, 25°C, 90°C, 125°C  
A
0
0
0
–5  
–5  
–10  
–5  
–10  
–10  
2.5  
2.55  
2.6  
2.65  
2.7  
2.75  
2.8  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
0
1
2
3
4
5
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
24012 G04  
24012 G06  
24012 G05  
Negative Extended Input Range  
Total Unadjusted Error (5V Supply)  
Positive Extended Input Range  
Total Unadjusted Error (5V Supply)  
Offset Error vs Reference Voltage  
10  
5
10  
5
50  
40  
30  
20  
10  
0
V
T
= 5V  
V
V
= 5V  
= 5V  
CC  
A
CC  
REF  
T
A
= 90°C  
T = 125°C  
A
= 25°C  
T
A
= 25°C  
0
0
T
= –55°C  
= 25°C  
A
T
T
= –45°C  
= –55°C  
A
T
= –45°C  
A
A
–5  
–5  
T
= 90°C  
A
V
V
= 5V  
= 5V  
CC  
REF  
T
= 125°C  
T
A
A
–10  
–10  
5.0  
5.05  
5.1  
5.15  
5.2  
5.25  
5.3  
–0.3 –0.25 –0.2 –0.15 –0.1 –0.05  
INPUT VOLTAGE (V)  
0
0
1
2
3
4
5
INPUT VOLTAGE (V)  
REFERENCE VOLTAGE (V)  
24012 G08  
24012 G07  
24012 G09  
5
LTC2401/LTC2402  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
RMS Noise vs Reference Voltage  
Offset Error vs VCC  
RMS Noise vs VCC  
20  
18  
16  
14  
12  
10  
8
5.0  
2.5  
0
5.0  
2.5  
V
T
= 2.5V  
V
T
= 5V  
V
T
= 2.5V  
REF  
= 25°C  
REF  
CC  
= 25°C  
= 25°C  
A
A
A
6
–2.5  
4
2
–5.0  
0
0
0
1
2
3
4
5
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
V
CC  
V
REFERENCE VOLTAGE (V)  
CC  
24012 G10  
24012 G11  
24012 G12  
Noise Histogram  
RMS Noise vs Code Out  
Offset Error vs Temperature  
350  
300  
5.0  
2.5  
0
1.00  
0.75  
0.50  
0.25  
0
V
V
V
= 5V  
= 5V  
V
V
V
= 5V  
= 5V  
V
V
V
= 5V  
= 5V  
CC  
REF  
IN  
CC  
REF  
IN  
CC  
REF  
IN  
= 0V  
= 0V  
= –0.3V TO 5.3V  
T
= 25°C  
A
250  
200  
150  
100  
50  
–2.5  
0
–2  
–5.0  
–55 –30 –5  
20  
45  
70  
95 120  
–1  
0
1
3
2
2.5  
–0.3  
5.3  
TEMPERATURE (°C)  
OUTPUT CODE (ppm)  
CODE OUT (HEX)  
24012 G15  
24012 G13  
24012 G14  
Full-Scale Error  
vs Reference Voltage  
Full-Scale Error vs Temperature  
Full-Scale Error vs VCC  
60  
50  
5.0  
2.5  
0
6
5
4
V
V
= 5V  
REF  
V
V
V
= 5V  
= 5V  
V
V
= 2.5V  
REF  
CC  
IN  
CC  
REF  
IN  
= V  
= 2.5V  
IN  
= 5V  
T
= 25°C  
A
40  
30  
3
2
1
0
20  
10  
0
–2.5  
–5.0  
–55 –30 –5  
20  
45  
70  
95 120  
0
1
2
3
4
5
2.7  
3.2  
3.7  
4.2  
4.7  
5.2  
TEMPERATURE (°C)  
REFERENCE VOLTAGE (V)  
V
CC  
24012 G16  
24012 G17  
24012 G18  
6
LTC2401/LTC2402  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Conversion Current  
vs Temperature  
Sleep Current vs Temperature  
Rejection vs Frequency at VCC  
30  
20  
10  
0
–60  
–75  
230  
220  
210  
200  
190  
180  
170  
160  
150  
V
V
T
= 4.1V  
= 0V  
CC  
IN  
A
= 25°C  
V
= 5.5V  
= 4.1V  
= 2.7V  
CC  
F
= 0  
O
V
= 2.7V  
CC  
V
CC  
CC  
V
= 5V  
CC  
–90  
V
–105  
–120  
1
100  
10k  
1M  
–30  
–5  
45  
70  
95 120  
–55 –30 –5  
20  
45  
70  
95 120  
–55  
20  
FREQUENCY AT V (Hz)  
TEMPERATURE (°C)  
CC  
TEMPERATURE (°C)  
24012 G21  
24012 G20  
24012 G19  
Rejection vs Frequency at VCC  
Rejection vs Frequency at VCC  
Rejection vs Frequency at VIN  
0
–60  
–75  
–40  
–60  
V
V
T
= 4.1V  
= 0V  
V
V
V
F
= 5V  
= 5V  
V
V
T
= 4.1V  
= 0V  
CC  
IN  
CC  
REF  
IN  
CC  
IN  
–20  
= 25°C  
= 2.5V  
= 25°C  
A
O
A
O
F
= 0  
= 0  
F
= 0  
O
–40  
–60  
–90  
–80  
–80  
–100  
–120  
–105  
–100  
–120  
–120  
15200 15250 15300 15350 15400 15450 15500  
1
50  
100  
150  
200  
250  
0
50  
100  
150  
200  
250  
FREQUENCY AT V (Hz)  
FREQUENCY AT V (Hz)  
CC  
IN  
FREQUENCY AT V (Hz)  
CC  
24012 G23  
24012 G24  
24012 G22  
Rejection vs Frequency at VIN  
Rejection vs Frequency at VIN  
Rejection vs Frequency at VIN  
0
–60  
–70  
0
–20  
–40  
V
V
V
= 5V  
CC  
= 5V  
REF  
–20  
= 2.5V  
IN  
F
O
= 0  
–80  
–40  
–60  
–90  
–60  
–80  
–100  
–110  
–120  
–130  
–140  
–80  
–100  
–120  
–100  
–120  
–140  
SAMPLE RATE = 15.36kHz ±2%  
15100  
15200  
15300  
15400  
15500  
f /2  
S
f
–12  
–8  
–4  
0
4
8
12  
0
S
FREQUENCY AT V (Hz)  
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)  
INPUT FREQUENCY  
IN  
24012 G26  
24012 G25  
24012 G27  
7
LTC2401/LTC2402  
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TYPICAL PERFOR A CE CHARACTERISTICS  
INL vs Output Rate  
Resolution vs Output Rate  
24  
20  
16  
12  
8
24  
20  
16  
12  
8
V
V
O
= 5V  
REF  
= EXTERNAL  
CC  
= 5V  
F
T
= –55°C  
A
T
= 90°C  
A
T
= 25°C  
A
T
= –55°C  
A
T
= 90°C  
A
T
= 25°C  
A
V
V
O
= 5V  
REF  
= EXTERNAL  
CC  
= 5V  
F
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
OUTPUT RATE (Hz)  
OUTPUT RATE (Hz)  
24012 G28  
24012 G29  
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PIN FUNCTIONS  
VCC (Pin 1): Positive Supply Voltage. Bypass to GND  
(Pin 6) with a 10µF tantalum capacitor in parallel with  
0.1µF ceramic capacitor as close to the part as possible.  
be connected directly to a ground plane through a mini-  
mum length trace or it should be the single-point-ground  
in a single-point grounding system.  
FSSET (Pin 2): Full-Scale Set Input. This pin defines the  
full-scale input value. When VIN = FSSET, the ADC outputs  
full scale (FFFFFH). The total reference voltage is  
CS (Pin 7): Active LOW Digital Input. A LOW on this pin  
enables the SDO digital output and wakes up the ADC.  
Following each conversion, the ADC automatically enters  
the Sleep mode and remains in this low power state as  
long as CS is HIGH. A LOW on CS wakes up the ADC. A  
LOW-to-HIGH transition on this pin disables the SDO  
digitaloutput.ALOW-to-HIGHtransitiononCSduringthe  
Data Output transfer aborts the data transfer and starts a  
new conversion.  
FSSET – ZSSET  
.
CH0, CH1 (Pins 4, 3): Analog Input Channels. The input  
voltage range is –0.125 • VREF to 1.125 • VREF. For  
VREF > 2.5V, the input voltage range may be limited by the  
absolute maximum rating of –0.3V to VCC + 0.3V. Conver-  
sions are performed alternately between CH0  
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on  
the LTC2401.  
SDO (Pin 8): Three-State Digital Output. During the data  
output period, this pin is used for serial data output. When  
the chip select CS is HIGH (CS = VCC), the SDO pin is in a  
high impedance state. During the Conversion and Sleep  
periods, this pin can be used as a conversion status out-  
put. The conversion status can be observed by pulling CS  
LOW.  
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the  
zero-scale input value. When VIN = ZSSET, the ADC  
outputs zero scale (00000H).  
GND (Pin 6): Ground. Shared pin for analog ground,  
digitalground,referencegroundandsignalground.Should  
8
LTC2401/LTC2402  
U
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PIN FUNCTIONS  
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal  
SerialClockOperationmode, SCKisusedasdigitaloutput  
fortheinternalserialinterfaceclockduringthedataoutput  
period. In the External Serial Clock Operation mode, SCK  
is used as digital input for the external serial interface. An  
internal pull-up current source is automatically activated  
in Internal Serial Clock Operation mode. The Serial Clock  
mode is determined by the level applied to SCK at power  
up and the falling edge of CS.  
FO (Pin 10): Frequency Control Pin. Digital input that  
controls the ADC’s notch frequencies and conversion  
time. When the FO pin is connected to VCC (FO = VCC), the  
converter uses its internal oscillator and the digital filter’s  
first null is located at 50Hz. When the FO pin is connected  
to GND (FO = 0V), the converter uses its internal oscillator  
and the digital filter’s first null is located at 60Hz. When FO  
isdrivenbyanexternalclocksignalwithafrequencyfEOSC  
,
the converter uses this signal as its clock and the digital  
filter first null is located at a frequency fEOSC/2560.  
U
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FUNCTIONAL BLOCK DIAGRA  
INTERNAL  
OSCILLATOR  
V
CC  
GND  
AUTOCALIBRATION  
AND CONTROL  
F
O
(INT/EXT)  
V
IN  
∫
∫
∫
SDO  
SERIAL  
INTERFACE  
∑
ADC  
SCK  
CS  
V
REF  
DECIMATING FIR  
DAC  
24012 FD  
TEST CIRCUITS  
V
CC  
3.4k  
C
SDO  
SDO  
= 20pF  
3.4k  
C
= 20pF  
LOAD  
LOAD  
Hi-Z TO V  
Hi-Z TO V  
OL  
OH  
OH  
V
V
TO V  
OL  
V
OL  
V
OH  
TO V  
OH  
OL  
TO Hi-Z  
24012 TC02  
TO Hi-Z  
24012 TC01  
9
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
Converter Operation Cycle  
Through timing control of the CS and SCK pins, the  
LTC2401/LTC2402 offer several flexible modes of opera-  
tion (internal or external SCK and free-running conversion  
modes). These various modes do not require program-  
ming configuration registers; moreover, they do not dis-  
turbthecyclicoperationdescribedabove. Thesemodesof  
operation are described in detail in the Serial Interface  
Timing Modes section.  
The LTC2401/LTC2402 are low power, delta-sigma ana-  
log-to-digital converters with an easy to use 3-wire serial  
interface. Their operation is simple and made up of three  
states. The converter operating cycle begins with the  
conversion, followed by a low power sleep state and  
concluded with the data output (see Figure 1). The 3-wire  
interface consists of serial data output (SDO), a serial  
clock (SCK) and a chip select (CS).  
Conversion Clock  
Initially, the LTC2401/LTC2402 perform a conversion.  
Once the conversion is complete, the device enters the  
sleep state. While in this sleep state, power consumption  
is reduced by an order of magnitude. The part remains in  
thesleepstateaslongasCSislogicHIGH. Theconversion  
result is held indefinitely in a static shift register while the  
converter is in the sleep state.  
A major advantage delta-sigma converters offer over  
conventional type converters is an on-chip digital filter  
(commonly known as Sinc or Comb filter). For high  
resolution, low frequency applications, this filter is typi-  
cally designed to reject line frequencies of 50Hz or 60Hz  
plus their harmonics. In order to reject these frequencies  
in excess of 110dB, a highly accurate conversion clock is  
required. The LTC2401/LTC2402 incorporate an on-chip  
highly accurate oscillator. This eliminates the need for  
externalfrequencysettingcomponentssuchascrystalsor  
oscillators.Clockedbytheon-chiposcillator,theLTC2401/  
LTC2402 reject line frequencies (50Hz or 60Hz ±2%) a  
minimum of 110dB.  
Once CS is pulled low, the device begins outputting the  
conversion result. There is no latency in the conversion  
result. The data output corresponds to the conversion just  
performed. This result is shifted out on the serial data out  
pin (SDO) under the control of the serial clock (SCK). Data  
is updated on the falling edge of SCK allowing the user to  
reliably latch data on the rising edge of SCK, see Figure 3.  
The data output state is concluded once 32 bits are read  
out of the ADC or when CS is brought HIGH. The device  
automatically initiates a new conversion cycle and the  
cycle repeats.  
Ease of Use  
The LTC2401/LTC2402 data output has no latency, filter  
settlingorredundantdataassociatedwiththeconversion  
cycle.Thereisaone-to-onecorrespondencebetweenthe  
conversion and the output data. Therefore, multiplexing  
an analog input voltage is easy.  
CONVERT  
SLEEP  
The LTC2401/LTC2402 perform offset and full-scale cali-  
brations every conversion cycle. This calibration is trans-  
parent to the user and has no effect on the cyclic operation  
described above. The advantage of continuous calibration  
is extreme stability of offset and full-scale readings with  
respect to time, supply voltage change and temperature  
drift.  
1
CS AND  
SCK  
0
Power-Up Sequence  
DATA OUTPUT  
The LTC2401/LTC2402 automatically enter an internal  
reset state when the power supply voltage VCC drops  
below approximately 2.2V. This feature guarantees the  
24012 F01  
Figure 1. LTC2401/LTC2402 State Transition Diagram  
10  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
integrityoftheconversionresultandoftheserialinterface  
modeselectionwhichisperformedattheinitialpower-up.  
(See the 2-wire I/O sections in the Serial Interface Timing  
Modes section.)  
U
V
+ 0.3V  
CC  
FS  
+ 0.12V  
FS  
SET  
REF  
SET  
ABSOLUTE  
NORMAL  
EXTENDED  
INPUT  
RANGE  
MAXIMUM  
INPUT  
When the VCC voltage rises above this critical threshold,  
the converter creates an internal power-on-reset (POR)  
signal with duration of approximately 0.5ms. The POR  
signal clears all internal registers. Following the POR  
signal, the LTC2401/LTC2402 start a normal conversion  
cycle and follows the normal succession of states de-  
scribed above. The first conversion result following POR  
is accurate within the specifications of the device.  
INPUT  
RANGE  
RANGE  
ZS  
SET  
REF  
ZS  
SET  
– 0.12V  
–0.3V  
24012 F02  
(V  
REF  
= FS  
– ZS  
)
SET  
SET  
Figure 2. LTC2401/LTC2402 Input Range  
Reference Voltage Range  
The LTC2401/LTC2402 can accept a reference voltage  
the parasitic capacitance of the connection between this  
series resistance and the VIN pin as low as possible;  
therefore, the resistor should be located as close as  
practical to the VIN pin. The effect of the series resistance  
on the converter accuracy can be evaluated from the  
curves presented in the Analog Input/Reference Current  
section. In addition, a series resistor will introduce a  
temperature dependent offset error due to the input leak-  
age current. A 1nA input leakage current will develop a  
1ppm offset error on a 5k resistor if VREF = 5V. This error  
has a very strong temperature dependency.  
(VREF = FSSET – ZSSET) from 0V to VCC. The converter  
output noise is determined by the thermal noise of the  
front-end circuits, and as such, its value in microvolts is  
nearly constant with reference voltage. A decrease in  
reference voltage will not significantly improve the  
converter’s effective resolution. On the other hand, a  
reduced reference voltage will improve the overall con-  
verter INL performance. The recommended range for the  
LTC2401/LTC2402 voltage reference is 100mV to VCC.  
Input Voltage Range  
Output Data Format  
The converter is able to accommodate system level  
offset and gain errors as well as system level overrange  
situations due to its extended input range, see Figure 2.  
The LTC2401/LTC2402 convert input signals within the  
extended input range of –0.125 • VREF to 1.125 • VREF  
(VREF = FSSET – ZSSET).  
The LTC2401/LTC2402 serial output data stream is 32 bits  
long. The first 4 bits represent status information indicat-  
ing the sign, selected channel, input range and conversion  
state. The next 24 bits are the conversion result, MSB first.  
The remaining 4 bits are sub LSBs beyond the 24-bit level  
that may be included in averaging or discarded without  
loss of resolution.  
ForlargevaluesofVREF (VREF =FSSET –ZSSET), thisrange  
is limited by the absolute maximum voltage range of  
–0.3V to (VCC + 0.3V). Beyond this range, the input ESD  
protection devices begin to turn on and the errors due to  
the input leakage current increase rapidly.  
Bit 31 (first output bit) is the end of conversion (EOC)  
indicator. This bit is available at the SDO pin during the  
conversion and sleep states whenever the CS pin is LOW.  
ThisbitisHIGHduringtheconversionandgoesLOWwhen  
the conversion is complete.  
Input signals applied to VIN may extend below ground by  
–300mV and above VCC by 300mV. In order to limit any  
fault current, a resistor of up to 5k may be added in series  
with the VIN pin without affecting the performance of the  
device. In the physical layout, it is important to maintain  
Bit 30 (second output bit) for the LTC2402, this bit is LOW  
if the last conversion was performed on CH0 and HIGH for  
CH1. This bit is always low for the LTC2401.  
11  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
Bit 29 (third output bit) is the conversion result sign indi-  
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this  
bitisLOW.Thesignbitchangesstateduringthezerocode.  
HIGH to LOW at the completion of a conversion. This  
signal may be used as an interrupt for an external micro-  
controller. Bit 31 (EOC) can be captured on the first rising  
edge of SCK. Bit 30 is shifted out of the device on the first  
falling edge of SCK. The final data bit (Bit 0) is shifted out  
on the falling edge of the 31st SCK and may be latched on  
the rising edge of the 32nd SCK pulse. On the falling edge  
of the 32nd SCK pulse, SDO goes HIGH indicating a new  
conversion cycle has been initiated. This bit serves as EOC  
(Bit 31) for the next conversion cycle. Table 2 summarizes  
the output data format.  
Bit 28 (forth output bit) is the extended input range (EXR)  
indicator. If the input is within the normal input range  
0 ≤ VIN ≤ VREF, this bit is LOW. If the input is outside the  
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.  
The function of these bits is summarized in Table 1.  
Table 1. LTC2401/LTC2402 Status Bits  
Bit 31  
EOC  
Bit 30  
CH0/CH1  
Bit 29  
SIG  
Bit 28  
EXR  
Input Range  
> V  
As long as the voltage on the VIN pin is maintained within  
the –0.3V to (VCC + 0.3V) absolute maximum operating  
range, a conversion result is generated for any input value  
from –0.125 • VREF to 1.125 • VREF. For input voltages  
greaterthan1.125•VREF,theconversionresultisclamped  
to the value corresponding to 1.125 • VREF. For input  
voltages below –0.125 • VREF, the conversion result is  
V
0
0
0
0
0/1  
0/1  
0/1  
0/1  
1
1
1
0
0
1
IN  
REF  
0 < V ≤ V  
IN  
REF  
+
–
V
V
= 0 /0  
1/0  
0
IN  
IN  
< 0  
Bit 27 (fifth output bit) is the most significant bit (MSB).  
Bits 27-4 are the 24-bit conversion result MSB first.  
Bit 4 is the least significant bit (LSB).  
clamped to the value corresponding to –0.125 • VREF  
.
Frequency Rejection Selection (FO Pin Connection)  
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may  
be included in averaging or discarded without loss of  
resolution.  
The LTC2401/LTC2402 internal oscillator provides better  
than 110dB normal mode rejection at the line frequency  
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For  
60Hz rejection, FO (Pin 10) should be connected to GND  
(Pin 6) while for 50Hz rejection the FO pin should be  
connected to VCC (Pin 1).  
DataisshiftedoutoftheSDOpinundercontroloftheserial  
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO  
remains high impedance and any SCK clock pulses are  
ignored by the internal data out shift register.  
The selection of 50Hz or 60Hz rejection can also be made  
by driving FO to an appropriate logic level. A selection  
change during the sleep or data output states will not  
In order to shift the conversion result out of the device, CS  
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe  
deviceonceCSispulledLOW.EOCchangesrealtimefrom  
CS  
BIT 31  
EOC  
BIT 30  
BIT 29  
SIG  
BIT 28  
EXT  
BIT 27  
MSB  
BIT 4  
BIT 0  
SDO  
SCK  
LSB  
24  
CH0/CH1  
Hi-Z  
1
2
3
4
5
27  
28  
32  
SLEEP  
DATA OUTPUT  
CONVERSION  
24012 F03  
Figure 3. Output Data Timing  
12  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
U
Table 2. LTC2401/LTC2402 Output Data Format  
Bit 31  
EOC  
Bit 30  
CH SELECT  
Bit 29  
SIG  
Bit 28  
EXR  
Bit 27  
MSB  
Bit 26  
Bit 25  
Bit 24  
Bit 23  
…
Bit 4  
Bit 3-0  
Input Voltage  
> 9/8 • V  
LSB SUB LSBs*  
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
CH0/CH1  
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
1
1
0
1
0
1
0
1
0
1
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IN  
REF  
9/8 • V  
1
REF  
V
V
+ 1LSB  
1
REF  
REF  
1
3/4V + 1LSB  
1
REF  
3/4V  
1
REF  
1/2V + 1LSB  
1
REF  
1/2V  
1
REF  
1/4V + 1LSB  
1
REF  
1/4V  
1
REF  
+
–
0 /0  
1/0**  
–1LSB  
0
0
0
–1/8 • V  
REF  
V
< –1/8 • V  
REF  
IN  
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.  
**The sign bit changes state during the 0 code.  
disturb the converter operation. If the selection is made  
duringtheconversionstate, theresultoftheconversionin  
progress may be outside specifications but the following  
conversions will not be affected.  
Whenever an external clock is not present at the FO pin, the  
converterautomaticallyactivatesitsinternaloscillatorand  
enters the Internal Conversion Clock mode. The LTC2401/  
LTC2402 operation will not be disturbed if the change of  
conversion clock source occurs during the sleep state or  
during the data output state while the converter uses an  
When a fundamental rejection frequency different from  
50Hz or 60Hz is required or when the converter must be  
synchronized with an outside source, the LTC2401/  
LTC2402 can operate with an external conversion clock.  
The converter automatically detects the presence of an  
external clock signal at the FO pin and turns off the internal  
oscillator. The frequency fEOSC of the external signal must  
be at least 2560Hz (1Hz notch frequency) to be detected.  
The external clock signal duty cycle is not significant as  
long as the minimum and maximum specifications for the  
high and low periods tHEO and tLEO are observed.  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
While operating with an external conversion clock of a  
frequency fEOSC, the LTC2401/LTC2402 provide better  
than 110dB normal mode rejection in a frequency range  
fEOSC/2560 ±4% and its harmonics. The normal mode  
rejection as a function of the input frequency deviation  
from fEOSC/2560 is shown in Figure 4.  
–12  
–8  
–4  
0
4
8
12  
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)  
24012 F04  
Figure 4. LTC2401/LTC2402 Normal Mode Rejection When  
Using an External Oscillator of Frequency fEOSC  
13  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
external serial clock. If the change occurs during the  
conversion state, the result of the conversion in progress  
may be outside specifications but the following conver-  
sions will not be affected. If the change occurs during the  
data output state and the converter is in the Internal SCK  
mode, the serial clock duty cycle may be affected but the  
serial data stream will remain valid.  
input. The internal or external SCK mode is selected on  
power-up and then reselected every time a HIGH-to-LOW  
transition is detected at the CS pin. If SCK is HIGH or float-  
ing at power-up or during this transition, the converter  
enters the internal SCK mode. If SCK is LOW at power-up  
or during this transition, the converter enters the external  
SCK mode.  
Table 3 summarizes the duration of each state as a  
function of FO.  
Serial Data Output (SDO)  
The serial data output pin, SDO (Pin 8), drives the serial  
data during the data output state. In addition, the SDO pin  
is used as an end of conversion indicator during the  
conversion and sleep states.  
SERIAL INTERFACE  
The LTC2401/LTC2402 transmit the conversion results  
and receives the start of conversion command through a  
synchronous 3-wire interface. During the conversion and  
sleep states, this interface can be used to assess the  
converter status and during the data output state it is used  
to read the conversion result.  
When CS (Pin 7) is HIGH, the SDO driver is switched to a  
high impedance state. This allows sharing the serial  
interface with other devices. If CS is LOW during the  
convert or sleep state, SDO will output EOC. If CS is LOW  
duringtheconversionphase, theEOCbitappearsHIGHon  
the SDO pin. Once the conversion is complete, EOC goes  
LOW. The device remains in the sleep state until the first  
rising edge of SCK occurs while CS = 0.  
Serial Clock Input/Output (SCK)  
The serial clock signal present on SCK (Pin 9) is used to  
synchronizethedatatransfer.Eachbitofdataisshiftedout  
the SDO pin on the falling edge of the serial clock.  
Chip Select Input (CS)  
In the Internal SCK mode of operation, the SCK pin is an  
output and the LTC2401/LTC2402 create their own serial  
clock by dividing the internal conversion clock by 8. In the  
External SCK mode of operation, the SCK pin is used as  
The active LOW chip select, CS (Pin 7), is used to test the  
conversionstatusandtoenablethedataoutputtransferas  
described in the previous sections.  
Table 3. LTC2401/LTC2402 State Duration  
State  
Operating Mode  
Duration  
CONVERT  
Internal Oscillator  
F = LOW  
(60Hz Rejection)  
133ms  
O
F = HIGH  
O
160ms  
(50Hz Rejection)  
External Oscillator  
F = External Oscillator  
20510/f  
s
EOSC  
O
with Frequency f  
kHz  
EOSC  
(f  
EOSC  
/2560 Rejection)  
SLEEP  
As Long As CS = HIGH Until CS = 0 and SCK  
DATA OUTPUT  
Internal Serial Clock  
External Serial Clock with  
F = LOW/HIGH  
(Internal Oscillator)  
As Long As CS = LOW But Not Longer Than 1.67ms  
(32 SCK cycles)  
O
F = External Oscillator with  
As Long As CS = LOW But Not Longer Than 256/f  
ms  
EOSC  
O
Frequency f  
kHz  
(32 SCK cycles)  
EOSC  
As Long As CS = LOW But Not Longer Than 32/f ms  
SCK  
Frequency f  
kHz  
(32 SCK cycles)  
SCK  
14  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
U
In addition, the CS signal can be used to trigger a new  
conversion cycle before the entire serial data transfer has  
been completed. The LTC2401/LTC2402 will abort any  
serial data transfer in progress and start a new conversion  
cycle anytime a LOW-to-HIGH transition is detected at the  
CSpinaftertheconverterhasenteredthedataoutputstate  
(i.e., after the first rising edge of SCK occurs with CS = 0).  
The serial clock mode is selected on the falling edge of CS.  
Toselecttheexternalserialclockmode,theserialclockpin  
(SCK) must be LOW during each CS falling edge.  
The serial data output pin (SDO) is Hi-Z as long as CS is  
HIGH. At any time during the conversion cycle, CS may be  
pulled LOW in order to monitor the state of the converter.  
While CS is pulled LOW, EOC is output to the SDO pin. EOC  
= 1 while a conversion is in progress and EOC = 0 if the  
device is in the sleep state. Independent of CS, the device  
automatically enters the low power sleep state once the  
conversion is complete.  
Finally, CS can be used to control the free-running modes  
of operation, see Serial Interface Timing Modes section.  
Grounding CS will force the ADC to continuously convert  
at the maximum output rate selected by FO. Tying a  
capacitor to CS will reduce the output rate and power  
dissipation by a factor proportional to the capacitor’s  
value, see Figures 12 to 14.  
When the device is in the sleep state (EOC = 0), its  
conversion result is held in an internal static shift register.  
The device remains in the sleep state until the first rising  
edge of SCK is seen while CS is LOW. Data is shifted out  
the SDO pin on each falling edge of SCK. This enables  
external circuitry to latch the output on the rising edge of  
SCK. EOC can be latched on the first rising edge of SCK  
and the last bit of the conversion result can be latched on  
the 32nd rising edge of SCK. On the 32nd falling edge of  
SCK, thedevicebeginsanewconversion. SDOgoesHIGH  
(EOC = 1) indicating a conversion is in progress.  
SERIAL INTERFACE TIMING MODES  
The LTC2401/LTC2402’s 3-wire interface is SPI and  
MICROWIRE compatible. This interface offers several  
flexible modes of operation. These include internal/exter-  
nal serial clock, 2- or 3-wire I/O, single cycle conversion  
and autostart. The following sections describe each of  
these serial interface timing modes in detail. In all these  
cases, the converter can use the internal oscillator (FO =  
LOW or FO = HIGH) or an external oscillator connected to  
the FO pin. Refer to Table 4 for a summary.  
At the conclusion of the data cycle, CS may remain LOW  
and EOC monitored as an end-of-conversion interrupt.  
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.  
As described above, CS may be pulled LOW at any time in  
order to monitor the conversion status.  
External Serial Clock, Single Cycle Operation  
(SPI/MICROWIRE Compatible)  
Typically, CS remains LOW during the data output state.  
However, the data output state may be aborted by pulling  
CS HIGH anytime between the first rising edge and the  
32nd falling edge of SCK, see Figure 6. On the rising edge  
This timing mode uses an external serial clock to shift out  
the conversion result and a CS signal to monitor and  
control the state of the conversion cycle, see Figure 5.  
Table 4. LTC2401/LTC2402 Interface Timing Modes  
SCK  
Conversion  
Cycle  
Control  
Data  
Output  
Control  
Connection  
and  
Waveforms  
Configuration  
Source  
External  
External  
Internal  
Internal  
Internal  
External SCK, Single Cycle Conversion  
External SCK, 2-Wire I/O  
CS and SCK  
SCK  
CS and SCK  
SCK  
Figures 5, 6  
Figure 7  
Internal SCK, Single Cycle Conversion  
Internal SCK, 2-Wire I/O, Continuous Conversion  
Internal SCK, Autostart Conversion  
CS ↓  
CS ↓  
Figures 8, 9  
Figure 10  
Figure 11  
Continuous  
Internal  
Internal  
C
EXT  
15  
LTC2401/LTC2402  
APPLICATIO S I FOR ATIO  
W U U  
U
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
9
8
7
6
REFERENCE VOLTAGE  
ZS + 0.1V TO V  
FS  
SCK  
SDO  
CS  
SET  
SET CC  
3
4
5
3-WIRE  
SERIAL I/O  
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
REF  
(V  
= FS  
– ZS  
)
REF  
SET  
SET  
0V TO FS  
SET  
– 100mV  
GND  
SET  
CS  
TEST EOC  
TEST EOC  
TEST EOC  
BIT 31  
EOC  
BIT 30  
CH0/CH1  
BIT 29  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 26  
BIT 4  
LSB  
BIT 0  
SDO  
SUB LSB  
Hi-Z  
Hi-Z  
Hi-Z  
SCK  
(EXTERNAL)  
CONVERSION  
SLEEP  
DATA OUTPUT  
CONVERSION  
24012 F05  
Figure 5. External Serial Clock, Single Cycle Operation  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
1
10  
V
F
O
CC  
LTC2402  
2
3
4
5
9
8
7
6
REFERENCE VOLTAGE  
FS  
SET  
SCK  
SDO  
CS  
ZS  
+ 0.1V TO V  
SET  
CC  
3-WIRE  
SERIAL I/O  
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
REF  
(V  
= FS  
SET  
– ZS  
)
REF  
SET  
0V TO FS  
SET  
– 100mV  
GND  
SET  
CS  
TEST EOC  
TEST EOC  
TEST EOC  
BIT 0  
EOC  
BIT 31  
EOC  
BIT 30  
BIT 29  
SIG  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 9  
BIT 8  
SDO  
CH0/CH1  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
SCK  
(EXTERNAL)  
SLEEP  
CONVERSION  
DATA OUTPUT  
SLEEP  
DATA OUTPUT  
CONVERSION  
24012 F06  
Figure 6. External Serial Clock, Reduced Data Output Length  
16  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
U
of CS, the device aborts the data output state and imme-  
diately initiates a new conversion. This is useful for  
systems not requiring all 32 bits of output data, aborting  
an invalid conversion cycle or synchronizing the start of a  
conversion.  
progress and EOC = 0 once the conversion enters the low  
power sleep state. On the falling edge of EOC, the conver-  
sion result is loaded into an internal static shift register.  
The device remains in the sleep state until the first rising  
edge of SCK. Data is shifted out the SDO pin on each  
falling edge of SCK enabling external circuitry to latch  
data on the rising edge of SCK. EOC can be latched on the  
first rising edge of SCK. On the 32nd falling edge of SCK,  
SDO goes HIGH (EOC = 1) indicating a new conversion  
has begun.  
External Serial Clock, 2-Wire I/O  
This timing mode utilizes a 2-wire serial I/O interface. The  
conversion result is shifted out of the device by an exter-  
nally generated serial clock (SCK) signal, see Figure 7. CS  
maybepermanentlytiedtoground(Pin6),simplifyingthe  
user interface or isolation barrier.  
Internal Serial Clock, Single Cycle Operation  
This timing mode uses an internal serial clock to shift out  
the conversion result and a CS signal to monitor and  
control the state of the conversion cycle, see Figure 8.  
The external serial clock mode is selected at the end of the  
power-on reset (POR) cycle. The POR cycle is concluded  
approximately 0.5ms after VCC exceeds 2.2V. The level  
applied to SCK at this time determines if SCK is internal or  
external. SCK must be driven LOW prior to the end of POR  
in order to enter the external serial clock timing mode.  
In order to select the internal serial clock timing mode, the  
serial clock pin (SCK) must be floating (Hi-Z) or pulled  
HIGH prior to the falling edge of CS. The device will not  
enter the internal serial clock mode if SCK is driven LOW  
on the falling edge of CS. An internal weak pull-up resistor  
is active on the SCK pin during the falling edge of CS;  
therefore, the internal serial clock timing mode is auto-  
matically selected if SCK is not externally driven.  
Since CS is tied LOW, the end-of-conversion (EOC) can  
be continuously monitored at the SDO pin during the  
convert and sleep states. EOC may be used as an inter-  
rupt to an external controller indicating the conversion  
result is ready. EOC = 1 while the conversion is in  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
3
4
5
9
8
7
6
REFERENCE VOLTAGE  
FS  
SET  
SCK  
SDO  
CS  
ZS  
+ 0.1V TO V  
SET  
CC  
2-WIRE SERIAL I/O  
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
REF  
(V  
= FS  
– ZS  
)
REF  
SET  
SET  
0V TO FS  
SET  
– 100mV  
GND  
SET  
CS  
BIT 31  
EOC  
BIT 30  
CH0/CH1  
BIT 29  
SIG  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 26  
BIT 4  
LSB  
BIT 0  
SDO  
24  
SCK  
(EXTERNAL)  
CONVERSION  
SLEEP  
DATA OUTPUT  
CONVERSION  
24012 F07  
Figure 7. External Serial Clock, CS = 0 Operation  
17  
LTC2401/LTC2402  
APPLICATIO S I FOR ATIO  
W U U  
U
V
CC  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
10k  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
9
8
7
6
REFERENCE VOLTAGE  
ZS + 0.1V TO V  
FS  
SET  
SCK  
SDO  
CS  
SET CC  
3
4
5
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
REF  
(V  
= FS  
SET  
– ZS  
)
REF  
SET  
0V TO FS  
SET  
– 100mV  
GND  
SET  
<t  
EOCtest  
CS  
TEST EOC  
TEST EOC  
BIT 31  
EOC  
BIT 30  
BIT 29  
SIG  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 26  
BIT 4  
BIT 0  
SDO  
CH0/CH1  
LSB  
24  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
SCK  
(INTERNAL)  
CONVERSION  
SLEEP  
DATA OUTPUT  
CONVERSION  
2400 F08  
Figure 8. Internal Serial Clock, Single Cycle Operation  
If CS remains LOW longer than tEOCtest, the first rising  
edge of SCK will occur and the conversion result is serially  
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson  
this first rising edge of SCK and concludes after the 32nd  
rising edge. Data is shifted out the SDO pin on each falling  
edgeofSCK.Theinternallygeneratedserialclockisoutput  
to the SCK pin. This signal may be used to shift the  
conversion result into external circuitry. EOC can be  
latchedonthefirstrisingedgeofSCKandthelastbitofthe  
conversionresultonthe32ndrisingedgeofSCK. Afterthe  
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays  
HIGH, and a new conversion starts.  
The serial data output pin (SDO) is Hi-Z as long as CS is  
HIGH. At any time during the conversion cycle, CS may be  
pulled LOW in order to monitor the state of the converter.  
Once CS is pulled LOW, SCK goes LOW and EOC is output  
to the SDO pin. EOC = 1 while a conversion is in progress  
and EOC = 0 if the device is in the sleep state.  
WhentestingEOC,iftheconversioniscomplete(EOC=0),  
thedevicewillexitthesleepstateandenterthedataoutput  
state if CS remains LOW. In order to prevent the device  
from exiting the low power sleep state, CS must be pulled  
HIGH before the first rising edge of SCK. In the internal  
SCK timing mode, SCK goes HIGH and the device begins  
outputting data at time tEOCtest after the falling edge of CS  
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW  
duringthefallingedgeofEOC).ThevalueoftEOCtest is23µs  
if the device is using its internal oscillator (F0 = logic LOW  
or HIGH). If FO is driven by an external oscillator of  
frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled  
HIGH before time tEOCtest, the device remains in the sleep  
state. The conversion result is held in the internal static  
shift register.  
Typically, CS remains LOW during the data output state.  
However, the data output state may be aborted by pulling  
CS HIGH anytime between the first and 32nd rising edge  
of SCK, see Figure 9. On the rising edge of CS, the device  
aborts the data output state and immediately initiates a  
new conversion. This is useful for systems not requiring  
all 32 bits of output data, aborting an invalid conversion  
cycle, or synchronizing the start of a conversion. If CS is  
pulled HIGH while the converter is driving SCK LOW, the  
18  
LTC2401/LTC2402  
W U U  
APPLICATIO S I FOR ATIO  
U
V
CC  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
10k  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
3
4
5
9
8
7
6
REFERENCE VOLTAGE  
FS  
SET  
SCK  
SDO  
CS  
ZS  
+ 0.1V TO V  
SET  
CC  
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
SET  
FS  
REF  
+ 0.12V  
SET  
REF  
(V  
= FS  
SET  
– ZS  
)
REF  
SET  
0V TO FS  
SET  
– 100mV  
GND  
SET  
>t  
EOCtest  
<t  
EOCtest  
CS  
TEST EOC  
TEST EOC  
TEST EOC  
BIT 0  
EOC  
BIT 31  
EOC  
BIT 30  
CH0/CH1  
BIT 29  
SIG  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 26  
BIT 8  
SDO  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
SCK  
(INTERNAL)  
SLEEP  
CONVERSION  
DATA OUTPUT  
SLEEP  
DATA OUTPUT  
CONVERSION  
24012 F09  
Figure 9. Internal Serial Clock, Reduced Data Output Length  
internal pull-up is not available to restore SCK to a logic  
HIGH state. This will cause the device to exit the internal  
serial clock mode on the next falling edge of CS. This can  
be avoided by adding an external 10k pull-up resistor to  
the SCK pin or by never pulling CS HIGH when SCK is  
LOW.  
A similar situation may occur during the sleep state when  
CS is pulsed HIGH-LOW-HIGH in order to test the conver-  
sionstatus. Ifthedeviceisinthesleepstate(EOC=0), SCK  
will go LOW. Once CS goes HIGH (within the time period  
defined above as tEOCtest), the internal pull-up is activated.  
For a heavy capacitive load on the SCK pin, the internal  
pull-up may not be adequate to return SCK to a HIGH level  
before CS goes low again. This is not a concern under  
normal conditions where CS remains LOW after detecting  
EOC = 0. This situation is easily overcome by adding an  
external 10k pull-up resistor to the SCK pin.  
Whenever SCK is LOW, the LTC2401/LTC2402’s internal  
pull-up at pin SCK is disabled. Normally, SCK is not  
externally driven if the device is in the internal SCK timing  
mode. However, certain applications may require an ex-  
ternal driver on SCK. If this driver goes Hi-Z after output-  
ting a LOW signal, the LTC2401/LTC2402’s internal pull-  
up remains disabled. Hence, SCK remains LOW. On the  
next falling edge of CS, the device is switched to the  
externalSCKtimingmode. Byaddinganexternal10kpull-  
up resistor to SCK, this pin goes HIGH once the external  
driver goes Hi-Z. On the next CS falling edge, the device  
will remain in the internal SCK timing mode.  
Internal Serial Clock, 2-Wire I/O,  
Continuous Conversion  
This timing mode uses a 2-wire, all output (SCK and SDO)  
interface. The conversion result is shifted out of the device  
by an internally generated serial clock (SCK) signal, see  
Figure 10. CS may be permanently tied to ground (Pin 6),  
simplifying the user interface or isolation barrier.  
19  
LTC2401/LTC2402  
APPLICATIO S I FOR ATIO  
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U
V
CC  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
10k  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
9
8
7
6
REFERENCE VOLTAGE  
ZS + 0.1V TO V  
FS  
SET  
SCK  
SDO  
CS  
SET  
CC  
3
4
5
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
REF  
)
SET  
SET  
FS  
REF  
+ 0.12V  
SET  
(V  
= FS  
– ZS  
REF  
SET  
0V TO FS  
– 100mV  
GND  
SET  
SET  
CS  
BIT 31  
EOC  
BIT 30  
BIT 29  
SIG  
BIT 28  
EXR  
BIT 27  
MSB  
BIT 26  
BIT 4  
LSB  
BIT 0  
SDO  
CH0/CH1  
24  
SCK  
(INTERNAL)  
CONVERSION  
DATA OUTPUT  
CONVERSION  
24012 F10  
SLEEP  
Figure 10. Internal Serial Clock, Continuous Operation  
The internal serial clock mode is selected at the end of the  
power-on reset (POR) cycle. The POR cycle is concluded  
approximately 0.5ms after VCC exceeds 2.2V. An internal  
weak pull-up is active during the POR cycle; therefore, the  
internal serial clock timing mode is automatically selected  
if SCK is not externally driven LOW (if SCK is loaded such  
that the internal pull-up cannot pull the pin HIGH, the  
external SCK mode will be selected).  
rising edge of SCK. After the 32nd rising edge, SDO goes  
HIGH(EOC=1)indicatinganewconversionisinprogress.  
SCK remains HIGH during the conversion.  
Internal Serial Clock, Autostart Conversion  
This timing mode is identical to the internal serial clock,  
2-wire I/O described above with one additional feature.  
Instead of grounding CS, an external timing capacitor is  
tied to CS.  
During the conversion, the SCK and the serial data output  
pin (SDO) are HIGH (EOC = 1). Once the conversion is  
complete, SCK and SDO go LOW (EOC = 0) indicating the  
conversion has finished and the device has entered the  
low power sleep state. The part remains in the sleep state  
a minimum amount of time (1/2 the internal SCK period)  
thenimmediatelybeginsoutputtingdata.Thedataoutput  
cyclebeginsonthefirstrisingedgeofSCKandendsafter  
the 32nd rising edge. Data is shifted out the SDO pin on  
each falling edge of SCK. The internally generated serial  
clock is output to the SCK pin. This signal may be used  
to shift the conversion result into external circuitry. EOC  
can be latched on the first rising edge of SCK and the last  
bit of the conversion result can be latched on the 32nd  
While the conversion is in progress, the CS pin is held  
HIGH by an internal weak pull-up. Once the conversion is  
complete, the device enters the low power sleep state and  
an internal 25nA current source begins discharging the  
capacitor tied to CS, see Figure 11. The time the converter  
spends in the sleep state is determined by the value of the  
external timing capacitor, see Figures 12 and 13. Once the  
voltageatCSfallsbelowaninternalthreshold(≈1.4V), the  
device automatically begins outputting data. The data  
output cycle begins on the first rising edge of SCK and  
ends on the 32nd rising edge. Data is shifted out the SDO  
pin on each falling edge of SCK. The internally generated  
serial clock is output to the SCK pin. This signal may be  
20  
LTC2401/LTC2402  
W U U  
APPLICATIO S I FOR ATIO  
U
V
CC  
2.7V TO 5.5V  
V
CC  
1µF  
= INTERNAL OSC/50Hz REJECTION  
10k  
1
10  
= EXTERNAL CLOCK SOURCE  
= INTERNAL OSC/60Hz REJECTION  
V
F
O
CC  
LTC2402  
2
9
8
7
6
REFERENCE VOLTAGE  
ZS + 0.1V TO V  
FS  
SCK  
SDO  
CS  
SET  
SET  
CC  
3
4
5
ANALOG INPUT RANGE  
CH1  
CH0  
ZS  
ZS  
– 0.12V  
TO  
REF  
)
SET  
SET  
FS  
REF  
+ 0.12V  
SET  
(V  
= FS  
– ZS  
REF  
SET  
C
EXT  
0V TO FS  
– 100mV  
GND  
SET  
SET  
V
CC  
CS  
GND  
BIT 31  
EOC  
BIT 30  
CH0/CH1  
BIT 29  
SIG  
BIT 0  
SDO  
Hi-Z  
Hi-Z  
SCK  
(INTERNAL)  
CONVERSION  
DATA OUTPUT  
CONVERSION  
SLEEP  
24012 F11  
Figure 11. Internal Serial Clock, Autostart Operation  
7
6
8
7
6
5
5
4
3
2
1
V
CC  
= 5V  
V
= 3V  
CC  
4
3
2
V
= 5V  
CC  
1
0
V
= 3V  
CC  
0
1
10  
100  
100000  
10  
100  
10000  
100000  
1000  
10000  
0
1000  
CAPACITANCE ON CS (pF)  
CAPACITANCE ON CS (pF)  
24012 F12  
24012 F13  
Figure 12. CS Capacitance vs tSAMPLE  
Figure 13. CS Capacitance vs Output Rate  
21  
LTC2401/LTC2402  
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APPLICATIO S I FOR ATIO  
used to shift the conversion result into external circuitry.  
After the 32nd rising edge, CS is pulled HIGH and a new  
conversion is immediately started. This is useful in appli-  
cations requiring periodic monitoring and ultralow power.  
Figure 14 shows the average supply current as a function  
of capacitance on CS.  
as 100µs. However, some considerations are required to  
take advantage of exceptional accuracy and low supply  
current.  
The digital output signals (SDO and SCK in Internal SCK  
mode of operation) are less of a concern because they are  
not generally active during the conversion state.  
It should be noticed that the external capacitor discharge  
current is kept very small in order to decrease the con-  
verter power dissipation in the sleep state. In the autostart  
modetheanalogvoltageontheCSpincannotbeobserved  
without disturbing the converter operation using a regular  
oscilloscope probe. When using this configuration, it is  
important to minimize the external leakage current at the  
CS pin by using a low leakage external capacitor and  
properly cleaning the PCB surface.  
In order to preserve the LTC2401/LTC2402’s accuracy, it  
is very important to minimize the ground path impedance  
whichmayappearinserieswiththeinputand/orreference  
signal and to reduce the current which may flow through  
this path. The GND pin should be connected to a low  
resistance ground plane through a minimum length trace.  
The use of multiple via holes is recommended to further  
reduce the connection resistance.  
Inanalternativeconfiguration,theGNDpinoftheconverter  
canbethesingle-point-groundinasinglepointgrounding  
system. The input signal ground, the reference signal  
ground, the digital drivers ground (usually the digital  
ground)andthepowersupplyground(theanalogground)  
should be connected in a star configuration with the com-  
mon point located as close to the GND pin as possible.  
The internal serial clock mode is selected every time the  
voltage on the CS pin crosses an internal threshold volt-  
age. An internal weak pull-up at the SCK pin is active while  
CS is discharging; therefore, the internal serial clock  
timing mode is automatically selected if SCK is floating. It  
is important to ensure there are no external drivers pulling  
SCK LOW while CS is discharging.  
The power supply current during the conversion state  
should be kept to a minimum. This is achieved by restrict-  
ing the number of digital signal transitions occurring  
during this period.  
300  
250  
V
V
= 5V  
= 3V  
CC  
CC  
200  
150  
While a digital input signal is in the range 0.5V to  
(VCC – 0.5V), the CMOS input receiver draws additional  
current from the power supply. It should be noted that,  
when any one of the digital input signals (FO, CS and SCK  
inExternalSCKmodeofoperation)iswithinthisrange,the  
LTC2401/LTC2402 power supply current may increase  
even if the signal in question is at a valid logic level. For  
micropower operation and in order to minimize the poten-  
tial errors due to additional ground pin current, it is  
recommendedtodrivealldigitalinputsignalstofullCMOS  
levels [VIL < 0.4V and VOH > (VCC – 0.4V)].  
100  
50  
0
1
10  
100  
1000  
10000 100000  
CAPACITANCE ON CS (pF)  
24012 F14  
Figure 14. CS Capacitance vs Supply Current  
Severe ground pin current disturbances can also occur  
due to the undershoot of fast digital input signals. Under-  
shootandovershootcanoccurbecauseoftheimpedance  
mismatch at the converter pin when the transition time of  
an external control signal is less than twice the propaga-  
tion delay from the driver to LTC2401/LTC2402. For  
DIGITAL SIGNAL LEVELS  
The LTC2401/LTC2402’s digital interface is easy to use.  
Its digital inputs (FO, CS and SCK in External SCK mode of  
operation)acceptstandardTTL/CMOSlogiclevelsandthe  
internalhysteresisreceiverscantolerateedgeratesasslow  
22  
LTC2401/LTC2402  
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reference, on a regular FR-4 board, signal propagation  
velocity is approximately 183ps/inch for internal traces  
and 170ps/inch for surface traces. Thus, a driver gener-  
ating a control signal with a minimum transition time of  
1ns must be connected to the converter pin through a  
trace shorter than 2.5 inches. This problem becomes  
particularly difficult when shared control lines are used  
and multiple reflections may occur. The solution is to  
carefully terminate all transmission lines close to their  
characteristic impedance.  
LTC2401/LTC2402’sinternalswitchedcapacitornetwork  
is clocked at 153,600Hz corresponding to a 6.5µs sam-  
pling period. Fourteen time constants are required each  
time a capacitor is switched in order to achieve 1ppm  
settling accuracy.  
Therefore, the equivalent time constant at VIN and VREF  
should be less than 6.5µs/14 = 460ns in order to achieve  
1ppm accuracy.  
Input Current (VIN)  
Parallel termination near the LTC2401/LTC2402 pin will  
eliminate this problem but will increase the driver power  
dissipation. A series resistor between 27Ω and 56Ω  
placed near the driver or near the LTC2401/LTC2402 pin  
will also eliminate this problem without additional power  
dissipation. The actual resistor value depends upon the  
trace impedance and connection topology.  
Ifcompletesettlingoccursontheinput,conversionresults  
will be uneffected by the dynamic input current. If the  
settling is incomplete, it does not degrade the linearity  
performance of the device. It simply results in an offset/  
full-scale shift, see Figure 16. To simplify the analysis of  
input dynamic current, two separate cases are assumed:  
large capacitance at VIN (CIN > 0.01µF) and small capaci-  
tance at VIN (CIN < 0.01µF).  
Driving the Input and Reference  
The analog input and reference of the typical delta-sigma  
analog-to-digital converter are applied to a switched ca-  
pacitor network. This network consists of capacitors  
switching between the analog input (VIN), ZSSET (Pin 5)  
and FSSET (Pin 2). The result is small current spikes seen  
at both VIN and VREF. A simplified input equivalent circuit  
is shown in Figure 15.  
TUE  
The key to understanding the effects of this dynamic  
input current is based on a simple first order RC time  
constant model. Using the internal oscillator, the  
ZS  
SET  
FS  
SET  
V
IN  
24012 F16  
V
CC  
Figure 16. Offset/Full-Scale Shift  
R
SW  
5k  
I
I
REF(LEAK)  
REF(LEAK)  
FS  
SET  
If the total capacitance at VIN (see Figure 17) is small  
(<0.01µF), relatively large external source resistances (up  
to 20k for 20pF parasitic capacitance) can be tolerated  
withoutanyoffset/full-scaleerror. Figures18and19show  
a family of offset and full-scale error curves for various  
small valued input capacitors (CIN < 0.01µF) as a function  
of input source resistance.  
V
CC  
I
IN  
AVERAGE INPUT CURRENT:  
= 0.25(V – 0.5 • V )fC  
REF EQ  
R
SW  
5k  
I
I
I
IN(LEAK)  
IN(LEAK)  
IN  
IN  
CH0/CH1  
C
EQ  
2.5pF (TYP)  
R
SW  
5k  
24012 F15  
ZS  
SET  
SWITCHING FREQUENCY  
f = 153.6kHz FOR INTERNAL OSCILLATOR (f = LOGIC LOW OR HIGH)  
f = f  
O
FOR EXTERNAL OSCILLATORS  
For large input capacitor values (CIN > 0.01µF), the input  
spikes are averaged by the capacitor into a DC current. The  
gain shift becomes a linear function of input source  
EOSC  
Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit  
23  
LTC2401/LTC2402  
APPLICATIO S I FOR ATIO  
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10  
R
SOURCE  
V
IN  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
INTPUT  
SIGNAL  
SOURCE  
LTC2401/  
LTC2402  
V
V
V
= 5V  
C
PAR  
20pF  
CC  
C
IN  
= 5V  
REF  
= 5V  
IN  
T
= 25°C  
A
24012 F17  
Figure 17. An RC Network at VIN  
C
C
C
C
C
C
= 22µF  
IN  
IN  
IN  
IN  
IN  
IN  
= 10µF  
= 1µF  
50  
40  
= 0.1µF  
= 0.01µF  
= 0.001µF  
V
V
V
= 5V  
CC  
= 5V  
REF  
= 0V  
IN  
–80  
T
= 25°C  
A
0
200  
400  
600  
800  
1000  
C
= 0.01µF  
IN  
R
(Ω)  
SOURCE  
30  
20  
24012 F20  
C
= 1000pF  
IN  
Figure 20. Full-Scale Error vs RSOURCE (Large C)  
C
= NO CAP  
IN  
10  
0
V
V
V
= 5V  
30  
10  
CC  
C
= 100pF  
IN  
= 5V  
REF  
= 5V  
C
IN  
= NO CAP  
IN  
T
= 25°C  
A
–10  
1
10  
100  
1k  
10k  
100k  
R
(Ω)  
SOURCE  
24012 F18  
C
= 0.01µF  
IN  
–10  
–30  
–50  
C
= 1000pF  
IN  
Figure 18. Offset vs RSOURCE (Small C)  
C
IN  
= 100pF  
80  
60  
40  
20  
0
C
C
C
C
C
C
= 22µF  
IN  
IN  
IN  
IN  
IN  
IN  
= 10µF  
= 1µF  
= 0.1µF  
= 0.01µF  
= 0.001µF  
0
10  
100  
1k  
10k  
100k  
R
(Ω)  
SOURCE  
24012 F21  
V
V
V
= 5V  
CC  
REF  
IN  
= 5V  
= 0V  
Figure 21. Full-Scale Error vs RSOURCE (Small C)  
T
= 25°C  
A
In addition to the input current spikes, the input ESD  
protection diodes have a temperature dependent leakage  
current. This leakage current, nominally 1nA (±10nA  
max), resultsinafixedoffsetshiftof10µVfora10ksource  
resistance.  
0
200  
400  
600  
800  
1000  
R
(Ω)  
SOURCE  
24012 F19  
The effect of input leakage current is evident for CIN = 0 in  
Figures 18 and 21. A leakage current of 3nA results in a  
150µV (30ppm) error for a 50k source resistance. As  
Figure 19. Offset vs RSOURCE (Large C)  
resistance independent of input capacitance, see Figures  
20 and 21. The equivalent input impedance is 6.25MΩ.  
This results in ±400µA of input dynamic current at the  
extreme values of VIN (VIN = 0V and VIN = VREF, when  
VREF = 5V). This corresponds to a 0.8ppm shift in offset  
and full-scale readings for every 10Ω of input source  
resistance.  
R
SOURCE gets larger, the switched capacitor input current  
begins to dominate.  
Reference Current (VREF  
)
Similar to the analog input, the reference input has a  
dynamic input current. This current has negligible effect  
24  
LTC2401/LTC2402  
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on the offset. However, the reference current at VIN = VREF  
is similar to the input current at full-scale. For large values  
of reference capacitance (CVREF > 0.01µF), the full-scale  
error shift is 0.08ppm/Ω of external reference resistance  
independent of the capacitance at VREF, see Figure 22. If  
the capacitance tied to VREF is small (CVREF < 0.01µF), an  
input resistance of up to 20k (20pF parasitic capacitance  
at VREF) may be tolerated, see Figure 23.  
atnodeVREF issmall(CVREF <0.01µF),thereferenceinput  
can tolerate large external resistances without reduction  
in INL, see Figure 24. If the external capacitance is large  
(CVREF > 0.01µF), the linearity will be degraded by  
0.04ppm/Ω independent of capacitance at VREF, see  
Figure 25.  
In addition to the dynamic reference current, the VREF ESD  
protection diodes have a temperature dependent leakage  
current.Thisleakagecurrent,nominally1nA(±10nAmax),  
results in a fixed full-scale shift of 10µV for a 10k source  
resistance.  
Unlike the analog input, the integral nonlinearity of the  
device can be degraded with excessive external RC time  
constants tied to the reference input. If the capacitance  
160  
50  
V
V
T
= 5V  
= 5V  
V
V
V
= 5V  
= 5V  
CC  
REF  
CC  
REF  
IN  
= 25°C  
= 5V  
A
40  
30  
20  
T
= 25°C  
A
120  
80  
40  
0
C
= 1000pF  
IN  
C
= 0.01µF  
IN  
C
= 100pF  
IN  
C
= 0.1µF  
IN  
C
= 1µF  
IN  
C
= 20pF  
IN  
C
= 0.01µF  
IN  
10  
0
C
= 10µF  
IN  
0
200  
400  
600  
800  
1000  
100  
1k  
RESISTANCE AT V  
10k  
(Ω)  
100k  
RESISTANCE AT V  
(Ω)  
REF  
REF  
24012 F22  
24012 F24  
Figure 22. Full-Scale Error vs RVREF (Large C)  
Figure 24. INL Error vs RVREF (Small C)  
40  
50  
V
V
V
= 5V  
= 5V  
V
V
T
= 5V  
= 5V  
CC  
REF  
IN  
CC  
REF  
C
VREF  
= 10µF  
= 5V  
= 25°C  
A
C
= 1µF  
VREF  
T
= 25°C  
A
25  
0
30  
20  
10  
0
C
VREF  
= 0.1µF  
C
IN  
= 10µF  
C
= 20pF  
IN  
C
= 100pF  
C
IN  
= 1000pF  
IN  
–25  
C
= 0.01µF  
VREF  
–50  
100  
1k  
RESISTANCE AT V  
10k  
(Ω)  
100k  
0
200  
400  
600  
800  
1000  
REF  
RESISTANCE AT V  
(Ω)  
REF  
24012 F23  
24012 F25  
Figure 23. Full-Scale Error vs RVFEF (Small C)  
Figure 25. INL Error vs RVREF (Large C)  
25  
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ANTIALIASING  
Single Ended Half-Bridge Digitizer  
with Reference and Ground Sensing  
One of the advantages delta-sigma ADCs offer over con-  
ventional ADCs is on-chip digital filtering. Combined with  
a large oversampling ratio, the LTC2401/LTC2402 signifi-  
cantly simplify antialiasing filter requirements.  
Sensors convert real world phenomena (temperature,  
pressure, gas levels, etc.) into a voltage. Typically, this  
voltage is generated by passing an excitation current  
through the sensor. The wires connecting the sensor to  
the ADC form parasitic resistors RP1 and RP2. The excita-  
tion current also flows through parasitic resistors RP1 and  
RP2, as shown in Figure 27. The voltage drop across these  
parasitic resistors leads to systematic offset and full-scale  
errors.  
The digital filter provides very high rejection except at  
integer multiples of the modulator sampling frequency  
(fS), see Figure 26. The modulator sampling frequency is  
256 • FO, where FO is the notch frequency (typically 50Hz  
or 60Hz). The bandwidth of signals not rejected by the  
digitalfilterisnarrow(≈0.2%)comparedtothebandwidth  
of the frequencies rejected.  
In order to eliminate the errors associated with these  
parasitic resistors, the LTC2401/LTC2402 include a full-  
scale set input (FSSET) and a zero-scale set input  
(ZSSET).AsshowninFigure28,theFSSET pinactsasazero  
current full-scale sense input. Errors due to parasitic  
resistance RP1 in series with the half-bridge sensor are  
removed by the FSSET input to the ADC. The absolute full-  
scale output of the ADC (data out = FFFFFFHEX ) will occur  
As a result of the oversampling ratio (256) and the digital  
filter, minimal (if any) antialias filtering is required in front  
of the LTC2401/LTC2402. If passive RC components are  
placed in front of the LTC2401/LTC2402, the input dy-  
namic current should be considered (see Input Current  
section). In cases where large effective RC time constants  
are used, an external buffer amplifier may be required to  
minimize the effects of input dynamic current.  
+
–
R
P1  
V
FULL-SCALE ERROR  
The modulator contained within the LTC2401/LTC2402  
can handle large-signal level perturbations without satu-  
rating. Signal levels up to 40% of VREF do not saturate the  
analog modulator. These signals are limited by the input  
ESDprotectionto300mVbelowgroundand300mVabove  
VCC.  
+
–
I
SENSOR  
SENSOR OUTPUT  
EXCITATION  
+
–
R
P2  
V
OFFSET ERROR  
24012 F27  
Figure 27. Errors Due to Excitation Currents  
0
–20  
–40  
1
V
CC  
R
I
I
I
= 0  
P1  
DC  
LTC2401  
SET  
2
3
–60  
–80  
V
FS  
V
B
R
DC  
P3  
= 0  
9
8
7
SCK  
3-WIRE  
SPI INTERFACE  
I
EXCITATION  
SDO  
CS  
IN  
–100  
–120  
–140  
R
DC  
P4  
= 0  
5
6
V
A
ZS  
SET  
R
P5  
R
10  
P2  
GND  
F
O
f /2  
S
f
0
S
24012 F03  
INPUT FREQUENCY  
24012 F26  
Figure 28. Half-Bridge Digitizer with  
Zero-Scale and Full-Scale Sense  
Figure 26. Sinc4 Filter Rejection  
26  
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at VIN = VB = FSSET, see Figure 29. Similarly, the offset  
errors due to RP2 are removed by the ground sense input  
ZSSET. The absolute zero output of the ADC (data out =  
000000HEX) occurs at VIN = VA= ZSSET. Parasitic resistors  
RP3 to RP5 have negligible errors due to the 1nA (typ)  
leakage current at pins FSSET, ZSSET and VIN. The wide  
dynamic input range (–300mV to 5.3V) and low noise  
(0.6ppm RMS) enable the LTC2401 or the LTC2402 to  
directly digitize the output of the bridge sensor.  
temperature probe and a cold junction temperature sen-  
sor. Absolute temperature measurements can be  
performed with a variety of thermocouples using digital  
cold junction compensation.  
The selection between CH0 and CH1 is automatic. Initially,  
after power-up, a conversion is performed on CH0. For  
each subsequent conversion, the input channel selection  
is alternated. Embedded within the serial data output is a  
status bit indicating which channel corresponds to the  
conversion result. If the conversion was performed on  
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion  
was performed on CH1 (see Figure 31).  
The LTC2402 is ideal for applications requiring continu-  
ous monitoring of two input sensors. As shown in  
Figure 30, the LTC2402 can monitor both a thermocouple  
12.5%  
EXTENDED  
RANGE  
FFFFF  
H
00000  
H
12.5%  
UNDER  
RANGE  
ZS  
FS  
SET  
SET  
V
IN  
24012 F29  
Figure 29. Transfer Curve with Zero-Scale and Full-Scale Set  
2.7V TO 5.5V  
LTC2402  
1
2
3
4
5
10  
9
V
F
O
CC  
12k  
FS  
SCK  
SDO  
CS  
SET  
PROCESSOR  
COLD JUNCTION  
8
CH1  
CH0  
ZS  
THERMISTOR  
7
24012 F30  
100Ω  
6
GND  
SET  
+
–
ISOLATION  
BARRIER  
THERMOCOUPLE  
Figure 30. Isolated Temperature Measurement  
27  
LTC2401/LTC2402  
APPLICATIO S I FOR ATIO  
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SCK  
• • •  
• • •  
SDO  
CH1 DATA OUT  
CH0 DATA OUT  
24012 F31  
EOC  
EOC  
CH1  
CH0  
Figure 31. Embedded Selected Channel Indicator  
I
I
EXCITATION  
5V  
1
= 0  
DC  
V
CC  
2
FS  
SET  
LTC2402  
9
SCK  
SDO  
CS  
350Ω  
350Ω  
350Ω  
3
4
8
3-WIRE  
SPI INTERFACE  
CH1  
CH0  
7
350Ω  
10  
I
= 0  
DC  
F
O
5
ZS  
SET  
GND  
24012 F32  
Figure 32. Pseudo Differential Strain Guage Application  
There are no extra control or status pins required to  
perform the alternating 2-channel measurements. The  
LTC2402 only requires two digital signals (SCK and SDO).  
This simplification is ideal for isolated temperature mea-  
surements or systems where minimal control signals are  
available.  
the common mode input voltage. Many applications  
currently using fully differential analog-to-digital con-  
verters for any of the above reasons may migrate to a  
pseudo differential conversion using the LTC2402.  
Direct Connection to a Full Bridge  
TheLTC2402interfacesdirectlytoa4-or6-wirebridge,as  
shown in Figure 32. The LTC2402 includes a FSSET and a  
ZSSET forsensingtheexcitationvoltagedirectlyacrossthe  
bridge. This eliminates errors due to excitation currents  
flowing through parasitic resistors. The LTC2402 also  
includes two single ended input channels which can tie  
directly to the differential output of the bridge. The two  
conversionresultsmaybedigitallysubtractedyieldingthe  
differential result.  
Pseudo Differential Applications  
Generally, designers choose fully differential topologies  
for several reasons. First, the interface to a 4- or 6-wire  
bridge is simple (it is a differential output). Second, they  
requiregoodrejectionoflinefrequencynoise. Third, they  
typically look at a small differential signal sitting on a  
large common mode voltage; they need accurate  
measurements of the differential signal independent of  
28  
LTC2401/LTC2402  
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The LTC2402’s single ended rejection of line frequencies the noise level of the device (3µVRMS) times the square  
(±2%) and harmonics is better than 110dB. Since the root of 2, independent of the common mode input voltage.  
device performs two independent single ended conver-  
Typically, a bridge sensor outputs 2mV/V full scale. With  
sions each with >110dB rejection, the overall common  
a 5V excitation, this translates to a full-scale output of  
mode and differential rejection is much better than the  
10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414),  
80dB rejection typically found in other differential input  
this circuit yields 2,300 counts with no averaging or  
delta-sigma converters.  
amplification. If more counts are required, several conver-  
In addition to excellent rejection of line frequency noise, sions may be averaged (the number of effective counts is  
the LTC2402 also exhibits excellent single ended noise increased by a factor of square root of 2 for each doubling  
rejection over a wide range of frequencies due to its 4th of averages).  
order sinc filter. Each single ended conversion indepen-  
An RTD Temperature Digitizer  
dentlyrejectshighfrequencynoise(>60Hz). Caremustbe  
taken to insure noise at frequencies below 15Hz and at  
multiples of the ADC sample rate (15,360Hz) are not  
present. For this application, it is recommended the  
LTC2402 is placed in close proximity to the bridge sensor  
in order to reduce the noise injected into the ADC input. By  
performingthreesuccessiveconversions(CH0-CH1-CH0),  
the drift and low frequency noise can be measured and  
compensated for digitally.  
RTDs used in remote temperature measurements often  
have long lead lengths between the ADC and RTD sensor.  
These long lead lengths lead to voltage drops due to  
excitation current in the interconnect to the RTD. This  
voltage drop can be measured and digitally removed using  
the LTC2402 (see Figure 33).  
The excitation current (typically 200µA) flows from the  
ADC through a long lead length to the remote temperature  
sensor (RTD). This current is applied to the RTD, whose  
resistance changes as a function of temperature (100Ω to  
400Ωfor0°Cto800°C). Thesameexcitationcurrentflows  
back to the ADC ground and generates another voltage  
drop across the return leads. In order to get an accurate  
measurement of the temperature, these voltage drops  
must be measured and removed from the conversion  
result. Assumingtheresistanceisapproximatelythesame  
Theabsoluteaccuracy(lessthan10ppmtotalerror)ofthe  
LTC2402 enables extremely accurate measurement of  
small signals sitting on large voltages. Each of the two  
pseudo differential measurements performed by the  
LTC2402 is absolutely accurate independent of the com-  
mon mode voltage output from the bridge. The pseudo  
differential result obtained from digitally subtracting the  
two single ended conversion results is accurate to within  
5V  
1
V
CC  
2
4
FS  
SET  
LTC2402  
9
8
7
I
I
= 200µA  
= 200µA  
SCK  
SDO  
CS  
EXCITATION  
25Ω  
25Ω  
5k  
3-WIRE  
SPI INTERFACE  
CH0  
CH1  
+
–
R1  
EXCITATION  
1000pF  
3
P
t
V
RTD  
100Ω  
10  
I
= 0  
F
DC  
O
5k  
5
ZS  
SET  
R2  
0.1µF  
GND  
24012 F33  
Figure 33. RTD Remote Temperature Measurement  
29  
LTC2401/LTC2402  
W U U  
U
APPLICATIO S I FOR ATIO  
for the forward and return paths (R1 = R2), the auxiliary  
channel on the LTC2402 can measure this drop. These  
errors are then removed with simple digital correction.  
During power-up, the LTC2402 becomes active at VCC =  
2.3V, while the isolated side of the LTC1535 must wait for  
V
CC2 to reach its undervoltage lockout threshold of 4.2V.  
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a  
high impedance state, allowing the 1kΩ pull-down to  
define the logic state at SCK. When the LTC2402 first  
becomes active, it samples SCK; a logic “0” provided by  
the 1kΩ pull-down invokes the external serial clock mode.  
In this mode, the LTC2402 is controlled by a single clock  
line from the nonisolated side of the barrier, through the  
LTC1535’sdriveroutputY.Theentirepower-upsequence,  
from the time power is applied to VCC1 until the LT1761’s  
output has reached 5V, is approximately 1ms.  
The result of the first conversion on CH0 corresponds to  
aninputvoltageofVRTD +R1•IEXCITATION. Theresultofthe  
second conversion (CH1) is –R1 • IEXCITATION. Note, the  
LTC2402’s input range is not limited to the supply rails, it  
has underrange capabilities. The device’s input range is  
–300mV to VREF + 300mV. Adding the two conversion  
results together, the voltage drop across the RTD’s leads  
are cancelled and the final result is VRTD  
.
An Isolated, 24-Bit Data Acquisition System  
DatareturnstothenonisolatedsidethroughtheLTC1535’s  
receiver at RO. An internal divider on receiver input B sets  
a logic threshold of approximately 3.4V at input A, facili-  
tating communications with the LTC2402’s SDO output  
without the need for any external components.  
The LTC1535 is useful for signal isolation. Figure 34  
shows a fully isolated, 24-bit differential input A/D con-  
verterimplementedwiththeLTC1535andLTC2402.Power  
on the isolated side is regulated by an LT1761-5.0 low  
noise, low dropout micropower regulator. Its output is  
suitable for driving bridge circuits and for ratiometric  
applications.  
1/2 BAT54C  
LT1761-5  
IN  
OUT  
+
10µF  
10µF  
16V  
SHDN BYP  
GND  
+
10µF  
10V  
TANT  
TANT  
T1  
1µF  
2
10µF  
CERAMIC  
1/2 BAT54C  
+
10µF  
10V  
TANT  
2
2
LTC2402  
ST1 ST2  
V
CC2  
“SDO”  
RO  
RE  
DE  
DI  
A
B
Y
Z
F
O
V
CC  
LTC1535  
G1 G2  
SCK FS  
SET  
“SCK”  
V
SDO  
CS  
CH1  
CH0  
CC1  
1k  
LOGIC 5V  
GND ZS  
SET  
+
10µF  
10V  
TANT  
= LOGIC COMMON  
1
2
2
1
1
2
24012 F09  
= FLOATING COMMON  
ISOLATION  
BARRIER  
1
2
T1 = COILTRONICS CTX02-14659  
OR SIEMENS B78304-A1477-A3  
Figure 34. Complete, Isolated 24-Bit Data Acquisition System  
30  
LTC2401/LTC2402  
U W  
U
PACKAGE I FOR ATIO  
Dimensions in inches (millimeters) unless otherwise noted.  
MS10 Package  
10-Lead Plastic MSOP  
(LTC DWG # 05-08-1661)  
0.118 ± 0.004*  
(3.00 ± 0.102)  
10 9  
8
7 6  
0.118 ± 0.004**  
(3.00 ± 0.102)  
0.193 ± 0.006  
(4.90 ± 0.15)  
1
2
3
4 5  
0.040 ± 0.006  
(1.02 ± 0.15)  
0.034 ± 0.004  
(0.86 ± 0.102)  
0.007  
(0.18)  
0° – 6° TYP  
SEATING  
PLANE  
0.009  
(0.228)  
REF  
0.021 ± 0.006  
(0.53 ± 0.015)  
0.006 ± 0.004  
(0.15 ± 0.102)  
0.0197  
(0.50)  
BSC  
MSOP (MS10) 1098  
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,  
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE  
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.  
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.  
31  
LTC2401/LTC2402  
U
TYPICAL APPLICATIO  
convert either the thermal couple output or the thermistor  
cold juntion output. After each conversion, the devices  
enter their sleep state and wait for the SCK signal before  
clocking out data and beginning the next conversion.  
Figure 35 shows the block diagram of a demo circuit  
(contact LTC for a demonstration) of a multichannel  
isolated temperature measurement system. This circuit  
decodes an address to select which LTC2402 receives a  
32-bit burst of SCK signal. All devices independently  
D1  
RE  
R0  
V
CC  
FS  
SET  
LTC1535  
LTC1535  
LTC1535  
A
Y
SDO  
LTC2402  
SCK  
CH1  
CH0  
ZS  
SET  
SCK  
HC138  
D1  
RE  
R0  
V
CC  
FS  
SET  
A
Y
SDO  
LTC2402  
+
2500V  
–
SCK  
CH1  
CH0  
ZS  
SET  
D1  
RE  
R0  
V
CC  
FS  
SET  
HC138  
A
Y
SDO  
LTC2402  
SCK  
CH1  
CH0  
SD0  
ZS  
SET  
SEE FIGURE 34 FOR  
THE COMPLETE CIRCUIT  
HC595  
ADDRESS  
LATCH  
24012 F35  
D
IN  
(ADDRESS  
OR COUNTER)  
Figure 35. Mulitchannel Isolated Temperature Measurement System  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
Precision Bandgap Reference, 2.5V, 5V  
COMMENTS  
LT1019  
3ppm/°C Drift, 0.05% Max  
LTC1050  
Precision Chopper Stabilized Op Amp  
Precision Bandgap Reference, 5V  
No External Components 5µV Offset, 1.6µV Noise  
P-P  
LT1236A-5  
LTC1391  
0.05% Max, 5ppm/°C Drift  
8-Channel Multiplexer  
Low R : 45Ω, Low Charge Injection Serial Interface  
ON  
LT1460  
Micropower Series Reference  
0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions  
50µA Supply Current, 3ppm/°C Drift  
LT1461-2.5  
LTC1535  
Precision Micropower Voltage Reference  
Isolated RS485 Transceiver  
2500V  
Isolation  
RMS  
LTC2400  
24-Bit, No Latency ∆Σ ADC in SO-8  
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC  
24-Bit, Fully Differential, No Latency ∆Σ ADC in SSOP-16  
24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10  
24-Bit, No Latency ∆Σ ADC  
4ppm INL, 10ppm Total Unadjusted Error, 200µA  
LTC2404/LTC2408  
LTC2410  
4ppm INL, 10ppm Total Unadjusted Error, 200µA  
0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA  
0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA  
Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise  
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400  
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408  
LTC2411  
LTC2413  
LTC2420  
20-Bit, No Latency ∆Σ ADC in SO-8  
4-/8-Channel, 20-Bit, No Latency ∆Σ ADC  
LTC2424/LTC2428  
24012f LT/LCG 1000 4K • PRINTED IN USA  
LINEAR TECHNOLOGY CORPORATION 2000  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
32  
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com  

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