LTC2410IGN#TRPBF_技术文档

LTC2410

24-Bit No Latency ∆Σ™ ADC

with Differential Input and

Differential Reference

FEATURES

DESCRIPTION

The LTC^®2410 is a 2.7V to 5.5V micropower 24-bit dif-

ferential ∆Σ analog to digital converter with an integrated

oscillator, 2ppm INL and 0.16ppm RMS noise. It uses

delta-sigma technology and provides single cycle settling

time for multiplexed applications. Through a single pin,

the LTC2410 can be configured for better than 110dB

input differential mode rejection at 50Hz or 60Hz 2ꢀ, or

it can be driven by an external oscillator for a user defined

rejection frequency. The internal oscillator requires no

external frequency setting components.

n

Differential Input and Differential Reference with

GND to V Common Mode Range

CC

n

2ppm INL, No Missing Codes

2.5ppm Full-Scale Error

0.1ppm Offset

0.16ppm Noise

Single Conversion Settling Time for Multiplexed

Applications

Internal Oscillator—No External Components

Required

110dB Min, 50Hz or 60Hz Notch Filter

24-Bit ADC in Narrow SSOP-16 Package

(SO-8 Footprint)

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200µA) and Auto Shutdown

Fully Differential Version of LTC2400

n

The converter accepts any external differential reference

voltage from 0.1V to V for flexible ratiometric and re-

CC

mote sensing measurementconfigurations. The full-scale

n

differential input range is from –0.5V

to 0.5V . The

REFCM

, may be independently set

REF

reference common mode voltage, V

, and the input

common mode voltage, V

INCM

anywherewithintheGNDtoV rangeoftheLTC2410.The

CC

APPLICATIONS

DC common mode input rejection is better than 140dB.

n

The LTC2410 communicates through a flexible 3-wire

digital interface which is compatible with SPI and MI-

CROWIRE protocols.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No

Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Direct Sensor Digitizer

n

Weight Scales

n

Direct Temperature Measurement

Gas Analyzers

Strain-Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

6-Digit DVMs

n

TYPICAL APPLICATION

2.7V TO 5.5V

V

CC

1µF

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

2

14

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2410

2

3

+

REF

V

12 SDO

13 SCK

11 CS

CC

3

4

+

BRIDGE

IMPEDANCE

100Ω TO 10k

13

REFERENCE

VOLTAGE

REF

5

+

SCK

IN

3-WIRE

SPI INTERFACE

–

LTC2410

GND

6

–

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

–

4

+

ANALOG INPUT RANGE

REF

IN

SDO

F

O

–0.5V

TO 0.5V

REF

–

1, 7, 8

14

IN

CS

1, 7, 8, 9, 10, 15, 16

9, 10,

GND

15, 16

2410 TA01

2410 TA02

2410fa

1

For more information www.linear.com/LTC2410

LTC2410

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage (V ) to GND....................... –0.3V to 7V

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

Analog Input Pins Voltage

V

CC

+

to GND......................................–0.3V to (V + 0.3V)

CC

F

O

REF

IN

Reference Input Pins Voltage

–

+

–

SCK

SDO

CS

to GND......................................–0.3V to (V + 0.3V)

CC

Digital Input Voltage to GND .........–0.3V to (V + 0.3V)

CC

IN

Digital Output Voltage to GND.......–0.3V to (V + 0.3V)

CC

GND

Operating Temperature Range

LTC2410C ............................................... 0°C to 70°C

LTC2410I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θ = 110°C/W

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC2410CGN#PBF

LTC2410IGN#PBF

TAPE AND REEL

PART MARKING

2410

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

TEMPERATURE RANGE

LTC2410CGN#TRPBF

LTC2410IGN#TRPBF

0°C to 70°C

2410I

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V (Note 5)

24

Bits

REF

CC

REF

IN

–

REF

+

Integral Nonlinearity

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V (Note 6)

= 2.5V (Note 6)

1

2

5

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

14

ppm of V

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V (Note 6)

INCM

+

–

l

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

0.5

0.25

µV

CC

+

–

GND ≤ IN = IN ≤ V (Note 14)

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

10

nV/°C

ppm of V

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

2.5V ≤ REF ≤ V , REF = GND,

2.5

12

CC

REF

+

–

+

IN = 0.75REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

2.5

ppm of V /°C

REF

CC

+

–

+

IN = 0.75REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V

REF

CC

+

–

+

IN = 0.25 • REF , IN = 0.75 • REF

+

–

Negative Full-Scale Error Drift 2.5V ≤ REF ≤ V , REF = GND,

0.03

ppm of V /°C

CC

REF

+

–

IN = 0.25 • REF , IN = 0.75 • REF

2410fa

2

For more information www.linear.com/LTC2410

LTC2410

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Total Unadjusted Error

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V

= 2.5V

3

4

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

INCM

+

–

Output Noise

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND,

0.8

µV

RMS

CC

–

+

GND ≤ IN = IN ≤ V , (Note 13)

CC

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

l

Input Common Mode Rejection DC

2.5V ≤ REF ≤ V , REF = GND,

130

140

dB

CC

–

+

GND ≤ IN = IN ≤ V

CC

+

–

Input Common Mode Rejection

60Hz 2ꢀ

2.5V ≤ REF ≤ V , REF = GND,

140

110

130

dB

CC

–

+

GND ≤ IN = IN ≤ V , (Note 7)

CC

+

–

Input Common Mode Rejection

50Hz 2ꢀ

2.5V ≤ REF ≤ V , REF = GND,

CC

–

+

GND ≤ IN = IN ≤ V , (Note 8)

CC

Input Normal Mode Rejection

60Hz 2ꢀ

(Note 7)

140

Input Normal Mode Rejection

50Hz 2ꢀ

(Note 8)

+

–

Reference Common Mode

Rejection DC

2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,

CC

–

+

V

= 2.5V, IN = IN = GND

REF

+

–

+

Power Supply Rejection, DC

REF = 2.5V, REF = GND, IN = IN = GND

120

dB

+

–

+

Power Supply Rejection, 60Hz 2ꢀ

Power Supply Rejection, 50Hz 2ꢀ

REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)

+

–

+

REF = 2.5V, REF = GND, IN = IN = GND, (Note 8)

ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

l

IN

Absolute/Common Mode IN Voltage

GND – 0.3V

V

+ 0.3V

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3V

/2

V

Input Differential Voltage Range

–V /2

REF

V

IN

REF

+

–

(IN – IN )

+

–

+

l

REF

Absolute/Common Mode REF Voltage

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1V

CC

V

Reference Differential Voltage Range

V

CC

REF

+

–

(REF – REF )

+

C (IN )

IN Sampling Capacitance

18

1

pF

nA

S

–

C (IN )

IN Sampling Capacitance

S

+

C (REF )

REF Sampling Capacitance

S

–

C (REF )

REF Sampling Capacitance

S

+

l

I

(IN )

IN DC Leakage Current

CS = V , IN = GND

–10

10

DC_LEAK

CC

–

(IN )

IN DC Leakage Current

CS = V , IN = GND

1

10

CC

+

(REF )

REF DC Leakage Current

CS = V , REF = 5V

1

CC

–

(REF )

REF DC Leakage Current

CS = V , REF = GND

1

CC

2410fa

3

For more information www.linear.com/LTC2410

LTC2410

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

High Level Input Voltage

2.7V ≤ V ≤ 5.5V

2.5

2.0

V

IH

IL

IH

IL

CC

CS, F

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

CS, F

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 9)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 9)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 9)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 9)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

IN

CS, F

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 9)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F

O

Digital Input Capacitance

SCK

(Note 9)

IN

l

High Level Output Voltage

SDO

I = –800µA

O

V

– 0.5V

V

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 10)

O

V

CC

Low Level Output Voltage

SCK

I = 1.6mA (Note 10)

O

0.4

10

V

I

Hi-Z Output Leakage

SDO

–10

µA

OZ

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

2.7

5.5

V

CC

I

Supply Current

Conversion Mode

Sleep Mode

CC

l

CS = 0V (Note 12)

200

20

300

30

µA

CS = V (Note 12)

CC

2410fa

4

For more information www.linear.com/LTC2410

LTC2410

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER

CONDITIONS

MIN

2.56

0.25

TYP

MAX

500

390

UNITS

kHz

µs

l

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

EOSC

HEO

µs

LEO

F = 0V

l

130.86

157.03

133.53

160.23

EOSC

136.20

163.44

ms

CONV

O

F = V

O

CC

20510/f

(in kHz)

External Oscillator (Note 11)

f

Internal SCK Frequency

Internal Oscillator (Note 10)

External Oscillator (Notes 10, 11)

19.2

kHz

ISCK

f

/8

EOSC

l

D

Internal SCK Duty Cycle

(Note 10)

(Note 9)

45

55

ꢀ

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

External SCK High Period

2000

ESCK

250

1.64

LESCK

ns

HESCK

DOUT_ISCK

Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12)

External Oscillator (Notes 10, 11)

l

1.67

EOSC

1.70

ms

256/f

(in kHz)

l

t

External SCK 32-Bit Data Output Time (Note 9)

CS ↓ to SDO Low Z

32/f

(in kHz)

ms

ns

DOUT_ESCK

ESCK

0

200

1

CS ↑ to SDO High Z

2

(Note 10)

(Note 9)

0

CS ↓ to SCK ↓

3

50

CS ↓ to SCK ↑

4

220

50

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 8: F = V (internal oscillator) or f

oscillator).

Note 9: The converter is in external SCK mode of operation such that the

SCK pin is used as digital input. The frequency of the clock signal driving

= 128000Hz 2ꢀ (external

O

CC

EOSC

Note 2: All voltage values are with respect to GND.

SCK during the data output is f

and is expressed in kHz.

ESCK

Note 3: V = 2.7 to 5.5V unless otherwise specified.

Note 10: The converter is in internal SCK mode of operation such that the

SCK pin is used as digital output. In this mode of operation the SCK pin

CC

+

–

+

–

V

= REF – REF , V

= (REF + REF )/2;

= (IN + IN )/2.

REF

REFCM

+

–

+

–

= IN – IN , V

has a total equivalent load capacitance C

= 20pF.

IN

INCM

LOAD

Note 4: F pin tied to GND or to V or to external conversion clock source

Note 11: The external oscillator is connected to the F pin. The external

O

CC

O

with f

= 153600Hz unless otherwise specified.

oscillator frequency, f , is expressed in kHz.

EOSC

Note 5: Guaranteed by design, not subject to test.

Note 12: The converter uses the internal oscillator.

F = 0V or F = V

Note 13: The output noise includes the contribution of the internal

.

CC

O

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

calibration operations.

Note 7: F = 0V (internal oscillator) or f

= 153600Hz 2ꢀ (external

Note 14: Guaranteed by design and test correlation.

O

EOSC

oscillator).

2410fa

5

For more information www.linear.com/LTC2410

LTC2410

TYPICAL PERFORMANCE CHARACTERISTICS

Total Unadjusted Error vs

Temperature (V_CC= 5V,

V_REF= 5V)

Total Unadjusted Error vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Total Unadjusted Error vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

1.5

1.0

1.5

1.0

10

8

V

= 5V

CC

+

REF = 2.5V

–

REF = GND

6

V

= 2.5V

INCM

= GND

REF

4

T

= 90°C

= 1.25V

A

0.5

F

O

2

T = 25°C

A

T

= 90°C

= 25°C

= –45°C

0

A

0

V

= 5V

T

= 90°C

= 25°C

–2

–4

–6

–8

–10

CC

A

+

V

= 2.7V

CC

REF = 5V

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

+

–

REF = 2.5V

REF = GND

–

REF = GND

V

F

= 5V

INCM

= GND

REF

T

= –45°C

V

= 2.5V

INCM

= GND

A

REF

= 2.5V

T

= –45°C

1

A

= 1.25V

O

F

O

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

–0.5

0

0.5

(V)

V

(V)

V

(V)

IN

2410 G01

2410 G02

2410 G03

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 5V)

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Integral Nonlinearity vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

1.5

1.0

1.5

1.0

10

8

V

= 2.7V

V

F

= 2.5V

REF

CC

V

= 5V

+

CC

T

= –45°C

REF = 2.5V

= 1.25V

A

+

INCM

O

REF = 5V

–

REF = GND

= GND

–

REF = GND

6

T

= –45°C

= 25°C

A

T

= 25°C

A

V

F

= 5V

INCM

= GND

REF

T

4

A

= 2.5V

0.5

O

T

= 90°C

2

A

0

T

= 90°C

A

V

= 5V

–2

–4

–6

–8

–10

CC

+

T

= 90°C

= 25°C

REF = 2.5V

A

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

–

REF = GND

T

V

F

= 2.5V

INCM

= GND

REF

= 1.25V

= –45°C

A

O

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

–0.5

0

0.5

1

(V)

V

(V)

V

(V)

IN

2410 G04

2410 G05

2410 G06

Noise Histogram (Output Rate =

7.5Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

7.5Hz, V_CC= 5V, V_REF= 2.5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.105ppm

σ = 0.153ppm

DISTRIBUTION

m = 0.067ppm

σ = 0.151ppm

DISTRIBUTION

m = 0.033ppm

σ = 0.293ppm

V

= 5V

V

= 5V

V

= 5V

CC

REF

IN

CC

REF

IN

CC

REF

= 5V

= 2.5V

= 0V

IN

+

–

REF = 5V

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 2.5V

IN = 1.25V

6

IN = 2.5V

IN = 1.25V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F

= GND

O

T = 25°C

A

O

T

O

T

A

4

2

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–1.6

–0.8

0

0.8

1.6

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2410 G07

2410 G08

2410 G10

2410fa

6

For more information www.linear.com/LTC2410

LTC2410

TYPICAL PERFORMANCE CHARACTERISTICS

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 2.5V)

Noise Histogram (Output Rate =

7.5Hz, V_CC= 2.7V, V_REF= 2.5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 2.7V, V_REF= 2.5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.014ppm

σ = 0.292ppm

DISTRIBUTION

m = 0.079ppm

σ = 0.298ppm

DISTRIBUTION

m = 0.177ppm

σ = 0.297ppm

V

= 5V

V

= 2.7V

V

= 2.7V

CC

REF

IN

CC

REF

IN

CC

REF

= 2.5V

= 0V

IN

+

–

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 1.25V

6

IN = 1.25V

F

= 460800Hz

= 25°C

F

= GND

= 25°C

F

= 460800Hz

O

T = 25°C

A

O

T

O

T

A

4

2

0

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2410 G11

2410 G13

2410 G14

Long-Term Noise Histogram

(Time = 60 Hrs, V_CC= 5V,

V_REF= 5V)

RMS Noise vs Input Differential

Voltage

Consectutive ADC Readings vs

Time

12

10

8

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

GAUSSIAN DISTRIBUTION

m = 0.101837ppm

σ = 0.154515ppm

V

= 5V

CC

= 5V

REF

+

0.6

REF = 5V

–

REF = GND

0.4

ADC CONSECUTIVE

READINGS

V

= 2.5V

= GND

= 25°C

INCM

F

O

0.2

V

= 5V

T

CC

REF

IN

A

6

0

= 0V

+

–0.2

–0.4

–0.6

–0.8

–1.0

REF = 5V

–

4

REF = GND

+

–

IN = 2.5V

+

–

V

= 5V

T = 25°C

A

IN = 2.5V

CC

IN = 2.5V

+

= 5V REF = 5V IN = 2.5V

2

REF

F

= GND

= 25°C

–

O

A

= 0V REF = GND

IN

T

F

= GND

O

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

0

5

10 15 20 25 30 35 40 45 50 55 60

TIME (HOURS)

–2.5 –2 –1.5 –1 –0.5

0

0.5

1

1.5

2

2.5

OUTPUT CODE (ppm OF V

)

INPUT DIFFERENTIAL VOLTAGE (V)

REF

2410 G16

2410 G17

2410 G18

RMS Noise vs V_INCM

RMS Noise vs Temperature (T_A)

RMS Noise vs V_CC

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

+

–

REF = 2.5V

V

= 5V

CC

+

REF = GND

REF = 5V

–

V

= 2.5V

REF

REF = GND

+

–

IN = GND

IN = 2.5V

–

IN = GND

IN = 2.5V

F

= GND

= 25°C

O

A

V

F

= 0V

= GND

IN

T

V

= 5V

O

CC

+

REF = 5V

–

REF = GND

V

= 5V

REF

+

–

IN = V

INCM

= 0V

= GND

= 25°C

IN = V

V

IN

F

O

A

T

–0.5 0 0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

V

INCM

(V)

TEMPERATURE (°C)

V

CC

2410 G19

2410 G20

2410 G21

2410fa

7

For more information www.linear.com/LTC2410

LTC2410

TYPICAL PERFORMANCE CHARACTERISTICS

RMS Noise vs V_REF

Offset Error vs V_INCM

Offset Error vs Temperature (T_A)

850

825

800

775

750

725

700

675

650

0.3

0.2

0.3

0.2

V

= 5V

CC

–

REF = GND

+

–

IN = GND

F

= GND

= 25°C

O

A

0.1

T

V

= 5V

CC

+

REF = 5V

0

–

V

= 5V

REF = GND

CC

+

REF = 5V

V

= 5V

REF

–

+

–

REF = GND

IN = V

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

INCM

= 0V

= GND

= 25°C

+

–

IN = 2.5V

IN = V

IN = 2.5V

V

F

IN

V

F

= 0V

= GND

IN

O

T

A

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–0.5 0 0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

V

(V)

INCM

TEMPERATURE (°C)

REF

2410 G22

2410 G23

2410 G24

+Full-Scale Error vs

Temperature (T_A)

Offset Error vs V_CC

Offset Error vs V_REF

0.3

0.2

0.3

0.2

3

2

0.1

1

0

+

–

REF = 2.5V

V

= 5V

V

= 5V

CC

REF = GND

CC

–

+

REF = GND

REF = 5V

V

= 2.5V

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–1

–2

–3

REF

+

–

+

IN = GND

REF = GND

IN = GND

+

–

IN = 2.5V

IN = GND

F

= GND

= 25°C

IN = GND

F

= GND

= 25°C

O

A

O

A

T

F = GND

T

O

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–45 –30 –15

0

15 30 45 60 75 90

V

TEMPERATURE (°C)

CC

REF

2410 G25

2410 G26

2410 G27

–Full-Scale Error vs

Temperature (T_A)

+Full-Scale Error vs V_CC

–Full-Scale Error vs V_REF

3

2

3

2

3

2

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = GND

IN = 2.5V

1

F

= GND

O

0

+

–

V

= 5V

CC

REF = 2.5V

+

REF = V

REF

REF = GND

–

–1

–2

–3

REF = GND

–1

–2

–3

–1

–2

–3

V

= 2.5V

REF

+

–

+

IN = 0.5 • REF

IN = 1.25V

–

IN = GND

F

= GND

= 25°C

O

A

F

= GND

= 25°C

O

A

T

–45 –30 –15

0

15 30 45 60 75 90

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

TEMPERATURE (°C)

V

CC

REF

2410 G30

2410 G28

2410 G29

2410fa

8

For more information www.linear.com/LTC2410

LTC2410

TYPICAL PERFORMANCE CHARACTERISTICS

–Full-Scale Error vs V_CC

–Full-Scale Error vs V_REF

PSRR vs Frequency at V_CC

3

2

3

2

0

–20

+

V

= 5V

V

= 4.1V

DC

1.4V

REF = 2.5V

CC

+

–

REF = V

REF = 2.5V

REF = GND

REF

–

REF = GND

V

= 2.5V

REF

+

–

+

–

+

IN = GND

–40

+

–

IN = 0.5 • REF

IN = GND

IN = 1.25V

1

F

= GND

= 25°C

F

= GND

T = 25°C

A

F

= GND

= 25°C

O

A

–60

T

A

0

–80

–1

–2

–3

–1

–2

–3

–100

–120

–140

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

0.01

0.1

1

10

100

V

FREQUENCY AT V (Hz)

CC

REF

2410 G31

2410 G32

2410 G33

PSRR vs Frequency at V_CC

0

–20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+

V

= 4.1V

1.4V

REF = 2.5V

V

= 4.1V

0.7V

DC

CC

DC

CC

+

–

+

REF = 2.5V

REF = GND

REF = 2.5V

–20

–40

–

+

–

REF = GND

IN = GND

REF = GND

+

–

+

–

IN = GND

–40

IN = GND

F

= GND

= 25°C

IN = GND

O

A

F

= GND

= 25°C

T

F

= GND

T = 25°C

A

O

A

O

–60

T

–80

–100

–120

–140

–100

–120

–140

0

30 60 90 120 150 180 210 240

FREQUENCY AT V (Hz)

1

10

100

1k

10k 100k

1M

7600 7620 7640 7660 7680 7700 7720 7740

FREQUENCY AT V (Hz)

CC

2410 G34

2410 G35

2410 G36

Conversion Current vs

Temperature (T_A)

Conversion Current vs

Output Data Rate

Sleep Current vs Temperature (T_A)

1100

1000

900

800

700

600

500

400

300

200

100

220

210

200

190

180

170

160

23

22

21

20

19

18

17

16

F

O

= GND

V

= 5V

F = GND

O

CC

+

CS = GND

SCK = NC

SDO = NC

REF = 5V

CS = V

CC

–

REF = GND

SCK = NC

SDO = NC

+

–

IN = GND

V

= 5.5V

CC

IN = GND

V

= 5.5V

= 2.7V

CC

T

= 25°C

= EXTERNAL OSC

A

O

F

V

= 4.1V

CC

CS = GND

SCK = NC

SDO = NC

V

= 4.1V

= 2.7V

CC

–45 –30 –15

0

15 30 45 60 75 90

0

5

10

15

20

25

–45 –30 –15

0

15 30 45 60 75 90

2410 G37

2410 G39

TEMPERATURE (°C)

OUTPUT DATA RATE (READINGS/SEC) ^{2410 G38}

TEMPERATURE (°C)

2410fa

9

For more information www.linear.com/LTC2410

LTC2410

PIN FUNCTIONS

GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple

SDO (Pin 12): Three-State Digital Output. During the Data

ground pins internally connected for optimum ground

Output period, this pin is used as serial data output. When

current flow and V decoupling. Connect each one of

the chip select CS is HIGH (CS = V ) the SDO pin is in a

CC

these pins to a ground plane through a low impedance

connection. All seven pins must be connected to ground

for proper operation.

high impedance state. During the Conversion and Sleep

periods, this pin is used as the conversion status output.

TheconversionstatuscanbeobservedbypullingCSLOW.

V

(Pin 2): Positive Supply Voltage. Bypass to GND

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

fortheinternalserialinterfaceclockduringtheDataOutput

period. In External Serial Clock Operation mode, SCK is

used as digital input for the external serial interface clock

during the Data Output period. A weak internal pull-up is

automatically activated in Internal Serial Clock Operation

mode. The Serial Clock Operation mode is determined by

the logic level applied to the SCK pin at power up or during

the most recent falling edge of CS.

CC

(Pin 1) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

+

–

REF (Pin 3), REF (Pin 4): Differential Reference Input.

The voltage on these pins can have any value between

+

GNDandV aslongasthereferencepositiveinput, REF ,

CC

is maintained more positive than the reference negative

–

input, REF , by at least 0.1V.

+

–

IN (Pin 5), IN (Pin 6): Differential Analog Input. The

voltage on these pins can have any value between

F (Pin 14): Frequency Control Pin. Digital input that

O

GND – 0.3V and V + 0.3V. Within these limits the con-

CC

controls the ADC’s notch frequencies and conversion

+

–

verter bipolar input range (V = IN – IN ) extends from

IN

time. When the F pin is connected to V (F = V ), the

O

CC

O

CC

–0.5 • (V ) to 0.5 • (V ). Outside this input range the

REF

converter uses its internal oscillator and the digital filter

converter produces unique overrange and underrange

first null is located at 50Hz. When the F pin is connected

O

output codes.

to GND (F = OV), the converter uses its internal oscillator

O

CS (Pin 11): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

and the digital filter first null is located at 60Hz. When F is

O

EOSC

driven by an external clock signal with a frequency f

,

the converter uses this signal as its system clock and the

digital filter first null is located at a frequency f

/2560.

EOSC

2410fa

10

For more information www.linear.com/LTC2410

LTC2410

FUNCTIONAL BLOCK DIAGRAM

INTERNAL

OSCILLATOR

V

CC

GND

AUTOCALIBRATION

AND CONTROL

F

O

(INT/EXT)

+

IN

+

–

∫

SDO

SERIAL

INTERFACE

∑

ADC

SCK

+

CS

REF

–

DECIMATING FIR

–

+

DAC

2410 FD

Figure 1. Functional Block Diagram

TEST CIRCUIT

V

CC

1.69k

SDO

1.69k

C

= 20pF

C

= 20pF

LOAD

2410 TA04

2410 TA03

Hi-Z TO V

OH

OL

V

TO V

V

TO V

OL

OH

OL

TO Hi-Z

2410fa

11

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

CONVERTER OPERATION

Through timing control of the CS and SCK pins, the

LTC2410 offers several flexible modes of operation

(internal or external SCK and free-running conversion

modes).Thesevariousmodesdonotrequireprogramming

configuration registers; moreover, they do not disturb the

cyclic operation described above. These modes of opera-

tion are described in detail in the Serial Interface Timing

Modes section.

Converter Operation Cycle

TheLTC2410isalowpower,delta-sigmaanalog-to-digital

converter with an easy to use 3-wire serial interface (see

Figure 1). Its operation is made up of three states. The

converter operating cycle begins with the conversion,

followed by the low power sleep state and ends with the

data output (see Figure 2). The 3-wire interface consists

of serial data output (SDO), serial clock (SCK) and chip

select (CS).

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50 or 60Hz

plus their harmonics. The filter rejection performance is

directly related to the accuracy of the converter system

clock.TheLTC2410incorporatesahighlyaccurateon-chip

oscillator. This eliminates the need for external frequency

settingcomponentssuchascrystalsoroscillators.Clocked

by the on-chip oscillator, the LTC2410 achieves a mini-

mum of 110dB rejection at the line frequency (50Hz or

60Hz 2ꢀ).

Initially, the LTC2410 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

While in this sleep state, power consumption is reduced

by an order of magnitude. The part remains in the sleep

state as long as CS is HIGH. The conversion result is held

indefinitely in a static shift register while the converter is

in the sleep state.

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result. The data output corresponds to the conversion

just performed. This result is shifted out on the serial data

out pin (SDO) under the control of the serial clock (SCK).

Data is updated on the falling edge of SCK allowing the

user to reliably latch data on the rising edge of SCK (see

Figure 3). The data output state is concluded once 32 bits

are read out of the ADC or when CS is brought HIGH. The

device automatically initiates a new conversion and the

cycle repeats.

Ease of Use

The LTC2410 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

The LTC2410 performs offset and full-scale calibrations

every conversion cycle. This calibration is transparent to

theuserandhasnoeffectonthecyclicoperationdescribed

above. Theadvantageofcontinuouscalibrationisextreme

stability of offset and full-scale readings with respect to

time, supply voltage change and temperature drift.

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

Power-Up Sequence

The LTC2410 automatically enters an internal reset state

TRUE

DATA OUTPUT

when the power supply voltage V drops below approxi-

CC

mately 2.2V. This feature guarantees the integrity of the

conversion result and of the serial interface mode selec-

tion. (See the 2-wire I/O sections in the Serial Interface

2410 F02

Figure 2. LTC2410 State Transition Diagram

Timing Modes section.)

2410fa

12

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

+

–

WhentheV voltagerisesabovethiscriticalthreshold,the

Input signals applied to IN and IN pins may extend by

CC

converter creates an internal power-on-reset (POR) signal

with a duration of approximately 0.5ms. The POR signal

clears all internal registers. Following the POR signal, the

LTC2410 starts a normal conversion cycle and follows the

successionofstatesdescribedabove.Thefirstconversion

result following POR is accurate within the specifications

of the device if the power supply voltage is restored within

the operating range (2.7V to 5.5V) before the end of the

POR time interval.

300mV below ground and above V . In order to limit any

fault current, resistors of up to 5k may be added in series

CC

+

–

with the IN and IN pins without affecting the perfor-

mance of the device. In the physical layout, it is important

to maintain the parasitic capacitance of the connection

between these series resistors and the corresponding

pins as low as possible; therefore, the resistors should

be located as close as practical to the pins. The effect of

the series resistance on the converter accuracy can be

evaluated from the curves presented in the Input Current/

Reference Current sections. In addition, series resistors

will introduce a temperature dependent offset error due

to the input leakage current. A 1nA input leakage current

Reference Voltage Range

Thisconverteracceptsatrulydifferentialexternalreference

voltage.Theabsolute/commonmodevoltagespecification

+

–

will develop a 1ppm offset error on a 5k resistor if V

5V. This error has a very strong temperature dependency.

=

REF

for the REF and REF pins covers the entire range from

+

GND to V . For correct converter operation, the REF pin

CC

–

must always be more positive than the REF pin.

Output Data Format

The LTC2410 can accept a differential reference voltage

The LTC2410 serial output data stream is 32 bits long.

The first 3 bits represent status information indicating

the sign and conversion state. The next 24 bits are the

conversion result, MSB first. The remaining 5 bits are

sub LSBs beyond the 24-bit level that may be included

in averaging or discarded without loss of resolution. The

third and fourth bit together are also used to indicate an

underrange condition (the differential input voltage is

below –FS) or an overrange condition (the differential

input voltage is above +FS).

from0.1VtoV .Theconverteroutputnoiseisdetermined

CC

by the thermal noise of the front-end circuits, and as such,

its value in nanovolts is nearly constant with reference

voltage. A decrease in reference voltage will not signifi-

cantly improve the converter’s effective resolution. On the

other hand, a reduced reference voltage will improve the

converter’s overall INL performance. A reduced reference

voltagewillalsoimprovetheconverterperformancewhen

operated with an external conversion clock (external F

O

signal) at substantially higher output data rates (see the

Output Data Rate section).

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Input Voltage Range

The analog input is truly differential with an absolute/

+

–

common mode range for the IN and IN input pins

extending from GND – 0.3V to V + 0.3V. Outside

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

CC

these limits, the ESD protection devices begin to turn

on and the errors due to input leakage current increase

rapidly. Within these limits, the LTC2410 converts the

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If V is >0, this bit is HIGH. If V is <0,

+

–

IN

bipolar differential input signal, V = IN – IN , from

IN

this bit is LOW.

–FS = –0.5 • V

to +FS = 0.5 • V

where V

=

REF

+

–

REF – REF . Outside this range, the converter indicates

the overrange or the underrange condition using distinct

output codes.

Bit28(fourthoutputbit)isthemostsignificantbit(MSB)of

the result. This bit in conjunction with Bit 29 also provides

the underrange or overrange indication. If both Bit 29 and

Bit 28areHIGH, the differential inputvoltage is above +FS.

2410fa

13

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

If both Bit 29 and Bit 28 are LOW, the differential input

voltage is below –FS.

Data is shifted out of the SDO pin under control of the

serial clock (SCK), see Figure 3. Whenever CS is HIGH,

SDO remains high impedance and any externally gener-

ated SCK clock pulses are ignored by the internal data

out shift register.

The function of these bits is summarized in Table 1.

Table 1. LTC2410 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

In order to shift the conversion result out of the device,

CS must first be driven LOW. EOC is seen at the SDO pin

of the device once CS is pulled LOW. EOC changes real

time from HIGH to LOW at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on

the first falling edge of SCK. The final data bit (Bit 0) is

shifted out on the falling edge of the 31st SCK and may

be latched on the rising edge of the 32nd SCK pulse. On

the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

Input Range

EOC

DMY

SIG

MSB

V

≥ 0.5 • V

0

1

0

1

0

IN

REF

0V ≤ V < 0.5 • V

0

1

IN

REF

–0.5 • V ≤ V < 0V

0

REF

IN

V

< –0.5 • V

0

IN

REF

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0

may be included in averaging or discarded without loss

of resolution.

CS

BIT 31

BIT 30

“0”

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 5

BIT 0

SDO

SCK

LSB

24

EOC

Hi-Z

1

2

3

4

5

26

27

32

SLEEP

DATA OUTPUT

CONVERSION

2410 F03

Figure 3. Output Data Timing

Table 2. LTC2410 Output Data Format

Differential Input Voltage

V *

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bit 27

Bit 26

Bit 25

…

Bit 0

IN

V * ≥ 0.5 • V **

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

…

0

1

0

1

0

1

0

1

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

REF

0.25 • V ** – 1LSB

REF

0

–1LSB

–0.25 • V **

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

REF

V * < –0.5 • V **

0

IN

REF

+

–

*The differential Input voltage V = IN – IN .

IN

+

–

**The differential reference voltage V = REF – REF .

REF

2410fa

14

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LTC2410

APPLICATIONS INFORMATION

+

–

–80

–85

As long as the voltage on the IN and IN pins is main-

tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum

CC

–90

operating range, a conversion result is generated for any

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

differential input voltage V from –FS = –0.5 • V

to

IN

REF

+FS = 0.5 • V . For differential input voltages greater

REF

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

–12

–8

–4

0

4

8

12

Frequency Rejection Selection (F )

O

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

/2560(%)

2410 F04

EOSC

The LTC2410 internal oscillator provides better than

110dB normal mode rejection at the line frequency and

all its harmonics for 50Hz 2ꢀ or 60Hz 2ꢀ. For 60Hz

Figure 4. LTC2410 Normal Mode Rejection When

Using an External Oscillator of Frequency f_EOSC

rejection, F should be connected to GND while for 50Hz

O

rejection the F pin should be connected to V .

O

CC

tor and enters the Internal Conversion Clock mode. The

LTC2410 operation will not be disturbed if the change of

conversion clock source occurs during the sleep state

or during the data output state while the converter uses

an external serial clock. If the change occurs during the

conversion state, the result of the conversion in progress

may be outside specifications but the following conver-

sions will not be affected. If the change occurs during the

data output state and the converter is in the Internal SCK

mode, the serial clock duty cycle may be affected but the

serial data stream will remain valid.

The selection of 50Hz or 60Hz rejection can also be made

by driving F to an appropriate logic level. A selection

O

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2410 can

operate with an external conversion clock. The converter

automatically detects the presence of an external clock

Table 3 summarizes the duration of each state and the

achievable output data rate as a function of F .

O

signal at the F pin and turns off the internal oscillator.

O

The frequency f

of the external signal must be at least

EOSC

2560Hz(1Hznotchfrequency)tobedetected.Theexternal

clock signal duty cycle is not significant as long as the

minimum and maximum specifications for the high and

SERIAL INTERFACE PINS

TheLTC2410transmitstheconversionresultsandreceives

the start of conversion command through a synchronous

3-wire interface. During the conversion and sleep states,

this interface can be used to assess the converter status

and during the data output state it is used to read the

conversion result.

low periods t

and t

are observed.

HEO

LEO

While operating with an external conversion clock of a

frequency f , the LTC2410 provides better than 110dB

EOSC

normal mode rejection in a frequency range f

4ꢀ and its harmonics. The normal mode rejection as a

function of the input frequency deviation from f

is shown in Figure 4.

/2560

EOSC

Serial Clock Input/Output (SCK)

/2560

EOSC

The serial clock signal present on SCK (Pin 13) is used to

synchronize the data transfer. Each bit of data is shifted

out the SDO pin on the falling edge of the serial clock.

Whenever an external clock is not present at the F pin,

O

the converter automatically activates its internal oscilla-

2410fa

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LTC2410

APPLICATIONS INFORMATION

Table 3. LTC2410 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

(60Hz Rejection)

133ms, Output Data Rate ≤ 7.5 Readings/s

O

F = HIGH

O

160ms, Output Data Rate ≤ 6.2 Readings/s

(50Hz Rejection)

External Oscillator

F = External Oscillator

20510/f

s, Output Data Rate ≤ f /20510 Readings/s

EOSC EOSC

O

with Frequency f

kHz

EOSC

(f /2560 Rejection)

EOSC

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock

F = LOW/HIGH

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.67ms

(32 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

(32 SCK cycles)

ms

EOSC

O

Frequency f

kHz

EOSC

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/f ms

(32 SCK cycles)

SCK

Frequency f

kHz

SCK

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2410 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

internal or external SCK mode is selected on power-up

and then reselected every time a HIGH-to-LOW transition

is detected at the CS pin. If SCK is HIGH or floating at

power-uporduringthistransition,theconverterentersthe

internal SCK mode. If SCK is LOW at power-up or during

thistransition,theconverterenterstheexternalSCKmode.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversion status and to enable the data output transfer

as described in the previous sections.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2410 will abort any serial data

transfer in progress and start a new conversion cycle any-

time a LOW-to-HIGH transition is detected at the CS pin

after the converter has entered the data output state (i.e.,

after the first rising edge of SCK occurs with CS = LOW).

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO

pin is used as an end of conversion indicator during the

conversion and sleep states.

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

GroundingCSwillforcetheADCtocontinuouslyconvertat

the maximum output rate selected by F . Tying a capacitor

O

to CS will reduce the output rate and power dissipation by

a factor proportional to the capacitor’s value, see Figures

12 to 14.

When CS (Pin 11) is HIGH, the SDO driver is switched

to a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase, theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

SERIAL INTERFACE TIMING MODES

The LTC2410’s 3-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes

of operation. These include internal/external serial clock,

2-or3-wireI/O,singlecycleconversionandautostart.The

2410fa

16

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LTC2410

APPLICATIONS INFORMATION

following sections describe each of these serial interface

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0

if the device is in the sleep state. Independent of CS, the

deviceautomaticallyentersthelowpowersleepstateonce

the conversion is complete.

timing modes in detail. In all these cases, the converter

can use the internal oscillator (F = LOW or F = HIGH)

O

or an external oscillator connected to the F pin. Refer to

O

Table 4 for a summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

When the device is in the sleep state (EOC = 0), its con-

version result is held in an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK is seen while CS is LOW. Data is shifted out

the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

The serial clock mode is selected on the falling edge of

CS. To select the external serial clock mode, the serial

clock pin (SCK) must be LOW during each CS falling edge.

Table 4. LTC2410 Interface Timing Modes

Conversion

Cycle

Control

Data

Output

Control

Connection

and

Waveforms

SCK

Configuration

Source

External

Internal

External SCK, Single Cycle Conversion

External SCK, 2-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 5, 6

Figure 7

Internal SCK, Single Cycle Conversion

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal SCK, Autostart Conversion

Figures 8, 9

Figure 10

Figure 11

CS ↓

Continuous

Internal

C

EXT

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

2

14

13

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2410

3

4

+

–

REFERENCE

VOLTAGE

REF

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 31

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SUB LSB

SDO

EOC

Hi-Z

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2410 F05

Figure 5. External Serial Clock, Single Cycle Operation

2410fa

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LTC2410

APPLICATIONS INFORMATION

SCK. EOC can be latched on the first rising edge of SCK externally generated serial clock (SCK) signal, see Figure

and the last bit of the conversion result can be latched on 7. CS may be permanently tied to ground, simplifying the

the 32nd rising edge of SCK. On the 32nd falling edge of user interface or isolation barrier.

SCK, the device begins a new conversion. SDO goes HIGH

The external serial clock mode is selected at the end of the

(EOC = 1) indicating a conversion is in progress.

power-on reset (POR) cycle. The POR cycle is concluded

At the conclusion of the data cycle, CS may remain LOW approximately 0.5ms after V exceeds 2.2V. The level

CC

and EOC monitored as an end-of-conversion interrupt. applied to SCK at this time determines if SCK is internal

Alternatively, CS may be driven HIGH setting SDO to Hi-Z. or external. SCK must be driven LOW prior to the end of

As described above, CS may be pulled LOW at any time PORinordertoentertheexternalserialclocktimingmode.

in order to monitor the conversion status.

Since CS is tied LOW, the end-of-conversion (EOC) can

Typically, CS remains LOW during the data output state. be continuously monitored at the SDO pin during the

However, the data output state may be aborted by pull- convert and sleep states. EOC may be used as an interrupt

ing CS HIGH anytime between the first rising edge and to an external controller indicating the conversion result

the 32nd falling edge of SCK, see Figure 6. On the rising is ready. EOC = 1 while the conversion is in progress and

edge of CS, the device aborts the data output state and EOC = 0 once the conversion enters the low power sleep

immediately initiates a new conversion. This is useful for state. On the falling edge of EOC, the conversion result

systems not requiring all 32 bits of output data, aborting is loaded into an internal static shift register. The device

an invalid conversion cycle or synchronizing the start of remains in the sleep state until the first rising edge of SCK.

a conversion.

Data is shifted out the SDO pin on each falling edge of

SCK enabling external circuitry to latch data on the rising

edge of SCK. EOC can be latched on the first rising edge

of SCK. On the 32nd falling edge of SCK, SDO goes HIGH

(EOC = 1) indicating a new conversion has begun.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface.

The conversion result is shifted out of the device by an

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

2

14

13

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2410

3

+

REFERENCE

REF

SCK

VOLTAGE

4

–

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 0

BIT 31

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 9

BIT 8

SDO

EOC

Hi-Z

SCK

(EXTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

2410 F06

Figure 6. External Serial Clock, Reduced Data Output Length

2410fa

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LTC2410

APPLICATIONS INFORMATION

Internal Serial Clock, Single Cycle Operation

In order to select the internal serial clock timing mode,

the serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resis-

This timing mode uses an internal serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

2

14

13

V

F

O

CC

LTC2410

3

+

REFERENCE

REF

SCK

VOLTAGE

4

–

2-WIRE

INTERFACE

0.1V TO V

CC

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

CS

BIT 31

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

EOC

24

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2410 F07

Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)

2.7V TO 5.5V

V

CC

V

^CC= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

1µF

2

14

13

V

F

O

CC

LTC2410

10k

3

4

+

REFERENCE

VOLTAGE

REF

SCK

–

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

<t

EOCtest

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

24

Hi-Z

SCK

(INTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2410 F08

Figure 8. Internal Serial Clock, Single Cycle Operation

2410fa

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LTC2410

APPLICATIONS INFORMATION

tor is active on the SCK pin during the falling edge of CS;

therefore,theinternalserialclocktimingmodeisautomati-

cally selected if SCK is not externally driven.

remains in the sleep state. The conversion result is held

in the internal static shift register.

If CS remains LOW longer than t , the first rising

EOCtest

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins

on this first rising edge of SCK and concludes after the

32nd rising edge. Data is shifted out the SDO pin on each

falling edge of SCK. The internally generated serial clock

is output to the SCK pin. This signal may be used to shift

the conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result on the 32nd rising edge of SCK.

After the 32nd rising edge, SDO goes HIGH (EOC = 1),

SCK stays HIGH and a new conversion starts.

When testing EOC, if the conversion is complete (EOC =

0), the device will exit the sleep state and enter the data

output state if CS remains LOW. In order to prevent the

device from exiting the low power sleep state, CS must

be pulled HIGH before the first rising edge of SCK. In

the internal SCK timing mode, SCK goes HIGH and the

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

device begins outputting data at time t

after the

EOCtest

after EOC goes

falling edge of CS (if EOC = 0) or t

EOCtest

LOW (if CS is LOW during the falling edge of EOC). The

value of t is 23µs if the device is using its internal

EOCtest

oscillator (F = logic LOW or HIGH). If F is driven by an

O

external oscillator of frequency f

, then t

is 3.6/

EOSC

EOCtest

, the device

f

. If CS is pulled HIGH before time t

EOSC

EOCtest

2.7V TO 5.5V

V

CC

V

^CC= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

1µF

2

14

13

V

F

O

CC

10k

LTC2410

3

+

–

REFERENCE

REF

SCK

VOLTAGE

4

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

<t

EOCtest

GND

>t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 31

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 8

SDO

SCK

EOC

Hi-Z

(INTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

2410 F09

Figure 9. Internal Serial Clock, Reduced Data Output Length

2410fa

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APPLICATIONS INFORMATION

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

beavoidedbyaddinganexternal10kpull-upresistortothe

SCK pin or by never pulling CS HIGH when SCK is LOW.

to a HIGH level before CS goes low again. This is not a

concern under normal conditions where CS remains LOW

after detecting EOC = 0. This situation is easily overcome

by adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

Whenever SCK is LOW, the LTC2410’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certainapplicationsmayrequireanexternaldriveronSCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2410’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge,thedevicewillremainintheinternalSCKtimingmode.

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. Theconversionresultisshiftedoutofthedevice

by an internally generated serial clock (SCK) signal, see

Figure 10. CS may be permanently tied to ground, sim-

plifying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after V exceeds 2.2V. An internal

CC

weak pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sion status. If the device is in the sleep state (EOC = 0),

SCK will go LOW. Once CS goes HIGH (within the time

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

period defined above as t ), the internal pull-up is

EOCtest

activated. For a heavy capacitive load on the SCK pin,

the internal pull-up may not be adequate to return SCK

2.7V TO 5.5V

V

^CC= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

1µF

2

14

V

CC

F

O

LTC2410

3

+

–

13

REFERENCE

REF

SCK

VOLTAGE

4

2-WIRE

INTERFACE

0.1V TO V

CC

5

6

12

11

+

ANALOG INPUT RANGE

IN

SDO

–0.5V

TO 0.5V

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

CS

BIT 31

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

EOC

24

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

2410 F10

SLEEP

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

2410fa

21

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LTC2410

APPLICATIONS INFORMATION

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data output

cycle begins on the first rising edge of SCK and ends after

the 32nd rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. EOC can

be latched on the first rising edge of SCK and the last bit

of the conversion result can be latched on the 32nd rising

edge of SCK. After the 32nd rising edge, SDO goes HIGH

(EOC = 1) indicating a new conversion is in progress. SCK

remains HIGH during the conversion.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 11. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 12 and 13. Once the

voltage at CS falls below an internal threshold (≈1.4V),

the device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 32nd rising edge. Data is shifted out the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 14 shows the average supply current as a function

of capacitance on CS.

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

2

14

13

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2410

3

+

REFERENCE

REF

SCK

VOLTAGE

4

–

2-WIRE

INTERFACE

0.1V TO V

CC

5

6

12

11

+

ANALOG INPUT RANGE

IN

SDO

–0.5V

TO 0.5V

REF

–

IN

CS

1, 7, 8, 9, 10, 15, 16

GND

C

EXT

V

CC

CS

GND

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 0

SDO

Hi-Z

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2410 F11

Figure 11. Internal Serial Clock, Autostart Operation

2410fa

22

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

7

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode,theanalogvoltageontheCSpincannotbeobserved

without disturbing the converter operation using a regular

oscilloscope probe. When using this configuration, it is

important to minimize the external leakage current at

the CS pin by using a low leakage external capacitor and

properly cleaning the PCB surface.

6

5

4

3

2

V

= 5V

CC

1

0

V

= 3V

CC

The internal serial clock mode is selected every time the

voltageontheCSpincrossesaninternalthresholdvoltage.

An internal weak pull-up at the SCK pin is active while CS

is discharging; therefore, the internal serial clock timing

mode is automatically selected if SCK is floating. It is

important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

10

100

100000

1

1000

10000

CAPACITANCE ON CS (pF)

2410 F12

Figure 12. CS Capacitance vs t_SAMPLE

8

7

6

V

= 5V

PRESERVING THE CONVERTER ACCURACY

CC

5

V

= 3V

CC

The LTC2410 is designed to reduce as much as possible

theconversionresultsensitivitytodevicedecoupling,PCB

layout, anti-aliasing circuits, line frequency perturbations

and so on. Nevertheless, in order to preserve the extreme

accuracy capability of this part, some simple precautions

are desirable.

4

3

2

1

0

10

100

10000

100000

0

1000

CAPACITANCE ON CS (pF)

Digital Signal Levels

2410 F13

The LTC2410’s digital interface is easy to use. Its digital

Figure 13. CS Capacitance vs Output Rate

inputs(F ,CSandSCKinExternalSCKmodeofoperation)

O

accept standard TTL/CMOS logic levels and the internal

hysteresis receivers can tolerate edge rates as slow as

100µs. However, some considerations are required to

takeadvantageoftheexceptionalaccuracyandlowsupply

current of this converter.

300

250

V

= 5V

= 3V

CC

200

150

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

100

50

0

While a digital input signal is in the range 0.5V to

(V – 0.5V), the CMOS input receiver draws additional

CC

1

10

100

1000

10000 100000

current from the power supply. It should be noted that,

CAPACITANCE ON CS (pF)

when any one of the digital input signals (F , CS and SCK

O

2410 F14

in External SCK mode of operation) is within this range,

Figure 14. CS Capacitance vs Supply Current

the LTC2410 power supply current may increase even if

2410fa

23

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

the signal in question is at a valid logic level. For micro-

input terminals may result into a DC offset error. Such

perturbations may occur due to asymmetric capacitive

power operation, it is recommended to drive all digital

input signals to full CMOS levels [V < 0.4V and V

>

coupling between the F signal trace and the converter

IL

OH

O

(V – 0.4V)].

input and/or reference connection traces. An immediate

CC

solution is to maintain maximum possible separation be-

During the conversion period, the undershoot and/or

overshootofafastdigitalsignalconnectedtotheLTC2410

pins may severely disturb the analog to digital conversion

process. Undershoot and overshoot can occur because of

the impedance mismatch at the converter pin when the

transition time of an external control signal is less than

twice the propagation delay from the driver to LTC2410.

For reference, on a regular FR-4 board, signal propagation

velocityisapproximately183ps/inchforinternaltracesand

170ps/inch for surface traces. Thus, a driver generating a

control signal with a minimum transition time of 1ns must

be connected to the converter pin through a trace shorter

than2.5inches.Thisproblembecomesparticularlydifficult

when shared control lines are used and multiple reflec-

tions may occur. The solution is to carefully terminate all

transmissionlinesclosetotheircharacteristicimpedance.

tween the F signal trace and the input/reference signals.

O

WhentheF signalisparallelterminatedneartheconverter,

O

substantial AC current is flowing in the loop formed by

the F connection trace, the termination and the ground

O

return path. Thus, perturbation signals may be inductively

coupled into the converter input and/or reference. In this

situation, the user must reduce to a minimum the loop

area for the F signal as well as the loop area for the dif-

O

ferential input and reference connections.

Driving the Input and Reference

The input and reference pins of the LTC2410 converter

are directly connected to a network of sampling capaci-

tors. Depending upon the relation between the differential

input voltage and the differential reference voltage, these

capacitors are switching between these four pins transfer-

ring small amounts of charge in the process. A simplified

equivalent circuit is shown in Figure 15.

Parallel termination near the LTC2410 pin will eliminate

this problem but will increase the driver power dissipa-

tion. A series resistor between 27Ω and 56Ω placed near

the driver or near the LTC2410 pin will also eliminate this

problem without additional power dissipation. The actual

resistor value depends upon the trace impedance and

connection topology.

For a simple approximation, the source impedance R

S

+

–

+

–

driving an analog input pin (IN , IN , REF or REF ) can

be considered to form, together with R and C (see

SW

EQ

Figure 15), a first order passive network with a time

constant τ = (R + R ) • C . The converter is able to

S

SW

EQ

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The multiple ground pins used

in this package configuration, as well as the differential

input and reference architecture, reduce substantially the

converter’s sensitivity to ground currents.

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on

the four input analog pins is quasi-independent so each

time constant should be considered by itself and, under

worst-case circumstances, the errors may add.

When using the internal oscillator (F = LOW or HIGH),

O

Particular attention must be given to the connection of

the LTC2410’s front-end switched-capacitor network is

clocked at 76800Hz corresponding to a 13µs sampling

period. Thus, for settling errors of less than 1ppm, the

driving source impedance should be chosen such that τ ≤

13µs/14=920ns.Whenanexternaloscillatoroffrequency

the F signal when the LTC2410 is used with an external

O

conversion clock. This clock is active during the conver-

sion time and the normal mode rejection provided by the

internal digital filter is not very high at this frequency. A

normal mode signal of this frequency at the converter

referenceterminalsmayresultintoDCgainandINLerrors.

A normal mode signal of this frequency at the converter

f

is used, the sampling period is 2/f

and, for a

EOSC

settling error of less than 1ppm, τ ≤ 0.14/f

.

2410fa

24

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

Input Current

R

SOURCE

+

IN

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

theINLperformanceoftheconverter. Figure15showsthe

mathematical expressions for the average bias currents

C

PAR

V

+ 0.5V

– 0.5V

C

INCM

IN

≅20pF

LTC2410

SOURCE

–

IN

2410 F16

C

PAR

≅20pF

+

–

flowing through the IN and IN pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

Figure 16. An RC Network at IN⁺and IN^–

50

The effect of this input dynamic current can be analyzed

C

= 0.01µF

IN

C

= 0.001µF

using the test circuit of Figure 16. The C

capacitor

IN

C

PAR

40

30

20

10

0

includes the LTC2410 pin capacitance (5pF typical) plus

thecapacitanceofthetestfixtureusedtoobtaintheresults

shown in Figures 17 and 18. A careful implementation can

bring the total input capacitance (C + C ) closer to 5pF

= 100pF

IN

C

= 0pF

IN

V

= 5V

CC

+

–

IN

PAR

REF = 5V

REF = GND

thus achieving better performance than the one predicted

byFigures17and18.Forsimplicity,twodistinctsituations

can be considered.

+

–

IN = 5V

IN = 2.5V

F

= GND

= 25°C

O

T

A

For relatively small values of input capacitance (C

<

1

10

100

1k

(Ω)

10k

100k

IN

R

SOURCE

0.01µF), the voltage on the sampling capacitor settles

almostcompletelyandrelativelylargevaluesforthesource

2410 F17

Figure 17. +FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

impedance result in only small errors. Such values for C

IN

V

CC

I

+

REF

R

(TYP)

SW

V

_IN+ V_INCM− V_REFCM

I

I IN⁺

=

LEAK

20k

(

)

AVG

0.5•R_EQ

V

REF

−V_IN+ V_INCM− V_REFCM

0.5•R_EQ

I IN⁻

LEAK

(

V

CC

1.5•V_REF− V_INCM+ V_REFCM

V²

I

+

IN

I REF⁺

=

−

IN

R

SW

(TYP)

20k

(

)

I

AVG

LEAK

0.5•R_EQ

V_REF•R_EQ

V

+

IN

−1.5•V_REF− V_INCM+ V_REFCM

0.5•R_EQ

V²

V_REF•R_EQ

I REF⁻

=

IN

C

+

EQ

(

18pF

(TYP)

where:

V

CC

I

–

IN

V_REF=REF⁺−REF⁻

R

(TYP)

SW

I

LEAK

20k

REF⁺+REF



⁻

V

V_REFCM

=





2





V

_IN=IN⁺−IN⁻

V

CC

I

–

IN⁺−IN



⁻

REF

(TYP)

20k

SW

V

=

I

INCM





LEAK

2





2410 F15

V

REF

R_EQ= 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch F =LOW

(

)

O

R_EQ= 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch F =HIGH

O

R_EQ= 0.555•10¹²/ f_EOSCEXTERNAL OSCILLATOR

(

)

SWITCHING FREQUENCY

f

= 76800Hz INTERNAL OSCILLATOR (F = LOW OR HIGH)

SW

O

= 0.5 • f

EXTERNAL OSCILLATOR

EOSC

Figure 15. LTC2410 Equivalent Analog Input Circuit

2410fa

25

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

12

0

input resistance is 0.28 • 10 /f

Ω and each ohm of

EOSC

V

= 5V

CC

+

–

+

source resistance driving IN or IN will result in

REF = 5V

–

REF = GND

–10

–20

–30

–40

–50

–6

+

–

1.78 • 10 • f

gain error. The effect of the source

EOSCppm

IN = GND

IN = 2.5V

resistance on the two input pins is additive with respect to

this gain error. The typical +FS and –FS errors as a func-

F

= GND

= 25°C

O

A

T

+

tion of the sum of the source resistance seen by IN and

IN for large values of C are shown in Figures 19 and 20.

–

C

= 0.01µF

IN

C

= 0.001µF

IN

C

In addition to this gain error, an offset error term may

also appear. The offset error is proportional with the

mismatch between the source impedance driving the two

= 100pF

IN

C

= 0pF

IN

1

10

100

R

1k

(Ω)

10k

100k

+

–

input pins IN and IN and with the difference between the

input and reference common mode voltages. While the

input drive circuit nonzero source impedance combined

with the converter average input current will not degrade

the INL performance, indirect distortion may result from

the modulation of the offset error by the common mode

component of the input signal. Thus, when using large

SOURCE

2410 F18

Figure 18. –FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

will deteriorate the converter offset and gain performance

without significant benefits of signal filtering and the user

is advised to avoid them. Nevertheless, when small val-

ues of C are unavoidably present as parasitics of input

IN

C capacitor values, it is advisable to carefully match the

IN

multiplexers, wires, connectors or sensors, the LTC2410

can maintain its exceptional accuracy while operating

with relative large values of source resistance as shown in

Figures17and18.Thesemeasuredresultsmaybeslightly

different from the first order approximation suggested

earlier because they include the effect of the actual second

order input network together with the nonlinear settling

+

–

source impedance seen by the IN and IN pins. When

F = LOW (internal oscillator and 60Hz notch), every 1Ω

O

mismatch in source impedance transforms a full-scale

common mode input signal into a differential mode input

signal of 0.28ppm. When F = HIGH (internal oscillator

O

and 50Hz notch), every 1Ω mismatch in source imped-

ance transforms a full-scale common mode input signal

process of the input amplifiers. For small C values, the

IN

into a differential mode input signal of 0.23ppm. When F

O

+

–

settling on IN and IN occurs almost independently and

there is little benefit in trying to match the source imped-

ance for the two pins.

is driven by an external oscillator with a frequency f

,

EOSC

every1Ωmismatchinsourceimpedancetransformsafull-

scale common mode input signal into a differential mode

–6

input signal of 1.78 • 10 • f

. Figure 21 shows the

Larger values of input capacitors (C > 0.01µF) may be

EOSCppm

IN

typical offset error due to input common mode voltage for

variousvaluesofsourceresistanceimbalancebetweenthe

required in certain configurations for anti-aliasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

+

–

IN and IN pins when large C values are used.

IN

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

When F = LOW (internal oscillator and 60Hz notch), the

O

typical differential input resistance is 1.8MΩ which will

generate a gain error of approximately 0.28ppm for each

+

–

ohm of source resistance driving IN or IN . When F =

O

HIGH (internal oscillator and 50Hz notch), the typical dif-

ferential input resistance is 2.16MΩ which will generate

a gain error of approximately 0.23ppm for each ohm of

Themagnitudeofthedynamicinputcurrentdependsupon

thesizeoftheverystableinternalsamplingcapacitorsand

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

+

–

source resistance driving IN or IN . When F is driven

O

by an external oscillator with a frequency f

nal conversion clock operation), the typical differential

(exter-

EOSC

2410fa

26

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

300

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock.Whenrelativelystableresistors(50ppm/°C)areused

for the external source impedance seen by IN and IN ,

the expected drift of the dynamic current, offset and gain

errors will be insignificant (about 1% of their respective

valuesovertheentiretemperatureandvoltagerange).Even

for the most stringent applications, a one-time calibration

operation may be sufficient.

V

= 5V

CC

C

= 1µF, 10µF

IN

+

REF = 5V

–

REF = GND

240

180

120

60

+

–

IN = 3.75V

+

–

IN = 1.25V

F

= GND

= 25°C

O

A

T

C

= 0.1µF

IN

C

= 0.01µF

IN

0

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA ( 10nA max), results

inasmalloffsetshift. A100Ωsourceresistancewillcreate

a 0.1µV typical and 1µV maximum offset voltage.

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2410 F19

Figure 19. +FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

0

C

= 0.01µF

= 0.1µF

IN

Reference Current

–60

–120

–180

–240

–300

In a similar fashion, the LTC2410 samples the differential

+

–

reference pins REF and REF transferring small amount

of charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gain and INL performance. The effect of this current can

be analyzed in the same two distinct situations.

C

IN

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

O

A

C

= 1µF, 10µF

IN

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

Forrelativelysmallvaluesoftheexternalreferencecapaci-

R

SOURCE

tors(C <0.01µF),thevoltageonthesamplingcapacitor

2410 F20

REF

Figure 20. –FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

120

V

= 5V

CC

values for C

will deteriorate the converter offset and

REF

+

100

80

REF = 5V

A

B

–

REF = GND

IN = IN = V

gainperformancewithoutsignificantbenefitsofreference

filtering and the user is advised to avoid them.

+

–

INCM

60

40

C

D

E

F

Larger values of reference capacitors (C

> 0.01µF)

20

REF

0

may be required as reference filters in certain configura-

tions. Suchcapacitorswillaveragethereferencesampling

charge and the external source resistance will see a quasi

–20

–40

–60

–80

–100

–120

F

T

R

C

= GND

= 25°C

O

A

G

constantreferencedifferentialimpedance.WhenF =LOW

O

– = 500Ω

SOURCEIN

= 10µF

(internaloscillatorand60Hznotch), thetypicaldifferential

reference resistance is 1.3MΩ which will generate a gain

error of approximately 0.38ppm for each ohm of source

IN

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V

(V)

INCM

A: ∆R = +400Ω

IN

E: ∆R = –100Ω

IN

+

–

resistancedrivingREF orREF . WhenF =HIGH(internal

B: ∆R = +200Ω

F: ∆R = –200Ω

IN

O

IN

C: ∆R = +100Ω

G: ∆R = –400Ω

IN

oscillator and 50Hz notch), the typical differential refer-

ence resistance is 1.56MΩ which will generate a gain

error of approximately 0.32ppm for each ohm of source

D: ∆R = 0Ω

2410 F21

IN

Figure 21. Offset Error vs Common Mode Voltage

(V_INCM= IN⁺= IN^–) and Input Source Resistance Imbalance

(∆R_IN= R_SOURCEIN⁺– R_SOURCEIN^–) for Large C_INValues (C_IN≥ 1µF)

+

–

resistance driving REF or REF . When F is driven by

O

2410fa

27

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

an external oscillator with a frequency f

(external

= HIGH (internal oscillator and 50Hz notch), every 100Ω

EOSC

+

–

conversion clock operation), the typical differential ref-

of source resistance driving REF or REF translates into

12

erence resistance is 0.20 • 10 /f

Ω and each ohm

about 1.1ppm additional INL error. When F is driven by

EOSC

O

+

–

of source resistance driving REF or REF will result in

an external oscillator with a frequency f

, every 100Ω

EOSC

–6

+

–

2.47 • 10 • f

gain error. The effect of the source

of source resistance driving REF or REF translates

EOSCppm

–6

resistanceonthetworeferencepinsisadditivewithrespect

into about 8.73 • 10 • f

additional INL error.

EOSCppm

+

–

to this gain error. The typical FS and FS errors for vari-

Figure 26 shows the typical INL error due to the source

+

–

ous combinations of source resistance seen by the REF

resistance driving the REF or REF pins when large C

REF

–

and REF pins and external capacitance C

connected

values are used. The effect of the source resistance on

the two reference pins is additive with respect to this INL

error. In general, matching of source impedance for the

REF

to these pins are shown in Figures 22, 23, 24 and 25.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

+

–

REF and REF pins does not help the gain or the INL er-

ror. The user is thus advised to minimize the combined

WhenF =LOW(internaloscillatorand60Hznotch),every

O

+

–

source impedance driving the REF and REF pins rather

than to try to match it.

+

–

100Ω of source resistance driving REF or REF trans-

lates into about 1.34ppm additional INL error. When F

O

0

50

C

= 0.01µF

REF

V

= 5V

CC

+

REF = 5V

C

= 0.001µF

REF

–

REF = GND

–10

–20

–30

–40

–50

40

30

20

10

0

+

–

C

= 100pF

IN = 5V

REF

IN = 2.5V

C

= 0pF

REF

F

= GND

= 25°C

O

A

T

V

= 5V

CC

+

–

REF = 5V

C

= 0.01µF

REF = GND

REF

+

–

IN = GND

C

= 0.001µF

REF

IN = 2.5V

F

= GND

= 25°C

O

C

= 100pF

REF

T

A

C

= 0pF

REF

1

10

100

1k

10k

100k

1

10

100

1k

10k

100k

R

(Ω)

R

(Ω)

SOURCE

2410 F22

2410 F23

Figure 22. +FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

Figure 23. –FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

0

450

C

= 0.01µF

= 0.1µF

REF

V

= 5V

CC

C

REF

= 1µF, 10µF

+

REF = 5V

–

REF = GND

–90

–180

–270

–360

–450

360

270

180

90

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

O

A

C

T

REF

C

= 0.1µF

REF

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 3.75V

C

= 0.01µF

REF

IN = 1.25V

C

= 1µF, 10µF

F

= GND

= 25°C

REF

O

A

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2410 F24

2410 F25

Figure 24. +FS Error vs R_SOURCEat REF⁺or REF^–(Large C_REF

)

Figure 25. –FS Error vs R_SOURCEat REF⁺or REF^–(Large C_REF

)

2410fa

28

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

15

data output phases which are controlled by the user and

which can be made insignificantly short. When operated

R

= 1000Ω

12

9

SOURCE

with an external conversion clock (F connected to an

O

R

= 500Ω

SOURCE

6

external oscillator), the LTC2410 output data rate can be

3

increasedasdesired.Thedurationoftheconversionphase

0

is20510/f

.Iff

=153600Hz,theconverterbehaves

EOSC

–3

–6

–9

–12

–15

R

= 100Ω

SOURCE

as if the internal oscillator is used and the notch is set at

60Hz. There is no significant difference in the LTC2410

performance between these two operation modes.

An increase in f

over the nominal 153600Hz will

EOSC

–0.5–0.4–0.3–0.2–0.1

0

/V

0.1 0.2 0.3 0.4 0.5

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

V

INDIF REFDIF

V

= 5V

F = GND

O

CC

REF+ = 5V

C

= 10µF

REF

REF– = GND

V

T = 25°C

A

+

–

= 0.5 • (IN + IN ) = 2.5V

2410 F26

INCM

Figure 26. INL vs Differential Input Voltage (V_IN= IN⁺= IN^–)

and Reference Source Resistance (R_SOURCEat REF⁺and REF^–)

for Large C_REFValues (C_REF≥ 1µF)

First, a change in f

will result in a proportional change

EOSC

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line

frequency. In many applications, the subsequent per-

formance degradation can be substantially reduced by

relying upon the LTC2410’s exceptional common mode

rejection and by carefully eliminating common mode to

differential mode conversion sources in the input circuit.

Theusershouldavoidsingle-endedinputfiltersandshould

maintain a very high degree of matching and symmetry

The magnitude of the dynamic reference current depends

uponthesizeoftheverystableinternalsamplingcapacitors

andupontheaccuracyoftheconvertersamplingclock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

+

–

used for the external source impedance seen by REF

in the circuits driving the IN and IN pins.

–

and REF , the expected drift of the dynamic current gain

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

error will be insignificant (about 1% of its value over the

entire temperature and voltage range). Even for the most

stringent applications a one-time calibration operation

may be sufficient.

input and/or reference capacitors (C , C ) are used,

IN REF

the previous section provides formulae for evaluating the

In addition to the reference sampling charge, the refer-

ence pins ESD protection diodes have a temperature de-

pendent leakage current. This leakage current, nominally

1nA ( 10nA max), results in a small gain error. A 100Ω

source resistance will create a 0.05µV typical and 0.5µV

maximum full-scale error.

effect of the source resistance upon the converter perfor-

mance for any value of f

. If small external input and/

IN REF

EOSC

or reference capacitors (C , C ) are used, the effect of

the external source resistance upon the LTC2410 typical

performance can be inferred from Figures 17, 18, 22 and

23 in which the horizontal axis is scaled by 153600/f

.

EOSC

Third,anincreaseinthefrequencyoftheexternaloscillator

above460800Hz(amorethan3×increaseintheoutputdata

rate) will start to decrease the effectiveness of the internal

auto-calibration circuits. This will result in a progressive

degradationintheconverteraccuracyandlinearity.Typical

measured performance curves for output data rates up to

Output Data Rate

Whenusingitsinternaloscillator,theLTC2410canproduce

up to 7.5 readings per second with a notch frequency of

60Hz (F = LOW) and 6.25 readings per second with a

O

notch frequency of 50Hz (F = HIGH). The actual output

O

data rate will depend upon the length of the sleep and

25 readings per second are shown in Figures 27, 28, 29,

2410fa

29

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

500

450

400

350

300

250

200

150

100

50

30, 31, 32, 33 and 34. In order to obtain the highest pos-

sible level of accuracy from this converter at output data

rates above 7.5 readings per second, the user is advised

to maximize the power supply voltage used and to limit

the maximum ambient operating temperature. In certain

circumstances, a reduction of the differential reference

voltage may be beneficial.

V

= 5V

CC

+

REF = 5V

–

REF = GND

V

= 2.5V

INCM

= 0V

IN

F

= EXTERNAL OSCILLATOR

O

Input Bandwidth

T

= 25°C

T

= 85°C

20

A

4

0

The combined effect of the internal Sinc digital filter and

0

5

10

15

25

oftheanaloganddigitalautocalibrationcircuitsdetermines

theLTC2410inputbandwidth.Whentheinternaloscillator

OUTPUT DATA RATE (READINGS/SEC)

2410 F27

is used with the notch set at 60Hz (F = LOW), the 3dB

O

Figure 27. Offset Error vs Output Data Rate and Temperature

input bandwidth is 3.63Hz. When the internal oscillator

is used with the notch set at 50Hz (F = HIGH), the 3dB

O

7000

input bandwidth is 3.02Hz. If an external conversion clock

V

= 5V

CC

generator of frequency f

is connected to the F pin,

EOSC

O

+

6000

5000

4000

3000

2000

1000

0

REF = 5V

–6

–

REF = GND

the 3dB input bandwidth is 0.236 • 10 • f

.

EOSC

+

–

IN = 3.75V

IN = 1.25V

Due to the complex filtering and calibration algorithms

utilized, the converter input bandwidth is not modeled

very accurately by a first order filter with the pole located

at the 3dB frequency. When the internal oscillator is used,

the shape of the LTC2410 input bandwidth is shown in

F

= EXTERNAL OSCILLATOR

O

Figure 35 for F = LOW and F = HIGH. When an external

O

EOSC

T

= 25°C

T

= 85°C

20

A

oscillator of frequency f

is used, the shape of the

0

5

10

15

25

LTC2410 input bandwidth can be derived from Figure 35,

OUTPUT DATA RATE (READINGS/SEC)

2410 F28

F = LOW curve in which the horizontal axis is scaled by

O

EOSC

f

/153600.

Figure 28. +FS Error vs Output Data Rate and Temperature

Theconversionnoise(800nV

typicalforV =5V)can

REF

RMS

be modeled by a white noise source connected to a noise

free converter. The noise spectral density is 62.75nV√Hz

foraninfinitebandwidthsourceand86.1nV√Hzforasingle

0.5MHz pole source. From these numbers, it is clear that

particular attention must be given to the design of external

amplification circuits. Such circuits face the simultaneous

requirements of very low bandwidth (just a few Hz) in

order to reduce the output referred noise and relatively

high bandwidth (at least 500kHz) necessary to drive the

input switched-capacitor network. A possible solution is

a high gain, low bandwidth amplifier stage followed by a

high bandwidth unity-gain buffer.

0

T

= 25°C

T = 85°C

A

–1000

–2000

–3000

–4000

–5000

–6000

–7000

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

F

= EXTERNAL OSCILLATOR

O

0

5

10

15

20

25

OUTPUT DATA RATE (READINGS/SEC)

2410 F29

When external amplifiers are driving the LTC2410, the

ADC input referred system noise calculation can be

Figure 29. –FS Error vs Output Data Rate and Temperature

2410fa

30

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

24

22

20

18

16

14

12

10

8

T

= 25°C

T

= 25°C

23

22

21

20

19

18

17

16

15

14

13

12

A

T

= 85°C

A

T

= 85°C

A

RESOLUTION = LOG (V /INL )

MAX

2

REF

V

= 5V

CC

+

REF = 5V

V

= 5V

CC

–

+

REF = GND

REF = 5V

–

V

= 2.5V

REF = GND

INCM

= 0V

V

= 2.5V

IN

INCM

F

O

= EXTERNAL OSCILLATOR

–2.5V < V < 2.5V

IN

RESOLUTION = LOG (V /NOISE

)

F = EXTERNAL OSCILLATOR

O

2

REF

RMS

0

5

10

15

20

25

0

5

10

15

20

25

OUTPUT DATA RATE (READINGS/SEC)

2410 F30

2410 F31

Figure 30. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Temperature

Figure 31. Resolution (INL_RMS≤ 1LSB)

vs Output Data Rate and Temperature

250

24

23

22

21

20

19

18

17

16

15

14

13

12

V

= 5V

REF

V

= 5V

225

200

175

150

125

100

75

CC

+

REF = GND

V

= 2.5V

INCM

= 0V

V

= 2.5V

IN

REF

F

= EXTERNAL OSCILLATOR

= 25°C

O

A

T

V

= 5V

CC

–

REF = GND

V

F

= 2.5V

INCM

= 0V

IN

= EXTERNAL OSCILLATOR

= 25°C

50

O

T

A

25

RESOLUTION = LOG (V /NOISE

)

2

REF

RMS

V

= 2.5V

15

V

= 5V

REF

0

5

10

20

25

0

5

10

15

20

25

OUTPUT DATA RATE (READINGS/SEC)

2410 F32

2410 F33

Figure 32. Offset Error vs Output

Data Rate and Reference Voltage

Figure 33. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Temperature

22

20

18

16

14

12

10

8

0.0

–0.5

–1.0

–1.5

V

= 2.5V

REF

V

= 5V

REF

F

O

= HIGH

F = LOW

O

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

RESOLUTION =

LOG (V /INL )

MAX

2

REF

T

= 25°C

A

CC

V

= 5V

–

REF = GND

= 0.5 • REF

+

V

INCM

–0.5V • V

< V < 0.5 • V

REF

IN REF

F

O

= EXTERNAL OSCILLATOR

0

5

10

15

20

25

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

OUTPUT DATA RATE (READINGS/SEC)

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2410 F34

2410 F35

Figure 34. Resolution (INL_MAX≤ 1LSB)

vs Output Data Rate and Reference Voltage

Figure 35. Input Signal Bandwidth

Using the Internal Oscillator

2410fa

31

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

100

10

1

simplified by Figure 36. The noise of an amplifier driving

the LTC2410 input pin can be modeled as a band limited

white noise source. Its bandwidth can be approximated

by the bandwidth of a single pole lowpass filter with a

F

= LOW

= HIGH

O

corner frequency f . The amplifier noise spectral density

i

O

is n . From Figure 36, using f as the x-axis selector, we

i

can find on the y-axis the noise equivalent bandwidth freq

i

of the input driving amplifier. This bandwidth includes

the band limiting effects of the ADC internal calibration

and filtering. The noise of the driving amplifier referred

to the converter input and including all these effects can

be calculated as N = n • √freq . The total system noise

0.1

1

10 100 1k

10k 100k 1M

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

2410 F36

i

(referred to the LTC2410 input) can now be obtained by

summing as square root of sum of squares the three ADC

input referred noise sources: the LTC2410 internal noise

Figure 36. Input Referred Noise Equivalent Bandwidth

of an Input Connected White Noise Source

+

(800nV), the noise of the IN driving amplifier and the

0

F

O

= HIGH

–

–10

–20

noise of the IN driving amplifier.

–30

If the F pin is driven by an external oscillator of frequency

O

–40

f

, Figure 36 can still be used for noise calculation if

EOSC

–50

the x-axis is scaled by f

the ratio f

/153600. For large values of

EOSC

–60

/153600, the Figure 36 plot accuracy begins

–70

EOSC

–80

to decrease, but in the same time the LTC2410 noise floor

rises and the noise contribution of the driving amplifiers

lose significance.

–90

–100

–110

–120

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f

S S S S S S S S S S S S

Normal Mode Rejection and Anti-aliasing

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2410 F37

One of the advantages delta-sigma ADCs offer over

conventional ADCs is on-chip digital filtering. Combined

with a large oversampling ratio, the LTC2410 significantly

simplifies anti-aliasing filter requirements.

Figure 37. Input Normal Mode Rejection,

Internal Oscillator and 50Hz Notch

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

F

= LOW OR

O

4

TheSinc digitalfilterprovidesgreaterthan120dBnormal

= EXTERNAL OSCILLATOR,

f

= 10 • f

EOSC

S

mode rejection at all frequencies except DC and integer

multiples of the modulator sampling frequency (f ). The

S

LTC2410’s auto-calibration circuits further simplify the

anti-aliasing requirements by additional normal mode

signal filtering both in the analog and digital domain.

Independent of the operating mode, f = 256 • f = 2048

S

N

• f

where f in the notch frequency and f

is

OUTMAX

N

OUTMAX

the maximum output data rate. In the internal oscillator

mode with a 50Hz notch setting, f = 12800Hz and with a

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f

S S S S S S S S S S

S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

60Hz notch setting f = 15360Hz. In the external oscillator

S

2410 F38

mode, f = f

/10.

S

EOSC

Figure 38. Input Normal Mode Rejection, Internal

Oscillator and 60Hz Notch or External Oscillator

2410fa

32

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

The combined normal mode rejection performance is

the normal mode rejection of the LTC2410 operating with

an internal oscillator and a 60Hz notch setting are shown

in Figure 41 superimposed over the theoretical calculated

curve. Similarly, typical measured values of the normal

mode rejection of the LTC2410 operating with an internal

oscillator and a 50Hz notch setting are shown in Figure

42 superimposed over the theoretical calculated curve.

shown in Figure 37 for the internal oscillator with 50Hz

notch setting (F = HIGH) and in Figure 38 for the internal

O

oscillator with 60Hz notch setting (F = LOW) and for

O

the external oscillator mode. The regions of low rejection

occurring at integer multiples of f have a very narrow

S

bandwidth.Magnifieddetailsofthenormalmoderejection

curves are shown in Figure 39 (rejection near DC) and

As a result of these remarkable normal mode specifica-

tions,minimal(ifany)anti-aliasfilteringisrequiredinfront

of the LTC2410. If passive RC components are placed in

front of the LTC2410, the input dynamic current should

be considered (see Input Current section). In cases where

large effective RC time constants are used, an external

buffer amplifier may be required to minimize the effects

of dynamic input current.

Figure 40 (rejection at f = 256f ) where f represents

S

N

the notch frequency. These curves have been derived for

the external oscillator mode but they can be used in all

operating modes by appropriately selecting the f value.

N

The user can expect to achieve in practice this level of

performance using the internal oscillator as it is demon-

strated by Figures 41 and 42. Typical measured values of

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

f

N

2f

N

3f

4f

N

5f

N

6f

N

7f

N

8f

N

250f 252f 254f 256f 258f 260f 262f

N N N N N N N

N

INPUT SIGNAL FREQUENCY (Hz)

2410 F39

2410 F40

Figure 39. Input Normal Mode Rejection

Figure 40. Input Normal Mode Rejection

0

–20

0

–20

MEASURED DATA

CALCULATED DATA

V

= 5V

MEASURED DATA

CALCULATED DATA

V

= 5V

CC

+

REF = 5V

REF = GND

REF = 5V

REF = GND

–

V

= 2.5V

V

= 2.5V

INCM

–40

= 5V

IN(P-P)

F

O

= GND

F = 5V

O

T

= 25°C

T = 25°C

A

–60

–80

–100

–120

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2410 F41

2410 F42

Figure 41. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full Scale (60Hz Notch)

Figure 42. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full Scale (50Hz Notch)

2410fa

33

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

Traditional high order delta-sigma modulators, while pro-

vidingverygoodlinearityandresolution,sufferfrompoten-

tial instabilities at large input signal levels. The proprietary

architecture used for the LTC2410 third order modulator

resolves this problem and guarantees a predictable stable

behavior at input signal levels of up to 150% of full scale.

Inmanyindustrialapplications,itisnotuncommontohave

to measure microvolt level signals superimposed over

volt level perturbations and LTC2410 is eminently suited

for such tasks. When the perturbation is differential, the

specification of interest is the normal mode rejection for

imposed over the more traditional normal mode rejection

ratio results obtained with a 5V peak-to-peak (full scale)

input signal. In Figure 43, the LTC2410 uses the internal

oscillator with the notch set at 60Hz (F = LOW) and in

O

Figure 44 it uses the internal oscillator with the notch set

at 50Hz (F = HIGH). It is clear that the LTC2410 rejection

O

performance is maintained with no compromises in this

extreme situation. When operating with large input signal

levels, the user must observe that such signals do not

violate the device absolute maximum ratings.

largeinputsignallevels.WithareferencevoltageV = 5V,

REF

SYNCHRONIZATION OF MULTIPLE LTC2410S

the LTC2410 has a full-scale differential input range of

5V peak-to-peak. Figures 43 and 44 show measurement

resultsfortheLTC2410normalmoderejectionratiowitha

7.5V peak-to-peak (150% of full scale) input signal super-

Since the LTC2410’s absolute accuracy (total unadjusted

error)is5ppm,applicationsutilizingmultiplesynchronized

ADCs are possible.

0

–20

V

= 5V

= 7.5V

V

= 5V

CC

IN(P-P)

+

REF = 5V

REF = GND

IN(P-P)

–

(150% OF FULL SCALE)

V

= 2.5V

= GND

INCM

–40

F

O

T

= 25°C

A

–60

–80

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

2410 F43

Figure 43. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)

0

V

= 5V

= 7.5V

V

= 5V

CC

IN(P-P)

+

REF = 5V

REF = GND

V

IN(P-P)

–20

–40

–

(150% OF FULL SCALE)

= 2.5V

INCM

F

O

= 5V

T

= 25°C

A

–60

–80

–100

–120

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2410 F44

Figure 44. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)

2410fa

34

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

Simultaneous Sampling with Two LTC2410s

fourLTC2410sareinterleavedunderthecontrolofseparate

CS signals. This increases the effective output rate from

7.5Hz to 30Hz (up to a maximum of 60Hz). Additionally,

the one-shot output spectrum is unfolded allowing further

digitalsignalprocessingoftheconversionresults.SCKand

SDO may be common to all four LTC2410s. The four CS

rising edges equally divide one LTC2410 conversion cycle

(7.5Hz for 60Hz notch frequency). In order to synchronize

the start of conversion to CS, 31 or less SCK clock pulses

must be applied to each ADC.

OnesuchapplicationissynchronizingmultipleLTC2410s,

see Figure 45. The start of conversion is synchronized

to the rising edge of CS. In order to synchronize mul-

tiple LTC2410s, CS is a common input to all the ADCs.

To prevent the converters from autostarting a new conver-

sion at the end of data output read, 31 or fewer SCK clock

signals are applied to the LTC2410 instead of 32 (the 32nd

falling edge would start a conversion). The exact timing

and frequency for the SCK signal is not critical since it is

only shifting out the data. In this case, two LTC2410’s

simultaneouslystartandendtheirconversioncyclesunder

the external control of CS.

Both the synchronous and 4× output rate applications use

the external serial clock and single cycle operation with

reduced data output length (see Serial Interface Timing

Modes section and Figure 6). An external oscillator clock

is applied commonly to the FO pin of each LTC2410 in

order to synchronize the sampling times. Both circuits

may be extended to include more LTC2410s.

Increasing the Output Rate Using Mulitple LTC2410s

A second application uses multiple LTC2410s to increase

the effective output rate by 4×, see Figure 46. In this case,

SCK2

SCK1

EXTERNAL OSCILLATOR

(153,600HZ)

LTC2410

#1

LTC2410

#2

V

F

O

V

F

O

CC

+

–

+

–

REF

SCK

SDO

CS

REF

SCK

SDO

CS

CONTROLLER

+

IN

–

IN

GND

CS

SDO1

SDO2

V +

REF

V –

REF

CS

SCK1

SCK2

SDO1

SDO2

31 OR LESS CLOCK CYCLES

2410 F45

Figure 45. Synchronous Conversion—Extendable

2410fa

35

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

V

+

–

REF

EXTERNAL OSCILLATOR

(153,600HZ)

LTC2410

#1

LTC2410

#2

LTC2410

#3

LTC2410

#4

V

F

O

V

F

O

V

F

V

F

O

CC

O

CC

+

–

+

–

+

–

+

–

REF

SCK

SDO

CS

REF

SCK

SDO

CS

REF

SCK

SDO

CS

REF

SCK

SDO

CS

+

IN

–

IN

GND

CONTROLLER

SCK

SDO

CS1

CS2

CS3

CS4

CS1

CS2

CS3

CS4

31 OR LESS

CLOCK PULSES

SCK

SDO

2410 F46

Figure 46. Using Multiple LTC2410s to Increase Output Data Rate

BRIDGE APPLICATIONS

issue. For those systems that require accurate measure-

ment of a small incremental change on a significant tare

weight, the lack of history effects in the LTC2400 family

is of great benefit.

Typical strain gauge based bridges deliver only 2mV/Volt

of excitation. As the maximum reference voltage of the

LTC2410is5V,remotesensingofappliedexcitationwithout

additional circuitry requires that excitation be limited to

5V. This gives only 10mV full scale input signal, which

can be resolved to 1 part in 10000 without averaging.

For many solid state sensors, this is still better than the

sensor. Averaging 64 samples however reduces the noise

level by a factor of eight, bringing the resolving power to

1 part in 80000, comparable to better weighing systems.

Hysteresis and creep effects in the load cells are typically

much greater than this. Most applications that require

strain measurements to this level of accuracy are measur-

ing slowly changing phenomena, hence the time required

to average a large number of readings is usually not an

For those applications that cannot be fulfilled by the

LTC2410alone,compensatingforerrorinexternalamplifi-

cationcanbedoneeffectivelyduetothe“nolatency”feature

oftheLTC2410.Nolatencyoperationallowssamplesofthe

amplifier offset and gain to be interleaved with weighing

measurements. The use of correlated double sampling

allows suppression of 1/f noise, offset and thermocouple

effects within the bridge. Correlated double sampling in-

volvesalternatingthepolarityofexcitationanddealingwith

thereversalofinputpolaritymathematically.Alternatively,

bridge excitation can be increased to as much as 10V,

2410fa

36

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

if one of several precision attenuation techniques is used

to produce a precision divide operation on the reference

signal. Another option is the use of a reference within the

5V input range of the LTC2410 and developing excitation

via fixed gain, or LTC1043 based voltage multiplication,

along with remote feedback in the excitation amplifiers,

as shown in Figures 52 and 53.

devices,RFIsuppressionandwiring.TheLTC2410exhibits

extremely low temperature dependent drift. As a result,

exposure to external ambient temperature ranges does

not compromise performance. The incorporation of any

amplificationconsiderablycomplicatesthermalstability,as

inputoffsetvoltagesandcurrents,temperaturecoefficient

of gain settling resistors all become factors.

Figure47showsanexampleofasimplebridgeconnection.

Note that it is suitable for any bridge application where

measurement speed is not of the utmost importance.

For many applications where large vessels are weighed,

the average weight over an extended period of time is of

concern and short term weight is not readily determined

due to movement of contents, or mechanical resonance.

Often, large weighing applications involve load cells

located at each load bearing point, the output of which

can be summed passively prior to the signal processing

circuitry, actively with amplification prior to the ADC, or

can be digitized via multiple ADC channels and summed

mathematically. The mathematical summation of the out-

put of multiple LTC2410’s provides the benefit of a root

square reduction in noise. The low power consumption

of the LTC2410 makes it attractive for multidrop com-

munication schemes where the ADC is located within the

load-cell housing.

The circuit in Figure 48 shows an example of a simple

amplification scheme. This example produces a differ-

ential output with a common mode voltage of 2.5V, as

determined by the bridge. The use of a true three amplifier

instrumentationamplifierisnotnecessary,astheLTC2410

has common mode rejection far beyond that of most am-

plifiers. The LTC1051 is a dual autozero amplifier that can

be used to produce a gain of 15 before its input referred

noise dominates the LTC2410 noise. This example shows

againof34, thatisdeterminedbyafeedbacknetworkbuilt

usingaresistorarraycontaining8individualresistors.The

resistorsareorganizedtooptimizetemperaturetrackingin

the presence of thermal gradients. The second LTC1051

buffers the low noise input stage from the transient load

steps produced during conversion.

The gain stability and accuracy of this approach is very

good,duetoastatisticalimprovementinresistormatching.

A gain of 34 may seem low, when compared to common

practiceinearliergenerationsofload-cellinterfaces, how-

ever the accuracy of the LTC2410 changes the rationale.

Achieving high gain accuracy and linearity at higher gains

may prove difficult, while providing little benefit in terms

of noise reduction.

A direct connection to a load cell is perhaps best incorpo-

rated into the load-cell body, as minimizing the distance

to the sensor largely eliminates the need for protection

LT1019

+

R1

At a gain of 100, the gain error that could result from

typical open-loop gain of 160dB is –1ppm, however,

worst-case is at the minimum gain of 116dB, giving a

gain error of –158ppm. Worst-case gain error at a gain

of 34, is –54ppm. The use of the LTC1051A reduces the

worst-case gain error to –33ppm. The advantage of gain

higher than 34, then becomes dubious, as the input re-

ferred noise sees little improvement1 and gain accuracy

is potentially compromised.

2

V

REF

3

4

12

13

+

REF

SDO

SCK

350Ω

BRIDGE

–

5

11

+

IN

CS

LTC2410

6

14

–

IN

F

O

GND

R2

1, 7, 8, 9,

10, 15, 16

Note that this 4-amplifier topology has advantages over

thetypicalintegrated3-amplifierinstrumentationamplifier

in that it does not have the high noise level common in

2410 F47

R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS

the output stage that usually dominates when an instru-

Figure 47. Simple Bridge Connection

2410fa

37

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

mentation amplifier is used at low gain. If this amplifier

is used at a gain of 10, the gain error is only 10ppm and

Remote Half Bridge Interface

As opposed to full bridge applications, typical half bridge

applications must contend with nonlinearity in the bridge

output,assignalswingisoftenmuchgreater.Applications

include RTD’s, thermistors and other resistive elements

thatundergosignificantchangesovertheirspan.Forsingle

variableelementbridges,thenonlinearityofthehalfbridge

output can be eliminated completely; if the reference arm

of the bridge is usedas the referenceto theADC, as shown

in Figure 50. The LTC2410 can accept inputs up to 1/2

input referred noise is reduced to 0.1µV . The buffer

RMS

stages can also be configured to provide gain of up to 50

with high gain stability and linearity.

Figure 49 shows an example of a single amplifier used to

produce single-ended gain. This topology is best used in

applications where the gain setting resistor can be made

to match the temperature coefficient of the strain gauges.

If the bridge is composed of precision resistors, with only

one or two variable elements, the reference arm of the

bridgecanbemadetoactinconjunctionwiththefeedback

resistor to determine the gain. If the feedback resistor is

incorporatedintothedesignoftheloadcell,usingresistors

which match the temperature coefficient of the load-cell

elements, good results can be achieved without the need

for resistors with a high degree of absolute accuracy. The

common mode voltage in this case, is again a function of

the bridge output. Differential gain as used with a 350Ω

V

. Hence, the reference resistor R1 must be at least

REF

2x the highest value of the variable resistor.

In the case of 100Ω platinum RTD’s, this would suggest

a value of 800Ω for R1. Such a low value for R1 is not

advisable due to self-heating effects. A value of 25.5k is

shown for R1, reducing self-heating effects to acceptable

levels for most sensors.

The basic circuit shown in Figure 50 shows connections

for a full 4-wire connection to the sensor, which may be

located remotely. The differential input connections will

reject induced or coupled 60Hz interference, however,

1

bridge is A = (R1+ R2)/(R1+175Ω). Common mode gain

V

ishalfthedifferentialgain.Themaximumdifferentialsignal

that can be used is 1/4 V , as opposed to 1/2 V

in

REF

Input referred noise for A = 34 is approximately 0.05µV

, whereas at a gain of 50, it would

RMS

the 2-amplifier topology above.

V

be 0.048µV

.

RMS

5V

REF

0.1µF

1

5V

8

3

2

+

–

0.1µF

U1A

4

5V

2

8

2

3

350Ω

BRIDGE

–

+

V

CC

1

3

4

12

+

–

U2A

REF

SDO

15

14

4

5

12

13

SCK

1

4

RN1

16

5

11

+

6

11

7

10

8

9

IN

CS

2

3

13

LTC2410

6

5

6

5

–

+

–

+

7

6

14

–

IN

U2B

U1B

F

O

GND

1, 7, 8, 9,

10, 15, 16

2410 F48

RN1 = 5k × 8 RESISTOR ARRAY

U1A, U1B, U2A, U2B = 1/2 LTC1051

Figure 48. Using Autozero Amplifiers to Reduce Input Referred Noise

2410fa

38

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

the reference inputs do not have the same rejection. If

60Hz or other noise is present on the reference input, a

low pass filter is recommended as shown in Figure 51.

Note that you cannot place a large capacitor directly at

the junction of R1 and R2, as it will store charge from

the sampling process. A better approach is to produce a

low pass filter decoupled from the input lines with a high

value resistor (R3).

The circuit shown in Figure 51 shows a more rigorous

example of Figure 50, with increased noise suppression

and more protection for remote applications.

Figure 52 shows an example of gain in the excitation cir-

cuit and remote feedback from the bridge. The LTC1043’s

provide voltage multiplication, providing 10V from a 5V

reference with only 1ppm error. The amplifiers are used

at unity gain and introduce very little error due to gain

error or due to offset voltages. A 1µV/°C offset voltage

drift translates into 0.05ppm/°C gain error. Simpler alter-

natives, with the amplifiers providing gain using resistor

arrays for feedback, can produce results that are similar

to bridge sensing schemes via attenuators. Note that the

amplifiers must have high open-loop gain or gain error

will be a source of error. The fact that input offset voltage

has relatively little effect on overall error may lead one to

use low performance amplifiers for this application. Note

that the gain of a device such as an LF156, (25V/mV over

temperature) will produce a worst-case error of –180ppm

at a noise gain of 3, such as would be encountered in an

inverting gain of 2, to produce –10V from a 5V reference.

The use of a third resistor in the half bridge, between the

variable and fixed elements gives essentially the same

result as the two resistor version, but has a few benefits.

If, for example, a 25k reference resistor is used to set the

excitationcurrentwitha100ΩRTD,thenegativereference

input is sampling the same external node as the positive

input and may result in errors if used with a long cable.

For short cable applications, the errors may be acceptalby

low. If instead the single 25k resistor is replaced with a

10k 5% and a 10k 0.1% reference resistor, the noise level

introduced at the reference, at least at higher frequencies,

willbereduced. Afiltercanbeintroducedintothenetwork,

in the form of one or more capacitors, or ferrite beads,

as long as the sampling pulses are not translated into an

error. The reference voltage is also reduced, but this is

not undesirable, as it will decrease the value of the LSB,

although, not the input referred noise level.

5V

+

10µF

0.1µF

5V

350Ω

2

BRIDGE

0.1µV

V

7

CC

3

4

+

–

+

REF

175Ω

1µF

6

LTC1050S8

+

2

–

20k

5

+

4

IN

1µF

R1

4.99k

R2

46.4k

LTC2410

6

–

IN

GND

1, 7, 8, 9,

10, 15, 16

R1 + R2

2410 F49

A

= 9.95 =

V

(

)

R1 + 175Ω

Figure 49. Bridge Amplification Using a Single Amplifier

2410fa

39

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

The error associated with the 10V excitation would be

–80ppm. Hence, overall reference error could be as high

as 130ppm, the average of the two.

Figure 54 shows the use of an LTC2410 with a differential

multiplexer. This is an inexpensive multiplexer that will

contribute some error due to leakage if used directly with

the output from the bridge, or if resistors are inserted as

a protection mechanism from overvoltage. Although the

bridge output may be within the input range of the A/D and

multiplexer in normal operation, some thought should be

given to fault conditions that could result in full excitation

voltage at the inputs to the multiplexer or ADC. The use of

amplification prior to the multiplexer will largely eliminate

errors associated with channel leakage developing error

voltages in the source impedance.

Figure 53 shows a similar scheme to provide excitation

using resistor arrays to produce precise gain. The circuit

is configured to provide 10V and –5V excitation to the

bridge, producing a common mode voltage at the input to

the LTC2410 of 2.5V, maximizing the AC input range for

applications where induced 60Hz could reach amplitudes

up to 2V

.

RMS

The last two example circuits could be used where mul-

tiple bridge circuits are involved and bridge output can

be multiplexed onto a single LTC2410, via an inexpensive

multiplexer such as the 74HC4052.

V

S

2.7V TO 5.5V

2

V

CC

3

4

+

–

R1

25.5k

0.1%

REF

LTC2410

5

6

+

IN

PLATINUM

100Ω

–

RTD

GND

1, 7, 8, 9,

10, 15, 16

2410 F50

Figure 50. Remote Half Bridge Interface

5V

2

R2

V

10k

CC

3

4

+

–

0.1%

REF

+

R3

10k

5%

560Ω

1µF

R1

LTC1050

10k, 5%

–

LTC2410

10k

5

6

+

IN

PLATINUM

100Ω

–

RTD

GND

1, 7, 8, 9,

10, 15, 16

2410 F51

Figure 51. Remote Half Bridge Sensing with Noise Suppression on Reference

2410fa

40

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

15V

U1

15V

7

LTC1043

4

200Ω

10V

5V

3

2

8

7

+

10V

LT1236-5

20Ω

6

+

Q1

2N3904

LTC1150

1µF

11

12

47µF

0.1µF

*

–

4

–15V

33Ω

10V

14

13

10µF

0.1µF

1k

17

350Ω

BRIDGE

5V

0.1µF

2

V

CC

LTC2410

+

3

REF

–10V

4

–

REF

33Ω

5

6

+

IN

–

IN

U2

15V

7

GND

LTC1043

1, 7, 8, 9,

10, 15, 16

Q2

3

2

5

15

8

6

+

2N3906

20Ω

6

LTC1150

2

3

*

–

4

–15V

18

0.1µF

1k

*FLYING CAPACITORS ARE

1µF FILM (MKP OR EQUIVALENT)

5V

U2

LTC1043

4

SEE LTC1043 DATA SHEET FOR

DETAILS ON UNUSED HALF OF U1

7

11

12

1µF

FILM

*

200Ω

14

13

–10V

17

–10V

2410 F52

Figure 52. LTC1043 Provides Precise 4× Reference for Excitation Voltages

2410fa

41

For more information www.linear.com/LTC2410

LTC2410

APPLICATIONS INFORMATION

15V

5V

3

2

+

LT1236-5

20Ω

Q1

2N3904

1/2

LT1112

1

+

C3

47µF

C1

0.1µF

–

C1

0.1µF

22Ω

RN1

10k

10V

5V

1

2

3

2

RN1

10k

V

CC

4

350Ω BRIDGE

TWO ELEMENTS

VARYING

LTC2410

+

3

REF

4

–

REF

5

6

+

IN

–5V

–

IN

8

RN1

10k

GND

1, 7, 8, 9,

10, 15, 16

RN1

10k

7

5

6

15V

C2

0.1µF

33Ω

×2

RN1 IS CADDOCK T914 10K-010-02

8

6

–

Q2, Q3

2N3906

×2

20Ω

1/2

LT1112

7

5

+

4

–15V

2410 F53

–15V

Figure 53. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier

5V

+

16

2

47µF

12

14

15

11

V

CC

3

4

+

–

REF

LTC2410

74HC4052

1

5

6

13

3

+

IN

–

2

4

TO OTHER

DEVICES

GND

1, 7, 8, 9,

10, 15, 16

6

8

9

10

A0

A1

2410 F54

Figure 54. Use a Differential Multiplexer to Expand Channel Capability

2410fa

42

For more information www.linear.com/LTC2410

LTC2410

TYPICAL APPLICATIONS

Sample Driver for LTC2410 SPI Interface

The performance of the LTC2410 can be verified using

the demonstration board DC291A, see Figure 57 for the

schematic. This circuit uses the computer’s serial port to

generate power and the SPI digital signals necessary for

starting a conversion and reading the result. It includes

a Labview application software program (see Figure 58)

which graphically captures the conversion results. It can

be used to determine noise performance, stability and

with an external source, linearity. As exemplified in the

schematic, the LTC2410 is extremely easy to use. This

demonstration board and associated software is available

by contacting Linear Technology.

The LTC2410 has a very simple serial interface that makes

interfacing to microprocessors and microcontrollers very

easy.

The listing in Figure 56 is a simple assembler routine for

the 68HC11 microcontroller. It uses PORT D, configur-

ing it for SPI data transfer between the controller and

the LTC2410. Figure 55 shows the simple 3-wire SPI

connection.

The code begins by declaring variables and allocating four

memory locations to store the 32-bit conversion result.

ThisisfollowedbyinitializingPORTD’sSPIconfiguration.

The program then enters the main sequence. It activates

the LTC2410’s serial interface by setting the SS output

low, sending a logic low to CS. It next waits in a loop for

a logic low on the data line, signifying end-of-conversion.

Aftertheloopissatisfied,fourSPItransfersarecompleted,

retrievingtheconversion. Themainsequenceendsbyset-

ting SS high. This places the LTC2410’s serial interface in

a high impedance state and initiates another conversion.

68HC11

SCK (PD4)

MISO (PD2)

SS (PD5)

13

12

11

SCK

LTC2410 SDO

CS

2410 F55

Figure 55. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface

2410fa

43

For more information www.linear.com/LTC2410

LTC2410

TYPICAL APPLICATIONS

*****************************************************

* This example program transfers the LTC2410’s 32-bit output

*

* conversion result into four consecutive 8-bit memory locations. *

*****************************************************

*68HC11 register definition

PORTD EQU

*

$1008

Port D data register

“ – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD”

Port D data direction register

SPI control register

“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”

SPI status register

DDRD

SPSR

*

EQU

$1009

$1028

SPSR

*

EQU

$1029

$102A

“SPIF,WCOL, – ,MODF; – , – , – , – “

SPI data register; Read-Buffer; Write-Shifter

SPDR

*

* RAM variables to hold the LTC2410’s 32 conversion result

*

DIN1

DIN2

DIN3

DIN4

*

EQU

$00

$01

$02

$03

This memory location holds the LTC2410’s bits 31 - 24

This memory location holds the LTC2410’s bits 23 - 16

This memory location holds the LTC2410’s bits 15 - 08

This memory location holds the LTC2410’s bits 07 - 00

**********************

* Start GETDATA Routine *

**********************

*

ORG

LDS

$C000

Program start location

INIT1

*

#$CFFF Top of C page RAM, beginning location of stack

#$2F

LDAA

–,–,1,0;1,1,1,1

–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X

STAA

LDAA

STAA

PORTD Keeps SS* a logic high when DDRD, bit 5 is set

#$38

–,–,1,1;1,0,0,0

SS*, SCK, MOSI are configured as Outputs

MISO, TxD, RxD are configured as Inputs

DDRD

*

*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output

LDAA

STAA

#$50

SPCR

The SPI is configured as Master, CPHA = 0, CPOL = 0

and the clock rate is E/2

(This assumes an E-Clock frequency of 4MHz. For higher E-

Clock frequencies, change the above value of $50 to a value

that ensures the SCK frequency is 2MHz or less.)

*

GETDATA PSHX

PSHY

PSHA

LDX

#$0

The X register is used as a pointer to the memory locations

that hold the conversion data

*

LDY

#$1000

BCLR

PORTD, Y %00100000

This sets the SS* output bit to a logic

low, selecting the LTC2410

*

2410fa

44

For more information www.linear.com/LTC2410

LTC2410

TYPICAL APPLICATIONS

**********************************

* The next short loop waits for the

* LTC2410’s conversion to finish before

* starting the SPI data transfer

*

**********************************

*

CONVEND LDAA

PORTD

#%00000100

Retrieve the contents of port D

Look at bit 2

ANDA

*

Bit 2 = Hi; the LTC2410’s conversion is not

complete

*

Bit 2 = Lo; the LTC2410’s conversion is complete

Branch to the loop’s beginning while bit 2 remains

high

BNE

CONVEND

*

********************

* The SPI data transfer *

********************

*

TRFLP1 LDAA

STAA

*

#$0

SPDR

Load accumulator A with a null byte for SPI transfer

This writes the byte in the SPI data register and starts

the transfer

WAIT1

LDAA

SPSR

This loop waits for the SPI to complete a serial

transfer/exchange by reading the SPI Status Register

The SPIF (SPI transfer complete flag) bit is the SPSR’s MSB

and is set to one at the end of an SPI transfer. The branch

will occur while SPIF is a zero.

BPL

WAIT1

*

LDAA

SPDR

0,X

Load accumulator A with the current byte of LTC2410 data

that was just received

Transfer the LTC2410’s data to memory

Increment the pointer

STAA

INX

CPX

BNE

#DIN4+1 Has the last byte been transferred/exchanged?

TRFLP1 If the last byte has not been reached, then proceed to the

next byte for transfer/exchange

PORTD,Y %00100000 This sets the SS* output bit to a logic high,

de-selecting the LTC2410

*

BSET

PULA

PULY

PULX

RTS

Restore the A register

Restore the Y register

Restore the X register

Figure 56. This is an Example of 68HC11 Code That Captures the LTC2410’s

Conversion Results Over the SPI Serial Interface Shown in Figure 55

2410fa

45

For more information www.linear.com/LTC2410

LTC2410

TYPICAL APPLICATIONS

D1

BAV74LT1

2

U1

U2

V

JP1

V

JP2

1

J1

EXT

CC

LT1460ACN8-2.5

LT1236ACN8-5

R1

10Ω

JUMPER

V

1

3

1

2

6

2

6

2

3

1

V

IN

OUT

IN

OUT

J2

GND

2

+

C1

10µF

35V

C2

22µF

25V

C3

10µF

35V

C4

100µF

16V

4

P1

DB9

R2

3

1

6

2

7

3

8

4

9

5

JP3

JUMPER

U3E

U3F

74HC14

1

3

R3

51k

10

11

12

13

2

JP4

V

CC

JUMPER

1

3

1

J3

CC

V

+

C5

2

BANANA JACK

C6

10µF

35V

1

U3B

74HC14

U3A

74HC14

J4

0.1µF

J5

GND

V

EXT

R4

51k

2

11

CS

4

5

3

6

2

9

1

8

BANANA JACK

V

CC

1

3

14

13

12

16

15

10

J6

+

–

+

REF

F

O

REF

4

5

6

REF

SCK

SDO

GND

U3C

74HC14

U3D

74HC14

BANANA JACK

R5

R6

3k

V

+

IN

1

J7

49.9

U4

LTC2410CGN

–

REF

1

BANANA JACK

R7

22k

1

J8

IN

3

2

GND GND GND GND

V

+

Q1

MMBT3904LT1

1

7

8

9

BANANA JACK

R8

51k

1

2

1

J9

IN

JP5

JUMPER

V

–

V

CC

BANANA JACK

NOTES:

1

J10

GND

BYPASS CAP

FOR U3

C7

0.1µF

INSTALL JUMBER JP1 AT PIN 1 AND PIN 2

INSTALL JUMBER JP2 AT PIN 1 AND PIN 2

INSTALL JUMBER JP3 AT PIN 1 AND PIN 2

2410 F57

Figure 57. 24-Bit A/D Demo Board Schematic

Figure 58. Display Graphic

2410fa

46

For more information www.linear.com/LTC2410

LTC2410

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.189 – .196*

.045 .005

(4.801 – 4.978)

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 .004

(0.38 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 REV B 0212

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2410fa

47

For more information www.linear.com/LTC2410

LTC2410

PCB LAYOUT AND FILM

Silkscreen Top

Top Layer

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48

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LTC2410

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

5, 9, 30, 31

6, 7

A

08/15 Updated f

maximum to 500kHz and all associated information.

EOSC

Removed 52.5Hz noise histograms.

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

49

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LTC2410

PCB LAYOUT AND FILM

Bottom Layer

RELATED PARTS

PART NUMBER

LT1019

DESCRIPTION

COMMENTS

Precision Bandgap Reference, 2.5V, 5V

3ppm/°C Drift, 0.05% Max

LT1025

Micropower Thermocouple Cold Junction Compensator

80µA Supply Current, 0.5°C Initial Accuracy

Precise Charge, Balanced Switching, Low Power

LTC1043

Dual Precision Instrumentation Switched Capacitor

Building Block

LTC1050

Precision Chopper Stabilized Op Amp

Precision Bandgap Reference, 5V

No External Components 5µV Offset, 1.6µV Noise

P-P

LT1236A-5

LT1460

0.05% Max, 5ppm/°C Drift

Micropower Series Reference

0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2400

24-Bit, No Latency ∆Σ ADC in SO-8

1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC in MSOP

24-Bit, No Latency ∆Σ ADC

LTC2401/LTC2402

LTC2404/LTC2408

LTC2411

1.45µV

Noise, 4ppm INL

RMS

LTC2413

Simultaneous 50Hz/60Hz Rejection, 800nV

Noise

RMS

LTC2420

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

20-Bit, No Latency ∆Σ ADC in SO-8

4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs

LTC2424/LTC2428

1.2ppm Noise, 8ppm INL Pin Compatible with LTC2404/LTC2408

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LT 0815 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

50

For more information www.linear.com/LTC2410

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2410

●

 LINEAR TECHNOLOGY CORPORATION 2000


型号：	LTC2410IGN#TRPBF
厂家：	Linear
描述：	LTC2410 - 24-Bit No Latency Delta Sigma ADC with Differential Input and Differential Reference; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管转换器
文件：	总50页 (文件大小：775K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2410IGN#TRPBF [Linear]

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