LTC2418_技术文档

LTC2412

2-Channel Differential Input

24-Bit No Latency ∆Σ ADC

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DESCRIPTIO

FEATURES

TheLTC^®2412isa2-channeldifferentialinputmicropower

24-bit No Latency ∆Σ^TManalog-to-digital converter with

anintegratedoscillator.Itprovides2ppmINLand0.16ppm

RMS noise over the entire supply range. The two differen-

tial channels are converted alternately with channel ID

included in the conversion results. It uses delta-sigma

technology and provides single conversion settling of the

digital filter. Through a single pin, the LTC2412 can be

configured for better than 110dB input differential mode

rejection at 50Hz or 60Hz ±2%, or it can be driven by an

external oscillator for a user defined rejection frequency.

The internal oscillator requires no external frequency

setting components.

■

2-Channel Differential Input with Automatic

Channel Selection (Ping-Pong)

■

Low Supply Current: 200µA, 4µA in Autosleep

■

Differential Input and Differential Reference with

GND to V_CCCommon Mode Range

2ppm INL, No Missing Codes

■

2.5ppm Full-Scale Error and 0.1ppm Offset

■

0.16ppm Noise, 22.5 Effective Number of Bits

■

No Latency: Digital Filter Settles in a Single Cycle and

Each Channel Conversion is Accurate

■

Internal Oscillator—No External Components

Required

■

110dB Min, 50Hz or 60Hz Notch Filter

■

Narrow SSOP-16 Package

The converter accepts any external differential reference

voltage from 0.1V to V_CCfor flexible ratiometric and

remote sensing measurement configurations. The full-

■

Single Supply 2.7V to 5.5V Operation

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APPLICATIO S

scale differential input range is from –0.5V_REFto 0.5V_REF

.

The reference common mode voltage, V_REFCM, and the

input common mode voltage, V_INCM, may be indepen-

dently set anywhere within the GND to V_CC. The DC

common mode input rejection is better than 140dB.

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

Gas Analyzers

Strain-Gage Transducers

Instrumentation

Data Acquisition

Industrial Process Control

6-Digit DVMs

■

The LTC2412 communicates through a flexible 3-wire

digital interface which is compatible with SPI and

MICROWIRE^TMprotocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

■

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TYPICAL APPLICATIO

Total Unadjusted Error vs Input

1.5

2.7V TO 5.5V

V

CC

1µF

1.0

= INTERNAL OSC/50Hz REJECTION

1

2

4

14

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

+

0.5

0

REF

CH0

LTC2412

5

3

13

12

11

–

T

= 90°C

= 25°C

CH0

SCK

SDO

CS

A

V

= 5V

CC

–0.5

–1.0

–1.5

+

THERMOCOUPLE

REF = 5V

3-WIRE

SPI INTERFACE

–

REF

REF = GND

T

= –45°C

A

6

7

V

= 5V

INCM

= GND

+

REF

CH1

= 2.5V

–

F

O

8, 9, 10, 15, 16

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

GND

2412 TA01

(V)

2412 TA02

IN

2412f

1

LTC2412

W W

U W

U

W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Notes 1, 2)

TOP VIEW

ORDER PART NUMBER

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Voltage

to GND.................................... –0.3V to (V_CC+ 0.3V)

Reference Input Voltage

to GND.................................... –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

Operating Temperature Range

LTC2412C ............................................... 0°C to 70°C

LTC2412I............................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

V

CC

+

LTC2412CGN

LTC2412IGN

REF

CH0

CH1

–

+

–

+

–

F

O

SCK

SDO

CS

GN PART MARKING

GND

2412

2412I

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes)

Integral Nonlinearity

0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)

●

24

Bits

REF

CC

REF

IN

–

REF

+

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

= 2.5V, (Note 6)

1

2

5

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

14

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

INCM

+

–

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

0.5

2.5

µV

CC

+

–

GND ≤ IN = IN ≤ V , (Note 14)

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

10

nV/°C

ppm of V

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

Negative Full-Scale Error Drift

Total Unadjusted Error

2.5V ≤ REF ≤ V , REF = GND,

●

2.5

12

CC

REF

+

–

+

IN = 0.75REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

2.5

ppm of V /°C

REF

CC

+

–

+

IN = 0.75REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V

REF

CC

+

–

+

IN = 0.25 • REF , IN = 0.75 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

ppm of V /°C

REF

CC

+

–

IN = 0.25 • REF , IN = 0.75 • REF

+

–

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

REF = 2.5V, REF = GND, V

= 1.25V

= 2.5V

3

4

ppm of V

CC

INCM

REF

+

–

CC

INCM

+

–

= 1.25V, (Note 6)

INCM

+

–

Output Noise

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND,

0.8

µV

RMS

CC

–

+

GND ≤ IN = IN ≤ V , (Note 13)

CC

2412f

2

LTC2412

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CO VERTER CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,

●

130

140

dB

CC

–

+

GND ≤ IN = IN ≤ V (Note 5)

CC

+

–

Input Common Mode Rejection

60Hz ±2%

2.5V ≤ REF ≤ V , REF = GND,

140

110

130

dB

CC

–

+

GND ≤ IN = IN ≤ V , (Notes 5, 7)

CC

+

–

Input Common Mode Rejection

50Hz ±2%

2.5V ≤ REF ≤ V , REF = GND,

CC

–

+

GND ≤ IN = IN ≤ V , (Notes 5, 8)

CC

Input Normal Mode Rejection

60Hz ±2%

(Notes 5, 7)

140

Input Normal Mode Rejection

(Note 5, 8)

50Hz ±2%

+

–

Reference Common Mode

Rejection DC

2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,

CC

–

+

V

= 2.5V, IN = IN = GND (Note 5)

REF

+

–

+

Power Supply Rejection, DC

REF = 2.5V, REF = GND, IN = IN = GND

120

dB

+

–

+

Power Supply Rejection, 60Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)

+

–

+

Power Supply Rejection, 50Hz ±2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 8)

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A ALOG I PUT A D REFERE CE _{The ● denotes specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

IN

Absolute/Common Mode IN Voltage

●

GND – 0.3

V

+ 0.3

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3

/2

V

Input Differential Voltage Range

–V /2

REF

V

IN

REF

+

–

(IN – IN )

+

–

+

REF

Absolute/Common Mode REF Voltage

●

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1

CC

V

Reference Differential Voltage Range

V

REF

CC

+

–

(REF – REF )

+

C (IN )

IN Sampling Capacitance

18

1

pF

nA

S

–

C (IN )

IN Sampling Capacitance

S

+

C (REF )

REF Sampling Capacitance

S

–

C (REF )

REF Sampling Capacitance

S

+

I

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = GND

●

–10

10

DC_LEAK

CC

–

(IN )

IN DC Leakage Current

CS = V = 5.5V, IN = 5.5V

1

10

CC

+

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = 5.5V

1

CC

–

(REF )

REF DC Leakage Current

CS = V = 5.5V, REF = GND

1

CC

2412f

3

LTC2412

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DIGITAL I PUTS A D DIGITAL OUTPUTS

The ● denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

IH

V

IL

V

IH

V

IL

High Level Input Voltage

●

2.5

2.0

V

CC

CS, F

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

CS, F

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 9)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 9)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 9)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 9)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 9)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F

O

Digital Input Capacitance

SCK

(Note 9)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 10)

O

– 0.5

V

Low Level Output Voltage

SCK

I = 1.6mA (Note 10)

O

0.4

10

V

I

Hi-Z Output Leakage

SDO

–10

µA

OZ

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POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

●

2.7

5.5

V

I

CC

Conversion Mode

Sleep Mode

CS = 0V

●

200

4

2

300

13

µA

CS = V (Note 12)

CC

CS = V , 2.7V ≤ V ≤ 3.3V

CC

(Note 12)

2412f

4

LTC2412

W U

TI I G CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.25

TYP

MAX

2000

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

390

µs

LEO

F = 0V

●

130.86

157.03

133.53

160.23

EOSC

136.20

163.44

(in kHz)

ms

CONV

O

F = V

O

CC

External Oscillator (Note 11)

20510/f

f

Internal SCK Frequency

Internal Oscillator (Note 10)

External Oscillator (Notes 10, 11)

19.2

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 10)

(Note 9)

●

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

2000

ESCK

250

1.64

LESCK

External SCK High Period

ns

HESCK

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

External Oscillator (Notes 10, 11)

●

1.67

1.70

ms

256/f

(in kHz)

EOSC

t

External SCK 32-Bit Data Output Time

CS ↓ to SDO Low Z

CS ↑ to SDO High Z

CS ↓ to SCK ↓

(Note 9)

●

32/f

(in kHz)

ms

ns

DOUT_ESCK

1

ESCK

0

200

t2

t3

t4

(Note 10)

(Note 9)

0

CS ↓ to SCK ↑

50

t

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

220

50

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 8: F_O= V_CC(internal oscillator) or f_EOSC= 128000Hz ±2%

(external oscillator).

Note 2: All voltage values are with respect to GND.

Note 9: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output. In this mode of operation the

SCK pin has a total equivalent load capacitance C_LOAD= 20pF.

Note 3: V_CC= 2.7V to 5.5V unless otherwise specified.

V

_REF= REF⁺– REF^–, V_REFCM= (REF⁺+ REF^–)/2; V_IN= IN⁺– IN^–,

V_INCM= (IN⁺+ IN^–)/2, IN⁺and IN^–are defined as the selected positive

(CH0⁺or CH1⁺) and negative (CH0^–or CH1^–) input respectively.

Note 4: F_Opin tied to GND or to V_CCor to external conversion clock

source with f_EOSC= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 11: The external oscillator is connected to the F_Opin. The external

oscillator frequency, f_EOSC, is expressed in kHz.

Note 12: The converter uses the internal oscillator.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer

curve. The deviation is measured from the center of the quantization

band.

F_O= 0V or F_O= V_CC

.

Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 7: F_O= 0V (internal oscillator) or f_EOSC= 153600Hz ±2%

Note 14: Guaranteed by design and test correlation.

(external oscillator).

2412f

5

LTC2412

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TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error vs

Temperature (V_CC= 5V,

Total Unadjusted Error vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Total Unadjusted Error vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

V

_REF= 5V)

1.5

1.0

1.5

1.0

10

8

V

= 5V

CC

+

REF = 2.5V

–

REF = GND

6

V

= 2.5V

INCM

= GND

REF

= 1.25V

4

T

= 90°C

A

0.5

F

O

2

T = 25°C

A

T

= 90°C

= 25°C

= –45°C

0

A

0

T

= 90°C

= 25°C

–2

A

V

= 5V

CC

V

= 2.7V

CC

–0.5

–1.0

–1.5

+

–0.5

–1.0

–1.5

+

REF = 5V

–4 REF = 2.5V

A

–

REF = GND

–6

T

= –45°C

V

O

= 5V

A

REF

INCM

V

= 2.5V

REF

T

= –45°C

A

= 2.5V

= 1.25V

–0.5

INCM

–8

F

= GND

F

O

= GND

–10

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

0

0.5

1

(V)

V

(V)

V

(V)

IN

2412 G01

2412 G02

2412 G03

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 5V)

Integral Nonlinearity vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

1.5

1.0

1.5

1.0

10

8

V

= 5V

V

= 2.7V

V

= 2.5V

REF

INCM

F = GND

O

CC

+

REF = 5V

T = –45°C

A

REF = 2.5V

= 1.25V

–

REF = GND

6

T

= –45°C

T = 25°C

A

V

O

= 5V

T

= 25°C

REF

INCM

A

= 2.5V

4

0.5

F

= GND

T

= 90°C

2

A

0

T

A

= 90°C

–2

–4

–6

–8

–10

V

= 5V

CC

T

= 90°C

= 25°C

A

+

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

REF = 2.5V

–

T

REF = GND

V

= 2.5V

INCM

= GND

REF

= –45°C

A

= 1.25V

F

O

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

–0.5

0

0.5

1

(V)

V

(V)

V

(V)

IN

2412 G04

2412 G05

2412 G06

Noise Histogram (Output Rate =

7.5Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 5V, V_REF= 5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.105ppm

σ = 0.153ppm

DISTRIBUTION

m = 0.067ppm

σ = 0.151ppm

DISTRIBUTION

m = 8.285ppm

σ = 0.311ppm

V

= 5V

V

= 5V

V

= 5V

CC

REF

IN

CC

REF

IN

CC

REF

= 5V

= 0V

IN

+

–

REF = 5V

–

REF = GND

+

–

+

–

+

–

IN = 2.5V

6

IN = 2.5V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

T

T = 25°C

A

4

2

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–9.8 –9.4 –9 –8.6 –8.2 –7.8 –7.4 –7 –6.6

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2412 G07

2412 G08

2412 G09

2412f

6

LTC2412

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TYPICAL PERFOR A CE CHARACTERISTICS

Noise Histogram (Output Rate =

7.5Hz, V_CC= 5V, V_REF= 2.5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 2.5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 5V, V_REF= 2.5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.033ppm

σ = 0.293ppm

DISTRIBUTION

m = 0.014ppm

σ = 0.292ppm

DISTRIBUTION

m = 3.852ppm

σ = 0.326ppm

V

= 5V

V

= 5V

V

= 5V

CC

REF

IN

CC

REF

IN

CC

REF

= 2.5V

= 0V

IN

+

–

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 1.25V

6

IN = 1.25V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

T

T = 25°C

A

4

2

0

–1.6

–0.8

0

0.8

1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–5.5 –5.1 –4.7 –4.3 –3.9 –3.5 –3.1 –2.7 –2.3

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2412 G10

2410 G11

2412 G12

Noise Histogram (Output Rate =

22.5Hz, V_CC= 2.7V, V_REF= 2.5V)

Noise Histogram (Output Rate =

7.5Hz, V_CC= 2.7V, V_REF= 2.5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 2.7V, V_REF= 2.5V)

12

10

8

12

10

8

10

9

8

7

6

5

4

3

2

1

0

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.079ppm

σ = 0.298ppm

DISTRIBUTION

m = 0.177ppm

σ = 0.297ppm

DISTRIBUTION

m = 3.714ppm

σ = 1.295ppm

V

= 2.7V

V

= 2.7V

V

= 2.7V

CC

REF

IN

CC

REF

IN

CC

REF

= 2.5V

= 0V

IN

+

–

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 1.25V

6

IN = 1.25V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

A

O

A

O

T

T = 25°C

A

4

2

0

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–10 –8.5 –7 –5.5 –4 –2.5 –1 0.5

OUTPUT CODE (ppm OF V

2

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2412 G13

2412 G14

2412 G15

Long-Term Noise Histogram

(Time = 60 Hrs, V_CC= 5V,

V_REF= 5V)

Consecutive ADC Readings

vs Time

RMS Noise

vs Input Differential Voltage

12

10

8

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

V

= 5V

GAUSSIAN DISTRIBUTION

m = 0.101837ppm

CC

REF

REF = 5V

+

σ = 0.154515ppm

–

0.6

REF = GND

V

= 2.5V

= GND

= 25°C

INCM

0.4

ADC CONSECUTIVE

READINGS

F

O

0.2

T

A

V

= 5V

CC

REF

IN

6

0

= 0V

+

–0.2

–0.4

–0.6

–0.8

–1.0

REF = 5V

–

4

REF = GND

+

–

IN = 2.5V

+

–

V

= 5V

T = 25°C

A

IN = 2.5V

CC

IN = 2.5V

+

= 5V REF = 5V IN = 2.5V

2

REF

F

= GND

= 25°C

–

O

A

= 0V REF = GND

IN

T

F

= GND

O

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

0

5

10 15 20 25 30 35 40 45 50 55 60

TIME (HOURS)

–2.5 –2 –1.5 –1 –0.5

0

0.5

1

1.5

2

2.5

OUTPUT CODE (ppm OF V

)

INPUT DIFFERENTIAL VOLTAGE (V)

REF

2412 G16

2412 G17

2412 G18

2412f

7

LTC2412

U W

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs V_INCM

RMS Noise vs Temperature (T_A)

RMS Noise vs V_CC

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

+

–

REF = 2.5V

REF = GND

V

= 2.5V

REF

+

IN = GND

–

IN = GND

F

= GND

O

A

T

= 25°C

V

= 5V

CC

+

REF = 5V

–

V

= 5V

REF = GND

CC

+

REF = 5V

V

= 5V

REF

–

+

–

REF = GND

IN = V

INCM

+

–

IN = 2.5V

IN = V

IN = 2.5V

V

F

A

= 0V

IN

O

V

F

= 0V

= GND

IN

O

T

= 25°C

–0.5 0 0.5

1

1.5

2

2.5

3

(V)

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

V

INCM

TEMPERATURE (°C)

V

CC

2412 G19

2412 G20

2412 G21

Offset Error vs V_INCM

RMS Noise vs V_REF

Offset Error vs Temperature (T_A)

850

825

800

775

750

725

700

675

650

0.3

0.2

0.3

0.2

V

= 5V

CC

–

REF = GND

+

–

IN = GND

F

= GND

= 25°C

O

A

0.1

T

V

= 5V

CC

+

0

REF = 5V

–

V

= 5V

CC

REF = GND

+

REF = 5V

V

= 5V

REF

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–

+

–

REF = GND

IN = V

INCM

+

–

IN = 2.5V

IN = V

V

IN = 2.5V

= 0V

IN

V

O

= 0V

= GND

IN

F

= GND

O

A

F

T

= 25°C

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–0.5 0 0.5

1

1.5

2

2.5

3

(V)

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

V

INCM

TEMPERATURE (°C)

REF

2412 G22

2412 G23

2412 G24

+Full-Scale Error

vs Temperature (T_A)

Offset Error vs V_CC

Offset Error vs V_REF

0.3

0.2

0.3

0.2

3

2

1

0.1

0

+

–

REF = 2.5V

V

= 5V

V

= 5V

CC

REF = GND

CC

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–1

–2

–3

–

+

REF = GND

REF = 5V

V

= 2.5V

REF

+

–

+

IN = GND

REF = GND

IN = GND

+

–

IN = 2.5V

IN = GND

F

= GND

= 25°C

IN = GND

F

= GND

O

A

O

A

T

F = GND

T

= 25°C

O

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–45 –30 –15

0

15 30 45 60 75 90

V

CC

TEMPERATURE (°C)

REF

2412 G25

2412 G26

2412 G27

2412f

8

LTC2412

U W

TYPICAL PERFOR A CE CHARACTERISTICS

–Full-Scale Error

vs Temperature (T_A)

+Full-Scale Error vs V_CC

+Full-Scale Error vs V_REF

3

2

3

2

3

2

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = GND

IN = 2.5V

1

F

= GND

O

0

+

–

REF = 2.5V

V

= 5V

CC

+

REF = GND

REF = V

REF

–1

–2

–3

–1

–2

–3

–1

–2

–3

–

V

= 2.5V

REF = GND

REF

+

–

+

IN = 1.25V

IN = 0.5 • REF

–

IN = GND

F

= GND

F

= GND

= 25°C

O

A

O

A

T

= 25°C

T

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–45 –30 –15

0

15 30 45 60 75 90

V

TEMPERATURE (°C)

CC

REF

2412 G28

2412 G29

2412 G30

–Full-Scale Error vs V_CC

PSRR vs Frequency at V_CC

–Full-Scale Error vs V_REF

3

2

3

2

0

+

–

REF = 2.5V

V

= 5V

V

= 4.1V ± 1.4V

DC

CC

+

REF = GND

REF = V

REF = 2.5V

REF

–

–20

–

V

= 2.5V

REF = GND

IN = GND

REF

+

–

+

–

IN = GND

–

+

IN = 1.25V

IN = 0.5 • REF

–40 IN = GND

1

F

= GND

= 25°C

F

= GND

= 25°C

F

= GND

= 25°C

O

A

O

A

O

A

T

–60

–80

0

–1

–2

–3

–1

–2

–3

–100

–120

–140

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

0.01

0.1

1

10

100

V

FREQUENCY AT V (Hz)

CC

REF

CC

2412 G31

2412 G32

2412 G33

PSRR vs Frequency at V_CC

0

–20

–40

0

V

= 4.1V ±1.4V

V

= 4.1V ±0.7V

V

= 4.1V

DC

CC

DC

CC DC P-P

CC

+

REF = 2.5V

–20

–40

–20

–40

–

REF = GND

+

–

+

–

+

–

IN = GND

F

= GND

= 25°C

F

= GND

F

= GND

= 25°C

O

A

O

A

T

= 25°C

A

T

–60

–80

–60

–80

–100

–120

–140

–100

–120

–140

–100

–120

–140

150 180 240

210

15300

15350

15450

0

30 60 90

15250

15400

10k

FREQUENCY AT V (Hz)

1M

120

1

10

100

1k

100k

FREQUENCY AT V (Hz)

CC

2412 G35

2412 G36

2412 G34

2412f

9

LTC2412

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Conversion Current

vs Temperature

Conversion Current

vs Output Data Rate

Sleep Mode Current

vs Temperature

1000

900

800

700

600

500

400

300

200

100

6

5

240

230

220

210

200

190

180

170

160

F

= GND

V

= V

CC

O

REF

+

CS = V

IN = GND

CC

V

= 5.5V

CC

–

SCK = NC

SDO = NC

IN = GND

SCK = NC

SDO = NC

CS = GND

V

= 5.5V

= 5V

CC

V

= 5V

CC

V

= 5V

CC

4

F

= GND

F

= EXT OSC

= 25°C

O

A

CS = GND

SCK = NC

SDO = NC

T

3

2

V

CC

V

= 3V

CC

V

= 3V

CC

V

= 3V

V

CC

= 2.7V

CC

1

0

V

CC

= 2.7V

15 30

0

10 20 30 40 50

OUTPUT DATA RATE (READINGS/SEC)

100

–45 –30 –15

0

15 30 45 60 75 90

TEMPERATURE (°C)

–45 –30 –15

0

45 60 75 90

60 70 80 90

TEMPERATURE (°C)

2412 G37

2412 G38

2412 G39

U

PI FU CTIO S

V_CC(Pin 1): Positive Supply Voltage. Bypass to GND with

a 10µF tantalum capacitor in parallel with 0.1µF ceramic

capacitor as close to the part as possible.

REF⁺(Pin 2), REF^–(Pin 3): Differential Reference Input.

ThevoltageonthesepinscanhaveanyvaluebetweenGND

and V_CCas long as the reference positive input, REF⁺, is

maintained more positive than the reference negative

input, REF ^–, by at least 0.1V.

CH0⁺(Pin 4): Positive Input for Differential Channel 0.

CH0^–(Pin 5): Negative Input for Differential Channel 0.

CH1⁺(Pin 6): Positive Input for Differential Channel 1.

CH1^–(Pin 7): Negative Input for Differential Channel 1.

The voltage on these four analog inputs (Pins 4 to 7) can

have any value between GND and V_CC. Within these limits

the converter bipolar input range (V_IN= IN⁺– IN^–) extends

from–0.5•(V_REF)to0.5•(V_REF). Outsidethisinputrange

the converter produces unique overrange and underrange

output codes.

CS (Pin 11): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

SDO (Pin 12): Three-State Digital Output. During the Data

Output period, this pin is used as serial data output. When

the chip select CS is HIGH (CS = V_CC) the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods, this pin is used as the conversion status output.

TheconversionstatuscanbeobservedbypullingCSLOW.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the Data

Output period. In External Serial Clock Operation mode,

SCK is used as digital input for the external serial interface

clock during the Data Output period. A weak internal pull-

up is automatically activated in Internal Serial Clock Op-

eration mode. The Serial Clock Operation mode is deter-

mined by the logic level applied to the SCK pin at power up

or during the most recent falling edge of CS.

GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins

internally connected for optimum ground current flow and

V_CCdecoupling. Connect each one of these pins to a ground

planethroughalowimpedanceconnection.Allfivepinsmust

be connected to ground for proper operation.

2412f

10

LTC2412

U

PI FU CTIO S

F_O(Pin 14): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to V_CC(F_O= V_CC), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the F_Opin is connected

to GND (F_O= OV), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When F_O

isdrivenbyanexternalclocksignalwithafrequencyf_EOSC

,

the converter uses this signal as its system clock and the

digital filter first null is located at a frequency f_EOSC/2560.

U

W

FU CTIO AL BLOCK DIAGRA

INTERNAL

OSCILLATOR

V

CC

GND

F

O

AUTOCALIBRATION

AND CONTROL

(INT/EXT)

+

CH0

+

–

IN

–

SCK

SDO

CS

CH0

DIFFERENTIAL

3RD ORDER

SERIAL

INTERFACE

MUX

∆Σ MODULATOR

+

CH1

–

+

–

CH1

DECIMATING FIR

CH0/CH1

PING-PONG

+

REF

2412 FD

–

REF

Figure 1. Functional Block Diagram

TEST CIRCUITS

V

CC

1.69k

SDO

C

= 20pF

1.69k

C

= 20pF

LOAD

Hi-Z TO V

OL

OH

V

TO V

V

OL

V

OH

TO V

OH

OL

TO Hi-Z

2412 TA04

TO Hi-Z

2412 TA03

2412f

11

LTC2412

U

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

after the first rising edge of SCK, the device begins

outputting the conversion result. Taking CS high at this

point will terminate the data output state and start a new

conversion. There is no latency in the conversion result.

The data output corresponds to the conversion just per-

formed. This result is shifted out on the serial data out pin

(SDO) under the control of the serial clock (SCK). Data is

updated on the falling edge of SCK allowing the user to

reliably latch data on the rising edge of SCK (see Figure 3).

The data output state is concluded once 32 bits are read

out of the ADC or when CS is brought HIGH. The device

automatically initiates a new conversion and the cycle

repeats.

Converter Operation Cycle

The LTC2412 is a low power, ∆Σ ADC with automatic

alternate channel selection between the two differential

channels and an easy-to-use 3-wire serial interface (see

Figure 1). Channel 0 is selected automatically at power up

and the two channels are selected alternately afterwards

(ping-pong). Its operation is made up of three states. The

converter operating cycle begins with the conversion,

followed by the low power sleep state and ends with the

data output (see Figure 2). The 3-wire interface consists

of serial data output (SDO), serial clock (SCK) and chip

select (CS).

Through timing control of the CS and SCK pins, the

LTC2412 offers several flexible modes of operation

(internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turbthecyclicoperationdescribedabove. Thesemodesof

operation are described in detail in the Serial Interface

Timing Modes section.

Initially, the LTC2412 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

The part remains in the sleep state as long as CS is HIGH.

Whileinthissleepstate,powerconsumptionisreducedby

nearly two orders of magnitude. The conversion result is

heldindefinitelyinastaticshiftregisterwhiletheconverter

is in the sleep state.

Once CS is pulled LOW, the device exits the low power

modeandentersthedataoutputstate. IfCSispulledHIGH

beforethefirstrisingedgeofSCK,thedevicereturnstothe

low power sleep mode and the conversion result is still

held in the internal static shift register. If CS remains LOW

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2412 incorporates a highly accu-

rate on-chip oscillator. This eliminates the need for exter-

nal frequency setting components such as crystals or

oscillators.Clockedbytheon-chiposcillator,theLTC2412

achieves a minimum of 110dB rejection at the line fre-

quency (50Hz or 60Hz ±2%).

POWER UP

+

–

IN = CH0 , IN = CH0

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

Ease of Use

The LTC2412 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle.Thereisaone-to-onecorrespondencebetweenthe

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

TRUE

DATA OUTPUT

SWITCH CHANNEL

2412 F02

Figure 2. LTC2412 State Transition Diagram

2412f

12

LTC2412

U

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APPLICATIO S I FOR ATIO

The LTC2412 performs offset and full-scale calibrations

every conversion cycle. This calibration is transparent to

the user and has no effect on the cyclic operation de-

scribed above. The advantage of continuous calibration is

extreme stability of offset and full-scale readings with re-

specttotime,supplyvoltagechangeandtemperaturedrift.

Input Voltage Range

The analog input is truly differential with an absolute/

common mode range for the CH0⁺/CH0^–or CH1⁺/CH1^–

input pins extending from GND – 0.3V to V_CC+ 0.3V.

Outside these limits, the ESD protection devices begin to

turn on and the errors due to input leakage current

increase rapidly. Within these limits, the LTC2412 con-

verts the bipolar differential input signal, V_IN= IN⁺– IN^–,

Power-Up Sequence

The LTC2412 automatically enters an internal reset state

when the power supply voltage V_CCdrops below approxi-

mately 2V. This feature guarantees the integrity of the

conversion result and of the serial interface mode selec-

tion. (See the 2-wire I/O sections in the Serial Interface

Timing Modes section.)

from –FS = –0.5 • V_REFto +FS = 0.5 • V_REFwhere V_REF

=

REF⁺– REF^–, with the selected channel referred as IN⁺and

IN^–. Outside this range, the converter indicates the

overrange or the underrange condition using distinct

output codes.

Input signals applied to the analog input pins may extend

by 300mV below ground and above V_CC. In order to limit

any fault current, resistors of up to 5k may be added in

series with the pins without affecting the performance of

the device. In the physical layout, it is important to main-

tain the parasitic capacitance of the connection between

these series resistors and the corresponding pins as low

as possible; therefore, the resistors should be located as

close as practical to the pins. The effect of the series

resistance on the converter accuracy can be evaluated

from the curves presented in the Input Current/Reference

Current sections. In addition, series resistors will intro-

duceatemperaturedependentoffseterrorduetotheinput

leakage current. A 1nA input leakage current will develop

a 1ppm offset error on a 5k resistor if V_REF= 5V. This error

has a very strong temperature dependency.

When the V_CCvoltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signalwithatypicaldurationof1ms.ThePORsignalclears

all internal registers and selects channel 0. Following the

POR signal, the LTC2412 starts a normal conversion cycle

and follows the succession of states described above. The

firstconversionresultfollowingPORisaccuratewithinthe

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Reference Voltage Range

This converter accepts a truly differential external refer-

ence voltage. The absolute/common mode voltage speci-

ficationfortheREF⁺andREF^–pinscoverstheentirerange

from GND to V_CC. For correct converter operation, the

REF⁺pin must always be more positive than the REF^–pin.

Output Data Format

The LTC2412 serial output data stream is 32 bits long. The

first 3 bits represent status information indicating the

conversion state, selected channel and sign. The next 24

bits are the conversion result, MSB first. The remaining 5

bits are sub LSBs beyond the 24-bit level that may be

included in averaging or discarded without loss of resolu-

tion. The third and fourth bit together are also used to

indicate an underrange condition (the differential input

voltage is below –FS) or an overrange condition (the

differential input voltage is above +FS).

The LTC2412 can accept a differential reference voltage

from 0.1V to V_CC. The converter output noise is deter-

mined by the thermal noise of the front-end circuits, and

as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

significantly improve the converter’s effective resolution.

On the other hand, a reduced reference voltage will im-

prove the converter’s overall INL performance. A reduced

reference voltage will also improve the converter perfor-

mance when operated with an external conversion clock

(external F_Osignal) at substantially higher output data

rates (see the Output Data Rate section).

2412f

13

LTC2412

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APPLICATIO S I FOR ATIO

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may

be included in averaging or discarded without loss of

resolution.

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

register.

Bit30(secondoutputbit)istheselectedchannelindicator.

The bit is LOW for channel 0 and HIGH for channel 1

selected.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bit is LOW.

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 31 (EOC) can be captured on the first rising

edge of SCK. Bit 30 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 31st SCK and may be latched on

the rising edge of the 32nd SCK pulse. On the falling edge

of the 32nd SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

Bit 28 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 29 also

provides the underrange or overrange indication. If both

Bit 29 and Bit 28 are HIGH, the differential input voltage is

above +FS. If both Bit 29 and Bit 28 are LOW, the

differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2412 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

Input Range

EOC CH0/CH1 SIG

MSB

V

≥ 0.5 • V

0

0 or 1

1

0

1

0

1

0

IN

REF

As long as the voltage on the analog input pins is main-

tainedwithinthe–0.3Vto(V_CC+0.3V)absolutemaximum

operating range, a conversion result is generated for any

differential input voltage V_INfrom –FS = –0.5 • V_REFto

+FS=0.5•V_REF.Fordifferentialinputvoltagesgreaterthan

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

0V ≤ V < 0.5 • V

IN

REF

–0.5 • V ≤ V < 0V

REF

IN

V

< –0.5 • V

IN

REF

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 5

BIT 0

SDO

SCK

LSB

24

CH0/CH1

Hi-Z

1

2

3

4

5

26

27

32

SLEEP

DATA OUTPUT

CONVERSION

2412 F03

Figure 3. Output Data Timing

2412f

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Table 2. LTC2412 Output Data Format

Differential Input Voltage

Bit 31

EOC

Bit 30

CH0/CH1

Bit 29

SIG

Bit 28

MSB

Bit 27

Bit 26

Bit 25

…

Bit 0

V

*

IN

V * ≥ 0.5 • V **

0

0/1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

…

0

1

0

1

0

1

0

1

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

REF

0.25 • V ** – 1LSB

REF

0

–1LSB

–0.25 • V **

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

REF

V * < –0.5 • V **

0

IN

REF

+

–

*The differential input voltage V = IN – IN .

IN

+

–

**The differential reference voltage V = REF – REF .

REF

normal mode rejection in a frequency range f_EOSC/2560

±4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from f_EOSC/2560

is shown in Figure 4.

Frequency Rejection Selection (F_O)

TheLTC2412internaloscillatorprovidesbetterthan110dB

normal mode rejection at the line frequency and all its

harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejec-

tion, F_Oshould be connected to GND while for 50Hz

rejection the F_Opin should be connected to V_CC.

WheneveranexternalclockisnotpresentattheF_Opin, the

converterautomaticallyactivatesitsinternaloscillatorand

enters the Internal Conversion Clock mode. The LTC2412

operation will not be disturbed if the change of conversion

clock source occurs during the sleep state or during the

data output state while the converter uses an external

serial clock. If the change occurs during the conversion

state, the result of the conversion in progress may be

The selection of 50Hz or 60Hz rejection can also be made

by driving F_Oto an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

–80

–85

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2412 can

operate with an external conversion clock. The converter

automatically detects the presence of an external clock

signal at the F_Opin and turns off the internal oscillator. The

frequency f_EOSCof the external signal must be at least

2560Hz (1Hz notch frequency) to be detected. The exter-

nal clock signal duty cycle is not significant as long as the

minimum and maximum specifications for the high and

low periods t_HEOand t_LEOare observed.

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–12

–8

–4

0

4

8

12

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

/2560(%)

2412 F04

EOSC

While operating with an external conversion clock of a

frequency f_EOSC, the LTC2412 provides better than 110dB

Figure 4. LTC2412 Normal Mode Rejection When

Using an External Oscillator of Frequency f_EOSC

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outside specifications but the following conversions will

notbeaffected.Ifthechangeoccursduringthedataoutput

state and the converter is in the Internal SCK mode, the

serial clock duty cycle may be affected but the serial data

stream will remain valid.

detected at the CS pin. If SCK is HIGH or floating at power-

up or during this transition, the converter enters the inter-

nal SCK mode. If SCK is LOW at power-up or during this

transition, the converter enters the external SCK mode.

Serial Data Output (SDO)

Table 3 summarizes the duration of each state and the

achievable output data rate as a function of F_O.

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

SERIAL INTERFACE PINS

The LTC2412 transmits the conversion results and re-

ceives the start of conversion command through a syn-

chronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

When CS (Pin 11) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase, theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to

synchronizethedatatransfer.Eachbitofdataisshiftedout

the SDO pin on the falling edge of the serial clock.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversionstatusandtoenablethedataoutputtransferas

described in the previous sections.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2412 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

internalorexternalSCKmodeisselectedonpower-upand

then reselected every time a HIGH-to-LOW transition is

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2412 will abort any serial data

transfer in progress and start a new conversion cycle

Table 3. LTC2412 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

(60Hz Rejection)

133ms, Output Data Rate ≤ 7.5 Readings/s

O

F = HIGH

O

160ms, Output Data Rate ≤ 6.2 Readings/s

(50Hz Rejection)

External Oscillator

F = External Oscillator

20510/f

s, Output Data Rate ≤ f

/20510 Readings/s

EOSC

O

EOSC

with Frequency f

kHz

EOSC

(f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH

DATA OUTPUT

Internal Serial Clock

External Serial Clock with

F = LOW/HIGH

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.67ms

(32 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

ms

EOSC

O

Frequency f

kHz

(32 SCK cycles)

EOSC

As Long As CS = LOW But Not Longer Than 32/f ms

SCK

Frequency f

kHz

(32 SCK cycles)

SCK

2412f

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anytime a LOW-to-HIGH transition is detected at the CS

pin after the converter has entered the data output state

(i.e., after the first rising edge of SCK occurs with

CS = LOW).

following sections describe each of these serial interface

timing modes in detail. In all these cases, the converter

can use the internal oscillator (F_O= LOW or F_O= HIGH) or

an external oscillator connected to the F_Opin. Refer to

Table 4 for a summary.

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by F_O.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

SERIAL INTERFACE TIMING MODES

The LTC2412’s 3-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

2-or3-wireI/O,singlecycleconversionandautostart.The

The serial clock mode is selected on the falling edge of CS.

Toselecttheexternalserialclockmode,theserialclockpin

(SCK) must be LOW during each CS falling edge.

Table 4. LTC2412 Interface Timing Modes

SCK

Conversion

Cycle

Control

Data

Output

Control

Connection

and

Waveforms

Configuration

Source

External

Internal

External SCK, Single Cycle Conversion

External SCK, 2-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 5, 6

Figure 7

Internal SCK, Single Cycle Conversion

Internal SCK, 2-Wire I/O, Continuous Conversion

CS ↓

Figures 8, 9

Figure 10

Continuous

Internal

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

2

3

4

5

6

7

+

–

+

REFERENCE

VOLTAGE

REF

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

3-WIRE

CH0

CH1

SPI INTERFACE

–

+

–

ANALOG INPUT RANGE

–0.5V TO 0.5V

REF REF

8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

CH0/CH1

SUB LSB

Hi-Z

SCK

(EXTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2412 F05

TEST EOC

(OPTIONAL)

Figure 5. External Serial Clock, Single Cycle Operation

2412f

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As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the device is in the sleep state. With CS high, the device

automatically enters the low power sleep state once the

conversion is complete.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the

32nd falling edge of SCK, see Figure 6. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for sys-

tems not requiring all 32 bits of output data, aborting an

invalid conversion cycle or synchronizing the start of a

conversion.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift regis-

ter. Data is shifted out the SDO pin on each falling edge of

SCK. This enables external circuitry to latch the output on

the rising edge of SCK. EOC can be latched on the first

rising edge of SCK and the last bit of the conversion result

can be latched on the 32nd rising edge of SCK. On the

32nd falling edge of SCK, the device begins a new conver-

sion. SDO goes HIGH (EOC = 1) indicating a conversion is

in progress.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

2

3

4

5

6

7

+

–

+

REFERENCE

VOLTAGE

REF

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

3-WIRE

CH0

CH1

SPI INTERFACE

–

+

–

ANALOG INPUT RANGE

–0.5V

TO 0.5V

REF

8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 9

BIT 8

SDO

CH0/CH1

Hi-Z

SCK

(EXTERNAL)

SLEEP

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC (OPTIONAL)

SLEEP

2412 F06

DATA

OUTPUT

Figure 6. External Serial Clock, Reduced Data Output Length

2412f

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2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

+

–

+

2

REFERENCE

REF

VOLTAGE

3

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

2-WIRE

INTERFACE

4

5

6

7

CH0

CH1

–

+

–

ANALOG INPUT RANGE

–0.5V TO 0.5V

REF REF

8, 9, 10, 15, 16

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

CH0/CH1

24

SCK

(EXTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

2412 F07

Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

typically 1ms after V_CCexceeds 2V. The level applied to

SCK at this time determines if SCK is internal or external.

SCK must be driven LOW prior to the end of POR in order

to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion ends. On the falling edge of

EOC, the conversion result is loaded into an internal static

shift register. Data is shifted out the SDO pin on each

falling edge of SCK enabling external circuitry to latch data

on the rising edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 32nd falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

WhentestingEOC,iftheconversioniscomplete(EOC=0),

the device will exit the sleep state during the EOC test. In

order to allow the device to return to the low power sleep

state, CS must be pulled HIGH before the first rising edge

of SCK. In the internal SCK timing mode, SCK goes HIGH

and the device begins outputting data at time t_EOCtestafter

the falling edge of CS (if EOC = 0) or t_EOCtestafter EOC goes

LOW (if CS is LOW during the falling edge of EOC). The

value of t_EOCtestis 23µs if the device is using its internal

oscillator (F₀= logic LOW or HIGH). If F_Ois driven by an

external oscillator of frequency f_EOSC, then t_EOCtestis

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

3.6/f_EOSC. If CS is pulled HIGH before time t_EOCtest, the

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V

2.7V TO 5.5V

CC

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

+

–

+

10k

2

REFERENCE

REF

VOLTAGE

3

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

4

5

6

7

3-WIRE

SPI INTERFACE

CH0

CH1

–

+

–

ANALOG INPUT RANGE

–0.5V

TO 0.5V

REF

8, 9, 10, 15, 16

GND

<t

EOCtest

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

CH0/CH1

24

Hi-Z

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

2412 F08

SLEEP

TEST EOC

(OPTIONAL)

Figure 8. Internal Serial Clock, Single Cycle Operation

device returns to the sleep state and the conversion result

is held in the internal static shift register.

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.

If CS remains LOW longer than t_EOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shiftedoutoftheSDOpin.Thedataoutputcycleconcludes

after the 32nd rising edge. Data is shifted out the SDO pin

oneachfallingedgeofSCK. Theinternallygeneratedserial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. EOC can

be latched on the first rising edge of SCK and the last bit

of the conversion result on the 32nd rising edge of SCK.

Afterthe32ndrisingedge, SDOgoesHIGH(EOC=1), SCK

stays HIGH and a new conversion starts.

Whenever SCK is LOW, the LTC2412’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certainapplicationsmayrequireanexternaldriveronSCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2412’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge, the device will remain in the internal SCK timing

mode.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the

conversion status. If the device is in the sleep state (EOC

=0),SCKwillgoLOW.OnceCSgoesHIGH(withinthetime

period defined above as t_EOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

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2.7V TO 5.5V

V

CC

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

+

–

+

10k

2

REFERENCE

REF

VOLTAGE

3

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

4

5

6

7

3-WIRE

SPI INTERFACE

CH0

CH1

–

+

–

ANALOG INPUT RANGE

–0.5V TO 0.5V

REF

8, 9, 10, 15, 16

GND

>t

<t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 8

SDO

CH0/CH1

Hi-Z

SCK

(INTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2412 F09

DATA

OUTPUT

TEST EOC

(OPTIONAL)

Figure 9. Internal Serial Clock, Reduced Data Output Length

internal pull-up may not be adequate to return SCK to a

HIGH level before CS goes low again. This is not a concern

under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

data output state. The data output cycle begins on the

first rising edge of SCK and ends after the 32nd rising

edge. Data is shifted out the SDO pin on each falling edge

of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result can be latched on the 32nd rising

edge of SCK. After the 32nd rising edge, SDO goes HIGH

(EOC=1)indicatinganewconversionisinprogress.SCK

remains HIGH during the conversion.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 10. CS may be permanently tied to ground, simpli-

fying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately1msafterV_CCexceeds2V. Aninternalweak

pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

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2.7V TO 5.5V

V

CC

1µF

= 50Hz REJECTION

1

14

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

V

F

O

CC

LTC2412

2

3

4

5

6

7

+

–

+

REFERENCE

VOLTAGE

REF

13

12

11

0.1V TO V

REF

SCK

SDO

CS

CC

2-WIRE

INTERFACE

CH0

CH1

–

+

–

ANALOG INPUT RANGE

–0.5V TO 0.5V

REF

8, 9, 10, 15, 16

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

CH0/CH1

24

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

2412 F10

Figure 10. Internal Serial Clock, Continuous Operation

PRESERVING THE CONVERTER ACCURACY

inExternalSCKmodeofoperation)iswithinthisrange,the

LTC2412 power supply current may increase even if the

signal in question is at a valid logic level. For micropower

operation, it is recommended to drive all digital input

signals to full CMOS levels [V_IL< 0.4V and V_OH

(V_CC– 0.4V)].

The LTC2412 is designed to reduce as much as possible

the conversion result sensitivity to device decoupling,

PCB layout, antialiasing circuits, line frequency perturba-

tions and so on. Nevertheless, in order to preserve the

extreme accuracy capability of this part, some simple

precautions are desirable.

>

During the conversion period, the undershoot and/or

overshootofafastdigitalsignalconnectedtotheLTC2412

pins may severely disturb the analog to digital conversion

process.Undershootandovershootcanoccurbecauseof

the impedance mismatch at the converter pin when the

transition time of an external control signal is less than

twice the propagation delay from the driver to LTC2412.

Forreference,onaregularFR-4board,signalpropagation

velocity is approximately 183ps/inch for internal traces

and 170ps/inch for surface traces. Thus, a driver gener-

ating a control signal with a minimum transition time of

1ns must be connected to the converter pin through a

trace shorter than 2.5 inches. This problem becomes

particularly difficult when shared control lines are used

and multiple reflections may occur. The solution is to

carefully terminate all transmission lines close to their

characteristic impedance.

Digital Signal Levels

The LTC2412’s digital interface is easy to use. Its digital

inputs(F_O,CSandSCKinExternalSCKmodeofoperation)

accept standard TTL/CMOS logic levels and the internal

hysteresis receivers can tolerate edge rates as slow as

100µs.However,someconsiderationsarerequiredtotake

advantage of the exceptional accuracy and low supply

current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

While a digital input signal is in the range 0.5V to

(V_CC– 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (F_O, CS and SCK

2412f

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Parallel termination near the LTC2412 pin will eliminate

thisproblembutwillincreasethedriverpowerdissipation.

A series resistor between 27Ω and 56Ω placed near the

driver or near the LTC2412 pin will also eliminate this

problem without additional power dissipation. The actual

resistor value depends upon the trace impedance and

connection topology.

Such perturbations may occur due to asymmetric capaci-

tivecouplingbetweentheF_Osignaltraceandtheconverter

input and/or reference connection traces. An immediate

solution is to maintain maximum possible separation

between the F_Osignal trace and the input/reference sig-

nals. When the F_Osignal is parallel terminated near the

converter, substantial AC current is flowing in the loop

formedbytheF_Oconnectiontrace, theterminationandthe

ground return path. Thus, perturbation signals may be

inductively coupled into the converter input and/or refer-

ence. In this situation, the user must reduce to a minimum

the loop area for the F_Osignal as well as the loop area for

the differential input and reference connections.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The multiple ground pins used

in this package configuration, as well as the differential

input and reference architecture, reduce substantially the

converter’s sensitivity to ground currents.

Driving the Input and Reference

Particular attention must be given to the connection of the

F_Osignal when the LTC2412 is used with an external

conversion clock. This clock is active during the conver-

sion time and the normal mode rejection provided by the

internal digital filter is not very high at this frequency. A

normal mode signal of this frequency at the converter

reference terminals may result into DC gain and INL

errors. A normal mode signal of this frequency at the

converterinputterminalsmayresultintoaDCoffseterror.

The input and reference pins of the LTC2412 converter are

directly connected to a network of sampling capacitors.

Depending upon the relation between the differential input

voltage and the differential reference voltage, these ca-

pacitorsareswitchingbetweenthesefourpinstransfering

small amounts of charge in the process. A simplified

equivalent circuit is shown in Figure 11, where IN⁺and IN^–

refertotheselecteddifferentialchannelandtheunselected

channel is omitted for simplicity.

V

CC

I

+

REF

R

(TYP)

V

_IN+ V_INCM− V_REFCM

SW

I IN⁺

=

I

LEAK

(

)

20k

AVG

0.5• R_EQ

−V_IN+ V_INCM− V_REFCM

0.5• R_EQ

V

REF

I IN⁻

(

V²

V

CC

1.5• V_REF− V_INCM+ V_REFCM

IN

I REF⁺

=

−

I

+

IN

(

)

AVG

R

(TYP)

20k

0.5• R_EQ

V

_REF• R_EQ

SW

I

LEAK

V²

−1.5• V_REF− V_INCM+ V_REFCM

0.5• R_EQ

IN

I REF⁻

=

+

V

+

(

)

AVG

C

V_REF• R_EQ

EQ

18pF

where:

(TYP)

V

V_REF= REF⁺−REF⁻

CC

I

–

IN

R

(TYP)

REF⁺+ REF⁻

SW

I

LEAK

V_REFCM

=

20k

2

V

_IN= IN⁺−IN⁻

IN⁺− IN⁻

V

CC

V

INCM

=

I

–

2

REF

(TYP)

20k

SW

I

LEAK

R_EQ= 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch F = LOW

(

)

O

2412 F11

V

R_EQ= 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch F = HIGH

REF

O

R_EQ= 0.555• 10¹²/ f_EOSCEXTERNAL OSCILLATOR

(

)

SWITCHING FREQUENCY

f

= 76800Hz INTERNAL OSCILLATOR (F = LOW OR HIGH)

SW

O

= 0.5 • f

EXTERNAL OSCILLATOR

EOSC

Figure 11. LTC2412 Equivalent Analog Input Circuit

2412f

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R

SOURCE

For a simple approximation, the source impedance R_S

driving an analog input pin (IN⁺, IN^–, REF⁺or REF^–) can be

considered to form, together with R_SWand C_EQ(see

Figure 11), a first order passive network with a time

constant τ = (R_S+ R_SW) • C_EQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

+

IN

C

PAR

V

+ 0.5V

– 0.5V

C

INCM

IN

20pF

LTC2412

–

IN

2412 F12

PAR

20pF

Figure 12. An RC Network at IN⁺and IN^–

50

Whenusingtheinternaloscillator(F_O=LOWorHIGH), the

LTC2412’sfront-endswitched-capacitornetworkisclocked

at 76800Hz corresponding to a 13µs sampling period.

Thus, for settling errors of less than 1ppm, the driving

sourceimpedanceshouldbechosensuchthatτ ≤13µs/14

= 920ns. When an external oscillator of frequency f_EOSCis

used, the sampling period is 2/f_EOSCand, for a settling

C

= 0.01µF

IN

C

= 0.001µF

IN

C

40

30

20

10

0

= 100pF

IN

C

= 0pF

IN

V

= 5V

CC

+

–

REF = 5V

REF = GND

+

–

IN = 5V

error of less than 1ppm, τ ≤ 0.14/f_EOSC

.

IN = 2.5V

F

T

= GND

O

A

= 25°C

Input Current

1

10

100

1k

10k

100k

R

(Ω)

SOURCE

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

theINLperformanceoftheconverter. Figure11showsthe

mathematical expressions for the average bias currents

flowing through the IN⁺and IN^–pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

2412 F13

Figure 13. +FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

0

V

= 5V

CC

+

REF = 5V

–

REF = GND

–10

–20

–30

–40

–50

+

–

IN = GND

IN = 2.5V

F

= GND

= 25°C

O

A

T

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 12. The C_PARcapacitor

includes the LTC2412 pin capacitance (5pF typical) plus

thecapacitanceofthetestfixtureusedtoobtaintheresults

shown in Figures 13 and 14. A careful implementation can

bring the total input capacitance (C_IN+ C_PAR) closer to 5pF

thus achieving better performance than the one predicted

by Figures 13 and 14. For simplicity, two distinct situa-

tions can be considered.

C

= 0.01µF

IN

C

= 0.001µF

IN

C

= 100pF

IN

C

= 0pF

IN

1

10

100

R

1k

(Ω)

10k

100k

SOURCE

2412 F14

Figure 14. –FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

for C_INwill deteriorate the converter offset and gain

performancewithoutsignificantbenefitsofsignalfiltering

and the user is advised to avoid them. Nevertheless, when

For relatively small values of input capacitance (C_IN

<

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

small values of C_INare unavoidably present as parasitics

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300

240

180

120

60

of input multiplexers, wires, connectors or sensors, the

LTC2412 can maintain its exceptional accuracy while

operatingwithrelativelargevaluesofsourceresistanceas

shown in Figures 13 and 14. These measured results may

be slightly different from the first order approximation

suggested earlier because they include the effect of the

actual second order input network together with the non-

linearsettlingprocessoftheinputamplifiers.ForsmallC_IN

values, the settling on IN⁺and IN^–occurs almost indepen-

dently and there is little benefit in trying to match the

source impedance for the two pins.

V

= 5V

CC

+

C

= 1µF, 10µF

REF = 5V

IN

–

REF = GND

+

–

IN = 3.75V

IN = 1.25V

F

= GND

= 25°C

O

A

T

C

IN

= 0.1µF

C

IN

= 0.01µF

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2412 F15

Larger values of input capacitors (C_IN> 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When F_O= LOW (internal oscillator and 60Hz notch), the

typical differential input resistance is 1.8MΩ which will

generate a gain error of approximately 0.28ppm at full-

scale for each ohm of source resistance driving IN⁺or IN.

When F_O= HIGH (internal oscillator and 50Hz notch), the

typical differential input resistance is 2.16MΩ which will

generate a gain error of approximately 0.23ppm at full-

scale for each ohm of source resistance driving IN⁺or IN.

When F_Ois driven by an external oscillator with a fre-

quency f_EOSC(external conversion clock operation), the

typical differential input resistance is 0.28 • 10¹²/f_EOSCΩ

and each ohm of source resistance driving IN⁺or IN^–will

resultin1.78•10^–6•f_EOSCppmgainerroratfull-scale.The

effect of the source resistance on the two input pins is

additivewithrespecttothisgainerror. Thetypical+FSand

–FS errors as a function of the sum of the source resis-

tanceseenbyIN⁺andIN^–forlargevaluesofC_INareshown

in Figures 15 and 16.

Figure 15. +FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

0

C

= 0.01µF

= 0.1µF

IN

–60

–120

–180

–240

–300

C

IN

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

C

= 1µF, 10µF

O

A

IN

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2412 F16

Figure 16. –FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

values, itisadvisabletocarefullymatchthesourceimped-

ance seen by the IN⁺and IN^–pins. When F_O= LOW

(internal oscillator and 60Hz notch), every 1Ω mismatch

in source impedance transforms a full-scale common

mode input signal into a differential mode input signal of

0.28ppm. When F_O= HIGH (internal oscillator and 50Hz

notch), every 1Ω mismatch in source impedance trans-

forms a full-scale common mode input signal into a differ-

ential mode input signal of 0.23ppm. When F_Ois driven by

an external oscillator with a frequency f_EOSC, every 1Ω

mismatch in source impedance transforms a full-scale

common mode input signal into a differential mode input

signal of 1.78 • 10^–6• f_EOSCppm. Figure 17 shows the

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

IN⁺and IN^–and with the difference between the input and

reference common mode voltages. While the input drive

circuitnonzerosourceimpedancecombinedwiththecon-

verter average input current will not degrade the INL

performance,indirectdistortionmayresultfromthemodu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large C_INcapacitor

typical offset error due to input common mode voltage for

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120

inasmalloffsetshift. A100Ωsourceresistancewillcreate

a 0.1µV typical and 1µV maximum offset voltage.

V

= 5V

CC

+

100

80

REF = 5V

A

–

REF = GND

+

–

IN = IN = V

INCM

60

B

Reference Current

40

C

D

E

F

20

In a similar fashion, the LTC2412 samples the differential

reference pins REF⁺and REF^–transfering small amount of

charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gainandINLperformance.Theeffectofthiscurrentcanbe

analyzed in the same two distinct situations.

0

–20

–40

–60

–80

–100

–120

F

= GND

O

A

G

T

= 25°C

SOURCEIN

= 10µF

R

C

– = 500Ω

IN

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V

(V)

INCM

A: ∆R = +400Ω

E: ∆R = –100Ω

IN

Forrelativelysmallvaluesoftheexternalreferencecapaci-

tors(C_REF<0.01µF),thevoltageonthesamplingcapacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for C_REFwill deteriorate the converter offset and

gainperformancewithoutsignificantbenefitsofreference

filtering and the user is advised to avoid them.

B: ∆R = +200Ω

F: ∆R = –200Ω

IN

C: ∆R = +100Ω

G: ∆R = –400Ω

IN

D: ∆R = 0Ω

2412 F17

IN

Figure 17. Offset Error vs Common Mode Voltage

(V_INCM= IN⁺= IN^–) and Input Source Resistance

Imbalance (∆R_IN= R_SOURCEIN+ – R_SOURCEIN–) for

Large C_INValues (C_IN≥ 1µF)

various values of source resistance imbalance between

the IN⁺and IN^–pins when large C_INvalues are used.

Larger values of reference capacitors (C_REF> 0.01µF) may

be required as reference filters in certain configurations.

Suchcapacitorswillaveragethereferencesamplingcharge

and the external source resistance will see a quasi con-

stant reference differential impedance. When F_O= LOW

(internaloscillatorand60Hznotch), thetypicaldifferential

reference resistance is 1.3MΩ which will generate a gain

error of approximately 0.38ppm at full-scale for each ohm

of source resistance driving REF⁺or REF^–. When F_O=

HIGH (internal oscillator and 50Hz notch), the typical

differential reference resistance is 1.56MΩ which will

generate a gain error of approximately 0.32ppm at full-

scale for each ohm of source resistance driving REF⁺or

REF^–. When F_Ois driven by an external oscillator with a

frequencyf_EOSC(externalconversionclockoperation),the

typical differential reference resistance is 0.20 • 10¹²/

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

Themagnitudeofthedynamicinputcurrentdependsupon

thesizeoftheverystableinternalsamplingcapacitorsand

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN⁺and

IN^–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

f

_EOSCΩ and each ohm of source resistance drving REF⁺or

REF^–will result in 2.47 • 10^–6• f_EOSCppm gain error at full-

scale. The effect of the source resistance on the two

reference pins is additive with respect to this gain error.

The typical +FS and –FS errors for various combinations

of source resistance seen by the REF⁺and REF^–pins and

external capacitance C_REFconnected to these pins are

shown in Figures 18, 19, 20 and 21.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

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0

50

40

30

20

10

0

V

= 5V

CC

C

= 0.01µF

REF

+

REF = 5V

–

C

= 0.001µF

REF

REF = GND

–10

–20

–30

–40

–50

+

–

IN = 5V

C

= 100pF

REF

IN = 2.5V

C

= 0pF

F

= GND

= 25°C

REF

O

A

T

V

= 5V

CC

+

–

REF = 5V

C

= 0.01µF

REF

REF = GND

+

–

C

= 0.001µF

REF

IN = GND

IN = 2.5V

C

= 100pF

REF

C

F

= GND

O

= 0pF

T

= 25°C

A

REF

1

10

100

R

1k

10k

100k

1

10

100

R

1k

(Ω)

10k

100k

(Ω)

SOURCE

2412 F18

2412 F19

Figure 18. +FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

Figure 19. –FS Error vs R_SOURCEat REF⁺or REF^–(Small C_IN)

0

450

V

= 5V

CC

C

= 0.01µF

REF

+

C

= 1µF, 10µF

REF = 5V

REF

–

REF = GND

–90

–180

–270

–360

–450

360

270

180

90

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

O

A

T

C

= 0.1µF

REF

C

REF

= 0.1µF

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

C

= 0.01µF

IN = 3.75V

REF

IN = 1.25V

C

= 1µF, 10µF

REF

F

= GND

= 25°C

O

A

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2412 F20

2412 F21

Figure 20. +FS Error vs R_SOURCEat REF⁺and REF^–(Large C_REF

)

Figure 21. –FS Error vs R_SOURCEat REF⁺and REF^–(Large C_REF

)

tworeferencepinsisadditivewithrespecttothisINLerror.

In general, matching of source impedance for the REF⁺

and REF^–pins does not help the gain or the INL error. The

user is thus advised to minimize the combined source

impedance driving the REF⁺and REF^–pins rather than to

try to match it.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

WhenF_O=LOW(internaloscillatorand60Hznotch),every

100ΩofsourceresistancedrivingREF⁺orREF^–translates

into about 1.34ppm additional INL error. When F_O= HIGH

(internaloscillatorand50Hznotch), every100Ωofsource

resistance driving REF⁺or REF^–translates into about

1.1ppm additional INL error. When F_Ois driven by an

external oscillator with a frequency f_EOSC, every 100Ω of

source resistance driving REF⁺or REF^–translates into

about 8.73 • 10^–6• f_EOSCppm additional INL error.

Figure 22 shows the typical INL error due to the source

resistance driving the REF⁺or REF^–pins when large C_REF

values are used. The effect of the source resistance on the

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors

2412f

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15

There is no significant difference in the LTC2412 perfor-

mance between these two operation modes.

R

= 1000Ω

12

9

SOURCE

R

= 500Ω

SOURCE

An increase in f_EOSCover the nominal 153600Hz will

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

6

3

0

–3

–6

–9

–12

–15

R

= 100Ω

SOURCE

First, a change in f_EOSCwill result in a proportional change

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line

frequency. In many applications, the subsequent perfor-

mance degradation can be substantially reduced by rely-

ing upon the LTC2412’s exceptional common mode

rejection and by carefully eliminating common mode to

differential mode conversion sources in the input circuit.

The user should avoid single-ended input filters and

should maintain a very high degree of matching and

symmetry in the circuits driving the IN⁺and IN^–pins.

–0.5–0.4–0.3–0.2–0.1

0

/V

0.1 0.2 0.3 0.4 0.5

V

INDIF REFDIF

V

= 5V

F = GND

O

CC

REF+ = 5V

C

= 10µF

REF

REF– = GND

T = 25°C

A

+

–

V

= 0.5 • (IN + IN ) = 2.5V

2412 F22

INCM

Figure 22. INL vs Differential Input Voltage (V_IN= IN⁺– IN^–)

and Reference Source Resistance (R_SOURCEat REF⁺and REF^–

for Large C_REFValues (C_REF≥ 1µF)

(50ppm/°C) are used for the external source impedance

seen by REF⁺and REF^–, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

valueovertheentiretemperatureandvoltagerange). Even

for the most stringent applications a one-time calibration

operation may be sufficient.

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

input and/or reference capacitors (C_IN, C_REF) are used, the

previous section provides formulae for evaluating the

effect of the source resistance upon the converter perfor-

mance for any value of f_EOSC. If small external input and/

or reference capacitors (C_IN, C_REF) are used, the effect of

the external source resistance upon the LTC2412 typical

performance can be inferred from Figures 13, 14, 18 and

Inadditiontothereferencesamplingcharge,thereference

pinsESDprotectiondiodeshaveatemperaturedependent

leakage current. This leakage current, nominally 1nA

(±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05µV typical and 0.5µV maxi-

mum full-scale error.

19 in which the horizontal axis is scaled by 153600/f_EOSC

.

Third, an increase in the frequency of the external oscilla-

torabove460800Hz(amorethan3×increaseintheoutput

data rate) will start to decrease the effectiveness of the

internal autocalibration circuits. This will result in a pro-

gressive degradation in the converter accuracy and linear-

ity. Typical measured performance curves for output data

rates up to 100 readings per second are shown in Fig-

ures 23, 24, 25, 26, 27, 28, 29 and 30. In order to obtain

the highest possible level of accuracy from this converter

at output data rates above 20 readings per second, the

userisadvisedtomaximizethepowersupplyvoltageused

and to limit the maximum ambient operating temperature.

In certain circumstances, a reduction of the differential

Output Data Rate

When using its internal oscillator, the LTC2412 can pro-

duceupto7.5readingspersecondwithanotchfrequency

of 60Hz (F_O= LOW) and 6.25 readings per second with a

notch frequency of 50Hz (F_O= HIGH). The actual output

data rate will depend upon the length of the sleep and data

output phases which are controlled by the user and which

can be made insignificantly short. When operated with an

external conversion clock (F_Oconnected to an external

oscillator), the LTC2412 output data rate can be increased

asdesired. Thedurationoftheconversionphaseis20510/

f_EOSC. If f_EOSC= 153600Hz, the converter behaves as if the

internal oscillator is used and the notch is set at 60Hz.

reference voltage may be beneficial.

2412f

28

LTC2412

U

W

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APPLICATIO S I FOR ATIO

7000

6000

5000

4000

3000

2000

1000

0

500

V

= 5V

CC

V

= 5V

CC

+

REF = 5V

450

400

350

300

250

200

150

100

50

REF = 5V

–

REF = GND

+

–

IN = 3.75V

V

= 2.5V

INCM

IN = 1.25V

= 0V

IN

F

= EXTERNAL OSCILLATOR

O

F

= EXTERNAL OSCILLATOR

O

T

= 85°C

A

T

= 85°C

A

T

= 25°C

A

T

A

= 25°C

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2412 F24

2412 F23

Figure 23. Offset Error vs Output Data Rate and Temperature

Figure 24. +FS Error vs Output Data Rate and Temperature

0

24

23

22

–1000

T

= 85°C

T

= 25°C

A

21

20

19

18

17

16

15

14

13

12

–2000

–3000

–4000

–5000

–6000

–7000

T

= 25°C

A

T

= 85°C

A

V

= 5V

CC

+

REF = 5V

V

= 5V

CC

–

+

REF = GND

REF = 5V

–

V

F

= 2.5V

REF = GND

INCM

+

–

= 0V

IN = 1.25V

IN

= EXTERNAL OSCILLATOR

IN = 3.75V

O

RESOLUTION = LOG (V /NOISE )

RMS

F

= EXTERNAL OSCILLATOR

2

REF

O

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2412 F25

2412 F26

Figure 25. –FS Error vs Output Data Rate and Temperature

Figure 26. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Temperature

22

250

RESOLUTION = LOG (V /INL

)

V

= 5V

CC

2

REF

MAX

+

225

200

175

150

125

100

75

REF = GND

20

18

16

14

12

10

8

V

F

= 2.5V

INCM

IN

= 0V

= EXTERNAL OSCILLATOR

= 25°C

O

T

= 85°C

T

= 25°C

A

V

= 5V

CC

V

= 5V

REF

+

REF = 5V

–

V

= 2.5V

REF = GND

REF

50

V

= 2.5V

INCM

–2.5V < V < 2.5V

IN

25

F

O

= EXTERNAL OSCILLATOR

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2412 F27

2412 F28

Figure 28. Offset Error vs Output

Data Rate and Reference Voltage

Figure 27. Resolution (INL_MAX≤ 1LSB)

vs Output Data Rate and Temperature

2412f

29

LTC2412

U

W

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APPLICATIO S I FOR ATIO

24

Input Bandwidth

23

V

= 5V

REF

The combined effect of the internal Sinc⁴digital filter and

of the analog and digital autocalibration circuits deter-

mines the LTC2412 input bandwidth. When the internal

oscillator is used with the notch set at 60Hz (F_O= LOW),

the 3dB input bandwidth is 3.63Hz. When the internal

oscillator is used with the notch set at 50Hz (F_O= HIGH),

the 3dB input bandwidth is 3.02Hz. If an external conver-

sionclockgeneratoroffrequencyf_EOSCisconnectedtothe

22

21

20

19

18

17

16

15

14

13

12

V

= 2.5V

REF

V

= 5V

CC

–

REF = GND

V

F

= 2.5V

INCM

= 0V

IN

= EXTERNAL OSCILLATOR

O

T

= 25°C

A

RESOLUTION = LOG (V /NOISE )

RMS

2

REF

F_Opin, the 3dB input bandwidth is 0.236 • 10^–6• f_EOSC

.

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

Due to the complex filtering and calibration algorithms

utilized,theconverterinputbandwidthisnotmodeledvery

accurately by a first order filter with the pole located at the

3dB frequency. When the internal oscillator is used, the

shape of the LTC2412 input bandwidth is shown in Fig-

ure 31 for F_O= LOW and F_O= HIGH. When an external

oscillator of frequency f_EOSCis used, the shape of the

LTC2412 input bandwidth can be derived from Figure 31,

F_O= LOW curve in which the horizontal axis is scaled by

f_EOSC/153600.

2412 F29

Figure 29. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Reference Voltage

22

RESOLUTION =

LOG (V /INL )

2

REF

MAX

20

18

16

14

12

10

8

V

= 2.5V

V

= 5V

REF

T

= 25°C

= 5V

A

CC

The conversion noise (800nV_RMStypical for V_REF= 5V)

can be modeled by a white noise source connected to a

noise free converter. The noise spectral density is

62.75nV/√Hz for an infinite bandwidth source and

86.1nV/√Hz for a single 0.5MHz pole source. From these

numbers, it is clear that particular attention must be given

to the design of external amplification circuits. Such

circuits face the simultaneous requirements of very low

bandwidth (just a few Hz) in order to reduce the output

referred noise and relatively high bandwidth (at least

500kHz) necessary to drive the input switched-capacitor

network. A possible solution is a high gain, low bandwidth

amplifier stage followed by a high bandwidth unity-gain

buffer.

V

–

REF = GND

= 0.5 • REF

+

V

INCM

–0.5V • V

< V < 0.5 • V

REF

IN REF

F

O

= EXTERNAL OSCILLATOR

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2412 F30

Figure 30. Resolution (INL_MAX≤ 1LSB)

vs Output Data Rate and Reference Voltage

0.0

–0.5

–1.0

–1.5

F

= HIGH

F = LOW

O

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

When external amplifiers are driving the LTC2412, the

ADCinputreferredsystemnoisecalculationcanbesimpli-

fied by Figure 32. The noise of an amplifier driving the

LTC2412 input pin can be modeled as a band limited white

noise source. Its bandwidth can be approximated by the

bandwidth of a single pole lowpass filter with a corner

frequency f_i. The amplifier noise spectral density is n_i.

From Figure 32, using f_ias the x-axis selector, we can find

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2412 F31

Figure 31. Input Signal Bandwidth

Using the Internal Oscillator

on the y-axis the noise equivalent bandwidth freq_iof the

2412f

30

LTC2412

U

W

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APPLICATIO S I FOR ATIO

100

10

1

input driving amplifier. This bandwidth includes the band

limitingeffectsoftheADCinternalcalibrationandfiltering.

The noise of the driving amplifier referred to the converter

input and including all these effects can be calculated as

N = n_i• √freq_i. The total system noise (referred to the

LTC2412 input) can now be obtained by summing as

squarerootofsumofsquaresthethreeADCinputreferred

noise sources: the LTC2412 internal noise (800nV), the

noise of the IN⁺driving amplifier and the noise of the IN^–

driving amplifier.

F

= LOW

= HIGH

O

0.1

1

10 100 1k 10k 100k 1M

If the F_Opin is driven by an external oscillator of frequency

f_EOSC, Figure32canstillbeusedfornoisecalculationifthe

x-axis is scaled by f_EOSC/153600. For large values of the

ratio f_EOSC/153600, the Figure 32 plot accuracy begins to

decrease, but in the same time the LTC2412 noise floor

rises and the noise contribution of the driving amplifiers

lose significance.

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

2412 F32

Figure 32. Input Referred Noise Equivalent Bandwidth

of an Input Connected White Noise Source

0

F

= HIGH

O

–10

–20

–30

–40

Normal Mode Rejection and Antialiasing

–50

–60

One of the advantages delta-sigma ADCs offer over con-

ventional ADCs is on-chip digital filtering. Combined with

a large oversampling ratio, the LTC2412 significantly

simplifies antialiasing filter requirements.

–70

–80

–90

–100

–110

–120

TheSinc⁴digitalfilterprovidesgreaterthan120dBnormal

mode rejection at all frequencies except DC and integer

multiples of the modulator sampling frequency (f_S). The

LTC2412’s autocalibration circuits further simplify the

antialiasing requirements by additional normal mode sig-

nal filtering both in the analog and digital domain. Inde-

pendent of the operating mode, f_S= 256 • f_N= 2048 •

f_OUTMAXwhere f_Nin the notch frequency and f_OUTMAXis

the maximum output data rate. In the internal oscillator

mode with a 50Hz notch setting, f_S= 12800Hz and with a

60Hz notch setting f_S= 15360Hz. In the external oscillator

mode, f_S= f_EOSC/10.

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f

S S S S S S S S S S S S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2412 F33

Figure 33. Input Normal Mode Rejection,

Internal Oscillator and 50Hz Notch

0

F

= LOW OR

O

–10

–20

= EXTERNAL

OSCILLATOR,

f

= 10 • f

EOSC

S

–30

–40

–50

–60

–70

–80

The combined normal mode rejection performance is

shown in Figure 33 for the internal oscillator with 50Hz

notch setting (F_O= HIGH) and in Figure 34 for the internal

oscillator with 60Hz notch setting (F_O= LOW) and for the

external oscillator mode. The regions of low rejection

occurring at integer multiples of f_Shave a very narrow

bandwidth.Magnifieddetailsofthenormalmoderejection

curves are shown in Figure 35 (rejection near DC) and

–90

–100

–110

–120

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f

S S S S S S S S S S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2412 F34

Figure 34. Input Normal Mode Rejection, Internal

Oscillator and 60Hz Notch or External Oscillator

2412f

31

LTC2412

U

W

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APPLICATIO S I FOR ATIO

Figure 36 (rejection at f_S= 256f_N) where f_Nrepresents the

notch frequency. These curves have been derived for the

external oscillator mode but they can be used in all

operating modes by appropriately selecting the f_Nvalue.

As a result of these remarkable normal mode specifica-

tions, minimal (if any) antialias filtering is required in front

of the LTC2412. If passive RC components are placed in

front of the LTC2412, the input dynamic current should be

considered (see Input Current section). In cases where

large effective RC time constants are used, an external

buffer amplifier may be required to minimize the effects of

dynamic input current.

The user can expect to achieve in practice this level of

performance using the internal oscillator as it is demon-

strated by Figures 37 and 38. Typical measured values of

the normal mode rejection of the LTC2412 operating with

an internal oscillator and a 60Hz notch setting are shown

in Figure 37 superimposed over the theoretical calculated

curve. Similarly, typical measured values of the normal

mode rejection of the LTC2412 operating with an internal

oscillator and a 50Hz notch setting are shown in Figure 38

superimposed over the theoretical calculated curve.

Traditional high order delta-sigma modulators, while pro-

viding very good linearity and resolution, suffer from po-

tential instabilities at large input signal levels. The

proprietary architecture used for the LTC2412 third order

modulator resolves this problem and guarantees a pre-

dictablestablebehavioratinputsignallevelsofupto150%

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

250f 252f 254f 256f 258f 260f 262f

N

0

f

2f

N

3f

4f

N

5f

6f

7f

8f

N

INPUT SIGNAL FREQUENCY (Hz)

2412 F36

2412 F35

Figure 35. Input Normal Mode Rejection

Figure 36. Input Normal Mode Rejection

0

–20

MEASURED DATA

CALCULATED DATA

V

= 5V

CC

+

REF = 5V

REF = GND

–

V

= 2.5V

INCM

= 5V

IN(P-P)

–40

F

= GND

O

T

A

= 25°C

–60

–80

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

2412 F37

Figure 37. Input Normal Mode Rejection vs Input Frequency

with Input Perturbation of 100% Full Scale (60Hz Notch)

2412f

32

LTC2412

U

W

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APPLICATIO S I FOR ATIO

of full scale. In many industrial applications, it is not un-

commontohavetomeasuremicrovoltlevelsignalssuper-

imposed over volt level perturbations and LTC2412 is

eminently suited for such tasks. When the perturbation is

differential,thespecificationofinterestisthenormalmode

rejection for large input signal levels. With a reference

voltage V_REF= 5V, the LTC2412 has a full-scale differen-

tialinputrangeof5Vpeak-to-peak.Figures39and40show

measurementresultsfortheLTC2412normalmoderejec-

tion ratio with a 7.5V peak-to-peak (150% of full scale)

input signal superimposed over the more traditional nor-

mal mode rejection ratio results obtained with a 5V peak-

to-peak (full scale) input signal. In Figure 39, the LTC2412

uses the internal oscillator with the notch set at 60Hz (F_O

= LOW) and in Figure 40 it uses the internal oscillator with

thenotchsetat50Hz(F_O=HIGH).ItisclearthattheLTC2412

rejectionperformanceismaintainedwithnocompromises

in this extreme situation. When operating with large input

signal levels, the user must observe that such signals do

not violate the device absolute maximum ratings.

Measuring Barometric Pressure and Temperature

with a Single Sensor

Figure 41 shows the LTC2412 measuring both tempera-

ture and pressure from an Intersema model MS5401-BM

absolute pressure sensor. The bridge has a nominal

impedanceof3.4k, atemperaturecoefficientofresistance

of 2900ppm/°C and a temperature coefficient of span of

–1900ppm/°C. R1 provides first order temperature com-

pensationoftheoutputspanbycausingthebridgevoltage

to increase by 1900ppm/°C, offsetting the –1900ppm/°C

TC of span. R1 should have a much smaller TC than that

of the bridge resistance; 50ppm/°C or less is satisfactory.

In addition to compensating the bridge output span, this

circuitalsoprovidesaconvenientwaytomeasureambient

temperature. Channel 1 of the LTC2412 measures the

bridge excitation voltage, which has a slope of approxi-

mately 3.2mV/°C. Channel 0 measures the bridge output,

which has a slope of 50mV/bar. The temperature reading

can also be used for second order compensation of the

pressure reading.

0

–20

MEASURED DATA

CALCULATED DATA

V

= 5V

CC

+

REF = 5V

REF = GND

–

V

= 2.5V

INCM

= 5V

IN(P-P)

–40

F

= 5V

O

T

= 25°C

A

–60

–80

–100

–120

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2412 F38

Figure 38. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch)

2412f

33

LTC2412

U

W

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APPLICATIO S I FOR ATIO

0

V

= 5V

= 7.5V

V

= 5V

IN(P-P)

CC

+

REF = 5V

REF = GND

IN(P-P)

–

–20

(150% OF FULL SCALE)

V

INCM

= 2.5V

F

T

= GND

= 25°C

O

–40

A

–60

–80

–100

–120

0

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

2412 F39

Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)

0

V

= 5V

= 7.5V

V

= 5V

IN(P-P)

CC

+

REF = 5V

REF = GND

IN(P-P)

–

–20

–40

(150% OF FULL SCALE)

V

INCM

= 2.5V

= 5V

= 25°C

F

O

T

A

–60

–80

–100

–120

0

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

INPUT FREQUENCY (Hz)

2412 F40

Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)

2412f

34

LTC2412

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.053 – .068

(1.351 – 1.727)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

GN16 (SSOP) 0502

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2412f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

35

LTC2412

U

TYPICAL APPLICATIO

5V

1

2

4.7µF

0.1µF

14

V

R1

F

O

CC

6.8k

+

50ppm/°C

REF

FO SELECTED

LTC2412

3

FOR 60Hz

4

5

6

7

3

REJECTION

+

–

+

CH0

CH1

13

4

1

SCK

SDO

CS

12

11

INTERSEMA

MSS401-BM

1 BAR FS

2

CH1¯

–

REF

8,9,10,15,16

GND

2412 TA05

Figure 41. Measure Barometric Pressure and Temperature with a Single Sensor

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1019

Precision Bandgap Reference, 2.5V, 5V

3ppm/°C Drift, 0.05% Max

Precise Charge, Balanced Switching, Low Power

LTC1043

Dual Precision Instrumentation Switched Capacitor

Building Block

LTC1050

Precision Chopper Stabilized Op Amp

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No External Components 5µV Offset, 1.6µV Noise

P-P

LT1236A-5

LT1461

0.05% Max, 5ppm/°C Drift

Micropower Precision LDO Reference

24-Bit, No Latency ∆Σ ADC in SO-8

High Accuracy 0.04% Max, 3ppm/°C Max Drift

LTC2400

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

LTC2401/LTC2402

LTC2404/LTC2408

LTC2410

1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

24-Bit, Fully Differential, No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC in MSOP

24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC

24-Bit, No Latency ∆Σ ADC

LTC2411

1.45µV

Noise, 2ppm INL

RMS

LTC2411-1

LTC2413

0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411

Simultaneous 50Hz/60Hz Rejection, 800nV Noise

RMS

LTC2414/LTC2418

LTC2415

8-/16-Channel, 24-Bit No Latency ∆Σ ADC

24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate

20-Bit, No Latency ∆Σ ADC in SO-8

0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

Pin Compatible with the LTC2410

LTC2420

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

4kHz Output Rate, 200nV Noise, 24.6 ENOBs

LTC2424/LTC2428

LTC2440

4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs

High Speed, Low Noise 24-Bit ADC

2412f

LT/TP 1202 2K • PRINTED IN USA

36 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002


型号：	LTC2418
厂家：	Linear
描述：	2-Channel Differential Input 24-Bit No Latency DS ADC 双通道差分输入24位无延迟DS ADC
文件：	总36页 (文件大小：409K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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