LTC2444CUHF#TRPBF_技术文档

LTC2444/LTC2445/

LTC2448/LTC2449

24-Bit High Speed

8-/16-Channel ∆∑ ADCs with

Selectable Speed/Resolution

DescripTion

FeaTures

The LTC^®2444/LTC2445/LTC2448/LTC2449 are 8-/16-

channel (4-/8-differential) high speed 24-bit No Latency

n

Up to 8 Differential or 16 Single-Ended Input Channels

n

Up to 8kHz Output Rate (External f )

O

™

n

Up to 4kHz Multiplexing Rate (External f )

∆Σ ADCs. They use a proprietary delta-sigma architec-

O

n

Selectable Speed/Resolution

ture enabling variable speed/resolution. Through a simple

4-wireserialinterface, tenspeed/resolutioncombinations

n

2µV

Noise at 1.76kHz Output Rate

RMS

n

200nV

Noise at 13.8Hz Output Rate with

6.9Hz/280nV

to 3.5kHz/25µV

(4kHz with external

RMS

Simultaneous 50Hz/60Hz Rejection

oscillator) can be selected with no latency between con-

version results or shift in DC accuracy (offset, full-scale,

linearity, drift). Additionally, a 2X speed mode can be

selected enabling output rates up to 7kHz (8kHz if an

external oscillator is used) with one cycle latency.

Guaranteed Modulator Stability and Lock-Up

Immunity for any Input and Reference Conditions

0.0005% INL, No Missing Codes

n

Autosleep Enables 20µA Operation at 6.9Hz

<5µV Offset (4.5V < V < 5.5V, –40°C to 85°C)

CC

Any combination of single-ended or differential inputs

can be selected with a common mode input range from

Differential Input and Differential Reference with

GND to V Common Mode Range

CC

ground to V , independent of V . While operating in

CC

REF

n

No Latency Mode, Each Conversion is Accurate Even

After a New Channel is Selected

the 1X speed mode the first conversion following a new

speed, resolution, or channel selection is valid. Since

there is no settling time between conversions, all 8 dif-

ferential channels can be scanned at a rate of 500Hz.

At the conclusion of each conversion, the converter is

internally reset eliminating any memory effects between

successive conversions and assuring stability of the high

order delta-sigma modulator.

n

Internal Oscillator—No External Components

LTC2445/LTC2449 Include MUXOUT/ADCIN for

External Buffering or Gain

n

Tiny QFN 5mm × 7mm Package

applicaTions

n

High Speed Multiplexing

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency ∆∑ and SoftSpan are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

n

Weight Scales

n

Auto Ranging 6-Digit DVMs

n

Direct Temperature Measurement

n

High Speed Data Acquisition

Typical applicaTion

LTC2444/LTC2448

RMS Noise vs Speed

Simple 24-Bit Variable Speed Data Acquisition System

100

4.5V TO 5.5V

V

= 5V

CC

= 5V

IN

REF

+

–

= V = 0V

1µF

IN

2X SPEED MODE

+

REF

V

CC

NO LATENCY MODE

CH0

CH1

= EXTERNAL OSCILLATOR

10

1

= INTERNAL OSCILLATOR

F

O

2.8µV AT 880Hz

(SIMULTANEOUS 50Hz/60Hz

REJECTION AT 6.9Hz OUTPUT RATE)

•

CH7

CH8

SDI

SCK

SDO

CS

280nV AT 6.9Hz

(50/60Hz REJECTION)

16-CHANNEL

MUX

VARIABLE SPEED/

RESOLUTION

+

–

4-WIRE

SPI INTERFACE

THERMOCOUPLE

•

DIFFERENTIAL

24-BIT ∆∑ ADC

CH15

COM

0.1

1

10

100

1000

10000

–

REF

CONVERSION RATE (Hz)

GND

LTC2448

2440 TA01b

2444 TA01a

2444589fc

1

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

absoluTe MaxiMuM raTings

(Notes 1, 2)

Supply Voltage (V ) to GND.......................–0.3V to 6V

Operating Temperature Range

CC

Analog Input Pins Voltage

LTC2444C/LTC2445C/

to GND......................................–0.3V to (V + 0.3V)

LTC2448C/LTC2449C............................... 0°C to 70°C

LTC2444I/LTC2445I/

LTC2448I/LTC2449I.............................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

CC

Reference Input Pins Voltage

to GND......................................–0.3V to (V + 0.3V)

CC

Digital Input Voltage to GND .........–0.3V to (V + 0.3V)

CC

Digital Output Voltage to GND.......–0.3V to (V + 0.3V)

CC

pin conFiguraTion

LTC2444

LTC2445

TOP VIEW

38 37 36 35 34 33 32

GND

BUSY

EXT

1

2

3

4

5

6

7

8

9

31 GND

GND

BUSY

EXT

1

2

3

4

5

6

7

8

9

31 GND

–

30 REF

+

REF

29

28

29

28

GND

COM

NC

V

CC

GND

COM

NC

V

CC

27 NC

26 NC

25 NC

24 NC

23 NC

27 MUXOUTN

26 ADCINN

25 ADCINP

24 MUXOUTP

23 NC

39

CH0

CH1 10

NC 11

NC 12

22 CH7

21 CH6

CH1 10

NC 11

NC 12

22 CH7

21 CH6

20

NC

13 14 15 16 17 18 19

UHF PACKAGE

13 14 15 16 17 18 19

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W

T

= 125°C, θ = 34°C/W

JMAX JA

JMAX

JA

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

LTC2448

LTC2449

TOP VIEW

38 37 36 35 34 33 32

GND

BUSY

EXT

1

2

3

4

5

6

7

8

9

31 GND

GND

BUSY

EXT

1

2

3

4

5

6

7

8

9

31 GND

–

30 REF

+

REF

29

28

29

28

GND

COM

CH0

V

CC

GND

COM

CH0

V

CC

27 NC

26 NC

25 NC

24 NC

27 MUXOUTN

26 ADCINN

25 ADCINP

24 MUXOUTP

23 CH15

39

CH1

23 CH15

22 CH14

21 CH13

CH1

CH2 10

CH3 11

CH4 12

CH2 10

CH3 11

CH4 12

22 CH14

21 CH13

20

CH12

13 14 15 16 17 18 19

UHF PACKAGE

13 14 15 16 17 18 19

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W

T

JMAX

= 125°C, θ = 34°C/W

JMAX

JA

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

2444589fc

2

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

orDer inForMaTion ^{http://www.linear.com/product/LTC2444#orderinfo}

LEAD FREE FINISH

LTC2444CUHF#PBF

LTC2444IUHF#PBF

LTC2445CUHF#PBF

LTC2445IUHF#PBF

LTC2448CUHF#PBF

LTC2448IUHF#PBF

LTC2449CUHF#PBF

LTC2449IUHF#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

38-Lead Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

LTC2444CUHF#TRPBF

LTC2444IUHF#TRPBF

LTC2445CUHF#TRPBF

LTC2445IUHF#TRPBF

LTC2448CUHF#TRPBF

LTC2448IUHF#TRPBF

LTC2449CUHF#TRPBF

LTC2449IUHF#TRPBF

2444

–40°C to 85°C

0°C to 70°C

2445

–40°C to 85°C

0°C to 70°C

2448

–40°C to 85°C

0°C to 70°C

2449

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Resolution (No Missing Codes)

Integral Nonlinearity

0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)

24

Bits

REF

CC

REF

IN

REF

+

–

V

= 5V, REF = 5V, REF = GND, V

= 2.5V, (Note 6)

5

3

15

5

ppm of V

CC

INCM

REF

+

–

REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

INCM

+

–

l

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

2.5

µV

CC

+

–

GND ≤ IN = IN ≤ V (Note 12)

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

20

nV/°C

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

+

–

l

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

Negative Full-Scale Error Drift

Total Unadjusted Error

REF = 5V, REF = GND, IN = 3.75V, IN = 1.25V

10

50

ppm of V

REF

+

–

+

–

REF = 2.5V, REF = GND, IN = 1.875V, IN = 0.625V

+

–

2.5V ≤ REF ≤ V , REF = GND,

IN = 0.75 • REF , IN = 0.25 • REF

0.2

ppm of V /°C

REF

CC

+

–

+

–

+

–

l

REF = 5V, REF = GND, IN = 1.25V, IN = 3.75V

10

50

ppm of V

REF

+

–

+

–

REF = 2.5V, REF = GND, IN = 0.625V, IN = 1.875V

+

–

2.5V ≤ REF ≤ V , REF = GND,

IN = 0.25 • REF , IN = 0.75 • REF

0.2

ppm of V /°C

REF

CC

+

–

+

–

5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V

15

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

= 2.5V

CC

INCM

+

–

REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

INCM

+

–

Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,

120

dB

CC

–

+

GND ≤ IN = IN ≤ V

CC

2444589fc

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For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

analog inpuT anD reFerence The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

l

IN

Absolute/Common Mode IN Voltage

GND – 0.3V

V

+ 0.3V

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3V

/2

V

Input Differential Voltage Range

–V /2

REF

V

IN

REF

+

–

(IN – IN )

+

–

+

l

REF

Absolute/Common Mode REF Voltage

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1V

CC

V

Reference Differential Voltage Range

V

CC

REF

+

–

(REF – REF )

+

C

IN Sampling Capacitance

2

1

pF

nA

S(IN )

–

IN Sampling Capacitance

S(IN )

+

REF Sampling Capacitance

S(REF )

–

REF Sampling Capacitance

S(REF )

+

–

+

–

l

I

Leakage Current, Inputs and Reference

CS = V , IN = GND, IN = GND,

–15

15

DC_LEAK(IN , IN ,

CC

+

–

+

–

REF = 5V, REF = GND

REF , REF )

+

–

I

Average Input/Reference Current

During Sampling

Varies, See Applications Section

nA

SAMPLE(IN , IN ,

+

–

REF , REF )

t

MUX Break-Before-Make

MUX Off Isolation

50

ns

OPEN

QIRR

V

IN

= 2V DC to 1.8MHz

120

dB

P-P

DigiTal inpuTs anD DigiTal ouTpuTs

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS

High Level Input Voltage, CS, F , SDI 4.5V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

l

V

2.5

IH

IL

IH

IL

O

CC

Low Level Input Voltage, CS, F , SDI

4.5V ≤ V ≤ 5.5V

0.8

V

O

CC

High Level Input Voltage SCK

Low Level Input Voltage SCK

4.5V ≤ V ≤ 5.5V (Note 8)

2.5

V

CC

4.5V ≤ V ≤ 5.5V (Note 8)

0.8

10

V

CC

I

Digital Input Current, CS, F , EXT, SDI

0V ≤ V ≤ V

CC

–10

µA

pF

V

IN

O

IN

Digital Input Current, SCK

0V ≤ V ≤ V (Note 8)

IN

CC

C

V

Digital Input Capacitance, CS, F , SDI

10

IN

O

Digital Input Capacitance, SCK

High Level Output Voltage, SDO, BUSY

Low Level Output Voltage, SDO, BUSY

High Level Output Voltage, SCK

Low Level Output Voltage, SCK

Hi-Z Output Leakage, SDO

(Note 8)

IN

l

I = –800µA

O

V

– 0.5V

OH

OL

OH

OL

CC

I = 1.6mA

O

0.4V

V

I = –800µA (Note 9)

O

V

CC

I = 1.6mA (Note 9)

O

0.4V

10

V

I

–10

µA

OZ

power requireMenTs

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

4.5

5.5

V

CC

I

Supply Current

Conversion Mode

Sleep Mode

CC

l

CS = 0V (Note 7)

8

11

30

mA

µA

CS = V (Note 7)

CC

2444589fc

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For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

TiMing characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

0.1

25

TYP

MAX

12

UNITS

MHz

ns

l

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

EOSC

HEO

10000

25

ns

LEO

l

OSR = 256 (SDI = 0)

OSR = 32768 (SDI = 1)

0.99

126

1.13

145

1.33

170

ms

CONV

40 • OSR +178

l

External Oscillator, 1X Mode

(Notes 10, 13)

ms

f

(kHz)

EOSC

f

Internal SCK Frequency

Internal Oscillator (Note 9)

External Oscillator (Notes 9, 10)

0.8

45

0.9

EOSC

1

MHz

Hz

ISCK

f

/10

l

D

Internal SCK Duty Cycle

(Note 9)

(Note 8)

55

20

%

MHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

ESCK

25

LESCK

External SCK High Period

ns

HESCK

DOUT_ISCK

l

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 9, 11)

External Oscillator (Notes 9, 10)

41.6

35.3

EOSC

30.9

µs

s

320/f

l

t

External SCK 32-Bit Data Output Time

CS ↓ to SDO Low Z

(Note 8)

32/f

s

ns

µs

ns

DOUT_ESCK

EOSC

(Note 12)

(Note 9)

0

25

1

CS ↑ to SDO High Z

CS ↓ to SCK ↓

2

5

3

l

(Notes 8, 12)

25

CS ↓ to SCK ↑

4

25

50

SCK ↓ to SDO Valid

KQMAX

(Note 5)

15

50

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

SDI Set-Up Before SCK ↑

SDI Hold After SCK ↑

KQMIN

5

6

7

8

(Note 5)

10

Note 7: The converter uses the internal oscillator.

Note 8: The converter is in external SCK mode of operation such that the

SCK pin is used as a digital input. The frequency of the clock signal driving

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

SCK during the data output is f

and is expressed in Hz.

ESCK

Note 2: All voltage values are with respect to GND.

Note 9: The converter is in internal SCK mode of operation such that the

SCK pin is used as a digital output. In this mode of operation, the SCK pin

Note 3: V = 4.5V to 5.5V unless otherwise specified.

CC

+

–

+

–

has a total equivalent load capacitance of C

= 20pF.

V

= REF – REF , V

= (REF + REF )/2;

= (IN + IN )/2.

LOAD

REF

REFCM

+

–

+

–

= IN – IN , V

Note 10: The external oscillator is connected to the F pin. The external

IN

INCM

O

oscillator frequency, f

, is expressed in Hz.

Note 4: F pin tied to GND or to external conversion clock source with

EOSC

O

f

= 10MHz unless otherwise specified.

Note 11: The converter uses the internal oscillator. F = 0V.

EOSC

O

Note 5: Guaranteed by design, not subject to test.

Note 12: Guaranteed by design and test correlation.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 13: There is an internal reset that adds an additional 5 to 15 f cycles

to the conversion time.

O

2444589fc

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For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

pin FuncTions

GND(Pins1,4,5,6,31,32,33):Ground.Multipleground

NC (Pins 24, 25, 26, 27): LTC2444/LTC2448 No Connect.

pinsinternallyconnectedforoptimumgroundcurrentflow

These pins can either be tied to ground or left floating.

and V decoupling. Connect each one of these pins to

CC

MUXOUTP (Pin 24): LTC2445/LTC2449 Positive Mul-

tiplexer Output. Used to drive the input to an external

buffer/amplifier.

a common ground plane through a low impedance con-

nection. All seven pins must be connected to ground for

proper operation.

ADCINP (Pin 25): LTC2445/LTC2449 Positive ADC Input.

BUSY (Pin 2): Conversion in Progress Indicator. This pin

is HIGH while the conversion is in progress and goes LOW

indicating the conversion is complete and data is ready.

It remains LOW during the sleep and data output states.

At the conclusion of the data output state, it goes HIGH

indicating a new conversion has begun.

Tie to output of buffer/amplifier driven by MUXOUTP.

ADCINN(Pin26):LTC2445/LTC2449NegativeADCInput.

Tie to output of buffer/amplifier driven by MUXOUTN.

MUXOUTN (Pin 27): LTC2445/LTC2449 Negative Mul-

tiplexer Output. Used to drive the input to an external

buffer/amplifier.

EXT (Pin 3): Internal/External SCK Selection Pin. This

pin is used to select internal or external SCK for output-

ting/inputting data. If EXT is tied low, the device is in the

external SCK mode and data is shifted out of the device

under the control of a user applied serial clock. If EXT is

tied high, the internal serial clock mode is selected. The

device generates its own SCK signal and outputs this on

the SCK pin. A framing signal BUSY (Pin 2) goes low

indicating data is being output.

V

(Pin28):PositiveSupplyVoltage. BypasstoGNDwith

CC

a 10µF tantalum capacitor in parallel with a 0.1µF ceramic

capacitor as close to the part as possible.

+

–

REF (Pin29),REF (Pin30):DifferentialReferenceInput.

The voltage on these pins can have any value between

+

GNDandV aslongasthereferencepositiveinput, REF ,

CC

is maintained more positive than the negative reference

+

input, REF , by at least 0.1V.

–

COM (Pin 7): The common negative input (IN ) for all

single ended multiplexer configurations. The voltage on

CH0 to CH15 and COM pins can have any value between

SDI (Pin 34): Serial Data Input. This pin is used to select

the speed, 1X or 2X mode, resolution, and input channel,

for the next conversion cycle. At initial power up, the

default mode of operation is CH0 to CH1, OSR of 256,

and 1X mode. The serial data input contains an enable

bit which determines if a new channel/speed is selected.

If this bit is low the following conversion remains at the

same speed and selected channel. The serial data input

is applied to the device under control of the serial clock

(SCK) during the data output cycle. The first conversion

following a new channel/speed is valid.

GND – 0.3V to V + 0.3V. Within these limits, the two

CC

+

–

selected inputs (IN and IN ) provide a bipolar input range

+

–

(V = IN – IN ) from –0.5 • V

to 0.5 • V . Outside

IN

REF

thisinputrange, theconverterproducesuniqueoverrange

and underrange output codes.

CH0 to CH15 (Pins 8 to 23): LTC2448/LTC2449 Analog

Inputs. May be programmed for single-ended or differ-

ential mode.

CH0toCH7(Pins9,10,13,14,17,18,21,22):LTC2444/

LTC2445 Analog Inputs. May be programmed for single-

ended or differential mode.

F (Pin 35): Frequency Control Pin. Digital input that con-

O

trols the internal conversion clock. When F is connected

O

to V or GND, the converter uses its internal oscillator.

CC

NC(Pins8,11,12,15,16,19,20,23):LTC2444/LTC2445

No Connect/Channel Isolation Shield. May be left floating

or tied to any voltage 0 to V in order to provide isolation

CC

for pairs of differential input channels.

2444589fc

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For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

pin FuncTions

CS (Pin 36): Active Low Chip Select. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion the ADC automatically enters

the sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS dur-

ing the Data Output aborts the data transfer and starts a

new conversion.

SCK (Pin 38): Bidirectional Digital Clock Pin. In internal

serial clock operation mode, SCK is used as a digital

output for the internal serial interface clock during the

data output period. In the external serial clock operation

mode, SCK is used as the digital input for the external

serial interface clock during the data output period. The

serial clock operation mode is determined by the logic

level applied to the EXT pin.

SDO (Pin 37): Three-State Digital Output. During the data

output period, this pin is used as serial data output. When

Exposed Pad (Pin 39): Ground. The exposed pad on the

bottomofthepackagemustbesolderedtothePCBground.

For prototyping purposes, this pin may remain floating.

the chip select CS is HIGH (CS = V ) the SDO pin is in

CC

a high impedance state. During the conversion and sleep

periods, this pin is used as the conversion status output.

TheconversionstatuscanbeobservedbypullingCSLOW.

This signal is HIGH while the conversion is in progress

and goes LOW once the conversion is complete.

2444589fc

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LTC2444/LTC2445/

LTC2448/LTC2449

FuncTional block DiagraM

INTERNAL

OSCILLATOR

V

CC

GND

F

AUTOCALIBRATION

AND CONTROL

O

(INT/EXT)

+

–

REF

CH0

CH1

+

–

+

–

IN

DIFFERENTIAL

3RD ORDER

∆∑ MODULATOR

SDI

SCK

SDO

CS

•

MUX

SERIAL

INTERFACE

CH15

COM

DECIMATING FIR

ADDRESS

2444589 F01

Figure 1. Functional Block Diagram

TesT circuiT

V

CC

SDO

1.69k

C

= 20pF

LOAD

SDO

C

= 20pF

LOAD

Hi-Z TO V

OH

V

TO V

OL

OH

TO Hi-Z

2444589 TC01

Hi-Z TO V

OL

V

TO V

OH

OL

TO Hi-Z

2444589 TC02

2444589fc

8

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CONVERTER OPERATION

corresponds to the conversion just performed. This result

is shifted out on the serial data out pin (SDO) under the

control of the serial clock (SCK). Data is updated on the

falling edge of SCK allowing the user to reliably latch data

on the rising edge of SCK (see Figure 3). The data output

state is concluded once 32 bits are read out of the ADC

or when CS is brought HIGH. The device automatically

initiates a new conversion and the cycle repeats.

Converter Operation Cycle

The LTC2444/LTC2445/LTC2448/LTC2449 are multi-

channel,highspeed,delta-sigmaanalog-to-digitalconvert-

ers with an easy to use 3- or 4-wire serial interface (see

Figure 1). Their operation is made up of three states. The

converter operating cycle begins with the conversion, fol-

lowed by the low power sleep state and ends with the data

output/input (see Figure 2). The 4-wire interface consists

of serial data input (SDI), serial data output (SDO), serial

clock (SCK) and chip select (CS). The interface, timing,

operation cycle and data out format is compatible with

Linear’s entire family of ∆Σ converters.

Through timing control of the CS, SCK and EXT pins, the

LTC2444/LTC2445/LTC2448/LTC2449 offer several flex-

ible modes of operation (internal or external SCK). These

variousmodesdonotrequireprogrammingconfiguration

registers;moreover,theydonotdisturbthecyclicoperation

described above. These modes of operation are described

in detail in the Serial Interface Timing Modes section.

POWER UP

IN =CH0, IN =CH1

OSR=256,1X MODE

+

–

Ease of Use

The LTC2444/LTC2445/LTC2448/LTC2449 data output

has no latency, filter settling delay or redundant data

associated with the conversion cycle while operating

in the 1X mode. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog voltages is easy. Speed/

resolutionadjustmentsmaybemadeseamlesslybetween

two conversions without settling errors.

CONVERT

SLEEP

CS = LOW

AND

SCK

TheLTC2444/LTC2445/LTC2448/LTC2449performoffset

and full-scale calibrations every conversion cycle. This

calibration is transparent to the user and has no effect

on the cyclic operation described above. The advantage

of continuous calibration is extreme stability of offset and

full-scale readings with respect to time, supply voltage

change and temperature drift.

CHANNEL SELECT

SPEED SELECT

DATA OUTPUT

2444589 F02

Figure 2. LTC2444/LTC2445/LTC2448/LTC2449

State Transition Diagram

Power-Up Sequence

Initially, the LTC2444/LTC2445/LTC2448/LTC2449 per-

form a conversion. Once the conversion is complete, the

deviceentersthesleepstate.Whileinthissleepstate,power

consumption is reduced below 10µA. The part remains

in the sleep state as long as CS is HIGH. The conversion

result is held indefinitely in a static shift register while the

converter is in the sleep state.

TheLTC2444/LTC2445/LTC2448/LTC2449automatically

enter an internal reset state when the power supply volt-

age V drops below approximately 2.2V. This feature

CC

guarantees the integrity of the conversion result and of

the serial interface mode selection.

WhentheV voltagerisesabovethiscriticalthreshold,the

CC

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result while operating in the 1x mode. The data output

converter creates an internal power-on-reset (POR) signal

with a duration of approximately 0.5ms. The POR signal

2444589fc

9

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Input Voltage Range

clears all internal registers. The conversion immediately

+

following a POR is performed on the input channel IN

RefertoFigure4.Theanaloginputistrulydifferentialwithan

absolute/commonmoderangefortheCH0toCH15andCOM

inputpinsextendingfromGND–0.3VtoV +0.3V.Outside

–

= CH0, IN = CH1 at an OSR = 256 in the 1X mode. Fol-

lowing the POR signal, the LTC2444/LTC2445/LTC2448/

LTC2449 start a normal conversion cycle and follow the

successionofstatesdescribedabove.Thefirstconversion

result following POR is accurate within the specifications

of the device if the power supply voltage is restored within

the operating range (4.5V to 5.5V) before the end of the

POR time interval.

CC

these limits, the ESD protection devices begin to turn on

and the errors due to input leakage current increase rap-

idly. Withintheselimits, theLTC2444/LTC2445/LTC2448/

LTC2449convertthebipolardifferentialinputsignal, V =

IN

+

–

+

–

IN – IN (where IN and IN are the selected input chan-

nels), from –FS = –0.5 • V to +FS = 0.5 • V where

REF

+

–

V

= REF – REF . Outside this range, the converter

REF

Reference Voltage Range

indicates the overrange or the underrange condition using

distinct output codes.

These converters accept a truly differential external

reference voltage. The absolute/common mode voltage

+

–

MUXOUT/ADCIN

specification for the REF and REF pins covers the entire

rangefromGNDtoV .Forcorrectconverteroperation,the

REF pin must always be more positive than the REF pin.

There are two differences between the LTC2444/LTC2448

and the LTC2445/LTC2449. The first is the RMS noise

performance. For a given OSR, the LTC2445/LTC2449

noise level is approximately √2 times lower (0.5 effective

bits)than that of the LTC2444/LTC2448.

CC

+

–

The LTC2444/LTC2445/LTC2448/LTC2449 can accept a

differential reference voltage from 0.1V to V . The con-

CC

verter output noise is determined by the thermal noise of

the front-end circuits, and as such, its value in microvolts

is nearly constant with reference voltage. A decrease in

reference voltage will not significantly improve the con-

verter’s effective resolution. On the other hand, a reduced

reference voltage will improve the converter’s overall INL

performance.

The second difference is the LTC2445/LTC2449 includes

MUXOUT/ADCIN pins. These pins enable an external buf-

fer or gain block to be inserted between the output of the

multiplexer and the input to the ADC. Since the buffer is

driven by the output of the multiplexer, only one circuit is

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32

SCK

SDI

1

0

EN

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19

EOC “0” SIG MSB

SGL

ODD

A2

A1

A0

OSR3 OSR2 OSR1 OSR0 TWOX

BIT 0

Hi-Z

SDO

LSB

BUSY

2444589 F03

Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing

2444589fc

10

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requiredforall16inputchannels.Additionally,thetranspar-

entcalibrationfeatureoftheLTC244Xfamilyautomatically

removes the offset errors of the external buffer.

beyond the 24-bit level. The third and fourth bit together

are also used to indicate an underrange condition (the

differential input voltage is below –FS) or an overrange

condition (the differential input voltage is above +FS).

In order to achieve optimum performance, the MUXOUT

andADCINpinsshouldnotbeshortedtogether.Inapplica-

tions where the MUXOUT and ADCIN need to be shorted

together, the LTC2444/LTC2448 should be used because

the MUXOUT and ADCIN are internally connected for

optimum performance.

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Output Data Format

The LTC2444/LTC2445/LTC2448/LTC2449 serial output

data stream is 32 bits long. The first 3 bits represent sta-

tus information indicating the sign and conversion state.

The next 24 bits are the conversion result, MSB first. The

remaining 5 bits are sub LSBs beyond the 24-bit level that

may be included in averaging or discarded without loss of

resolution.Inthecaseofultrahighresolutionmodes,more

than 24 effective bits of performance are possible (see

Table 5). Under these conditions, sub LSBs are included

in the conversion result and represent useful information

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If V is >0, this bit is HIGH. If V is <0,

IN

this bit is LOW.

Bit28(fourthoutputbit)isthemostsignificantbit(MSB)of

the result. This bit in conjunction with Bit 29 also provides

the underrange or overrange indication. If both Bit 29 and

Bit 28 are HIGH, the differentialinput voltageisabove +FS.

If both Bit 29 and Bit 28 are LOW, the differential input

voltage is below –FS.

V_CC+ 0.3V

V_CC

V_REF

2

V_REF

–V_REF

2

V_REF

2

–V_REF

2

GND

–0.3V

GND

V_CC

(a) Arbitrary

(b) Fully Differential

V_CC

V_REF

2

V_REF

2

–V_REF

2

–0.3V

GND

–0.3V

GND

(c) Pseudo Differential Bipolar

IN– or COM Biased

(d) Pseudo-Differential Unipolar

IN– or COM Grounded

+

Selected IN Ch

–

2444589 F04

Selected IN Ch or COM

Figure 4. Input Range

2444589fc

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The function of these bits is summarized in Table 1.

Table 1. LTC2444/LTC2445/LTC2448/LTC2449 Status Bits

the first falling edge of SCK. The final data bit (Bit 0) is

shifted out on the falling edge of the 31st SCK and may

be latched on the rising edge of the 32nd SCK pulse. On

the falling edge of the 32nd SCK pulse, SDO goes HIGH

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 31) for the next conversion cycle.

Table 2 summarizes the output data format.

BIT 31

BIT 30

DMY

BIT 29

SIG

BIT 28

MSB

INPUT RANGE

≥ 0.5 • V

EOC

V

IN

0

1

0

1

0

1

0

REF

0V ≤ V < 0.5 • V

IN

REF

–0.5 • V ≤ V < 0V

REF

IN

+

–

As long as the voltage on the IN and IN pins is main-

V

< –0.5 • V

IN

REF

tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum

CC

Bits 28 to 5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

operating range, a conversion result is generated for any

differential input voltage V from –FS = –0.5 • V

to

IN

REF

+FS = 0.5 • V . For differential input voltages greater

REF

Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to

0 may be included in averaging or discarded without loss

of resolution.

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

Data is shifted out of the SDO pin under control of the

serial clock (SCK), see Figure 3. Whenever CS is HIGH,

SDO remains high impedance and SCK is ignored.

SERIAL INTERFACE PINS

In order to shift the conversion result out of the device,

CS must first be driven LOW. EOC is seen at the SDO pin

of the device once CS is pulled LOW. EOC changes real

time from HIGH to LOW at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on

The LTC2444/LTC2445/LTC2448/LTC2449 transmit the

conversion results and receive the start of conversion

command through a synchronous 3- or 4-wire interface.

Duringtheconversionandsleepstates, thisinterfacecan

be used to assess the converter status and during the

data output state it is used to read the conversion result

and program the speed, resolution and input channel.

Table 2. LTC2444/LTC2445/LTC2448/LTC2449 Output Data Format

DIFFERENTIAL INPUT VOLTAGE

IN

BIT 31

EOC

BIT 30

DMY

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 25

…

BIT 0

V

*

V * ≥ 0.5 • V **

0

1

0

1

0

1

0

1

…

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

0

1

0

1

0

1

0

1

…

0

1

REF

0.25 • V ** – 1LSB

REF

0

1

0

1

0

1

0

1

0

1

…

0

1

–1LSB

–0.25 • V **

0

1

0

1

0

1

…

0

1

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

0

1

0

1

0

1

0

1

…

0

1

REF

V * < –0.5 • V **

IN

REF

+

–

+

–

*The differential input voltage V = IN – IN . **The differential reference voltage V = REF – REF .

IN

REF

2444589fc

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Serial Clock Input/Output (SCK)

serial input data stream under the control of SCK during

the data output cycle, see Figure 3.

The serial clock signal present on SCK (Pin 38) is used to

synchronize the data transfer. Each bit of data is shifted

out the SDO pin on the falling edge of the serial clock.

Initially, after powering up, the device performs a conver-

+

–

sion with IN = CH0, IN = CH1, OSR = 256 (output rate

nominally 880Hz), and 1X speed mode (no latency). Once

this first conversion is complete, the device enters the

sleep state and is ready to output the conversion result

and receive the serial data input stream programming the

speed/resolutionandinputchannelforthenextconversion.

At the conclusion of each conversion cycle, the device

enters this state.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2444/LTC2445/LTC2448/LTC2449

create their own serial clock. In the External SCK mode

of operation, the SCK pin is used as input. The internal or

external SCK mode is selected by tying EXT (Pin 3) LOW

for external SCK and HIGH for internal SCK.

Serial Data Output (SDO)

In order to change the speed/resolution or input chan-

nel, the first 3 bits shifted into the device are 101. This

is compatible with the programming sequence of the

LTC2414/LTC2418. If the sequence is set to 000 or 100,

the following input data is ignored (don’t care) and the

previously selected speed/resolution and channel remain

valid for the next conversion. Combinations other than

101, 100, and 000 of the 3 control bits should be avoided.

The serial data output pin, SDO (Pin 37), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO

pin is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 36) is HIGH, the SDO driver is switched

to a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH

on the SDO pin. Once the conversion is complete, EOC

goes LOW. The device remains in the sleep state until the

first rising edge of SCK occurs while CS = LOW.

If the first 3 bits shifted into the device are 101, then the

following 5 bits select the input channel for the following

conversion (see Tables 3 and 4). The next 5 bits select the

speed/resolution and mode 1X (no latency) 2X (double

output rate with one conversion latency), see Table 5. If

these 5 bits are set to all 0’s, the previous speed remains

selected for the next conversion. This is useful in appli-

cations requiring a fixed output rate/resolution but need

to change the input channel. In this case, the timing and

inputsequenceiscompatiblewiththeLTC2414/LTC2418.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 36), is used to test the

conversion status and to enable the data output transfer

as described in the previous sections.

When an update operation is initiated (the first 3 bits are

101) the first 5 bits are the channel address. The first

bit, SGL, determines if the input selection is differential

(SGL = 0) or single-ended (SGL = 1). For SGL = 0, two

adjacent channels can be selected to form a differential

input. For SGL = 1, one of 8 channels (LTC2444/LTC2445)

or one of 16 channels (LTC2448/LTC2449) is selected as

the positive input. The negative input is COM for all single

ended operations. The remaining 4 bits (ODD, A2, A1,

A0) determine which channel is selected. The LTC2448/

LTC2449 use all 4 bits to select one of 16 different input

channels (see Table 3) while in the case of the LTC2444/

LTC2445, A2 is always 0, and the remaining 3 bits select

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer

has been completed. The LTC2444/LTC2445/LTC2448/

LTC2449 will abort any serial data transfer in progress

and start a new conversion cycle anytime a LOW-to-HIGH

transition is detected at the CS pin after the converter has

entered the data output state.

Serial Data Input (SDI)

The serial data input (SDI, Pin 34) is used to select the

speed/resolution and input channel of the LTC2444/

LTC2445/LTC2448/LTC2449. SDI is programmed by a

one of 8 different input channels (see Table 4).

2444589fc

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Table 3. Channel Selection for the LTC2448/LTC2449

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL SIGN A2

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 COM

+

–

+

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

IN

+

IN

+

IN

+

IN

+

IN

–

+

IN

–

+

IN

–

+

IN

–

IN

–

IN

–

IN

–

IN

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

+

–

IN

*Default at power up

2444589fc

14

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Table 4. Channel Selection for the LTC2444/LTC2445 (Bit A2 Should Always Be 0)

MUX ADDRESS CHANNEL SELECTION

ODD/SIGN

SGL

0

A2

0

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

2

3

4

5

6

IN

7

IN

COM

+

–

+

0

1

0

1

IN

+

–

+

–

0

1

IN

+

–

+

–

IN

+

–

+

–

+

IN

+

IN

+

IN

–

IN

–

+

–

IN

+

–

IN

+

–

IN

+

–

1

IN

*Default at power up

Table 5. LTC2444/LTC2445/LTC2448/LTC2449 Speed/Resolution Selection

RMS NOISE RMS NOISE

OSR3 OSR2 OSR1 OSR0 TWOX LTC2444/LTC2448 LTC2445/LTC2449

ENOB

LTC2444/LTC2448 LTC2445/LTC2449

OSR

LATENCY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Keep Previous Speed/Resolution

23µV

4.4µV

2.8µV

2µV

23µV

3.5µV

2µV

17

64

none

20.1

21.3

21.8

22.4

22.9

23.4

24

128

20.8

256

1.4µV

1µV

21.3

512

1.4µV

1.1µV

720nV

530nV

350nV

280nV

21.8

1024

2048

4096

8192

16384

32768

750nV

510nV

375nV

250nV

200nV

22.1

22.7

23.2

23.8

24.4

24.6

24.1

Keep Previous Speed/Resolution

23µV

4.4µV

2.8µV

2µV

23µV

3.5µV

2µV

17

64

1 cycle

20.1

20.8

21.3

21.8

22.1

22.7

23.2

23.8

24.1

20.1

21.3

21.8

22.4

22.9

23.4

24

128

256

1.4µV

1µV

512

1.4µV

1.1µV

720nV

530nV

350nV

280nV

1024

2048

4096

8192

16384

32768

750nV

510nV

375nV

250nV

200nV

1 cycle

2444589fc

24.4

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15

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Speed Multiplier Mode

in cycle, the analog multiplexer output is switched. This

occurs at the end of the conversion cycle (just prior to

the data output cycle) for auto calibration. The time re-

quired to read the conversion enables more settling time

for the external buffer/amplifier. The offset/offset drift of

the external amplifier is automatically removed by the

converter’s auto calibration sequence for both the 1X and

2X speed modes.

In addition to selecting the speed/resolution, a speed

multiplier mode is used to double the output rate while

maintaining the selected resolution. The last bit of the

5-bit speed/resolution control word (TWOX, see Table 5)

determines if the output rate is 1X (no speed increase) or

2X (double the selected speed).

While operating in the 1X mode, the device combines two

internal conversions for each conversion result in order

to remove the ADC offset. Every conversion cycle, the

offset and offset drift are transparently calibrated greatly

simplifying the user interface. The resulting conversion

result has no latency. The first conversion following a

newly selected speed/resolution and input channel is

valid. This is identical to the operation of the LTC2440,

LTC2414 and LTC2418.

While operating in the 1X mode, if a new input channel

is selected the multiplexer is switched on the falling edge

of the 14th SCK (once the complete data input word is

programmed). The remaining data output sequence time

can be used to allow the external buffer/amplifier to settle.

BUSY

The BUSY output (Pin 2) is used to monitor the state of

conversion, data output and sleep cycle. While the part is

converting, the BUSY pin is HIGH. Once the conversion is

complete, BUSY goes LOW indicating the conversion is

complete and data out is ready. The part now enters the

LOW power sleep state. BUSY remains LOW while data is

shiftedoutofthedeviceandSDIisshiftedintothedevice.It

goes HIGH at the conclusion of the data input/output cycle

indicating a new conversion has begun. This rising edge

may be used to flag the completion of the data read cycle.

While operating in the 2X mode, the device performs a

running average of the last two conversion results. This

automatically removes the offset and drift of the device

while increasing the output rate by 2X. The resolution

(noise) remains the same. If a new channel is selected,

the conversion result is valid for all conversions after

the first conversion (one cycle latency). If a new speed/

resolution is selected, the first conversion result is valid

but the resolution (noise) is a function of the running av-

erage. All subsequent conversion results are valid. If the

mode is changed from either 1X to 2X or 2X to 1X without

changing the resolution or channel, the first conversion

result is valid.

Serial Interface Timing Modes

The LTC2444/LTC2445/LTC2448/LTC2449’s 3- or 4-wire

interfaceisSPIandMICROWIREcompatible.Thisinterface

offers several flexible modes of operation. These include

internal/external serial clock, 3- or 4-wire I/O, single cycle

conversion and autostart. The following sections describe

each of these serial interface timing modes in detail. In all

these cases, the converter can use the internal oscillator

If an external buffer/amplifier circuit is used for the

LTC2445/LTC2449, the 2X mode can be used to increase

the settling time of the amplifier between readings. While

operating in the 2X mode, the multiplexer output (input

to the external buffer/amplifier) is switched at the end of

each conversion cycle. Prior to concluding the data out/

(F = LOW) or an external oscillator connected to the F

O

pin. Refer to Table 6 for a summary.

Table 6. LTC2444/LTC2445/LTC2448/LTC2449 Interface Timing Modes

SCK

CONVERSION

CYCLE

DATA

CONNECTION

AND

OUTPUT

CONTROL

CONFIGURATION

SOURCE

External

Internal

CONTROL

WAVEFORMS

External SCK, Single Cycle Conversion

External SCK, 2-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 5, 6

Figure 7

Internal SCK, Single Cycle Conversion

Internal SCK, 2-Wire I/O, Continuous Conversion

Figures 8, 9

Figure 10

CS ↓

Continuous

Internal

2444589fc

16

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LTC2448/LTC2449

applicaTions inForMaTion

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

Independent of CS, the device automatically enters the

low power sleep state once the conversion is complete.

This timing mode uses an external serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

When the device is in the sleep state (EOC = 0), its con-

version result is held in an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK is seen. Data is shifted out the SDO pin on

each falling edge of SCK. This enables external circuitry

to latch the output on the rising edge of SCK. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result can be latched on the 32nd rising

edge of SCK. On the 32nd falling edge of SCK, the device

begins a new conversion. SDO goes HIGH (EOC = 1) and

BUSY goes HIGH indicating a conversion is in progress.

The serial clock mode is selected by the EXT pin. To select

the external serial clock mode, EXT must be tied low.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 (BUSY = 1) while a conversion is in progress

and EOC = 0 (BUSY = 0) if the device is in the sleep state.

4.5V TO 5.5V

1µF

28

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

35

V

F

O

CC

LTC2448

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

SPI INTERFACE

CH0

•

15

16

23

7

37

CH7

CH8

SDO

CS

36

ANALOG

INPUTS

•

2

CH15

COM

BUSY

GND

1,4,5,6,31,32,33,39

CS

TEST EOC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32

SCK

(EXTERNAL)

SDI

1

0

EN

SGL

ODD

A2

A1

A0

OSR3 OSR2 OSR1 OSR0 TWOX

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19

EOC “0” SIG MSB

BIT 0

LSB

Hi-Z

SDO

BUSY

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2444589 F05

Figure 5. External Serial Clock, Single Cycle Operation

2444589fc

17

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LTC2448/LTC2449

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At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z

and BUSY monitored for the completion of a conversion.

As described above, CS may be pulled LOW at any time

in order to monitor the conversion status on the SDO pin.

immediately initiates a new conversion. Thirteen serial

input data bits are required in order to properly program

the speed/resolution and input channel. If the data output

sequence is aborted prior to the 13th rising edge of SCK,

the new input data is ignored, and the previously selected

speed/resolutionandchannelareusedforthenextconver-

sion cycle. This is useful for systems not requiring all 32

bitsofoutputdata,abortinganinvalidconversioncycleor

synchronizing the start of a conversion. If a new channel

is being programmed, the rising edge of CS must come

after the 14th falling edge of SCK in order to store the

data input sequence.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pull-

ing CS HIGH anytime between the fifth falling edge and

the 32nd falling edge of SCK, see Figure 6. On the rising

edge of CS, the device aborts the data output state and

4.5V TO 5.5V

1µF

28

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

35

V

F

O

CC

LTC2448

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

15

16

23

7

37

CH7

CH8

SDO

CS

36

ANALOG

INPUTS

•

2

CH15

BUSY

GND

1,4,5,6,31,32,33,39

COM

CS

TEST EOC

1

5

1

2

3

4

5

6

SCK

(EXTERNAL)

SDI

DON'T CARE

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25

EOC “0” SIG MSB

Hi-Z

SDO

BUSY

SLEEP

DATA OUTPUT

CONVERSION

SLEEP

2444589 F06

Figure 6. External Serial Clock, Reduced Output Data Length

2444589fc

18

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LTC2444/LTC2445/

LTC2448/LTC2449

applicaTions inForMaTion

External Serial Clock, 2-Wire I/O

ler indicating the conversion result is ready. EOC = 1

(BUSY = 1) while the conversion is in progress and

EOC = 0 (BUSY = 0) once the conversion enters the low

power sleep state. On the falling edge of EOC/BUSY, the

conversion result is loaded into an internal static shift

register. The device remains in the sleep state until the

first rising edge of SCK. Data is shifted out the SDO pin

on each falling edge of SCK enabling external circuitry to

latch data on the rising edge of SCK. EOC can be latched

on the first rising edge of SCK. On the 32nd falling edge

of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a

new conversion has begun.

This timing mode utilizes a 2-wire serial I/O interface.

The conversion result is shifted out of the device by an

externally generated serial clock (SCK) signal, see Figure

7. CS may be permanently tied to ground, simplifying the

user interface or isolation barrier. The external serial clock

mode is selected by tying EXT LOW.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. Conversely, BUSY (Pin 2) may be used

to monitor the status of the conversion cycle. EOC or

BUSY may be used as an interrupt to an external control-

4.5V TO 5.5V

1µF

28

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

35

V

F

O

CC

LTC2448

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

15

16

23

7

37

CH7

SDO

CS

36

ANALOG

INPUTS

CH8

•

2

CH15

BUSY

GND

1,4,5,6,31,32,33,39

COM

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32

SCK

(EXTERNAL)

DON'T CARE

1

0

EN

SGL

ODD

A2

A1

A0

OSR3 OSR2 OSR1 OSR0 TWOX

DON'T CARE

BIT 0

SDI

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19

EOC “0” SIG MSB

LSB

SDO

BUSY

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2444589 F07

Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)

2444589fc

19

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LTC2448/LTC2449

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Internal Serial Clock, Single Cycle Operation

conversion and goes LOW at the conclusion. It remains

LOW until the result is read from the device.

This timing mode uses an internal serial clock to shift

out the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

When testing EOC, if the conversion is complete (EOC =

0), the device will exit the sleep state and enter the data

output state if CS remains LOW. In order to prevent the

device from exiting the low power sleep state, CS must

be pulled HIGH before the first rising edge of SCK. In the

internal SCK timing mode, SCK goes HIGH and the device

In order to select the internal serial clock timing mode,

the EXT pin must be tied HIGH.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state. Alterna-

tively, BUSY (Pin 2) may be used to monitor the status

of the conversion in progress. BUSY is HIGH during the

beginsoutputtingdataattimet

afterthefallingedge

EOCtest

of CS (if EOC = 0) or t

after EOC goes LOW (if CS is

EOCtest

LOW during the falling edge of EOC). The value of t

EOCt-

is 500ns. If CS is pulled HIGH before time t

, the

EOCtest

est

device remains in the sleep state. The conversion result

is held in the internal static shift register.

4.5V TO 5.5V

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

28

35

V

F

O

CC

LTC2448

1µF

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

15

16

23

7

37

CH7

SDO

CS

36

ANALOG

INPUTS

CH8

•

2

CH15

BUSY

GND

1,4,5,6,31,32,33,39

COM

<t

EOC(TEST)

CS

SCK

SDI

TEST EOC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

32

1

0

EN

SGL

ODD

A2

A1

A0

OSR3 OSR2 OSR1 OSR0 TWOX

DON'T CARE

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19

EOC “0” SIG MSB

BIT 0

LSB

Hi-Z

SDO

BUSY

SLEEP

DATA OUTPUT

CONVERSION

2444589 F08

Figure 8. Internal Serial Clock, Single Cycle Operation

2444589fc

20

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If CS remains LOW longer than t , the first rising

EOCtest

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. Thirteen

serial input data bits are required in order to properly pro-

gram the speed/resolution and input channel. If the data

output sequence is aborted prior to the 13th rising edge

of SCK, the new input data is ignored, and the previously

selectedspeed/resolutionandchannelareusedforthenext

conversion cycle. If a new channel is being programmed,

the rising edge of CS must come after the 14th falling

edge of SCK in order to store the data input sequence.

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins

on this first rising edge of SCK and concludes after the

32nd rising edge. Data is shifted out the SDO pin on each

falling edge of SCK. The internally generated serial clock

is output to the SCK pin. This signal may be used to shift

the conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result on the 32nd rising edge of SCK.

After the 32nd rising edge, SDO goes HIGH (EOC = 1),

SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

4.5V TO 5.5V

1µF

28

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

35

V

F

O

CC

LTC2448

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

SPI INTERFACE

CH0

•

15

16

23

7

37

CH7

CH8

SDO

CS

36

ANALOG

INPUTS

•

2

CH15

BUSY

GND

1,4,5,6,31,32,33,39

COM

<t

1

<t

EOC(TEST)

CS

TEST EOC

5

1

2

3

4

5

6

SCK

SDI

DON'T CARE

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25

EOC “0” SIG MSB

DON'T CARE

Hi-Z

SDO

BUSY

SLEEP

DATA OUTPUT

CONVERSION

SLEEP

2444589 F09

Figure 9. Internal Serial Clock, Reduced Data Output Length

2444589fc

21

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LTC2448/LTC2449

applicaTions inForMaTion

Internal Serial Clock, 2-Wire I/O, Continuous

Conversion

has entered the low power sleep state. The part remains in

the sleep state a minimum amount of time (≈500ns) then

immediately begins outputting data. The data output cycle

begins on the first rising edge of SCK and ends after the

32nd rising edge. Data is shifted out the SDO pin on each

falling edge of SCK. The internally generated serial clock

is output to the SCK pin. This signal may be used to shift

the conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result can be latched on the 32nd rising

edge of SCK. After the 32nd rising edge, SDO goes HIGH

(EOC = 1) indicating a new conversion is in progress. SCK

remains HIGH during the conversion.

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. Theconversionresultisshiftedoutofthedevice

by an internally generated serial clock (SCK) signal, see

Figure 10. CS may be permanently tied to ground, sim-

plifying the user interface or isolation barrier. The internal

serial clock mode is selected by tying EXT HIGH.

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the

conversioniscomplete,SCK,BUSYandSDOgoLOW(EOC

= 0) indicating the conversion has finished and the device

4.5V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

28

35

V

F

O

CC

LTC2448

29

30

8

34

38

+

–

REFERENCE

VOLTAGE

REF

SDI

SCK

0.1V TO V

CC

4-WIRE

CH0

•

SPI INTERFACE

15

16

23

7

37

CH7

SDO

CS

36

ANALOG

INPUTS

CH8

•

2

CH15

BUSY

GND

1,4,5,6,31,32,33,39

COM

CS

1

2

0

3

4

5

6

7

8

9

10

11

12

13

14

32

SCK

DON'T CARE

EN

SGL

ODD

A2

A1

A0

OSR3 OSR2 OSR1 OSR0 TWOX

DON'T CARE

BIT 0

SDI

BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19

LSB

EOC

“0”

SIG

MSB

SDO

BUSY

DATA OUTPUT

CONVERSION

2444589 F10

SLEEP

Figure 10. Internal Serial Clock, Continuous Operation

2444589fc

22

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LTC2448/LTC2449

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Normal Mode Rejection and Antialiasing

Table 7. OSR vs Notch Frequency (f_N) (with Internal Oscillator

Running at 9MHz)

One of the advantages delta-sigma ADCs offer over

conventional ADCs is on-chip digital filtering. Combined

with a large oversampling ratio, the LTC2444/LTC2445/

LTC2448/LTC2449 significantly simplify antialiasing filter

requirements.

OSR

NOTCH (f )

N

64

28.16kHz

14.08kHz

7.04kHz

3.52kHz

1.76kHz

880Hz

128

256

512

The LTC2444/LTC2445/LTC2448/LTC2449’s speed/

resolution is determined by the over sample ratio (OSR)

of the on-chip digital filter. The OSR ranges from 64 for

3.5kHz output rate to 32,768 for 6.9Hz (in No Latency

mode) output rate. The value of OSR and the sample rate

1024

2048

4096

440Hz

8192

16384

220Hz

110Hz

f determinethefiltercharacteristicsofthedevice.Thefirst

S

32768*

55Hz

NULL of the digital filter is at f and multiples of f where

N

*Simultaneous 50/60Hz rejection

f = f /OSR, see Figure 11 and Table 7. The rejection at

N

S

the frequency f 14% is better than 80dB, see Figure 12.

N

–80

–90

If F is grounded, f is set by the on-chip oscillator at

O

S

1.8MHz (over supply and temperature variations). At an

OSR of 32,768, the first NULL is at f = 55Hz and the

N

no latency output rate is f /8 = 6.9Hz. At the maximum

–100

–110

–120

–130

N

OSR, the noise performance of the device is 280nV

RMS

(LTC2444/LTC2448)and200nV

(LTC2445/LTC2449)

RMS

0

4

SINC ENVELOPE

–20

–40

–140

57 59

47 49 51 53 55

61 63

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2440 F12

–60

–80

Figure 12. LTC2444/LTC2445/LTC2448/LTC2449 Normal

Mode Rejection (Internal Oscillator)

–100

–120

–140

60

120

240

0

180

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2444589 F11

Figure 11. LTC2444/LTC2445/LTC2448/LTC2449 Normal

Mode Rejection (Internal Oscillator)

2444589fc

23

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LTC2444/LTC2445/

LTC2448/LTC2449

applicaTions inForMaTion

withbetterthan80dBrejectionof50Hz 2%and60Hz 2%.

Since the OSR is large (32,768) the wide band rejection

is extremely large and the antialiasing requirements are

clock applied to F results in a NULL at 0.6Hz plus all

O

harmonics up to 20kHz, see Figure 14. This is useful in

applications requiring digitalization of the DC component

of a noisy input signal and eliminates the need of placing

a 0.6Hz filter in front of the ADC.

simple. The first multiple of f occurs at 55Hz • 32,768 =

S

1.8MHz, see Figure 13.

The first NULL becomes f = 7.04kHz with an OSR of 256

Anexternaloscillatoroperatingfrom100kHzto12MHzcan

be implemented using the LTC1799 (resistor set SOT-23

oscillator), see Figure 17. By floating pin 4 (DIV) of the

LTC1799, the output oscillator frequency is:

N

(anoutputrateof880Hz)andF grounded.WhiletheNULL

O

has shifted, the sample rate remains constant. As a result

of constant modulator sampling rate, the linearity, offset

and full-scale performance remains unchanged as does





10k

10•R_SET



the first multiple of f .

f_OSC= 10MHz •

S





The sample rate f and NULL f , may also be adjusted by

S

N

driving the F pin with an external oscillator. The sample

The normal mode rejection characteristic shown in

Figure13isachievedbyapplyingtheoutputoftheLTC1799

(withR =100k)totheF pinontheLTC2444/LTC2445/

O

EOSC

rate is f = f

/5, where f

O

is the frequency of the

EOSC

S

clock applied to F . Combining a large OSR with a reduced

SET

O

sample rate leads to notch frequencies f near DC while

LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).

N

maintaining simple antialiasing requirements. A 100kHz

0

–20

–40

0

–20

–40

–60

1.8MHz

–80

–100

–120

–140

REJECTION > 120dB

–120

–140

1000000

2000000

0

2

4

6

10

0

8

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2444589 F13

2444589 F14

Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal

Mode Rejection (Internal Oscillator)

Figure 14. LTC2444/LTC2445/LTC2448/LTC2449 Normal

Mode Rejection (External Oscillator at 90kHz)

2444589fc

24

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Reduced Power Operation

Input Bandwidth and Frequency Rejection

4

In addition to adjusting the speed/resolution of the

LTC2444/LTC2445/LTC2448/LTC2449, the speed/reso-

lution/power dissipation may also be adjusted using the

automatic sleep mode. During the conversion cycle, the

LTC2444/LTC2445/LTC2448/LTC2449 draw 8mA supply

current independent of the programmed speed. Once the

conversion cycle is completed, the device automatically

enters a low power sleep state drawing 8µA. The device

remains in this state as long as CS is HIGH and data is not

shifted out. By adjusting the duration of the sleep state

(hold CS HIGH longer) and the duration of the conversion

cycle (programming OSR) the DC power dissipation can

be reduced, see Figure 15.

The combined effect of the internal SINC digital filter and

the digital and analog autocalibration circuits determines

theLTC2444/LTC2445/LTC2448/LTC2449inputbandwidth

V

CC

I

+

REF

R

(TYP)

SW

I

LEAK

500Ω

V

+

REF

LEAK

V

CC

I

+

IN

R

(TYP)

I

SW

LEAK

C

EQ

500Ω

5pF

V

+

IN

(TYP)

LEAK

MUX

(C = 2pF

EQ

SAMPLE CAP

V

CC

+ PARASITICS)

I

–

IN

R

(TYP)

500Ω

I

SW

LEAK

V

I

LEAK

Average Input Current

MUX

V

CC

The LTC2444/LTC2448 switch the input and reference to

a 2pF capacitor at a frequency of 1.8MHz. A simplified

equivalent circuit is shown in Figure 16. The sample ca-

pacitor for the LTC2445/LTC2449 is 4pF, and its average

input current is externally buffered from the input source.

I

–

REF

R

(TYP)

SW

I

LEAK

500Ω

2444589 F16

V

REF

LEAK

SWITCHING FREQUENCY

f

= 1.8MHz INTERNAL OSCILLATOR

SW

= f

/5 EXTERNAL OSCILLATOR

EOSC

Theaverageinputandreferencecurrentscanbeexpressed

in terms of the equivalent input resistance of the sample

Figure 16. LTC2444/LTC2448 Input Structure

capacitor, where: Req = 1/(f • Ceq)

SW

When using the internal oscillator, f is 1.8MHz and the

SW

equivalent resistance is approximately 110kΩ.

CONVERTER

SLEEP

CONVERT

SLEEP

CONVERT

SLEEP

STATE

DATA

OUT

DATA

OUT

CS

SUPPLY

CURRENT

8µA

8mA

8µA

8mA

8µA

2444589 F15

Figure 15. Reduced Power Timing Mode

2444589fc

25

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

applicaTions inForMaTion

4.5V TO 5.5V

1µF

28

2

V

BUSY

CC

LTC2448

REF

LTC1799

OUT

R

SET

29

30

8

35

38

37

36

+

REFERENCE

VOLTAGE

f

O

V

–

0.1µF

REF

SCK

SDO

CS

0.1V TO V

CC

3-WIRE

ANALOG INPUT

CH0

GND

SET

SPI INTERFACE

–0.5V

TO

REF

9

CH1

0.5V

•

1,4,5,6,31,32,33,39

3

EXT

GND

DIV

NC

2444589 F17

Figure 17. Simple External Clock Source

and rejection characteristics. The digital filter’s response

can be adjusted by setting the oversample ratio (OSR)

through the SPI interface or by supplying an external

Maximum Conversion Rate

The maximum conversion rate is the fastest possible rate

at which conversions can be performed.

conversion clock to the F pin.

O

First Notch Frequency

Table 8 lists the properties of the LTC2444/LTC2445/

LTC2448/LTC2449 with various combinations of overs-

ample ratio and clock frequency. Understanding these

propertiesisthekeytofinetuningthecharacteristicsofthe

LTC2444/LTC2445/LTC2448/LTC2449 to the application.

4

ThisisthefirstnotchintheSINC portionofthedigitalfilter

anddependsontheF clockfrequencyandtheoversample

O

ratio. Rejection at this frequency and its multiples (up to

the modulator sample rate of 1.8MHz) exceeds 120dB.

This is 8 times the maximum conversion rate.

Table 8. Performance vs Oversample Ratio

ENOB

REF

MAXIMUM CONVERSION

RATE (sps)

FIRST NOTCH

EFFECTIVE

–3dB POINT (Hz)

(V = 5V)

FREQUENCY (Hz)

NOISE BW (Hz)

OVER-

*RMS

NOISE

SAMPLE NOISE

External f External f

Internal

O

RATIO LTC2444/ LTC2445/ LTC2444 LTC2445/ Internal (1X Mode) (2X Mode) Internal External f 9MHz External f Internal External f

O

(OSR) LTC2448 LTC2449 LTC2449 LTC2449 Clock

O

[f /x]

O

[f /x]

O

Clock

[f /x]

O

Clock

3148

1574

787

[f /x]

Clock

1696

848

424

212

106

53

[f /x]

O

64

23µV

4.5µV

2.8µV

2µV

23µV

3.5µV

2µV

17

2816.35 f /2738

f /1458

o

28125

f /320

o

f /2860

o

f /5310

o

ø

128

20.1

20.8

21.3

21.8

22.1

22.7

23.2

23.8

24.1

20

1455.49 f /5298

f /2738 14062.5 f /640

o

f /5720

o

f /10600

o

256

21.3

21.8

22.4

22.9

23.4

24

740.18 f /10418

f /5298 7031.3 f /1280

o

f /11440

o

f /21200

o

512

1.4µV

1µV

373.28 f /20658 f /10418 3515.6 f /2560

394

f /22840

o

f /42500

o

1024

2048

4096

8192

16384

32768

1.4µV

1.1µV

720nV

530nV

350nV

280nV

187.45 f /41138 f /20658 1757.8 f /5120

197

f /45690

o

f /84900

o

750nV

510nV

375nV

250nV

200nV

93.93

f /82098 f /41138 878.9 f /10200

98.4

49.2

24.6

12.4

6.2

f /91460

f /170000

o

47.01 f /164018 f /82098 439.5 f /20500

f /183000

o

26.5

13.2

6.6

f /340000

o

23.52 f /327858 f /164018 219.7 f /41000

f /366000

o

f /679000

o

24.4

24.6

11.76 f /655538 f /327858 109.9 f /81900

f /731000

o

f /1358000

o

5.88 f /1310898 f /655538 54.9 f /163800

f /1463000

o

3.3

f /2717000

o

*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64

include effects from internal modulator quantization noise.

2444589fc

26

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

applicaTions inForMaTion

Effective Noise Bandwidth

In this way, the digital filter with its variable oversampling

ratiocangreatlyreducetheeffectsofexternalnoisesources.

TheLTC2444/LTC2445/LTC2448/LTC2449hasextremely

good input noise rejection from the first notch frequency

all the way out to the modulator sample rate (typically

1.8MHz). Effective noise bandwidth is a measure of how

the ADC will reject wideband input noise up to the modu-

lator sample rate. The example on the following page

shows how the noise rejection of the LTC2444/LTC2445/

LTC2448/LTC2449reducestheeffectivenoiseofanampli-

fier driving its input.

Automatic Offset Calibration of External

Buffers/Amplifiers

The LTC2445/LTC2449 enable an external amplifier to

be inserted between the multiplexer output and the ADC

input. This enables one external buffer/amplifier circuit to

be shared between all 17 analog inputs (16 single-ended

or 8 differential). The LTC2445/LTC2449 perform an

internal offset calibration every conversion cycle in order

to remove the offset and drift of the ADC. This calibration

is performed through a combination of front end switch-

ing and digital processing. Since the external amplifier is

placed between the multiplexer and the ADC, it is inside

the correction loop. This results in automatic offset cor-

rection and offset drift removal of the external amplifier.

Example: If an amplifier (e.g. LT1219) driving the input of

an LTC2444/LTC2445/LTC2448/LTC2449 has wideband

noiseof33nV/√Hz,band-limitedto1.8MHz,thetotalnoise

entering the ADC input is:

33nV/√Hz • √1.8MHz = 44.3µV.

When the ADC digitizes the input, its digital filter filters

out the wideband noise from the input signal. The noise

reduction depends on the oversample ratio which defines

the effective bandwidth of the digital filter.

The LT1368 is an excellent amplifier for this function. It

has rail-to-rail inputs and outputs, and it operates on a

single 5V supply. Its open-loop gain is 1M and its input

bias current is 10nA. It also requires at least a 0.1µF load

capacitor for compensation. It is this feature that sets it

apartfromotheramplifiers—theloadcapacitorattenuates

sampling glitches from the LTC2445/LTC2449 ADCIN

terminals, allowing it to achieve full performance of the

ADC with high impedance at the multiplexer inputs.

At an oversample of 256, the noise bandwidth of the ADC

is 787Hz which reduces the total amplifier noise to:

33nV/√Hz • √787Hz = 0.93µV.

The total noise is the RMS sum of this noise with the 2µV

noise of the ADC at OSR=256.

2

√(0.93µV) + (2µV) = 2.2µV.

Another benefit of the LT1368 is that it can be powered

from supplies equal to or greater than that of the ADC.

This can allow the inputs to span the entire absolute

Increasing the oversample ratio to 32768 reduces the

noise bandwidth of the ADC to 6.2Hz which reduces the

total amplifier noise to:

maximum of GND – 0.3V to V + 0.3V. Using a positive

CC

supply of 7.5V to 10V and a negative supply of –2.5 to –5V

gives the amplifier plenty of headroom over the LTC2445/

LTC2449 input range.

33nV/√Hz • √6.2Hz = 82nV.

The total noise is the RMS sum of this noise with the

200nV noise of the ADC at OSR = 32768.

2

√(82nV) + (200nV) = 216nV.

2444589fc

27

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

package DescripTion

Please refer to http://www.linear.com/product/LTC2444#packaging for the most recent package drawings.

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)

0.70 0.05

5.50 0.05

5.ꢀ5 0.05

4.ꢀ0 0.05

3.ꢀ5 0.05

3.00 REF

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

5.5 REF

6.ꢀ0 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 0.05

0.00 – 0.05

3.00 REF

5.00 0.ꢀ0

37

38

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

ꢀ

2

(SEE NOTE 6)

5.ꢀ5 0.ꢀ0

5.50 REF

7.00 0.ꢀ0

3.ꢀ5 0.ꢀ0

(UH) QFN REF C ꢀꢀ07

0.200 REF 0.25 0.05

0.50 BSC

R = 0.ꢀ25

TYP

R = 0.ꢀ0

TYP

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

2444589fc

28

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

revision hisTory ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

01/17 Updated Max values for f

5

EOSC

CONV

Updated formula for t

Updated Note 13

5

Inserted Figure 4, Input Range

11

26

Revised Table 8, Performance vs Oversample Ratio

2444589fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

For more information www.linear.com/LTC2444

LTC2444/LTC2445/

LTC2448/LTC2449

Typical applicaTion

External Buffers Provide High Impedance Inputs and Amplifier Offsets are Cancelled

SDI

SCK

SDO

CS

LTC2449

CH0-CH15/

COM

HIGH

SPEED

∆∑ ADC

17

MUX

2444589 TA02

2

3

–

1

1/2 LT1368

0.1µF

+

(EXTERNAL AMPLIFIERS)

5V

6

8

–

7

1/2 LT1368

5

0.1µF

+

4

0V

relaTeD parTs

PART NUMBER

LT^®1025

DESCRIPTION

Micropower Thermocouple Cold Junction Compensator

COMMENTS

80µA Supply Current, 0.5°C Initial Accuracy

LTC1043

Dual Precision Instrumentation Switched Capacitor Building Precise Charge, Balanced Switching, Low Power

Block

LTC1050

LT1236A-5

LT1461

Precision Chopper Stabilized Op Amp

Precision Bandgap Reference, 5V

No External Components 5µV Offset, 1.6µV Noise

P-P

0.05% Max, 5ppm/°C Drift

Micropower Series Reference, 2.5V

0.04% Max, 3ppm/°C Max Drift

Six Programmable Output Ranges

1LSB DNL, 600µA, Internal Reference, SO-8

Single Resistor Frequency Set

LTC1592

LTC1655

LTC1799

LTC2053

LTC2412

LTC2415

Ultraprecise 16-Bit SoftSpan™ DAC

16-Bit Rail-to-Rail Micropower DAC

Resistor Set SOT-23 Oscillator

Rail-to-Rail Instrumentation Amplifier

2-Channel, Differential Input, 24-Bit, No Latency ∆∑ ADC

1-Channel, Differential Input, 24-Bit, No Latency ∆∑ ADC

10µV Offset with 50nV/°C Drift, 2.5µV Noise 0.01Hz to 10Hz

P-P

0.16ppm Noise, 2ppm INL, 200µA

0.23ppm Noise, 2ppm INL, 2X Speed Mode

0.2ppm Noise, 2ppm INL, 200µA

0.56ppm Noise, 3ppm INL, 200µA

LTC2414/LTC2418 4-/8-Channel, Differential Input, 24-Bit, No Latency ∆∑ ADC

LTC2430/LTC2431 1-Channel, Differential Input, 20-Bit, No Latency ∆∑ ADC

LTC2436-1

LTC2440

2-Channel, Differential Input, 16-Bit, No Latency ∆∑ ADC

800nV

Noise, 0.12LBS INL, 0.006LBS Offset, 200µA

RMS

1-Channel, Differential Input, High Speed/Low Noise, 24-Bit, 2µV

No Latency ∆∑ ADC

Noise at 880Hz, 200nV

Noise at 6.9Hz,

RMS

0.005% INL, Up to 3.5kHz Output Rate

2444589fc

LT 0117 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

For more information www.linear.com/LTC2444

●

 LINEAR TECHNOLOGY CORPORATION 2004

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2444


型号：	LTC2444CUHF#TRPBF
厂家：	Linear
描述：	LTC2444 - 24-Bit High Speed 8-/16-Channel Delta Sigma ADCs with Selectable Speed/Resolution; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C 转换器
文件：	总30页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2444CUHF#TRPBF [Linear]

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