LTC2481HDD#TRPBF [Linear]
LTC2481 - 16-Bit Delta Sigma ADC with Easy Drive Input Current Cancellation and I<sup>2</sup>C Interface; Package: DFN; Pins: 10; Temperature Range: -40°C to 125°C;
| 型号： | LTC2481HDD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC2481 - 16-Bit Delta Sigma ADC with Easy Drive Input Current Cancellation and I<sup>2</sup>C Interface; Package: DFN; Pins: 10; Temperature Range: -40°C to 125°C |
| 文件： | 总40页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2481
16-Bit ∆Σ ADC with Easy Drive
Input Current Cancellation and I2C Interface
U
FEATURES
DESCRIPTIO
TheLTC®2481combinesa16-bitplussignNoLatency∆ΣTM
analog-to-digitalconverterwithpatentedEasyDriveTM tech-
nology and I2C digital interface. The patented sampling
scheme eliminates dynamic input current errors and the
shortcomings of on-chip buffering through automatic
cancellation of differential input current. This allows large
externalsourceimpedancesandinputsignals,withrail-to-
rail input range to be directly digitized while maintaining
exceptional DC accuracy.
■
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
Programmable Gain from 1 to 256
Integrated Temperature Sensor
GND to VCC Input/Reference Common Mode Range
2-Wire I2C Interface
■
■
■
■
■
■
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
The LTC2481 includes on-chip programmable gain, a
temperaturesensorandanoscillator.TheLTC2481canbe
configured through an I2C interface to provide a program-
mable gain from 1 to 256 in 8 steps, to digitize an external
signal or internal temperature sensor, reject line frequen-
cies (50Hz, 60Hz or simultaneous 50Hz/60Hz) as well as
a 2x speed-up mode.
■
■
■
■
■
■
■
2ppm (0.25LSB) INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
Selectable 2x Speed Mode
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Six Addresses Available and One Global Address for
Synchronization
Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package
The LTC2481 allows a wide common mode input range
(0V to VCC) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to VCC. The LTC2481 includes an on-chip trimmed oscil-
lator eliminating the need for external crystals or oscilla-
tors. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
■
U
APPLICATIO S
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Patent Pending.
■
Strain Gauge Transducers
■
Instrumentation
■
Industrial Process Control
■
DVMs and Meters
U
+
–
TYPICAL APPLICATIO
+FS Error vs R
at IN and IN
SOURCE
80
V
CC
V
V
V
V
= 5V
CC
= 5V
REF
60
40
20
+
= 3.75V
= 1.25V
IN
–
1µF
IN
F
= GND
O
T
A
= 25°C
SCL
SDA
+
10k
10k
2-WIRE
I C INTERFACE
I
= 0
REF
LTC2481
GND
V
C
IN
= 1µF
DIFF
CC
+
2
V
0
IN
–20
1µF
SENSE
CA0/F
0
6 ADDRESSES
–
–40
–60
–80
V
IN
CA1
2481 TA01
–
REF
1
10
100
10k
100k
1k
(Ω)
2481 TA04
R
SOURCE
2481f
1
LTC2481
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC) to GND...................... –0.3V to 6V
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
+
REF
10 CA0/F
0
1
2
3
4
5
V
9
8
7
6
CA1
GND
SDA
SCL
CC
–
11
REF
IN
+
–
IN
LTC2481C................................................... 0°C to 70°C
LTC2481I ................................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 125°C
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/ W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
DD PART MARKING*
LBPV
ORDER PART NUMBER
LTC2481CDD
LTC2481IDD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U W
ELECTRICAL CHARACTERISTICS ( OR AL SPEED)
The
●
denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
●
●
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V
= 5V, V
= 2.5V (Note 6)
2
1
10
ppm of V
ppm of V
CC
REF
IN(CM)
REF
REF
µV
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 13)
●
●
0.5
10
2.5
REF
CC
CC
CC
+
–
Offset Error Drift
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
nV/°C
ppm of V
REF
REF
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
25
REF
CC
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
–
+
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
●
ppm of V
REF
REF
CC
REF
REF
–
+
Negative Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
Total Unadjusted Error
5V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
= 2.5V (Note 6)
15
15
15
ppm of V
ppm of V
ppm of V
CC
REF
REF
IN(CM)
REF
REF
REF
5V ≤ V ≤ 5.5V, V
= 5V, V
CC
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 12)
0.6
420
1.4
µV
RMS
CC
REF
CC
Internal PTAT Signal
T = 27°C
A
mV
Internal PTAT Temperature Coefficient
Programmable Gain
mV/°C
See Table 2a
●
1
256
2481f
2
LTC2481
ELECTRICAL CHARACTERISTICS (2x SPEED)
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
●
●
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V
= 5V, V
= 2.5V (Note 6)
2
1
10
2
ppm of V
REF
CC
REF
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 13)
●
●
0.5
mV
REF
CC
CC
CC
+
–
Offset Error Drift
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
100
nV/°C
ppm of V
REF
REF
CC
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
25
REF
CC
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
–
+
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
●
●
ppm of V
REF
REF
CC
REF
REF
–
+
Negative Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
CC
REF
REF
V
/°C
REF
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V
0.84
µV
RMS
CC
REF
CC
Programmable Gain
See Table 2b
1
128
U
CO VERTER CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4)
A
PARAMETER
CONDITIONS
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
MIN
140
140
TYP
MAX
UNITS
dB
–
+
Input Common Mode Rejection DC
●
●
REF
CC
CC
–
+
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
dB
REF
CC
CC
–
+
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
●
●
●
●
●
140
110
110
87
dB
dB
dB
dB
dB
REF
CC
CC
–
+
Input Normal Mode Rejection
50Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 7)
120
120
REF
CC
CC
–
+
Input Normal Mode Rejection
60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 8)
REF CC CC
–
+
Input Normal Mode Rejection
50Hz/60Hz ±2%
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 9)
REF CC CC
–
+
Reference Common Mode
Rejection DC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
120
140
REF
CC
CC
–
+
Power Supply Rejection DC
V
V
V
= 2.5V, IN = IN = GND
120
120
120
dB
dB
dB
REF
REF
REF
–
+
Power Supply Rejection, 50Hz ±2%
Power Supply Rejection, 60Hz ±2%
= 2.5V, IN = IN = GND (Notes 7, 9)
–
+
= 2.5V, IN = IN = GND (Notes 8, 9)
U
U
U
U
A ALOG I PUT A D REFERE CE The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
+
–
FS
Full Scale of the Differential Input (IN – IN )
Least Significant Bit of the Output Code
●
●
●
●
0.5V /GAIN
REF
16
LSB
FS/2
+
–
V
V
Input Differential Voltage Range (IN – IN )
–FS
0.1
+FS
V
IN
+
–
Reference Voltage Range (REF – REF )
V
V
REF
CC
2481f
3
LTC2481
U
U
U
U
A ALOG I PUT A D REFERE CE The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
11
11
11
1
MAX
UNITS
pF
+
+
C (IN )
IN Sampling Capacitance
S
–
–
C (IN )
IN Sampling Capacitance
pF
S
C (V
)
V
Sampling Capacitance
pF
S
REF
DC_LEAK
DC_LEAK
REF
+
+
+
I
I
I
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
●
●
●
–10
–10
10
10
nA
–
–
–
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
1
nA
+
–
(V
)
REF , REF DC Leakage Current
Sleep Mode, V
= V
CC
–100
1
100
nA
DC_LEAK REF
REF
U
U
2
I C DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
0.7V
TYP
MAX
UNITS
V
V
V
V
High Level Input Voltage
●
●
●
●
●
V
V
IH
CC
Low Level Input Voltage
0.3V
CC
IL
Low Level Input Voltage for Address Pin
High Level Input Voltage for Address Pins
0.05V
V
IL(CA1)
CC
0.95V
V
IH(CA0/F0,CA1)
CC
R
INH
R
INL
R
INF
Resistance from CA0/F , CA1 to V to Set
Chip Address Bit to 1
10
10
kΩ
0
CC
Resistance from CA1 to GND to Set
Chip Address Bit to 0
●
●
●
kΩ
Resistance from CA0/F , CA1 to V or
GND to Set Chip Address Bit to Float
2
MΩ
0
CC
I
Digital Input Current
–10
10
µA
V
I
V
V
Hysteresis of Schmitt Trigger Inputs
Low Level Output Voltage SDA
(Note 5)
I = 3mA
0.05V
HYS
OL
CC
●
●
●
●
●
●
●
0.4
250
50
1
V
t
t
I
Output Fall Time from V
to V
Bus Load C 10pF to 400pF (Note 14)
20+0.1C
10
ns
ns
µA
pF
pF
pF
OF
IHMIN
ILMAX
B
B
Input Spike Suppression
Input Leakage
SP
IN
0.1V ≤ V ≤ V
CC
CC
IN
C
C
C
Capacitance for Each I/O Pin
I
Capacitance Load for Each Bus Line
External Capacitive Load on Chip
400
10
B
CAX
Address Pins (CA0/F ,CA1) for Valid Float
0
V
V
High Level CA0/F External Oscillator
2.7V ≤ V < 5.5V
●
●
V – 0.5V
CC
V
V
IH(EXT,OSC)
IL(EXT,OSC)
0
CC
Low Level CA0/F External Oscillator
2.7V ≤ V < 5.5V
0.5
0
CC
W U
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
Conversion Mode (Note 11)
Sleep Mode (Note 11)
●
●
160
1
250
2
µA
µA
CC
2481f
4
LTC2481
W U
TI I G CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 3)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
10
TYP
MAX
4000
100
UNITS
kHz
µs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
●
●
●
EOSC
HEO
0.125
0.125
100
µs
LEO
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
●
●
●
157.2
131.0
144.1
160.3
133.6
146.9
163.5
136.3
149.9
ms
ms
ms
ms
CONV_1
41036/f
EOSC
t
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
●
●
●
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
ms
ms
ms
ms
CONV_2
20556/f
EOSC
W U
2
I C TI I G CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Notes 3, 15)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
f
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
●
●
●
●
●
●
●
●
●
●
400
SCL
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock Pin
HIGH Period of the SCL Clock Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
0.6
HD(SDA)
LOW
1.3
µs
0.6
µs
HIGH
0.6
µs
SU(STA)
HD(DAT)
SU(DAT)
r
0
0.9
µs
Data Set-Up Time
100
20+0.1C
20+0.1C
0.6
ns
Rise Time for Both SDA and SCL Signals
Fall Time for Both SDA and SCL Signals
Set-Up Time for STOP Condition
(Note 14)
(Note 14)
300
300
ns
B
B
ns
f
µs
SU(STO)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 8: 60Hz mode (internal oscillator) or f
oscillator).
= 307.2kHz ±2% (external
EOSC
Note 2: All voltage values are with respect to GND.
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f
=
EOSC
280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/F pin. The
Note 3: V = 2.7V to 5.5V unless otherwise specified.
CC
+
–
+
–
0
V
V
= REF – REF , V
= (REF + REF )/2, FS = 0.5V /GAIN;
= (IN + IN )/2.
REF
REFCM
REF
+
–
+
–
external oscillator frequency, f
, is expressed in kHz.
EOSC
= IN – IN , V
IN
INCM
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
Note 4: Use internal conversion clock or external conversion clock source
with f = 307.2kHz unless otherwise specified.
EOSC
calibration operations.
Note 5: Guaranteed by design, not subject to test.
Note 13: Guaranteed by design and test correlation.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 14: C = capacitance of one bus line in pF.
B
Note 15: All values refer to V
and V
levels.
IH(MIN)
IL(MAX)
Note 7: 50Hz mode (internal oscillator) or f
oscillator).
= 256kHz ±2% (external
EOSC
2481f
5
LTC2481
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
CC
(V = 5V, V
= 5V)
(V = 5V, V
= 2.5V)
(V = 2.7V, V = 2.5V)
REF
CC
REF
CC
REF
3
2
3
2
3
2
V
V
V
= 5V
V
V
V
= 2.7V
= 2.5V
IN(CM)
V
V
V
= 5V
= 5V
IN(CM)
CC
CC
REF
CC
REF
= 2.5V
REF
= 1.25V
= 1.25V
= 2.5V
IN(CM)
1
0
1
0
1
0
–45°C
85°C
25°C
–45°C, 25°C, 90°C
–45°C, 25°C, 90°C
–1
–2
–3
–1
–2
–3
–1
–2
–3
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G03
2481 G02
2481 G01
Total Unadjusted Error
(V = 2.7V, V = 2.5V)
Total Unadjusted Error
Total Unadjusted Error
(V = 5V, V
= 2.5V)
(V = 5V, V
= 5V)
CC
REF
CC
REF
CC
REF
12
8
12
8
12
8
V
V
V
= 5V
V
V
V
= 5V
V
V
V
= 2.7V
CC
CC
CC
= 5V
= 2.5V
= 2.5V
REF
REF
85°C
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
IN(CM)
IN(CM)
85°C
85°C
25°C
25°C
25°C
4
0
4
0
4
0
–45°C
–45°C
–45°C
–4
–8
–4
–8
–4
–8
–12
–12
–12
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G04
2481 G05
2481 G06
Noise Histogram (6.8sps)
Noise Histogram (7.5sps)
Long-Term ADC Readings
14
12
5
4
14
12
V
= 5V, V
= 5V, V = 0V, V
= 2.5V
IN(CM)
10,000 CONSECUTIVE
READINGS
CC
REF
IN
10,000 CONSECUTIVE
READINGS
GAIN = 256, T = 25°C, RMS NOISE = 0.60µV
A
RMS = 0.59µV
AVERAGE = –0.19µV
RMS = 0.60µV
AVERAGE = –0.69µV
V
V
V
= 2.7V
= 2.5V
V
V
V
= 5V
= 5V
CC
REF
IN
CC
REF
IN
3
= 0V
10
8
= 0V
2
10
8
GAIN = 256
= 25°C
GAIN = 256
= 25°C
1
T
A
T
A
0
6
6
–1
–2
–3
–4
–5
4
4
2
2
0
0
–1.8 –1.2 –0.6
0
1.8
–3 –2.4
0.6 1.2
0
10
30
40
50
60
20
–1.8 –1.2 –0.6
0
1.8
–3 –2.4
0.6 1.2
TIME (HOURS)
OUTPUT READING (µV)
OUTPUT READING (µV)
2481 G08
2481 G09
2481 G07
2481f
6
LTC2481
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
RMS Noise vs V
RMS Noise vs Temperature (T )
A
IN(CM)
1.0
0.9
0.8
0.7
1.0
0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V
V
V
V
= 5V
= 5V
V
V
V
T
= 5V
= 5V
IN(CM)
= 25°C
V
V
V
V
= 5V
= 5V
CC
REF
IN
CC
REF
CC
REF
IN
= 0V
= 2.5V
= 0V
= GND
= GND
IN(CM)
A
IN(CM)
GAIN = 256
GAIN = 256
0.8
0.7
T
A
= 25°C
0.6
0.5
0.4
0.6
0.5
0.4
3
5
6
–1
0
1
2
4
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–45
0
30 45 60 75 90
–30 –15
15
INPUT DIFFERENTIAL VOLTAGE (V)
V
(V)
TEMPERATURE (°C)
IN(CM)
2481 G11
2481 G10
2481 G12
RMS Noise vs V
RMS Noise vs V
Offset Error vs V
IN(CM)
CC
REF
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
1.0
0.9
V
V
V
T
= 5V
= 5V
IN
= 25°C
V
V
V
= 2.5V
V
V
V
= 5V
= 0V
CC
REF
REF
CC
IN
= 0V
IN
IN(CM)
= 0V
= GND
= GND
IN(CM)
GAIN = 256
= 25°C
GAIN = 256
A
T
T
A
= 25°C
A
0.8
0.7
–0.1
–0.2
–0.3
0.6
0.5
0.4
0.6
0.5
0.4
3
5
6
–1
0
1
2
4
4.3
(V)
5.1 5.5
2.7 3.1 3.5 3.9
V
4.7
0
1
2
3
(V)
4
5
V
(V)
V
IN(CM)
REF
CC
2481 G15
2481 G13
2481 G14
Offset Error vs Temperature
Offset Error vs V
Offset Error vs V
REF
CC
0.3
0.2
0.1
0
0.3
0.2
0.3
0.2
+
–
V
V
V
V
= 5V
= 5V
REF = 2.5V
V
= 5V
CC
REF
IN
CC
–
REF = GND
REF = GND
= 0V
V
V
T
= 0V
V
V
T
= 0V
IN
IN(CM)
= 25°C
IN
IN(CM)
= 25°C
= GND
= GND
= GND
IN(CM)
A
A
0.1
0.1
0
0
–0.1
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
–0.2
–0.3
4.3
(V)
5.1
5.5
2.7 3.1
3.5 3.9
4.7
–45 –30 –15
0
15 30 45 60 75 90
0
1
2
3
4
5
TEMPERATURE (°C)
V
CC
V
REF
(V)
2481 G17
2481 G16
2481 G18
2481f
7
LTC2481
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Temperature Sensor
vs Temperature
Temperature Sensor Error
vs Temperature
On-Chip Oscillator Frequency
vs Temperature
0.40
0.35
0.30
0.25
0.20
5
4
310
308
306
304
302
300
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 1.4V
= 1.4V
3
2
1
0
–1
–2
–3
–4
–5
V
V
V
V
= 4.1V
REF
CC
= 2.5V
= 0V
IN
IN(CM)
= GND
–60
–30
0
30
60
90
120
–60
–30
0
30
60
90
120
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2481 G19
2481 G20
2481 G21
On-Chip Oscillator Frequency
vs V
PSRR vs Frequency at V
PSRR vs Frequency at V
CC
CC
CC
310
308
306
304
0
–20
0
V
V
= 4.1V DC ±1.4V
REF
IN = GND
V
V
V
= 2.5V
V
V
= 4.1V DC
= 2.5V
CC
REF
IN
CC
REF
= 2.5V
= 0V
–20
+
–
+
= GND
IN = GND
IN(CM)
–
IN = GND
IN = GND
–40
–40
T = 25°C
T
A
= 25°C
A
–60
–60
–80
–80
–100
–120
–100
–120
–140
302
300
–140
2.5
3.5
4.0
(V)
4.5
5.0
5.5
1
1k
10k 100k 1M
CC
0
60
140
200 220
3.0
10
100
20 40
80 100 120
160 180
V
FREQUENCY AT V (Hz)
CC
FREQUENCY AT V (Hz)
CC
2481 G22
2481 G23
2481 G24
Sleep Mode Current
vs Temperature
Conversion Current
vs Temperature
PSRR vs Frequency at V
CC
0
–20
–40
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
200
180
V
V
= 4.1V DC ±0.7V
REF
IN = GND
CC
= 2.5V
+
–
IN = GND
T
= 25°C
V
= 5V
A
CC
160
V
CC
= 5V
–60
–80
V
= 2.7V
CC
140
120
100
–100
–120
–140
V
CC
= 2.7V
30650
30700
30800
30600
30750
–45 –30 –15
0
15 30 45 60 75 90
60
–45 –30 –15
0
15 30 45
75 90
FREQUENCY AT V (Hz)
CC
TEMPERATURE (°C)
TEMPERATURE (°C)
2481 G25
2481 G26
2481 G27
2481f
8
LTC2481
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current
vs Output Data Rate
Integral Nonlinearity (2x Speed
Mode; V = 5V, V = 5V)
Integral Nonlinearity (2x Speed
Mode; V = 5V, V
= 2.5V)
CC
REF
CC
REF
500
450
400
350
300
250
200
150
100
3
2
3
2
V
= V
CC
V
V
V
= 5V
V
V
V
= 5V
REF
CC
CC
+
IN = GND
= 5V
= 2.5V
REF
REF
–
IN = GND
= 2.5V
= 1.25V
IN(CM)
IN(CM)
CA0/F = EXT OSC
0
T
A
= 25°C
V
= 5V
CC
1
0
1
0
90°C
25°C, 90°C
V
CC
= 3V
–45°C, 25°C
–1
–2
–3
–1
–2
–3
–45°C
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2481 G28
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2481 G29
2481 G30
Noise Histogram
(2x Speed Mode)
RMS Noise vs V
REF
(2x Speed Mode)
Integral Nonlinearity (2x Speed
Mode; V = 2.7V, V
= 2.5V)
CC
REF
3
1.0
0.8
0.6
0.4
0.2
0
16
RMS = 0.86µV
V
V
V
= 2.7V
10,000 CONSECUTIVE
READINGS
CC
AVERAGE = 0.184mV
= 2.5V
REF
IN(CM)
14
12
10
8
2
= 1.25V
V
V
V
= 5V
CC
REF
IN
= 5V
= 0V
1
0
GAIN = 256
= 25°C
90°C
T
A
6
–45°C, 25°C
–1
–2
–3
4
V
V
V
= 5V
= 0V
IN(CM)
= 25°C
CC
IN
2
= GND
T
A
0
–1.25 –0.75
–0.25
0.25
0.75
1.25
1
3
0
2
4
5
181.4
183.8
188.6
179
186.2
INPUT VOLTAGE (V)
V
(V)
OUTPUT READING (µV)
REF
2481 G31
2481 G33
2481 G32
Offset Error vs V
Offset Error vs Temperature
(2x Speed Mode)
IN(CM)
(2x Speed Mode)
200
198
196
194
192
190
188
186
184
182
180
240
230
220
210
200
190
180
170
160
V
V
V
T
= 5V
= 5V
IN
= 25°C
V
V
V
V
= 5V
= 5V
CC
REF
CC
REF
IN
= 0V
= 0V
= GND
A
IN(CM)
–1
1
2
3
4
5
6
–45 –30 –15
0
15 30 45 60 75 90
0
V
(V)
TEMPERATURE (°C)
IN(CM)
2481 G34
2481 G35
2481f
9
LTC2481
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Offset Error vs V
Offset Error vs V
REF
(2x Speed Mode)
PSRR vs Frequency at V
(2x Speed Mode)
CC
CC
(2x Speed Mode)
250
200
150
100
50
0
–20
240
230
220
210
V
V
V
= 2.5V
V
V
V
= 5V
= 0V
IN(CM)
= 25°C
A
V
= 4.1V DC
CC
REF
= 0V
CC
IN
+
REF = 2.5V
IN
IN(CM)
= 25°C
–
= GND
= GND
REF = GND
+
–
T
T
IN = GND
A
–40
IN = GND
T
= 25°C
A
–60
200
190
–80
–100
–120
–140
180
170
160
0
2.7
3
3.5
4
4.5
5
5.5
0
1
2
4
5
1
10
100
1k
10k 100k 1M
3
V
CC
(V)
V
(V)
FREQUENCY AT V (Hz)
CC
REF
2481 G36
2481 G37
2481 G38
PSRR vs Frequency at V
(2x Speed Mode)
PSRR vs Frequency at V
(2x Speed Mode)
CC
CC
0
0
V
= 4.1V DC ±0.7V
CC
+
REF = 2.5V
–20
–40
–20
–
REF = GND
IN = GND
+
–
–40 IN = GND
T = 25°C
A
–60
–80
–60
–80
–100
–120
–100
–120
–140
–140
80
100 120 140 160 180 200 220
0
60
20 40
30650
30700
30800
30600
30750
FREQUENCY AT V (Hz)
CC
FREQUENCY AT V (Hz)
CC
2481 G39
2481 G40
U
U
U
PI FU CTIO S
REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
more positive than the reference negative input, REF–, by
at least 0.1V.
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from –0.5 • VREF /GAIN to 0.5 • VREF/GAIN. Outside this
input range the converter produces unique overrange
and underrange output codes.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2481 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output
through the SDA pin on the falling edges of the SCL clock.
2481f
10
LTC2481
U
U
U
PI FU CTIO S
SDA (Pin 7): Bidirectional Serial Data Line of the I2C
Interface. In the transmitter mode (Read), the conversion
result is output through the SDA pin, while in the receiver
mode (Write), the device configuration bits are input
through the SDA pin. At data input mode, the pin is high
impedance; while at data output mode, it is an open-drain
N-channeldriverandthereforeanexternalpull-upresistor
or current source to VCC is needed.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating)
address control bit for the device I2C address.
CA0/F0 (Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/F0
pin, it is a two state (HIGH or Floating) address control bit
for the device I2C address. When the pin is driven by an
external clock signal with a frequency fEOSC of at least
10kHz, the converter uses this signal as its system clock
andthefundamentaldigitalfilterrejectionnullislocatedat
a frequency fEOSC/5120 and sets the Chip Address CA0
internally to a HIGH.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
U
U
W
FU CTIO AL BLOCK DIAGRA
2
+
REF
V
CC
1
+
IN
SCL
SDA
CA1
+
4
REF
6
7
+
–
IN
IN
–
IN
2
I C
5
3RD ORDER
∆ΣADC
SERIAL
INTERFACE
MUX
9
CA0/F
0
(1-256)
GAIN
10
–
REF
TEMP
SENSOR
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
–
REF
GND
3
8
2481 FD
2481f
11
LTC2481
W U U
U
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
The device will not acknowledge an external request
duringtheconversionstate. Afteraconversionisfinished,
thedeviceisreadytoacceptaread/writerequest. Oncethe
LTC2481 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains
a16-bit plus sign conversion result plus a readback of the
configuration bits corresponds to the conversion just
performed. This result is shifted out on the SDA pin under
the control of the SCL. Data is updated on the falling edges
of SCL allowing the user to reliably latch data on the rising
edge of SCL. In write operation, the device accepts one
configuration byte and the data is shifted in on the rising
edges of the SCL. A new conversion is initiated by a STOP
condition following a valid write operation or at the con-
clusion of a data read operation (read out all 24 bits).
Converter Operation Cycle
The LTC2481 is a low power, ∆Σ analog-to-digital con-
verter with an I2C interface. After power on reset, its
operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output/
input (see Figure 1).
POWER ON RESET
DEFAULT CONFIGURATION:
EXTERNAL INPUT GAIN = 1
50/60Hz REJECTION
1X SPEED, AUTOCAL
CONVERSION
SLEEP
I2C INTERFACE
The LTC2481 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface sup-
porting multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
can never drive the bus HIGH. The bus wires are exter-
nally connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both
lines are HIGH. Data on the I2C-bus can be transferred at
rates of up to 100kbit/s in the Standard-mode and up to
400kbit/s in the Fast-mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when per-
forming data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signalstopermitthattransfer. Atthesametimeanydevice
addressed is considered a slave.
NO
ACKNOWLEDGE
YES
DATA OUTPUT/INPUT
STOP
NO
OR READ
24-BITS
YES
2481 F01
Figure 1. LTC2481 State Transition Diagram
Initially, the LTC2481 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
staticshiftregisterwhiletheconverterisinthesleepstate.
2481f
12
LTC2481
W U U
APPLICATIO S I FOR ATIO
U
The LTC2481 can only be addressed as a slave. Once
addressed, itcanreceiveconfigurationbitsortransmitthe
last conversion result. Therefore the serial clock line SCL
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
on the I2C-bus.
leaves SDA HIGH to indicate a Not Acknowledge (NAK)
condition. ChangeofdatastatecanonlyhappenwhileSCL
is LOW.
Accessing the Special Features of the LTC2481
The LTC2481 combines a high resolution, low noise ∆Σ
analog-to-digitalconverterwithanon-chipselectabletem-
peraturesensor,programmablegain,programmabledigital
filter and output rate control. These special features are
selectedthroughasingle8-bitserialinputwordduringthe
data input/output cycle (see Figure 3).
The START and STOP Conditions
ASTARTconditionisgeneratedbytransitioningSDAfrom
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
The LTC2481 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode until a valid write cycle is performed. In this
default mode, the measured input is external, the GAIN is
1, the digital filter simultaneously rejects 50Hz and 60Hz
line frequency noise, and the speed mode is 1x (offset
automatically, continuously calibrated).
The I2C serial interface grants access to any or all special
functions contained within the LTC2481. In order to
change the mode of operation, a valid write address
followed by 8 bits of data are shifted into the device (see
Table 1). The first 3 bits (GS2, GS1, GS0) control the
GAIN of the converter from 1 to 256. The 4th bit is
reserved and should be low. The 5th bit (IM) is used to
select the internal temperature sensor as the conversion
input, while the 6th and 7th bits (FA, FB) combine to
determine the line frequency rejection mode. The 8th bit
(SPD) is used to double the output rate by disabling the
offset auto calibration.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The
repeated START (Sr) conditions are functionally identical
to the START (S).
Data Transferring
After the START condition, the I2C bus is busy and data
transfer is set between a master and a slave. Data is
transferred over I2C in groups of nine bits (one byte)
followed by an acknowledge bit, therefore each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an Acknowledge (ACK) by pulling SDA LOW or
SDA
tSU;DAT
tf
tLOW
tr
tr
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tHIGH
S
Sr
P
S
2481 F02
2
Figure 2. Definition of Timing for F/S-Mode Devices on the I C-Bus
2481f
13
LTC2481
APPLICATIO S I FOR ATIO
W U U
U
1
2
…
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
7-BIT ADDRESS
GS2 GS1 GS0
IM
FA
FB
SPD
W
ACK BY
LTC2481
ACK BY
LTC2481
START BY
MASTER
SLEEP
DATA INPUT
2481 F03
Figure 3. Timing Diagram for Writing to the LTC2481
Table 1. Selecting Special Modes
Rejection
Mode
Gain
GS2 GS1 GS0 IM FA FB SPD Comments
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 256, Autocalibration
External Input, Gain = 1, 2x Speed
Any
Rejection
Mode
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration
Reserved, Do Not Use
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Any
Speed
Any Gain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2481 TBL1
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Table 2a. The LTC2481 Performance vs GAIN in Normal Speed Mode (V = 5V, V
= 5V)
REF
CC
GAIN
1
±2.5
38.1
65536
5
4
±0.625
9.54
65536
5
8
±0.312
4.77
65536
5
16
±0.156
2.38
65536
5
32
±78m
1.19
65536
5
64
128
±19.5m
0.298
32768
5
256
UNIT
Input Span
LSB
±39m
0.596
65536
5
±9.76m
0.149
16384
8
V
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Table 2b. The LTC2481 Performance vs GAIN in 2x Speed Mode (V = 5V, V
= 5V)
CC
REF
16
GAIN
1
±2.5
38.1
65536
5
2
4
±0.625
9.54
65536
5
8
±0.312
4.77
65536
5
32
±78m
1.19
65536
5
64
±39m
0.596
45875
5
128
±19.5m
0.298
22937
5
UNIT
V
Input Span
LSB
±1.25
19.1
65536
5
±0.156
2.38
65536
5
µV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
µV
200
200
200
200
200
200
200
200
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
Rejection Mode (FA, FB)
GAIN (GS2, GS1, GS0)
The LTC2481 includes a high accuracy on-chip oscillator
with no required external components. Coupled with a 4th
order digital lowpass filter, the LTC2481 rejects line fre-
quency noise. In the default mode, the LTC2481 simulta-
neously rejects 50Hz and 60Hz by at least 87dB. The
LTC2481 can also be configured to selectively reject 50Hz
or 60Hz to better than 110dB.
The input referred gain of the LTC2481 is adjustable from
1 to 256. With a gain of 1, the differential input range is
±VREF/2 and the common mode input range is rail-to-rail.
As the GAIN is increased, the differential input range is
reduced to ±VREF/2 • GAIN but the common mode input
range remains rail-to-rail. As the differential gain is in-
creased, low level voltages are digitized with greater
resolution. At a gain of 256, the LTC2481 digitizes an input
signal range of ±9.76mV with over 16,000 counts.
Speed Mode (SPD)
The LTC2481 continuously performs offset calibrations.
Every conversion cycle, two conversions are automati-
cally performed (default) and the results combined. This
result is free from offset and drift. In applications where
the offset is not critical, the autocalibration feature can be
disabled with the benefit of twice the output rate.
Temperature Sensor (IM)
TheLTC2481includesanon-chiptemperaturesensor.The
temperaturesensorisselectedbysettingIM=1intheserial
input data stream. Conversions are performed directly on
the temperature sensor by the converter. While operating
in this mode, the device behaves as a temperature to bits
converter. The digital reading is proportional to the abso-
lute temperature of the device. This feature allows the
convertertolinearizetemperaturesensorsorcontinuously
removetemperatureeffectsfromexternalsensors.Several
applications leveraging this feature are presented in more
detail in the applications section. While operating in this
mode, the gain is set to 1 and the speed is set to normal in-
dependent of the control bits (GS2, GS1, GS0 and SPD).
Linearity, full-scale accuracy and full-scale drift are iden-
tical for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexerchannelchangestosettleinasingleconversion
cycle easing system overhead and increasing the effective
conversion rate.
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Table 3. LTC2481 Status Bits
LTC2481 Data Format
BIT 23
SIG
BIT 22
MSB
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2481’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. If the conversion is complete, it issues an
acknowledge (ACK) by pulling SDA LOW.
INPUT RANGE
V
≥ 0.5 • V
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
IN
REF
–0.5 • V
≤ V < 0V
IN
REF
V
< –0.5 • V
REF
IN
(MSB) of the result. The first two bits (SIG and MSB) can
be used to indicate over range conditions. If both bits are
HIGH, the differential input voltage is above +FS and the
following 16 bits are set to LOW to indicate an overrange
condition. If both bits are LOW, the input voltage is below
–FS and the following 16 bits are set to HIGH to indicate an
underrange condition. The function of these two bits is
summarized in Table 3. The next 16 bits contain the
conversion results in binary two’s complement format.
The remaining six bits are a readback of the configuration
register.
As long as the voltage on the IN+ and IN– pins is main-
tainedwithinthe–0.3Vto(VCC+0.3V)absolutemaximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF/GAIN
to +FS = 0.5 • VREF/GAIN. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
inputvoltagesbelow–FS,theconversionresultisclamped
to the value corresponding to –FS – 1LSB.
The LTC2481 has two registers. The output register
contains the result of the last conversion and a user
programmable configuration register that sets the con-
verter operation mode.
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1µA. When the LTC2481 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
andactsasatransmitter.Themasterandreceivercanread
uptothreebytesfromtheLTC2481.AfteracompleteRead
operation (3 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same input/output phase will be NAKed. The LTC2481
outputdatastreamis24bitslong, shiftedoutonthefalling
edges of SCL. The first bit is the conversion result sign bit
(SIG), see Tables 3 and 4. This bit is HIGH if VIN ≥ 0. It is
LOW if VIN <0. The second bit is the most significant bit
Table 4. LTC2481 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
IN
BIT 23
SIG
BIT 22
MSB
BIT 21
BIT 20
BIT 19
…
BIT 6
V
*
V * ≥ FS**
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
FS** – 1LSB
0.5 • FS**
0.5 • FS** – 1LSB
0
–1LSB
–0.5 • FS**
–0.5 • FS** – 1LSB
–FS**
V * < –FS**
IN
0
+
–
*The differential input voltage V = IN – IN . **The full-scale voltage FS = 0.5 • V /GAIN.
IN
REF
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LTC2481
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U
1
… 7
8
9
1
2 …
9
1
2
3
4
5
6
7
8
9
7-BIT
ADDRESS
R
SGN MSB D15
LSB PG2 PG1 PG0
X
IM
SPD
ACK BY
LTC2481
ACK BY
MASTER
NAK BY
MASTER
START BY
MASTER
SLEEP
DATA OUTPUT
2481 F04
Figure 4. Timing Diagram for Reading from the LTC2481
Initiating a New Conversion
OPERATION SEQUENCE
When the LTC2481 finishes a conversion, it automatically The LTC2481 acts as a transmitter or receiver. The device
enters the sleep state. Once in the sleep state, the device may be programmed to perform several functions. These
is ready for Read/Write operations. After the device ac- include measuring an external differential input signal or
knowledges a Read or Write request, the device exits the an integrated temperature sensor, setting a program-
sleepstateandentersthedatainput/outputstate. Thedata mable gain (from 1 to 256), selecting line frequency
input/output state concludes and the LTC2481 starts a rejection (50Hz, 60Hz, or simultaneous 50Hz and 60Hz),
new conversion once a STOP condition is issued by the and a 2x speed up mode.
master or all 24-bits of data are read out of the device.
Continuous Read
Duringthedatareadcycle,astopcommandmaybeissued
In applications where the configuration does not need to
change for each conversion cycle, the conversion result
can be continuously read. The configuration remains
unchanged from the last value written into the device. If
the device has not been written to since power up, the
configuration is set to the default value (Input External,
GAIN=1,simultaneous50Hz/60Hzrejection,and1xspeed
mode). The operation sequence is shown in Figure 6.
When the conversion is finished, the device may be
addressed for a read operation. At the end of a read
operation, a new conversion begins. At the conclusion
of the conversion cycle, the next result may be read
using the method described above. If the conversion
cycle is not concluded and a valid address selects the
device, the LTC2481 generates a NAK signal indicating
the conversion cycle is in progress.
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the 9th clock cycle of a byte read when the
bus is free (the ACK/NAK cycle).
LTC2481 Address
The LTC2481 has two address pins, enabling one in 6
possible addresses, as shown in Table 5.
Table 5. LTC2481 Address Assignment
CA1
CA0/F *
Address
0
LOW
HIGH
001 01 00
001 01 01
001 01 11
010 01 00
010 01 10
010 01 11
LOW
Floating
HIGH
Floating
Floating
HIGH
HIGH
Floating
HIGH
Floating
* CA0/F is treated as HIGH when driven by a valid external clock.
0
In addition to the configurable addresses listed in Table 5,
the LTC2481 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2481s.
2481f
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LTC2481
APPLICATIO S I FOR ATIO
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S
R/W
ACK
DATA
Sr
DATA TRANSFERRING
P
7-BIT ADDRESS
CONVERSION
SLEEP
DATA INPUT/OUTPUT
Figure 5. The LTC2481 Conversion Sequence
CONVERSION
2481 F05
S
7-BIT ADDRESS
R
ACK
READ
P
S
7-BIT ADDRESS
R
ACK
READ
P
CONVERSION
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2481 F06
Figure 6. Consecutive Reading at the Same Configuration
S
7-BIT ADDRESS
W
ACK
WRITE
Sr
7-BIT ADDRESS
ADDRESS
R
ACK
READ
P
CONVERSION
SLEEP
DATA INPUT
DATA OUTPUT
CONVERSION
2481 F08
Figure 7. Write, Read, Start Conversion
Continuous Read/Write
Synchronizing Multiple LTC2481s with the Global
Address Call
Once the conversion cycle is concluded, the LTC2481 can
be written to then read from, using the repeated Start (Sr)
command.
In applications where several LTC2481s are used on the
same I2C bus, all LTC2481s can be synchronized with the
global address call. To achieve this, first all the LTC2481s
must have completed the conversion cycle. The master
issues a Start, followed by the LTC2481 global address
1110111andaWriterequest.AllLTC2481swillbeselected
and acknowledge the request. The master then sends the
write byte (Optional) and ends the Write operation with a
STOP. This will update the configuration registers (if a
write byte was sent) and initiate a new conversion simul-
taneously on all the LTC2481s, as shown in Figure 9. In
order to synchronize the start of conversion without
affecting the configuration registers, the Write operation
canbeabortedwithaSTOP.Thisinitiatesanewconversion
on all the LTC2481s without changing the configuration
registers.
Figure 7 shows a cycle which begins with a data Write, a
repeated start, followed by a read, and concluded with a
stop command. The following conversion begins after all
24-bits are read out of the device or after the STOP
command and uses the newly programmed configura-
tion data.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Configuration Updating
At the conclusion of a conversion cycle, a Write cycle can
be initiated. Once the Write cycle is acknowledged, a stop
(P) command initiates a new conversion. If a new
configuration is required, this data can be written into the
device and a stop command initiates a new conversion,
see Figure 8.
2481f
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LTC2481
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S
7-BIT ADDRESS
W ACK
WRITE (OPTIONAL)
P
CONVERSION
SLEEP
DATA INPUT
CONVERSION
2481 F09
Figure 8. Start a New Conversion without Reading Old Conversion Result
SCL
SDA
LTC2481
LTC2481
…
LTC2481
S
GLOBAL ADDRESS
W ACK WRITE (OPTIONAL)
P
ALL LTC2481s IN SLEEP
CONVERSION OF ALL LTC2481s
DATA INPUT
2481 F10
Figure 9. Synchronize the LTC2481s with the Global Address Call
Easy Drive Input Current Cancellation
lated to the accuracy of the converter system clock. The
LTC2481incorporatesahighlyaccurateon-chiposcillator.
Thiseliminatestheneedforexternalfrequencysettingcom-
ponents such as crystals or oscillators.
The LTC2481 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input cur-
rent. This enables external RC networks and high imped-
ance sensors to directly interface to the LTC2481 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers enabling input
signals to swing all the way to ground and up to VCC.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale auto-calibration and the
absolute accuracy (full scale + offset + linearity) is main-
tained even with external RC networks.
Frequency Rejection Selection (CA0/F0)
TheLTC2481internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register (the default mode at power
up is simultaneous 50Hz/60Hz rejection).
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2481 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the CA0/F0 pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods tHEO and tLEO
are observed.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonlyimplementedasaSINCorCombfilter).Forhigh
resolution,lowfrequencyapplications,thisfilteristypically
designedtorejectlinefrequenciesof50Hzor60Hzplustheir
harmonics. The filter rejection performance is directly re-
2481f
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–80
–85
While operating with an external conversion clock of a
frequency fEOSC, the LTC2481 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 10.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Whenever an external clock is not present at the CA0/F0
pin, the converter automatically activates its internal os-
cillator and enters the Internal Conversion Clock mode.
CA0/F0 may be tied HIGH or left floating in order to set the
chip address. The LTC2481 operation will not be dis-
turbed if the change of conversion clock source occurs
during the sleep state or during the data output state while
the converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected.
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/5120(%)
2481 F11
EOSC
Figure 10. LTC2481 Normal Mode Rejection When
Using an External Oscillator
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Table 6 summarizes the duration of the conversion state of
each state and the achievable output data rate as a function
Power-Up Sequence
of fEOSC
.
The LTC2481 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi-
mately2V. Thisfeatureguaranteestheintegrityoftheconver-
sion result.
Ease of Use
The LTC2481 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2481 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
The LTC2481 performs offset and full-scale calibrations
everyconversioncycle.Thiscalibrationistransparenttothe
user and has no effect on the cyclic operation described
Table 6. LTC2481 State Duration
STATE
OPERATING MODE
DURATION
CONVERSION
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
CA0/F = External Oscillator
41036/f
s, Output Data Rate ≤ f
/41036 Readings/s for
0
EOSC
EOSC
with Frequency f
Hz
1x Speed Mode
20556/f s, Output Data Rate ≤ f
EOSC
(f
/5120 Rejection)
EOSC
/20556 Readings/s for
EOSC
EOSC
2x Speed Mode
2481f
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first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
If the same VREF source is used during calibration and
temperature measurement, the actual value of the VREF is
not needed to measure the temperature as shown in the
calculation below:
On-Chip Temperature Sensor
RSDA • VREF
TC =
– 273
The LTC2481 contains an on-chip PTAT (proportional to
absolutetemperature)signalthatcanbeusedasatempera-
turesensor.TheinternalPTAThasatypicalvalueof420mV
at 27°C and is proportional to the absolute temperature
value with a temperature coefficient of 420/(27 + 273) =
1.40mV/°C (SLOPE), as shown in Figure 11. The internal
PTAT signal is used in a single-ended mode referenced to
device ground internally. The GAIN is automatically set to
one (independent of the values of GS0, GS1, GS2) in order
to preserve the PTAT property at the ADC output code and
avoid an out of range error. The 1x speed mode with auto-
matic offset calibration is automatically selected for the in-
ternal PTAT signal measurement as well.
SLOPE
RSDA
R0SDA
=
• T0 + 273 – 273
(
)
600
V
= 5V
CC
IM = 1
SLOPE = 1.40mV/°C
500
400
300
200
–60
–30
0
30
60
90
120
When using the internal temperature sensor, if the output
code is normalized to RSDA = VPTAT/VREF, the temperature
is calculated using the following formula:
TEMPERATURE (°C)
2481 F12
Figure 11. Internal PTAT Signal vs Temperature
Reference Voltage Range
RSDA • VREF
TK =
and
TC =
in Kelvin
The LTC2481 external reference voltage range is 0.1V to
VCC. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt-
age. Since the transition noise (600nV) is much less than
the quantization noise (VREF/217), a decrease in the refer-
ence voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external FO signal) at substantially higher output
data rates (see the Output Data Rate section). VREF must
be ≥1.1V to use the internal temperature sensor.
SLOPE
RSDA • VREF
SLOPE
– 273 in °C
where SLOPE is nominally 1.4mV/°C.
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve absolute
temperature measurements, a one-time calibration is
needed to adjust the SLOPE value. The converter output of
the PTAT signal, R0SDA, is measured at a known tempera-
ture T0 (in °C) and the SLOPE is calculated as:
The reference input is differential. The differential refer-
ence input range (VREF = REF+ – REF–) is 100mV to VCC
and the common mode reference input range is 0V to VCC.
R0SDA • VREF
SLOPE =
T0 + 273
This calibrated SLOPE can be used to calculate the
temperature.
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Driving the Input and Reference
Input Voltage Range
The input and reference pins of the LTC2481 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltageandthedifferentialreferencevoltage, thesecapaci-
tors are switching between these four pins transferring
smallamountsofchargeintheprocess.Asimplifiedequiva-
lent circuit is shown in Figure 12.
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
andtheerrorsduetoinputleakagecurrentincreaserapidly.
Within these limits, the LTC2481 converts the bipolar
differential input signal, VIN = IN+ – IN–, from –FS to +FS
where FS = 0.5 • VREF/GAIN. Beyond this range, the
converter indicates the overrange or the underrange con-
dition using distinct output codes. Since the differential
input current cancellation does not rely on an on-chip
buffer, current cancellation as well as DC performance is
maintained rail-to-rail.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 12), a first order passive network with a time con-
stant τ = (RS + RSW) • CEQ. The converter is able to sample
the input signal with better than 1ppm accuracy if the
sampling period is at least 14 times greater than the input
circuit time constant τ. The sampling process on the four
input analog pins is quasi-independent so each time con-
stant should be considered by itself and, under worst-case
circumstances, the errors may add.
I
nput signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
manceofthedevices. Theeffectoftheseriesresistanceon
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sec-
tions. In addition, series resistors will introduce a tem-
perature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if VREF = 5V. This error has a
very strong temperature dependency.
When using the internal oscillator, the LTC2481’s front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2.5/fEOSC and, for a settling
error of less than 1ppm, τ ≤ 0.178/fEOSC
.
V
CC
+
I
REF
R
(TYP)
SW
I
I
LEAK
LEAK
10k
+
V
IN(CM) − VREF(CM)
V
I IN+
= I IN–
=
AVG
REF
(
)
(
)
AVG
0.5• REQ
2
2
1.5VREF
+
VREF(CM) – V
V
(
IN(CM)
)
1.5• VREF − V
+ VREFCM
0.5• VREF • DT
REQ
V
IN
V
INCM
IN
I REF+
=
−
−
≅
–
CC
+
(
)
I
IN
AVG
0.5• REQ
VREF • REQ
0.5•REQ
VREF •REQ
R
(TYP)
10k
SW
I
I
LEAK
LEAK
where:
+
V
IN
REF + REF–
C
+
⎛
⎞
EQ
VREFCM
=
12pF
REF+ − REF–
, VREF =
⎜
⎟
2
⎝
⎠
(TYP)
V
CC
V
IN
= IN+ −IN−
–
I
IN
R
R
(TYP)
+
SW
⎛
⎞
I
IN + IN−
LEAK
LEAK
V
INCM
=
10k
⎜
⎟
–
2
⎝
⎠
V
IN
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
I
V
CC
–
–
I
REF
REQ
=
0.833• 1012 / fEOSC EXTERNAL OSCILLATOR
(
)
(TYP)
SW
10k
I
I
LEAK
LEAK
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF IS INTERNALLY TIED TO GND
2480 F13
V
–
REF
SWITCHING FREQUENCY
f
f
= 123kHz INTERNAL OSCILLATOR
SW
SW
= 0.4 • f
EXTERNAL OSCILLATOR
EOSC
Figure 12. LTC2481 Equivalent Analog Input Circuit
2481f
22
LTC2481
W U U
APPLICATIO S I FOR ATIO
U
R
R
Automatic Differential Input Current Cancellation
SOURCE
+
IN
In applications where the sensor output impedance is low
(up to 10kΩ with no external bypass capacitor or up to
500Ωwith0.001µFbypass), completesettlingoftheinput
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
C
PAR
≅20pF
V
V
+ 0.5V
C
C
INCM
IN
EXT
LTC2481
SOURCE
–
IN
2481 F14
C
PAR
– 0.5V
INCM
IN
EXT
≅20pF
Formanyapplications,thesensoroutputimpedancecom-
bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10kΩ bridge driving a 0.1µF
bypass capacitor has a time constant several orders of
magnitude greater than the required maximum. Histori-
cally, settling issues were solved using buffers. These
buffers led to increased noise, reduced DC performance
(Offset/Drift), limited input/output swing (cannot digitize
signals near ground or VCC), added system cost and in-
creasedpower. TheLTC2481usesaproprietaryswitching
algorithm that forces the average differential input current
to zero independent of external settling errors. This allows
accurate direct digitization of high impedance sensors
without the need of buffers (see Figures 13 to 15). Addi-
tional errors resulting from mismatched leakage currents
must also be taken into account.
+
–
Figure 13. An RC Network at IN and IN
80
V
V
V
V
= 5V
CC
= 5V
REF
60
40
20
+
= 3.75V
= 1.25V
IN
–
IN
T
= 25°C
A
C
= 0pF
EXT
C
EXT
= 100pF
0
C
EXT
= 1nF, 0.1µF, 1µF
–20
–40
–60
–80
10
100
10k
1
100k
1k
R
(Ω)
SOURCE
2481 F15
+
–
Figure 14. +FS Error vs R
at IN and IN
SOURCE
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN++ IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
80
V
V
V
V
= 5V
CC
= 5V
REF
60
40
20
+
= 1.25V
= 3.75V
IN
–
IN
T
= 25°C
A
C
= 1nF, 0.1µF, 1µF
EXT
0
C
= 100pF
EXT
–20
C
= 0pF
EXT
–40
–60
–80
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ-
ential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN+ and IN–
also do not affect the accuracy.
10
100
10k
1
100k
1k
R
(Ω)
SOURCE
2481 F16
+
–
Figure 15. –FS Error vs R
at IN and IN
SOURCE
the common mode input current is proportional to the
difference between VINCM and VREFCM. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
2481f
23
LTC2481
W U U
U
APPLICATIO S I FOR ATIO
0.74µA(insimultaneous50Hz/60Hzrejectionmode). This
commonmodeinputcurrenthasnoeffectontheaccuracy
if the external source impedances tied to IN+ and IN– are
matched. Mismatches in these source impedances lead to
a fixed offset error but do not affect the linearity or full-
scale reading. A 1% mismatch in 1kΩ source resistances
leads to a 15ppm shift (74µV) in offset voltage.
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
thecommonmodeinputcurrenteffectsarerejectedbythe
large CMRR of the LTC2481 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errorsproportionaltothedifferencebetweenthecommon
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 7 summarizes the effects of mismatched
sourceimpedanceanddifferencesinreference/inputcom-
mon mode voltages.
Reference Current
In a similar fashion, the LTC2481 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gainandINLperformance.Theeffectofthiscurrentcanbe
analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settlesalmostcompletelyandrelativelylargevaluesforthe
source impedance result in only small errors. Such values
for CREF will deteriorate the converter offset and gain
performancewithoutsignificantbenefitsofreferencefilter-
ing and the user is advised to avoid them.
Table 7. Suggested Input Configuration for LTC2481
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
+
Constant
IN(CM)
C
> 1nF at Both
C
> 1nF at Both IN
Larger values of reference capacitors (CREF > 1nF) may be
requiredasreferencefiltersincertainconfigurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
EXT
+
EXT
–
–
V
– V
IN and IN . Can Take
and IN . Can Take Large
REF(CM)
Large Source Resistance Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
+
+
–
Varying
IN(CM)
C
> 1nF at Both IN
Minimize IN and IN
EXT
–
V
– V
and IN . Can Take Large Capacitors and Avoid
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistance is 1MΩ which generates a full-scale (VREF/2)
gain error of 0.51ppm for each ohm of source resistance
driving the REF+ and REF– pins. For 50Hz/60Hz mode, the
relateddifferenceresistanceis1.1MΩandtheresultingfull-
scale error is 0.46ppm for each ohm of source resistance
driving the REF+ and REF– pins. For 50Hz mode, the related
difference resistance is 1.2MΩ and the resulting full-scale
error is 0.42ppm for each ohm of source resistance driving
the REF+ and REF– pins. When CA0/F0 is driven by an
REF(CM)
Source Resistance with
Negligible Error
Large Source Impedance
(<5k Recommended)
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
2481f
24
LTC2481
W U U
APPLICATIO S I FOR ATIO
U
500
400
300
200
100
0
V
V
V
V
= 5V
CC
external oscillator with a frequency fEOSC (external conver-
sionclockoperation),thetypicaldifferentialreferenceresis-
tance is 0.30 • 1012/fEOSC Ω and each ohm of source
resistance driving the REF+ or REF– pins will result in 1.67
•10–6 •fEOSCppmgainerror. Thetypical+FSand–FSerrors
for various combinations of source resistance seen by the
REF+ or REF– pins and external capacitance connected to
that pin are shown in Figures 16-19.
C
= 1µF, 10µF
REF
= 5V
REF
+
= 3.75V
= 1.25V
IN
–
IN
T
= 25°C
A
C
REF
= 0.1µF
C
REF
= 0.01µF
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
–VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference
pin current as expressed in Figure 12. When using internal
oscillatorand60Hzmode, every100Ωofreferencesource
resistance translates into about 0.67ppm additional INL
90
0
200
400
R
600
(Ω)
800
1000
SOURCE
2481 F19
+
–
Figure 18. +FS Error vs R
at REF or REF (Large C
)
REF
SOURCE
0
–100
–200
V
V
V
V
= 5V
CC
80
70
60
50
40
30
20
10
0
= 5V
REF
+
= 3.75V
= 1.25V
IN
–
IN
T
= 25°C
A
C
= 0.01µF
REF
C
= 0.01µF
REF
C
= 0.001µF
REF
C
C
= 1µF, 10µF
REF
= 100pF
REF
–300
–400
–500
C
= 0pF
REF
C
= 0.1µF
REF
V
V
V
V
= 5V
= 5V
= 1.25V
= 3.75V
= 25°C
CC
REF
+
IN
–
IN
T
A
–10
0
10
100
1k
10k
100k
0
200
400
R
600
800
1000
R
(Ω)
SOURCE
(Ω)
SOURCE
2481 F17
2481 F20
+
–
+
–
Figure 19. –FS Error vs R
at REF or REF (Large C
)
REF
Figure 16. +FS Error vs R
at REF or REF (Small C
)
REF
SOURCE
SOURCE
10
0
10
V
V
V
A
C
= 5V
CC
8
6
= 5V
REF
IN(CM)
= 25°C
R = 1k
= 2.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
C
REF
C
= 0.01µF
REF
T
C
= 0.001µF
= 10µF
REF
4
= 100pF
REF
REF
C
= 0pF
2
R = 500Ω
R = 100Ω
0
–2
–4
–6
–8
–10
V
V
V
V
= 5V
= 5V
= 1.25V
= 3.75V
= 25°C
CC
REF
+
IN
–
IN
T
A
0
10
100
1k
10k
100k
–0.5
–0.3
–0.1
/V
0.1
(V)
0.3
0.5
R
(Ω)
V
SOURCE
IN REF
2481 F21
2481 F18
+
–
Figure 20. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for C > 1µF
Figure 17. –FS Error vs R
at REF or REF (Small C
)
REF
SOURCE
REF
2481f
25
LTC2481
W U U
U
APPLICATIO S I FOR ATIO
50
40
error.Whenusinginternaloscillatorand50Hz/60Hzmode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillatorand50Hzmode, every100Ωofreferencesource
resistance translates into about 0.56ppm additional INL
error. When CA0/F0 is driven by an external oscillator with
a frequency fEOSC, every 100Ω of source resistance driv-
V
V
V
= V
REF
IN(CM)
REF(CM)
= 5V
= V
CC
IN
= 0V
CA0/F = EXT CLOCK
0
30
20
T
= 85°C
A
10
0
ing REF+ or REF– translates into about 2.18 • 10–6
•
fEOSCppm additional INL error. Figure 20 shows the typi-
cal INL error due to the source resistance driving the REF+
or REF– pins when large CREF values are used. The user is
advised to minimize the source impedance driving the
REF+ and REF– pins.
T
= 25°C
A
–10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2481 F22
Figure 21. Offset Error vs Output Data Rate and Temperature
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and
60Hzmode.Whenusinginternaloscillatorand50Hz/60Hz
mode, the extra full-scale gain error is 0.067ppm. When
using internal oscillator and 50Hz mode, the extra gain
error is 0.061ppm. If an external clock is used, the corre-
sponding extra gain error is 0.24 • 10–6 • fEOSCppm.
3500
V
V
= V
REF
IN(CM)
CC
REF(CM)
= 5V
= V
3000
2500
CA0/F = EXT CLOCK
0
T
= 85°C
A
2000
1500
1000
500
T
= 25°C
A
0
10 20
40
50 60 70 80 90 100
0
30
OUTPUT DATA RATE (READINGS/SEC)
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than0.5%.Suchaspecificationcanalsobeeasilyachieved
by an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by VREF+ and VREF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
valueovertheentiretemperatureandvoltagerange). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
2481 F23
Figure 22. +FS Error vs Output Data Rate and Temperature
0
–500
–1000
T
= 25°C
A
–1500
–2000
–2500
–3000
T
= 85°C
A
V
V
= V
REF
IN(CM)
CC
REF(CM)
= 5V
CA0/F = EXT CLOCK
= V
0
–3500
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
Inadditiontothereferencesamplingcharge,thereferencepins
ESD protection diodes have a temperature dependent leakage
current. This leakage current, nominally 1nA (±100nA max),
results in a small gain error. A 100Ω source resistance will
create a 0.05µV typical and 5µV maximum full-scale error.
2481 F24
Figure 23. –FS Error vs Output Data Rate and Temperature
2481f
26
LTC2481
W U U
APPLICATIO S I FOR ATIO
U
Output Data Rate
Third,anincreaseinthefrequencyoftheexternaloscillator
above 1MHz (a more than 3X increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typi-
cal measured performance curves for output data rates up
to 100 readings per second are shown in Figures 21 to 28.
In order to obtain the highest possible level of accuracy
from this converter at output data rates above 20 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. In certain circumstances, a reduc-
tion of the differential reference voltage may be beneficial.
When using its internal oscillator, the LTC2481 produces
upto7.5samplespersecond(sps)withanotchfrequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignificantly short. When oper-
ated with an external conversion clock (CA0/F0 connected
toanexternaloscillator),theLTC2481outputdataratecan
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
Input Bandwidth
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
The combined effect of the internal SINC4 digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2481 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz, the 3dB input
bandwidth is 3.63Hz. When the internal oscillator is used
with the notch set at 50Hz, the 3dB input bandwidth is
3.02Hz. If an external conversion clock generator of fre-
quency fEOSC is connected to the CA0/F0 pin, the 3dB input
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mancedegradationcanbesubstantiallyreducedbyrelying
upon the LTC2481’s exceptional common mode rejection
and by carefully eliminating common mode to differential
mode conversion sources in the input circuit. The user
should avoid single-ended input filters and should main-
tain a very high degree of matching and symmetry in the
circuits driving the IN+ and IN– pins.
bandwidth is 11.8 • 10–6 • fEOSC
.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
atthe3dBfrequency. Whentheinternaloscillatorisused,
the shape of the LTC2481 input bandwidth is shown in
Figure 29. When an external oscillator of frequency fEOSC
isused, theshapeoftheLTC2481inputbandwidthcanbe
derived from Figure 29, 60Hz mode curve in which the
horizontal axis is scaled by fEOSC/307200.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/or
reference capacitors (CIN, CREF) are used, the effect of the
external source resistance upon the LTC2481 typical per-
formance can be inferred from Figures 14, 15, 16 and 17
Theconversionnoise(600nVRMS typicalforVREF =5V)can
be modeled by a white noise source connected to a noise
free converter. The noise spectral density is 47nV√Hz for
an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirementsofverylowbandwidth(justafewHz)inorder
to reduce the output referred noise and relatively high
in which the horizontal axis is scaled by 307200/fEOSC
.
2481f
27
LTC2481
W U U
U
APPLICATIO S I FOR ATIO
24
22
24
V
= V
= 5V
REF
T
= 25°C
CC
A
22
20
T
= 85°C
V
V
= 5V, V
= 2.5V
REF
A
CC
20
18
16
14
12
18
16
14
12
= V
V
V
V
= V
REF
IN(CM)
REF(CM)
IN(CM)
REF(CM)
= 5V
V
= 0V
= V
IN
CC
IN
CA0/F = EXT CLOCK
= 0V
0
T
A
= 25°C
CA0/F = EXT CLOCK
0
RES = LOG 2 (V /NOISE
)
RMS
RES = LOG 2 (V /NOISE
)
REF
REF
RMS
10
10
0
30
10 20
40
50 60 70 80 90 100
40
50 60 70 80 90 100
0
30
10 20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2481 F28
2481 F25
Figure 24. Resolution (Noise
≤ 1LSB)
Figure 27. Resolution (Noise
≤ 1LSB)
RMS
RMS
vs Output Data Rate and Temperature
vs Output Data Rate and Reference Voltage
22
20
18
22
20
18
V
= V
= 5V
REF
T
= 25°C
T
= 85°C
CC
A
A
16
14
12
10
16
14
12
10
V
= 5V, V
= 2.5V
REF
CC
V
V
= V
IN(CM) REF(CM)
= 0V
IN
V
V
= V
REF
IN(CM)
= V
REF(CM)
= 5V
CA0/F = EXT CLOCK
0
CC
T
= 25°C
A
CA0/F = EXT CLOCK
0
RES = LOG 2 (V /INL
)
REF
MAX
RES = LOG 2 (V /INL
)
REF
MAX
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
2481 F29
2481 F26
Figure 28. Resolution (INL
≤ 1LSB)
Figure 25. Resolution (INL
≤ 1LSB)
MAX
MAX
vs Output Data Rate and Reference Voltage
vs Output Data Rate and Temperature
20
V
V
= V
bandwidth (at least 500kHz) necessary to drive the input
switched-capacitor network. A possible solution is a high
gain, low bandwidth amplifier stage followed by a high
bandwidth unity-gain buffer.
IN(CM)
IN
REF(CM)
= 0V
CA0/F = EXT CLOCK
= 25°C
15
10
5
0
T
A
V
CC
= V
= 5V
REF
When external amplifiers are driving the LTC2481, the
ADC input referred system noise calculation can be
simplified by Figure 30. The noise of an amplifier driving
the LTC2481 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency fi. The amplifier noise spectral density
is ni. From Figure 30, using fi as the x-axis selector, we
can find on the y-axis the noise equivalent bandwidth
0
–5
V
= 5V, V
= 2.5V
REF
CC
–10
40
50 60 70 80 90 100
0
30
10 20
OUTPUT DATA RATE (READINGS/SEC)
2481 F27
Figure 26. Offset Error vs Output
Data Rate and Reference Voltage
2481f
28
LTC2481
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APPLICATIO S I FOR ATIO
U
0
–1
–2
–3
–4
–5
–6
freqi of the input driving amplifier. This bandwidth in-
cludes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving ampli-
fier referred to the converter input and including all these
effects can be calculated as N = ni • √freqi. The total
system noise (referred to the LTC2481 input) can now be
obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2481
internal noise, the noise of the IN+ driving amplifier and
the noise of the IN– driving amplifier.
50Hz AND
60Hz MODE
50Hz MODE
60Hz MODE
0
1
2
3
4
5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
If the CA0/F0 pin is driven by an external oscillator of
frequency fEOSC, Figure 30 can still be used for noise
calculation if the x-axis is scaled by fEOSC/307200. For
large values of the ratio fEOSC/307200, the Figure 30 plot
accuracy begins to decrease, but at the same time the
LTC2481noisefloorrisesandthenoisecontributionofthe
driving amplifiers lose significance.
2481 F30
Figure 29. Input Signal Using the Internal Oscillator
100
60Hz MODE
50Hz MODE
10
1
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2481 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2481
allowsexternallowpassfilteringwithoutdegradingtheDC
performance of the device.
0.1
0.1
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
2481 F31
The SINC4 digital filter provides greater than 120dB nor-
mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(fS). The LTC2481’s autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
modesignalfilteringbothintheanaloganddigitaldomain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
fEOSC/20. The performance of the normal mode rejection
is shown in Figures 31 and 32.
Figure 30. Input Refered Noise Equivalent Bandwidth
of an Input Connected White Noise Source
shown in Figure 33 (rejection near DC) and Figure 34
(rejection at fS = 256fN) where fN represents the notch
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the fN value.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 35, 36 and 37. Typical measured values of the
normal mode rejection of the LTC2481 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 35 superimposed over the theoretical calculated
curve. Similarly, the measured normal mode rejection of
the LTC2481 for the 50Hz rejection mode and 50Hz/60Hz
rejection mode are shown in Figures 36 and 37.
In 1x speed mode, the regions of low rejection occurring
at integer multiples of fS have a very narrow bandwidth.
Magnified details of the normal mode rejection curves are
2481f
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LTC2481
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APPLICATIO S I FOR ATIO
mon to have to measure microvolt level signals superim-
posed on volt level perturbations and the LTC2481 is
eminently suited for such tasks. When the perturbation is
differential,thespecificationofinterestisthenormalmode
rejection for large input signal levels. With a reference
voltageVREF = 5V, theLTC2481hasafull-scaledifferential
input range of 5V peak-to-peak. Figures 38 and 39 show
measurement results for the LTC2481 normal mode rejec-
tion ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional nor-
mal mode rejection ratio results obtained with a 5V peak-
to-peak (full scale) input signal. In Figure 38, the LTC2481
uses the internal oscillator with the notch set at 60Hz and
in Figure 39 it uses the internal oscillator with the notch set
at 50Hz. It is clear that the LTC2481 rejection performance
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2481. If passive RC components are placed in
front of the LTC2481, the input dynamic current should be
considered (see Input Current section). In this case, the
differentialinputcurrentcancellationfeatureoftheLTC2481
allows external RC networks without significant degrada-
tion in DC performance.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The pro-
prietary architecture used for the LTC2481 third order
modulatorresolvesthisproblemandguaranteesapredict-
able stable behavior at input signal levels of up to 150% of
full scale. In many industrial applications, it is not uncom-
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
f 2f 3f 4f 5f 6f 7f 8f 9f 10f
S S S S S S S S S S
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
S S S S S S S S S S S S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2481 F33
2481 F32
Figure 31. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 32. Input Normal Mode Rejection at DC
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
f
= f
EOSC/5120
N
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–120
250f 252f 254f 256f 258f 260f 262f
N
0
f
2f
3f
4f
5f
6f
7f
8f
N
N
N
N
N
N
N
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT SIGNAL FREQUENCY (Hz)
2481 F35
2481 F34
Figure 33. Input Normal Mode Rejection at DC
Figure 34. Input Normal Mode Rejection at f = 256f
s N
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30
LTC2481
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0
0
–20
–20
5V
V
5V
V
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2481 F36
2481 F37
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)
0
0
V
V
V
T
= 5V
= 5V
CC
V
V
= 5V
= 7.5V
IN(P-P)
IN(P-P)
REF
–20
–40
–20
–40
= 2.5V
INCM
(150% OF FULL SCALE)
= 25°C
A
–60
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
160
180
200
220
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
2481 F38
2481 F39
Figure 38. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (60Hz Notch)
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz/60Hz Mode)
0
–20
V
= 5V
CC
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2481 F40
Figure 39. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (50Hz Notch)
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31
LTC2481
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0
–20
–40
–60
–80
0
–20
–40
–60
–80
–100
–100
–120
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (f )
0
f
2f
3f
4f 5f
N
6f
7f
8f
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (f )
N
N
2481 F42
2481 F41
Figure 41. Input Normal Mode Rejection 2x Speed Mode
Figure 40. Input Normal Mode Rejection 2x Speed Mode
0
–70
MEASURED DATA
CALCULATED DATA
V
V
V
V
= 5V
CC
= 5V
REF
–80
–20
–40
= 2.5V
INCM
NO AVERAGE
= 5V
IN(P-P)
–90
T
= 25°C
A
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
–140
–60
–80
–100
–120
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
56
60
62
48 50
52
54
58
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2481 F43
2481 F44
Figure 43. Input Normal Mode Rejection 2x Speed Mode
Figure 42. Input Normal Mode Rejection vs Input
Frequency, 2x Speed Mode and 50Hz/60Hz Mode
5V
C8
1µF
C7
0.1µF
ISOTHERMAL
LT1236
2
6
5
1.7k
1
2
1.7k
IN OUT
TRIM
GND
4
R2
2k
+
6
7
9
10
REF
V
CC
R7
8k
SCL
SDA
CA1
4
5
+
+
–
IN
G1
NC1M4V0
LTC2481
–
R8
1k
CA0/F
0
IN
REF GND
3
8
2481 F45
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
26.3C
Figure 44. Calibration Setup
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LTC2481
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U
is maintained with no compromises in this extreme situa-
tion.Whenoperatingwithlargeinputsignallevels,theuser
must observe that such signals do not violate the device
absolute maximum ratings.
Complete Thermocouple Measurement System with
Cold Junction Compensation
TheLTC2481isidealfordirectdigitizationofthermocouples
andotherlowvoltageoutputsensors.Theinputhasatypical
offset error of 500nV (2.5µV max) offset drift of 10nV/°C
and a noise level of 600nVRMS. The input span may be
optimized for various sensors by setting the gain of the
PGA. Using an external 5V reference with a PGA gain of 64
gives a ±78mV input range—perfect for thermocouples.
Using the 2x speed mode of the LTC2481, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
ismaintainedasshowninFigures31and32. However, the
magnified details near DC and fS = 256fN are different, see
Figures 40 and 41. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
mode. Typical measured values of the normal mode
rejection of the LTC2481 operating with the internal oscil-
lator and 2x speed mode is shown in Figure 42.
Figure 45 (page 39 of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
meter,thecoldjunctiontemperaturesensormustbeatthe
same temperature as the junction between the thermo-
couple materials and the copper printed circuit board
traces. The tiny LTC2481 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
When the LTC2481 is configured in 2x speed mode, by
performing a running average, a SINC1 notch is combined
with the SINC4 digital filter, yielding the normal mode
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
The LTC2481’s 1.4mV/°C PTAT circuit measures the cold
junction temperature. Once the thermocouple voltage and
coldjunctiontemperatureareknown,therearemanyways
of calculating the thermocouple temperature including a
straight-lineapproximation, lookuptablesorapolynomial
curve fit. Calibration is performed by applying an accurate
500mV to the ADC input derived from an LT®1236 refer-
ence and measuring the local temperature with an accu-
rate thermometer as shown in Figure 44. In calibration
mode,theupanddownbuttonsareusedtoadjustthelocal
temperature reading until it matches an accurate ther-
mometer. Both the voltage and temperature calibration
are easily automated.
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effective output rate, as shown in Figure 43. The raw
output data provides a better than 70dB rejection over
48Hz to 62.4Hz, which covers both 50Hz ±2% and 60Hz
±2%. With running average on, the rejection is better than
87dB for both 50Hz ±2% and 60Hz ±2%.
The complete microcontroller code for this application is
available on the LTC2481 product webpage at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2481()
function controls the operation of the LTC2481 and is
listed below for reference.
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LTC2481
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/*
LTC248X.h
Processor setup and
Lots of useful defines for configuring the LTC2481 and LTC2485.
*/
#include <16F73.h>
// Device
#use delay(clock=6000000)
// 6MHz clock
//#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT
// Configuration fuses
#rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config.
#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port
#include "PCM73A.h"
#include "lcd.c"
// Various defines
// LCD driver functions
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the
// 8 bit config word.
#define READ
#define WRITE
0x01
0x00
// bitwise OR with address for read or write
#define LTC248XADDR 0b01001000
// The one and only LTC248X in this circuit,
// with both address lines floating.
// Select gain - 1 to 256 (also depends on speed setting)
#define GAIN1 0b00000000
#define GAIN2 0b00100000
#define GAIN3 0b01000000
#define GAIN4 0b01100000
#define GAIN5 0b10000000
#define GAIN6 0b10100000
#define GAIN7 0b11000000
#define GAIN8 0b11100000
// G = 1
// G = 4
// G = 8
(SPD = 0), G = 1
(SPD = 0), G = 2
(SPD = 0), G = 4
(SPD = 1)
(SPD = 1)
(SPD = 1)
(SPD = 1)
// G = 16 (SPD = 0), G = 8
// G = 32 (SPD = 0), G = 16 (SPD = 1)
// G = 64 (SPD = 0), G = 32 (SPD = 1)
// G = 128 (SPD = 0), G = 64 (SPD = 1)
// G = 256 (SPD = 0), G = 128 (SPD = 1)
// Select ADC source - differential input or PTAT circuit
#define VIN
#define PTAT
0b00000000
0b00001000
// Select rejection frequency - 50, 55, or 60Hz
#define R50
#define R55
#define R60
0b00000010
0b00000000
0b00000100
// Speed settings is bit 7 in the 2nd byte
#define SLOW
#define FAST
0b00000000 // slow output rate with autozero
0b00000001 // fast output rate with no autozero
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LTC2481
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/*
LTC2481.c
Basic voltmeter test program for LTC2481
Reads LTC2481 input at gain = 1, 1X speed mode, converts to volts,
and prints voltage to a 2 line by 16 character LCD display.
Mark Thoren
Linear Technonlgy Corporation
June 23, 2005
Written for CCS PCM compiler, Version 3.182
*/
#include "LTC248X.h"
/*** read_LTC2481() ************************************************************
This is the function that actually does all the work of talking to the LTC2481.
Arguments: addr - device address
config - configuration bits for next conversion
Returns:
zero if conversion is in progress,
32 bit signed integer with lower 8 bits clear, 24 bit LTC2481
output word in the upper 24 bits. Data is left-justified for
compatibility with the 24 bit LTC2485.
the i2c_xxxx() functions do the following:
void i2c_start(void): generate an i2c start or repeat start condition
void i2c_stop(void): generate an i2c stop condition
char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack
boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device
These functions are very compiler specific, and can use either a hardware i2c
port or software emulation of an i2c port. This example uses software emulation.
A good starting point when porting to other processors is to write your own
i2c functions. Note that each processor has its own way of configuring
the i2c port, and different compilers may or may not have built-in functions
for the i2c port.
When in doubt, you can always write a "bit bang" function for troubleshooting
purposes.
The "fourbytes" structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
Also note that the lower 4 bits are the configuration word from the previous
conversion.
2481f
35
LTC2481
APPLICATIO S I FOR ATIO
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*******************************************************************************/
signed int32 read_LTC2481(char addr, char config)
{
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
union
// adc_code.bits32
// adc_code.by.te0
// adc_code.by.te1
// adc_code.by.te2
// adc_code.by.te3
all 32 bits
byte 0
byte 1
byte 2
byte 3
{
signed int32 bits32;
struct fourbytes by;
} adc_code;
// Start communication with LTC2481:
i2c_start();
if(i2c_write(addr | WRITE))// If no acknowledge, return zero
{
i2c_stop();
return 0;
}
i2c_write(config);
i2c_start();
i2c_write(addr | READ);
adc_code.by.te3 = i2c_read();
adc_code.by.te2 = i2c_read();
adc_code.by.te1 = i2c_read();
adc_code.by.te0 = 0;
i2c_stop();
return adc_code.bits32;
} // End of read_LTC2481()
/*** initialize() **************************************************************
Basic hardware initialization of controller and LCD, send Hello message to LCD
*******************************************************************************/
void initialize(void)
{
// General initialization stuff.
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
// This is the important part - configuring the SPI port
setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock
CKP = 0; // Set up clock edges - clock idles low, data changes on
CKE = 1; // falling edges, valid on rising edges.
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LTC2481
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lcd_init();
// Initialize LCD
delay_ms(6);
printf(lcd_putc, "Hello!");
delay_ms(500);
// Obligatory hello message
// for half a second
} // End of initialize()
*** main() ********************************************************************
Main program initializes microcontroller registers, then reads the LTC2481
repeatedly
*******************************************************************************/
void main()
{
signed int32 x;
float voltage;
int16 timeout;
initialize();
// Integer result from LTC2481
// Variable for floating point math
// Hardware initialization
while(1)
{
delay_ms(1);
// Pace the main loop to something more than 1 ms
// This is a basic error detection scheme. The LTC248X will never take more than
// 163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50Hz, 55Hz, and 60Hz
// rejection modes, respectively.
// If read_LTC248X() does not return non-zero within this time period, something
// is wrong, such as an incorrect i2c address or bus conflict.
if((x = read_LTC2481(LTC248XADDR, GAIN1 | VIN | R55)) != 0)
{
// No timeout, everything is okay
timeout = 0;
// reset timer
x &= 0xFFFFFFC0;
x ^= 0x80000000;
voltage = (float) x;
// clear config bits so they don't affect math
// Invert MSB, result is 2's complement
// convert to float
voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31
lcd_putc('\f');
lcd_gotoxy(1,1);
// Clear screen
// Goto home position
printf(lcd_putc, "V %01.4f", voltage); // Display voltage
}
else
{
++timeout;
}
if(timeout > 200)
{
timeout = 200;
lcd_gotoxy(1,1);
// Prevent rollover
printf(lcd_putc, "ERROR - TIMEOUT");
delay_ms(500);
}
} // End of main loop
} // End of main()
2481f
37
LTC2481
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
0.38 ± 0.10
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2481f
38
LTC2481
U
TYPICAL APPLICATIO
5V
PIC16F73
RC7
C8
C7
0.1µF
20
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
5V
C6
V
1µF
DD
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
0.1µF
ISOTHERMAL
1.7k
1.7k
Y1
3
2
R2
2k
9
6MHz
6
REF
V
CC
SCL
SDA
OSC1
OSC2
4
5
+
–
IN
IN
7
10
LTC2481
–
D1
BAT54
R1
10k
10
TYPE K
THERMOCOUPLE
JACK
CAO/F
O
CA1 GND REF
1
5V
MCLR
9
8
3
(OMEGA MPJ-K-F)
5V
D7
V
CC
D6
D5
D4
EN
RW
RS
2 × 16 CHARACTER
LCD DISPLAY
(OPTREX DMC162488
OR SIMILAR)
6
5
4
3
5V
1
3
R6
5k
9
CONTRAST
V
V
SS
SS
19
GND D0 D1 D2 D3
2
2
5V
2481 F46
R3
R4
R5
CALIBRATE
10k 10k 10k
2
1
DOWN
UP
Figure 45. Complete Type K Thermocouple Meter
2481f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
39
LTC2481
RELATED PARTS
PART NUMBER
LT1236A-5
LT1460
DESCRIPTION
COMMENTS
Precision Bandgap Reference, 5V
Micropower Series Reference
0.05% Max Initial Accuracy, 5ppm/°C Drift
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LT1790
Micropower SOT-23 Low Dropout Reference Family
24-Bit, No Latency ∆Σ ADC in SO-8
24-Bit, No Latency ∆Σ ADC with Differential Inputs
LTC2400
LTC2410
0.8µV
Noise, 2ppm INL
RMS
LTC2411/LTC2411-1 24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP
1.45µV
Noise, 4ppm INL,
RMS
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency ∆Σ ADC with Differential Inputs
24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
LTC2415/
LTC2415-1
Pin Compatible with the LTC2410
LTC2414/LTC2418
LTC2440
8-/16-Channel 24-Bit, No Latency ∆ΣADCs
High Speed, Low Noise 24-Bit ∆Σ ADC
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
Pin Compatible with LTC2482/LTC2484
LTC2480
16-Bit ∆Σ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
LTC2482
LTC2483
LTC2484
LTC2485
16-Bit ∆Σ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
Pin Compatible with LTC2481/LTC2483
Pin Compatible with LTC2480/LTC2482
Pin Compatible with LTC2481/LTC2483
2
16-Bit ∆Σ ADC with Easy Drive Inputs, I C Interface
24-Bit ∆Σ ADC with Easy Drive Inputs
2
24-Bit ∆Σ ADC with Easy Drive Inputs, I C Interface and
Temperature Sensor
2481f
LT/LWI/TP 0805 500 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
40
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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