LTC2600IGN#TR [Linear]
LTC2600 - Octal 16-Bit Rail-to-Rail DACs in 16-Lead SSOP; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC2600IGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC2600 - Octal 16-Bit Rail-to-Rail DACs in 16-Lead SSOP; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2600/LTC2610/LTC2620
Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
FEATURES
DESCRIPTION
The LTC®2600/LTC2610/LTC2620 are octal 16-, 14- and
12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in
16-lead narrow SSOP and 20-lead 4mm × 5mm QFN
packages. They have built-in high performance output
buffers and are guaranteed monotonic.
n
Smallest Pin-Compatible Octal DACs:
LTC2600: 16 Bits
LTC2610: 14 Bits
LTC2620: 12 Bits
n
Guaranteed 16-Bit Monotonic Over Temperature
n
Wide 2.5V to 5.5V Supply Range
These parts establish new board-density benchmarks
for 16- and 14-bit DACs and advance performance
standards for output drive, crosstalk and load regulation
in single-supply, voltage-output multiples.
n
Low Power Operation: 250μA per DAC at 3V
n
Individual Channel Power-Down to 1μA, Max
n
Ultralow Crosstalk between DACs (<10μV)
n
High Rail-to-Rail Output Drive ( 15mA, Min)
n
ThepartsuseasimpleSPI/MICROWIREcompatible3-wire
serial interface which can be operated at clock rates up
to 50MHz. Daisy-chain capability and a hardware CLR
function are included.
Double-Buffered Digital Inputs
Pin Compatible 10-/8-Bit Versions
n
(LTC1660/LTC1665)
Tiny 16-Lead Narrow SSOP
and 20-Lead 4mm × 5mm QFN Packages
n
The LTC2600/LTC2610/LTC2620 incorporate a power-on
resetcircuit.Duringpower-up,thevoltageoutputsriseless
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place.
APPLICATIONS
n
Mobile Communications
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
Process Control and Industrial Automation
n
Instrumentation
Automatic Test Equipment
n
BLOCK DIAGRAM
(20)
GND
1
16
15
V
V
(17)
(16)
CC
DAC A
DAC H
(1)
V
2
OUTA
OUTH
Differential Nonlinearity (LTC2600)
1.0
DAC B
DAC C
DAC G
DAC F
V
V
V
(2)
3
4
14
13
(15)
OUTB
OUTC
OUTG
OUTF
V
V
= 5V
REF
CC
0.8
0.6
= 4.096V
0.4
V
(3)
(4)
(14)
(13)
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DAC D
DAC E
V
V
5
12
OUTD
REF
OUTE
CLR
SDO
(5)
(7)
(8)
6
7
8
11
10
9
(11)
(10)
(9)
POWER-ON
RESET
0
16384
32768
CODE
49152
65535
CONTROL
LOGIC
DECODE
2600 G21
CS/LD
SCK
32-BIT SHIFT REGISTER
SDI
2600 BD
NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE
2600fc
1
LTC2600/LTC2610/LTC2620
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND........................................... –0.3V to 6V
Storage Temperature Range.................. –65°C to 150°C
Maximum Junction Temperature........................... 125°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
Any Pin to V ............................................ –6V to 0.3V
CC
Operating Temperature Range
LTC2600C/LTC2610C/LTC2620C ............. 0°C to 70°C
LTC2600I/LTC2610I/LTC2620I............. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
20 19 18 17
1
2
3
4
5
6
7
8
V
V
V
V
V
16
15
14
13
12
11
10
9
GND
OUTA
CC
V
1
2
3
4
5
6
16
15
14
13
V
V
V
V
OUTA
OUTB
OUTC
OUTH
OUTG
OUTF
OUTE
V
V
OUTH
OUTG
OUTF
OUTE
V
V
OUTB
OUTC
21
V
V
V
OUTD
REF
OUTD
REF
12 NC
CLR
SDO
SDI
NC
11 CLR
CS/LD
SCK
7
8
9 10
GN PACKAGE
16-LEAD PLASTIC SSOP
= 125°C, θ = 150°C/W
UFD PACKAGE
20-LEAD (4mm s 5mm) PLASTIC QFN
= 150°C, θ = 43°C/W
T
JMAX
JA
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2600CUFD#PBF
LTC2600IUFD#PBF
LTC2600CGN#PBF
LTC2600IGN#PBF
LTC2610CUFD#PBF
LTC2610IUFD#PBF
LTC2610CGN#PBF
LTC2610IGN#PBF
LTC2620CUFD#PBF
LTC2620IUFD#PBF
LTC2620CGN#PBF
LTC2620IGN#PBF
TAPE AND REEL
PART MARKING*
2600
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2600CUFD#TRPBF
LTC2600IUFD#TRPBF
LTC2600CGN#TRPBF
LTC2600IGN#TRPBF
LTC2610CUFD#TRPBF
LTC2610IUFD#TRPBF
LTC2610CGN#TRPBF
LTC2610IGN#TRPBF
LTC2620CUFD#TRPBF
LTC2620IUFD#TRPBF
LTC2620CGN#TRPBF
LTC2620IGN#TRPBF
0°C to 70°C
20-Lead (4mm × 5mm) Plastic DFN
20-Lead (4mm × 5mm) Plastic DFN
16-Lead Plastic SSOP
2600
–40°C to 85°C
0°C to 70°C
2600
2600
16-Lead Plastic SSOP
–40°C to 85°C
0°C to 70°C
2610
20-Lead (4mm × 5mm) Plastic DFN
20-Lead (4mm × 5mm) Plastic DFN
16-Lead Plastic SSOP
2610
–40°C to 85°C
0°C to 70°C
2610
2610
16-Lead Plastic SSOP
–40°C to 85°C
0°C to 70°C
2620
20-Lead (4mm × 5mm) Plastic DFN
20-Lead (4mm × 5mm) Plastic DFN
16-Lead Plastic SSOP
2620
–40°C to 85°C
0°C to 70°C
2620
2620
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2600fc
2
LTC2600/LTC2610/LTC2620
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620
LTC2610
LTC2600
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
l
12
12
14
14
16
16
Bits
Bits
LSB
LSB
Monotonicity
V
V
V
V
= 5V, V = 4.096V (Note 2)
CC
CC
CC
REF
REF
DNL
INL
Differential Nonlinearity
= 5V, V = 4.096V (Note 2)
0.5
4
1
1
REF
Integral Nonlinearity
Load Regulation
= 5V, V = 4.096V (Note 2)
0.75
3
16
12
64
REF
= V = 5V, Midscale
CC
l
l
I
I
= 0mA to 15mA Sourcing
= 0mA to 15mA Sinking
0.025 0.125
0.025 0.125
0.1
0.1
0.5
0.5
0.3
0.3
2
2
LSB/mA
LSB/mA
OUT
OUT
V
= V = 2.5V, Midscale
CC
OUT
OUT
REF
I
I
l
l
= 0mA to 7.5mA Sourcing
= 0mA to 7.5mA Sinking
0.05 0.25
0.05 0.25
0.2
0.2
1
1
0.8
0.8
4
4
LSB/mA
LSB/mA
ZSE
Zero-Scale Error
Offset Error
V
V
= 5V, V = 4.096V Code = 0
1
9
1
1
3
9
9
1
1
3
9
9
mV
mV
CC
CC
REF
V
OS
= 5V, V = 4.096V (Note 7)
1
9
REF
V
Temperature
μV/°C
3
OS
Coefficient
GE
Gain Error
V
= 5V, V = 4.096V
%FSR
0.2
6.5
0.7
0.2
6.5
0.7
0.2
6.5
0.7
CC
REF
Gain Temperature
Coefficient
ppm/°C
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER
PSR Power Supply Rejection
CONDITIONS
MIN
TYP
MAX
UNITS
–80
dB
V
=
10%
= V = 5V, Midscale; –15mA ≤ I ≤ 15mA
OUT
CC
l
l
R
DC Output Impedance
V
REF
V
REF
0.025
0.030
0.15
0.15
Ω
Ω
OUT
CC
= V = 2.5V, Midscale; –7.5mA ≤ I
≤ 7.5mA
CC
OUT
DC Crosstalk (Note 4)
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (per Channel)
μV
μV/mA
μV
10
3.5
7.3
I
SC
Short-Circuit Output Current
V
= 5.5V, V = 5.6V
CC REF
l
l
Code: Zero Scale; Forcing Output to V
15
15
34
34
60
60
mA
mA
CC
Code: Full Scale; Forcing Output to GND
V
CC
= 2.5V, V = 5.6V
REF
l
l
Code: Zero Scale; Forcing Output to V
7.5
7.5
18
24
50
50
mA
mA
CC
Code: Full Scale; Forcing Output to GND
Reference Input
Input Voltage Range
l
l
0
V
V
kΩ
pF
CC
Resistance
Normal Mode
11
16
90
20
Capacitance
l
I
Reference Current, Power Down Mode All DACs Powered Down
0.001
1
μA
REF
2600fc
3
LTC2600/LTC2610/LTC2620
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Positive Supply Voltage
Supply Current
2.5
5.5
V
CC
l
l
l
l
I
V
V
= 5V (Note 3)
= 3V (Note 3)
2.6
2.0
0.35
0.10
4
3.2
1
mA
mA
μA
CC
CC
CC
All DACs Powered Down (Note 3) V = 5V
CC
All DACs Powered Down (Note 3) V = 3V
1
μA
CC
Digital I/O
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.5V to 5.5V
= 2.5V to 3.6V
2.4
2.0
V
V
IH
CC
CC
l
l
V
V
CC
V
CC
= 4.5V to 5.5V
= 2.5V to 5.5V
0.8
0.6
V
V
IL
l
l
l
l
V
V
I
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Load Current = –100μA
Load Current = +100μA
V
CC
– 0.4
V
V
OH
0.4
1
OL
V
= GND to V
CC
μA
pF
LK
IN
C
IN
Digital Input Capacitance
(Note 6)
8
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC2620
LTC2610
LTC2600
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
t
Settling Time (Note 8)
7
7
9
7
9
10
0.024% ( 1LSB at 12 Bits)
0.006% ( 1LSB at 14 Bits)
0.0015% ( 1LSB at 16 Bits)
S
μs
μs
Settling Time for 1LSB Step
(Note 9)
2.7
2.7
4.8
2.7
4.8
5.2
μs
μs
μs
0.024% ( 1LSB at 12 Bits)
0.006% ( 1LSB at 14 Bits)
0.0015% ( 1LSB at 16 Bits)
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
0.80
1000
12
0.80
1000
12
0.80
1000
12
V/μs
pF
At Midscale Transition
nV • s
kHz
Multiplying Bandwidth
180
180
180
e
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
n
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
μV
P-P
2600fc
4
LTC2600/LTC2610/LTC2620
TIMING CHARACTERISTICS The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6)
LTC2600/LTC2610/LTC2620
SYMBOL PARAMETER
= 2.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SDI Valid to SCK Setup
4
4
ns
ns
ns
ns
ns
ns
ns
1
SDI Valid to SCK Hold
2
3
4
5
6
7
8
SCK High Time
9
SCK Low Time
9
CS/LD Pulse Width
10
7
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SDO Propagation Delay from SCK Falling Edge
7
C
= 10pF
= 4.5V to 5.5V
= 2.5V to 5.5V
LOAD
l
l
V
CC
V
CC
20
45
ns
ns
l
l
l
t
t
CLR Pulse Width
20
7
ns
ns
9
CS/LD High to SCK Positive Edge
SCK Frequency
10
50% Duty Cycle
50
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: R = 2kΩ to GND or V .
L CC
Note 6: Guaranteed by design and not production tested.
Note 7: Inferred from measurement at code 256 (LTC2600),
code 64 (LTC2610) or code 16 (LTC2620), and at fullscale.
Note 2: Linearity and monotonicity are defined from code kL to code
Note 8: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
CC
REF
N
2N – 1, where N is the resolution and k is given by k = 0.016(2 /V ),
L
L
REF
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
rounded to the nearest whole code. For V = 4.096V and N = 16, k =
REF
L
Note 9: V = 5V, V = 4.096V. DAC is stepped 1LSB between half
CC
REF
256 and linearity is defined from code 256 to code 65,535.
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 3: Digital inputs at 0V or V
.
CC
Note 4: DC crosstalk is measured with V = 5V and V = 4.096V,
CC
REF
with the measured DAC at midscale, unless otherwise noted.
2600fc
5
LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.8
32
24
32
24
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
V
V
= 5V
REF
= 4.096V
= 4.096V
CC
= 4.096V
0.6
16
16
0.4
INL (POS)
INL (NEG)
8
8
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–8
–16
–24
–32
–16
–24
–32
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
2600 G21
2600 G20
2600 G22
DNL vs Temperature
INL vs VREF
DNL vs VREF
1.0
0.8
32
24
1.5
1.0
V
V
= 5V
REF
V
= 5.5V
V
= 5.5V
CC
CC
CC
= 4.096V
0.6
16
0.4
0.5
INL (POS)
INL (NEG)
DNL (POS)
DNL (NEG)
8
DNL (POS)
DNL (NEG)
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–0.5
–1.0
–1.5
–16
–24
–32
–50 –30 –10 10
30
50
70
90
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
V
(V)
REF
REF
2600 G23
2600 G24
2600 G25
Settling to 1LSB
Settling of Full-Scale Step
V
V
OUT
OUT
100μV/DIV
100μV/DIV
12.3μs
9.7μs
CS/LD
2V/DIV
CS/LD
2V/DIV
2600 G27
2600 G26
5μs/DIV
2μs/DIV
SETTLING TO 1LSB
V
= 5V, V
= 4.096V
REF
CC
V
= 5V, V
= 4.096V
1/4-SCALE TO 3/4-SCALE STEP
= 2k, C = 200pF
CC
REF
CODE 512 TO 65535 STEP
= 2k, C = 200pF
R
L
L
R
AVERAGE OF 2048 EVENTS
L
L
AVERAGE OF 2048 EVENTS
2600fc
6
LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2610
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to 1LSB
8
6
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
4
0.4
V
OUT
2
0.2
100μV/DIV
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
8.9μs
2600 G30
2μs/DIV
V
= 5V, V
= 4.096V
REF
CC
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
0
4096
8192
12288
16383
0
4096
8192
12288
16383
L
L
AVERAGE OF 2048 EVENTS
CODE
CODE
2600 G28
2600 G29
LTC2620
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to 1LSB
2.0
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
1.5
0.6
1.0
6.8μs
0.4
V
OUT
0.5
0.2
1mV/DIV
0
0
CS/LD
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
2600 G33
2μs/DIV
V
= 5V, V
= 4.096V
REF
CC
1/4-SCALE TO 3/4-SCALE STEP
R
= 2k, C = 200pF
0
1024
2048
3072
4095
0
1024
2048
3072
4095
L
L
AVERAGE OF 2048 EVENTS
CODE
CODE
2600 G31
2600 G32
LTC2600/LTC2610/LTC2620
Current Limiting
Load Regulation
Offset Error vs Temperature
0.10
1.0
0.8
3
2
CODE = MIDSCALE
CODE = MIDSCALE
0.08
V
V
= V = 5V
CC
REF
REF
0.06
0.04
0.6
= V = 3V
CC
0.4
1
0.02
0.2
0
0
0
V
= V = 5V
CC
REF
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V = 3V
CC
REF
REF
–1
–2
–3
V
= V = 5V
CC
V
= V = 3V
REF CC
–40 –30 –20 –10
0
10 20 30 40
–35 –25 –15 –5
5
15
25
35
–50 –30 –10 10
30
50
70
90
I
(mA)
I
(mA)
OUT
TEMPERATURE (°C)
OUT
2600 G01
2600 G02
2600 G03
2600fc
7
LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Zero-Scale Error vs Temperature
Gain Error vs Temperature
Offset Error vs VCC
3
2.5
2.0
1.5
1.0
0.5
0
0.4
0.3
3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –30 –10 10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
2600 G04
2600 G05
2600 G06
Gain Error vs VCC
ICC Shutdown vs VCC
Large-Signal Response
0.4
0.3
450
400
350
300
250
200
150
100
50
0.2
0.1
V
OUT
0.5V/DIV
0
–0.1
–0.2
–0.3
–0.4
V
= V = 5V
CC
REF
1/4-SCALE TO 3/4-SCALE
2.5μs/DIV
2600 G09
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
(V)
CC
CC
2600 G07
2600 G08
Headroom at Rails
vs Output Current
Midscale Glitch Impulse
Power-On Reset Glitch
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V SOURCING
V
OUT
V
CC
10mV/DIV
3V SOURCING
1V/DIV
12nV-s TYP
2.5μs/DIV
4mV PEAK
CS/LD
5V/DIV
V
OUT
10mV/DIV
5V SINKING
2600 G10
2600 G11
3V SINKING
250μs/DIV
0
1
2
3
4
5
6
7
8
9
10
I
(mA)
OUT
2600 G12
2600fc
8
LTC2600/LTC2610/LTC2620
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2600/LTC2610/LTC2620
Supply Current vs Logic Voltage
Exiting Power-Down to Midscale
Hardware CLR
2.4
V
= 5V
V
V
= 5V
REF
CC
CC
SWEEP SCK, SDI
AND CS/LD
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
= 2V
0V TO V
CC
V
OUT
V
OUT
0.5V/DIV
1V/DIV
DACs A TO G IN
POWER-DOWN MODE
CS/LD
5V/DIV
CLR
5V/DIV
2600 G15
2.5μs/DIV
2600 G14
1μs/DIV
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC VOLTAGE (V)
2600 G13
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
V
OUT
10μV/DIV
V
V
V
= 5V
CC
(DC) = 2V
REF
REF
(AC) = 0.2V
P-P
0
1
2
3
4
5
6
7
8
9
10
CODE = FULL SCALE
SECONDS
2600 G17
1k
10k
100k
1M
FREQUENCY (Hz)
2600 G16
Short-Circuit Output Current
vs VOUT (Sinking)
Short-Circuit Output Current
vs VOUT (Sourcing)
0mA
0mA
V
V
= 5.5V
REF
CODE = 0
1V/DIV
2600 G18
1V/DIV
2600 G19
CC
V
V
= 5.5V
REF
CC
= 5.6V
= 5.6V
CODE = FULL SCALE
V
SWEPT 0V TO V
OUT
CC
V
SWEPT V TO 0V
OUT
CC
2600fc
9
LTC2600/LTC2610/LTC2620
(GN/UFD)
PIN FUNCTIONS
GND (Pin 1/Pin 20): Analog Ground.
SDO(Pin10/Pin10):SerialInterfaceDataOutput.Thispin
is used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising
edges before being output at the next falling edge. SDO
is an active output and does not go high impedance, even
when CS/LD is taken to a logic high level.
V
to V
(Pins 2-5 and 12-15/Pins 1-48 and
OUTA
OUTH
13-16): DAC Analog Voltage Outputs. The output range
is 0 – V
.
REF
REF (Pin 6/Pin 5): Reference Voltage Input. 0V ≤ V
REF
≤ V .
CC
CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specified command (see Table 1)
is executed.
CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V. CMOS and
TTL compatible.
V
(Pin 16/Pin 17): Supply Voltage Input. 2.5V ≤ V
CC
CC
≤ 5.5V.
SCK (Pin 8/Pin 8): Serial Interface Clock Input. CMOS
and TTL compatible.
NC (Pin 6, Pin 12, Pin 18, Pin 19): No connection
SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is ap-
plied to SDI for transfer to the device at the rising edge
of SCK. The LTC2600, LTC2610 and LTC2620 accept input
word lengths of either 24 or 32 bits.
Exposed Pad (Pin 21): Ground. The exposed pad must
be soldered to the PUB.
2600fc
10
LTC2600/LTC2610/LTC2620
BLOCK DIAGRAM
(20)
GND
1
16
15
V
V
(17)
(16)
CC
DAC A
DAC H
(1)
V
2
OUTA
OUTH
DAC B
DAC C
DAC G
DAC F
V
V
V
V
(2)
3
4
14
13
(15)
OUTB
OUTC
OUTG
OUTF
(3)
(4)
(14)
(13)
DAC D
DAC E
V
V
5
12
OUTD
REF
OUTE
CLR
SDO
SDI
(5)
(7)
(8)
6
7
8
11
10
9
(11)
(10)
(9)
POWER-ON
RESET
CONTROL
LOGIC
DECODE
CS/LD
SCK
32-BIT SHIFT REGISTER
2600 BD02
NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE
2600fc
11
LTC2600/LTC2610/LTC2620
TIMING DIAGRAM
t
1
t
6
t
t
3
t
4
2
SCK
SDI
1
2
3
23
24
t
10
t
t
7
5
CS/LD
SDO
t
8
2600 F01
2600fc
12
LTC2600/LTC2610/LTC2620
OPERATION
Power-On Reset
Serial Interface
The LTC2600/LTC2610/LTC2620 clear the outputs to zero
scalewhenpowerisfirstapplied,makingsysteminitializa-
tion consistent and repeatable.
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI and
SCK buffers and enabling the input shift register. Data (SDI
input) is transferred at the next 24 rising SCK edges. The
4-bit command, C3-C0, is loaded first; then the 4-bit DAC
address, A3-A0; and finally the 16-bit data word. The data
word comprises the 16-, 14- or 12-bit input code, ordered
MSB-to-LSB,followedby0,2or4don’t-carebits(LTC2600,
LTC2610 and LTC2620 respectively). Data can only be
transferred to the device when the CS/LD signal is low.The
rising edge of CS/LD ends the data transfer and causes the
device to carry out the action specified in the 24-bit input
word. The complete sequence is shown in Figure 2a.
Forsomeapplications,downstreamcircuitsareactivedur-
ingDACpower-up,andmaybesensitivetononzerooutputs
from the DAC during this time. The LTC2600/2610/2620
contain circuitry to reduce the power-on glitch: the analog
outputstypicallyriselessthan10mVabovezeroscaledur-
ing power on if the power supply is ramped to 5V in 1ms
or more. In general, the glitch amplitude decreases as the
powersupplyramptimeisincreased.SeePower-OnReset
Glitch in the Typical Performance Characteristics section.
Power Supply Sequencing
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the block diagram.
The voltage at REF (Pin 6) should be kept within the
range –0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum
REF
CC
Ratings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at V (Pin 16) is in transition.
CC
Transfer Function
The digital-to-analog transfer function is
k
⎛
⎝
⎞
⎠
VOUT(IDEAL) ⎜
=
V
N ⎟ REF
2
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don’t-care bits are transferred to the device first, followed
by the 24-bit word as just described. Figure 2b shows the
where k is the decimal equivalent of the binary DAC
input code, N is the resolution and V
REF (Pin 6).
is the voltage at
REF
Table 1.
ADDRESS (n)*
COMMAND*
C3 C2 C1 C0
A3 A2 A1 A0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
*Command and address codes not shown are reserved and should not be used.
2600fc
13
LTC2600/LTC2610/LTC2620
OPERATION
INPUT WORD (LTC2600)
COMMAND
ADDRESS
DATA (16 BITS)
D6
D5 D4 D3 D2 D1
A3 A2
A0
D12
D0
C3
C1
C2
A1
D15 D14 D13
MSB
D11 D10 D9 D8
D7
C0
LSB
2600 TBL01
INPUT WORD (LTC2610)
COMMAND
ADDRESS
DATA (14 BITS + 2 DON’T-CARE BITS)
A3 A2
A0
D12
D6
D5 D4 D3 D2 D1
D0
X
X
X
C3
C1
A1
D13
D11 D10 D9 D8
D7
C2
C0
MSB
LSB
2600 TBL02
INPUT WORD (LTC2620)
COMMAND
ADDRESS
DATA (12 BITS + 4 DON’T-CARE BITS)
A3 A2
A0
D6
D5 D4 D3 D2 D1
D0
X
X
X
C3
C1
A1
D11 D10 D9 D8
MSB
D7
C2
C0
LSB
2600 TBL03
32-bit sequence. The 32-bit word is required for daisy-
chain operation, and is also available to accommodate
microprocessors which have a minimum word width of
16 bits (2 bytes).
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. Because of this, the devices can be addressed and
controlledindividuallybysimplyconcatenatingtheirinput
words; the first instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
first device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
TheSDOoutputcanbeusedtofacilitatecontrolofmultiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
2600fc
14
LTC2600/LTC2610/LTC2620
OPERATION
Power-Down Mode
Voltage Outputs
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer amplifiers and reference inputs are disabled, and
drawessentiallyzerocurrent.TheDACoutputsareputinto
a high-impedance state, and the output pins are passively
pulledtogroundthroughindividual90kresistors.Whenall
eight DACs are powered down, the master bias generation
circuit is also disabled. Input- and DAC-register contents
are not disturbed during power-down.
Eachofthe8rail-to-railamplifierscontainedintheseparts
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
permilliampereofforcedloadcurrentchangeisexpressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combi-
nation with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply and reference currents
are reduced by approximately 1/8 for each DAC powered
down; the effective resistance at REF (pin 6) rises accord-
ingly, becoming a high-impedance input (typically > 1GΩ)
when all eight DACs are powered down.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 1. The selected DAC is powered up as its voltage
output is updated.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
areinapowered-downstatepriortotheupdatecommand,
the power-up delay is 5μs. If, on the other hand, all eight
DACs are powered down, then the master bias genera-
tion circuit is also disabled and must be restarted. In this
Board Layout
TheexcellentloadregulationandDCcrosstalkperformance
of these devices is achieved in part by keeping “signal”
and“power”groundsseparatedinternallyandbyreducing
shared internal resistance to just 0.005Ω.
case, the power-up delay is greater: 12μs for V = 5V,
CC
30μs for V = 3V.
CC
2600fc
15
LTC2600/LTC2610/LTC2620
OPERATION
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
add directly to the effective DC output impedance of the
device (typically 0.025Ω), and will degrade DC crosstalk.
Note that the LTC2600/LTC2610/LTC2620 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
The PC board should have separate areas for the analog
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown
in Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to V . If V = V and the DAC
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shielditfromnoise.Analoggroundshouldbeacontinuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
CC
REF
CC
full-scale error (FSE) is positive, the output for the highest
codes limits at V as shown in Figure 3c. No full-scale
CC
limiting can occur if V is less than V – FSE.
REF
CC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
2600fc
16
LTC2600/LTC2610/LTC2620
OPERATION
2600fc
17
LTC2600/LTC2610/LTC2620
OPERATION
POSITIVE
FSE
V
REF
= V
CC
V
= V
CC
REF
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
32, 768
65, 535
INPUT CODE
(a)
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
2600 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2600fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
18
LTC2600/LTC2610/LTC2620
PACKAGE DESCRIPTION
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 p 0.05
2.65 p 0.05
4.50 p 0.05
3.10 p 0.05
1.50 REF
3.65 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
0.75 p 0.05
1.50 REF
19
4.00 p 0.10
R = 0.05 TYP
(2 SIDES)
20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
2.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD20) QFN 0506 REV
B
0.25 p 0.05
0.50 BSC
0.200 REF
R = 0.115
TYP
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2600fc
19
LTC2600/LTC2610/LTC2620
TYPICAL APPLICATION
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
V
V
V
CC
CC
REF
1
1
TP1
TP2
C1
R1, R3, R4
0.1μF
are 4.99k, 1%
R1
R3
R4
4
5
6
7
R2
7.5k
V
SDA
SS
C2
0.1μF
3
2
6
A2 SCL
11
16
REF
CLR
V
A1 WP
CC
C3
0.1μF
1
8
1
1
1
1
1
1
1
1
1
1
2
TP3
TP14
GND
A0
V
CC
V
V
V
OUTA
OUTB
OUTC
OUTD
DAC A
3
U1
24LC025
4
TP4
DAC B
TP15
GND
SCK
8
7
5
SCK
V
CS
12
13
14
15
TP5
DAC C
LS/LD
V
OUTE
14
12
10
8
6
4
13
11
9
7
5
V
OUTF
+
+
+
+
+
+
+
+
9
TP6
DAC D
SDI
V
V
+
+
+
+
+
+
OUTG
OUTH
10
SDO
MOSI
MISO
TP7
DAC E
GND
1
V
V
V
REF
CC
CC
U2
LTC2600CGN
3
1
1
TP8
DAC F
TP16
2
5V
V
IN
C4
C5
0.1μF
J1
HD2X7
TP9
DAC G
0.1μF
R5
7.5k
JP1
TP10
DAC H
R8
22Ω
ON/OFF
3
2
C10
100pF
DISABLE
ADC
7
4
3
2
8
V
IN
1
U4
V
V
MUXOUT ADCIN FS
CC CC
SET
LT1236ACS8-5
2
6
V
REF
V
IN
V
OUT
9
CH0
1
1
5V
TP11
REF
23
R6
7.5k
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
GND
4
CSADC
V
2
3
4.096V
20
25
19
21
24
CS
C7
4.7μF
6.3V
CSMUX
SCK
C6
JP2
V
0.1μF
REF
4-/8-CHANNEL
MUX
20-BIT
ADC
+
SCK
CLK
U5
D
IN
–
LT1461ACS8-4
SD0
2
3
6
V
LTC2424/LTC2428
CC
V
V
OUT
IN
1
26
SHDN
GND
FO
1
1
5V
TP12
CC
REF
5
ZS
SET
GND GND GND GND GND GND GND
16 18 22 27 28
R7
7.5k
V
2
3
C9
0.1μF
C8 REGULATOR
4
1
6
U3
LTC2428CG
1μF
16V
JP3
CC
TP13
GND
V
5V
RELATED PARTS
PART NUMBER
DESCRIPTION
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
COMMENTS
LTC1458: V = 4.5V to 5.5V, V
LTC1458/LTC1458L
= 0V to 4.096V
OUT
OUT
CC
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1654
Dual 14-Bit Rail-to-Rail V
DAC
Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA
= 5V(3V), Low Power, Deglitched
OUT
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1821
Single 16-Bit V
DAC with Serial Interface in SO-8
V
CC
OUT
Parrallel 5V/3V 16-Bit V
DAC
Low Power, Deglitched, Rail-to-Rail V
OUT
OUT
Octal 10/8-Bit V
DAC in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2μs for 10V Step
2600fc
LT 0309 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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