LTC2619CGN-1#PBF [Linear]
LTC2619 - Quad 16-/14-/12-Bit Rail-to-Rail DACs with I<sup>2</sup>C Interface; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C;型号: | LTC2619CGN-1#PBF |
厂家: | Linear |
描述: | LTC2619 - Quad 16-/14-/12-Bit Rail-to-Rail DACs with I<sup>2</sup>C Interface; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
文件: | 总22页 (文件大小:327K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit
Rail-to-Rail DACs with
2
I C Interface
Features
Description
TheLTC®2609/LTC2619/LTC2629arequad16-,14-and12-
bit,2.7Vto5.5Vrail-to-railvoltageoutputDACsina16-lead
SSOPpackage.Theyhavebuilt-inhighperformanceoutput
buffers and are guaranteed monotonic.
n
Smallest Pin-Compatible Quad DACs:
LTC2609: 16 Bits
LTC2619: 14 Bits
LTC2629: 12 Bits
n
Guaranteed Monotonic Over Temperature
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply, volt-
age-output DACs.
n
Separate Reference Inputs
n
27 Selectable Addresses
2
n
™
400kHz I C Interface
n
n
n
n
n
n
Wide 2.7V to 5.5V Supply Range
2
Thepartsusea2-wire, I Ccompatibleserialinterface. The
Low Power Operation: 250µA per DAC at 3V
Individual Channel Power Down to 1µA (Max)
High Rail-to-Rail Output Drive ( 15mA, Min)
Ultralow Crosstalk Between DACs (5µV)
LTC2609/LTC2619/LTC2629: Power-On Reset to
Zero-Scale
LTC2609/LTC2619/LTC2629 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
The LTC2609/LTC2619/LTC2629 incorporate a power-on
resetcircuit.Duringpower-up,thevoltageoutputsriseless
than 10mV above zero-scale; after power-up, they stay at
zero-scale until a valid write and update take place. The
power-on reset circuit resets the LTC2609-1/LTC2619-1/
LTC2629-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update take place.
n
n
LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset
to Mid-Scale
Tiny 16-Lead Narrow SSOP Package
applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245. Patent pending.
n
Mobile Communications
n
Process Control and Industrial Automation
n
Automatic Test Equipment and Instrumentation
Block Diagram
2
1
16
REFLO
GND
V
CC
REFA
REFD
15
3
4
V
V
OUTD
OUTA
Differential Nonlinearity
DAC A
DAC D
DAC C
14
(LTC2609)
1.0
V
V
V
= 5V
REF
OUTB
CC
V
OUTC
13
REFC
12
0.8
0.6
= 4.096V
DAC B
5
6
REFB
0.4
0.2
CONTROL
LOGIC
0
–0.2
–0.4
–0.6
–0.8
–1.0
32-BIT SHIFT REGISTER
CA0
11
CA1
10
CA2
SCL
SDA
8
9
ADDRESS
DECODE
LOGIC
2
I C
0
16384
32768
CODE
49152
65535
INTERFACE
2609 G02
7
2609 BD
26091929fb
ꢀ
LTC2609/LTC2619/LTC2629
aBsolute maximum ratings (Note 1)
Any Pin to GND............................................–0.3V to 6V
TOP VIEW
Any Pin to V ............................................–6V to 0.3V
CC
GND
REFLO
REFA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Maximum Junction Temperature........................... 125°C
Storage Temperature Range.................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
Operating Temperature Range:
REFD
V
OUTD
V
OUTA
V
OUTC
V
REFC
CA0
CA1
SDA
OUTB
LTC2609C/LTC2619C/LTC2629C
REFB
CA2
LTC2609C-1/LTC2619C-1/LTC2629C-1 .... 0°C to 70°C
LTC2609I/LTC2619I/LTC2629I
SCL
LTC2609I-1/LTC2619I-1/LTC2629I-1....–40°C to 85°C
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 135°C, θ = 150°C/W
JA
JMAX
orDer inFormation
LEAD FREE FINISH
LTC2609CGN#PBF
LTC2609CGN-1#PBF
LTC2609IGN#PBF
LTC2609IGN-1#PBF
LTC2619CGN#PBF
LTC2619CGN-1#PBF
LTC2619IGN#PBF
LTC2619IGN-1#PBF
LTC2629CGN#PBF
LTC2629CGN-1#PBF
LTC2629IGN#PBF
LTC2629IGN-1#PBF
TAPE AND REEL
PART MARKING*
2609
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
TEMPERATURE RANGE
LTC2609CGN#TRPBF
LTC2609CGN-1#TRPBF
LTC2609IGN#TRPBF
LTC2609IGN-1#TRPBF
LTC2619CGN#TRPBF
LTC2619CGN-1#TRPBF
LTC2619IGN#TRPBF
LTC2619IGN-1#TRPBF
LTC2629CGN#TRPBF
LTC2629CGN-1#TRPBF
LTC2629IGN#TRPBF
LTC2629IGN-1#TRPBF
0°C to 70°C
26091
2609I
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
2619I1
2619
26191
2619I
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
2619I1
2629
26291
2629I
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
2629I1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
26091929fb
ꢁ
LTC2609/LTC2619/LTC2629
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted.
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
l
12
12
14
14
16
16
Bits
Bits
LSB
LSB
Monotonicity
(Note 2)
(Note 2)
DNL
INL
Differential Nonlinearity (Note 2)
Integral Nonlinearity
Load Regulation
0.5
4
1
16
1
64
1
4
16
V
= V = 5V, Mid-Scale
OUT
OUT
REF
I
I
CC
l
l
= 0mA to 15mA Sourcing
= 0mA to 15mA Sinking
0.02 0.125
0.02 0.125
0.1
0.1
0.5
0.5
0.3
0.4
2
2
LSB/mA
LSB/mA
V
= V = 2.7V, Mid-Scale
OUT
OUT
REF
I
I
CC
l
l
= 0mA to 7.5mA Sourcing
= 0mA to 7.5mA Sinking
0.04 0.25
0.05 0.25
0.2
0.2
1
1
0.7
0.8
4
4
LSB/mA
LSB/mA
l
l
ZSE
Zero-Scale Error
Offset Error
Code = 0
(Note 4)
1.5
1
9
9
1.5
1
9
9
1.5
1
9
9
mV
mV
V
OS
V
OS
Temperature
6
6
6
µV/°C
Coefficient
Gain Error
Gain Temperature
Coefficient
l
GE
0.1
3
0.7
0.1
3
0.7
0.1
3
0.7
%FSR
ppm/°C
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded,
unless otherwise noted. (Note 9)
SYMBOL PARAMETER
PSR Power Supply Rejection
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
10%
–80
dB
l
l
R
OUT
DC Output Impedance
V
REF
V
REF
= V = 5V, Mid-Scale; –15mA ≤ I ≤ 15mA
OUT
0.030
0.035
0.15
0.15
Ω
Ω
CC
= V = 2.7V, Mid-Scale; –7.5mA ≤ I
≤ 7.5mA
CC
OUT
DC Crosstalk (Note 10)
Due to Full-Scale Output Change (Note 11)
Due to Load Current Change
Due to Powering Down (Per Channel)
5
4
4
µV
µV/mA
µV
ISC
Short-Circuit Output Current
V
= 5.5V, V = 5.5V
CC REF
l
l
Code: Zero-Scale; Forcing Output to V
15
15
36
36
60
60
mA
mA
CC
Code: Full-Scale; Forcing Output to GND
V
CC
= 2.7V, V = 2.7V
REF
l
l
Code: Zero-Scale; Forcing Output to V
7.5
7.5
22
30
50
50
mA
mA
CC
Code: Full-Scale; Forcing Output to GND
Reference Input
Input Voltage Range
l
l
0
V
V
kΩ
pF
CC
Resistance
Normal Mode
88
125
14
160
Capacitance
l
l
I
Reference Current, Power Down Mode DAC Powered Down
0.001
1
µA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
2.7
5.5
V
CC
l
l
l
l
I
V
V
= 5V (Note 3)
= 3V (Note 3)
1.25
1
0.35
0.15
2
1.6
1
mA
mA
µA
CC
CC
CC
DAC Powered Down (Note 3) V = 5V
CC
CC
DAC Powered Down (Note 3) V = 3V
1
µA
26091929fb
ꢂ
LTC2609/LTC2619/LTC2629
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted. (Note 9)
Digital I/O (Note 9)
l
V
V
V
V
Low Level Input Voltage
(SDA and SCL)
0.3V
V
V
IL
CC
l
l
l
l
l
l
High Level Input Voltage
(SDA and SCL)
0.7V
CC
IH
Low Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
See Test Circuit 1
See Test Circuit 2
See Test Circuit 2
See Test Circuit 2
Sink Current = 3mA
0.15V
V
IL(CAn)
IH(CAn)
CC
High Level Input Voltage on CAn
(n = 0, 1, 2)
0.85V
V
CC
R
R
R
Resistance from CAn (n = 0, 1, 2)
10
10
kΩ
kΩ
MΩ
INH
INL
INF
OL
to V to Set CAn = V
CC
CC
Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
Resistance from CAn (n = 0, 1, 2)
2
0
to V or GND to Set CAn = Float
CC
l
l
V
Low Level Output Voltage
Output Fall Time
0.4
V
t
t
I
V = V
B
to V = V
,
20 + 0.1C
250
ns
OF
O
IH(MIN)
O
IL(MAX)
B
C = 10pF to 400pF (Note 7)
l
Pulse Width of Spikes Suppressed by
Input Filter
0
50
ns
SP
l
l
l
l
Input Leakage
0.1V ≤ V ≤ 0.9V
1
µA
pF
pF
pF
IN
CC
IN
CC
C
C
C
I/O Pin Capacitance
(Note 12)
10
IN
Capacitive Load for Each Bus Line
400
10
B
External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
CAX
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded,
unless otherwise noted.
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
SYMBOL PARAMETER
AC Performance
CONDITIONS
t
Settling Time (Note 5)
0.024% ( 1LSB at 12 Bits)
0.006% ( 1LSB at 14 Bits)
0.0015% ( 1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
S
Settling Time for 1LSB Step
(Note 6)
0.024% ( 1LSB at 12 Bits)
0.006% ( 1LSB at 14 Bits)
0.0015% ( 1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
Multiplying Bandwidth
Output Voltage Noise Density
0.7
1000
12
180
120
100
0.7
1000
12
180
120
100
0.7
1000
12
180
120
100
V/µs
pF
nV • s
kHz
nV/√Hz
nV/√Hz
At Mid-Scale Transition
e
At f = 1kHz
At f = 10kHz
n
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µV
P-P
26091929fb
ꢃ
LTC2609/LTC2619/LTC2629
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 2.7V to 5.5V
CC
l
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
0
0.6
400
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
SCL
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
HD(STA)
LOW
HIGH
SU(STA)
HD(DAT)
SU(DAT)
r
1.3
0.6
0.6
0
0.9
Data Set-Up Time
100
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
(Note 7)
(Note 7)
20 + 0.1C
20 + 0.1C
0.6
300
300
B
B
f
SU(STO)
BUF
1.3
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
400
1
l
t
LDAC Low Pulse Width
20
ns
2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: V = 5V, V = 4.096V. DAC is stepped 1LSB between half scale
CC REF
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: C = capacitance of one bus line in pF.
B
Note 8: All values refer to V
and V
levels.
IH(MIN)
IL(MAX)
Note 2: Linearity and monotonicity are defined from code k to code
L
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
N
N
2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),
L
L
REF
rounded to the nearest whole code. For V = 4.096V and N = 16, k =
REF
L
Note 10: DC crosstalk is measured with V = 5V, REFA = REFB = REFC
CC
256 and linearity is defined from code 256 to code 65,535.
= REFD = 4.096V, with the measured DAC at mid-scale, unless otherwise
noted.
Note 3: SDA, SCL at 0V or V , CA0, CA1 and CA2 floating.
CC
Note 4: Inferred from measurement at code kL (see Note 2) and at full-Scale.
Note 5: V = 5V, V = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
Note 11: R = 2kΩ to GND or V
.
CC
L
CC
REF
Note 12: Guaranteed by design and not production tested.
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
26091929fb
ꢄ
LTC2609/LTC2619/LTC2629
typical perFormance characteristics
LTC2609
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
32
24
1.0
0.8
32
24
V
V
= 5V
REF
V
= 5V
CC
= 4.096V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
V
= 4.096V
0.6
16
16
0.4
8
INL (POS)
INL (NEG)
8
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–8
–16
–24
–32
–16
–24
–32
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–50 –30 –10 10
30
50
70
90
TEMPERATURE (°C)
2609 G01
2609 G02
2609 G03
DNL vs Temperature
INL vs VREF
DNL vs VREF
1.0
0.8
32
24
1.5
1.0
V
V
= 5V
REF
V
CC
= 5.5V
V
= 5.5V
CC
CC
= 4.096V
0.6
16
0.4
0.5
INL (POS)
INL (NEG)
DNL (POS)
DNL (NEG)
8
0.2
DNL (POS)
DNL (NEG)
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–8
–0.5
–1.0
–1.5
–16
–24
–32
–50 –30 –10 10
30
50
70
90
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
V
(V)
REF
REF
2609 G04
2609 G05
2609 G06
Settling to 1LSB
Settling of Full-Scale Step
V
V
OUT
100µV/DIV
OUT
100µV/DIV
12.3µs
9.7µs
9TH CLOCK
OF 3RD DATA
BYTE
9TH CLOCK OF
3RD DATA ꢀYTE
SCL
2V/DIV
SCR
2V/DIV
2609 G07
2609 G08
2µs/DIV
5µs/DIV
V
= 5V, V
= 4.096V
REF
SETTLING TO 1LSꢀ
CC
1/4 SCALE TO 3/4 SCALE STEP
V
= 5V, V
= 4.096V
CC
REF
R
= 2k, C = 200pF
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
L
L
AVERAGE OF 2048 EVENTS
26091929fb
ꢅ
LTC2609/LTC2619/LTC2629
typical perFormance characteristics
LTC2619
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to 1LSB
8
6
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
4
0.4
V
OUT
2
0.2
100µV/DIV
0
0
9TH CLOCK
OF 3RD DATA
BYTE
SCL
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
8.9µs
2609 G11
2µs/DIV
V
= 5V, V
= 4.096V
REF
CC
1/4 SCALE TO 3/4 SCALE STEP
R
= 2k, C = 200pF
0
4096
8192
CODE
12288
16383
0
4096
8192
CODE
12288
16383
L
L
AVERAGE OF 2048 EVENTS
2609 G09
2609 G10
LTC2629
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to 1LSB
2.0
1.5
1.0
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
1.0
6.8µs
0.4
V
OUT
0.5
0.2
1mV/DIV
0
0
9TH CLOCK
OF 3RD DATA
BYTE
SCL
2V/DIV
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
2609 G14
2µs/DIV
= 4.096V
V
= 5V, V
REF
CC
1/4 SCALE TO 3/4 SCALE STEP
= 2k, C = 200pF
R
0
1024
2048
CODE
3072
4095
0
1024
2048
CODE
3072
4095
L
L
AVERAGE OF 2048 EVENTS
2609 G12
2609 G13
26091929fb
ꢆ
LTC2609/LTC2619/LTC2629
typical perFormance characteristics
LTC2609/LTC2619/LTC2629
Current Limiting
Load Regulation
Offset Error vs Temperature
0.10
0.08
0.06
0.04
0.02
0
1.0
0.8
3
2
CODE = MID-SCALE
CODE = MID-SCALE
V
= V = 5V
CC
REF
0.6
V
= V = 3V
CC
REF
0.4
1
0.2
0
0
V
= V = 5V
CC
REF
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V = 3V
CC
REF
–1
–2
–3
V
= V = 5V
CC
V
= V = 3V
REF CC
REF
–40 –30 –20 –10
0
10 20 30 40
–35 –25 –15 –5
5
15
25
35
–50 –30 –10 10
30
50
70
90
I
(mA)
I
(mA)
OUT
TEMPERATURE (°C)
OUT
2609 G15
2609 G16
2609 G17
Zero-Scale Error vs Temperature
Gain Error vs Temperature
Offset Error vs VCC
3
2.5
2.0
1.5
1.0
0.5
0
0.4
0.3
3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–1
–2
–3
–50 –30 –10 10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2.5
3
3.5
4
4.5
5
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
2609 G18
2609 G19
2609 G20
Gain Error vs VCC
ICC Shutdown vs VCC
0.4
0.3
450
400
350
300
250
200
150
100
50
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
V
(V)
V
(V)
CC
CC
2609 G22
2609 G21
26091929fb
ꢇ
LTC2609/LTC2619/LTC2629
typical perFormance characteristics
LTC2609/LTC2619/LTC2629
Large-Signal Response
Mid-Scale Glitch Impulse
Power-On Reset Glitch
V
OUT
V
CC
10mV/DIV
V
1V/DIV
OUT
0.5V/DIV
4mV PEAK
SCL
2V/DIV
V
= V = 5V
CC
V
REF
OUT
1/4 SCALE TO 3/4 SCALE
10mV/DIV
2609 G24
2609 G23
2609 G25
2.5µs/DIV
250µs/DIV
2.5µs/DIV
Headroom at Rails
vs Output Current
Power-On Reset to Mid-Scale
Supply Current vs Logic Voltage
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
V
= V
CC
CC
REF
5V SOURCING
SWEEP SCL
AND SDA
0V TO V
AND V TO 0V
CC
CC
3V SOURCING
1V/DIV
V
CC
5V SINKING
V
OUT
3V SINKING
2606 G27
0
1
2
3
4
I
5
(mA)
6
7
8
9
10
500µs/DIV
0
0.5
1
1.5
2
2.5
5
3
3.5 4 4.5
LOGIC VOLTAGE (V)
OUT
2609 G26
2609 G28
26091929fb
ꢈ
LTC2609/LTC2619/LTC2629
typical perFormance characteristics
LTC2609/LTC2619/LTC2629
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
V
OUT
–15
–18
–21
–24
–27
–30
–33
–36
10µV/DIV
V
V
V
= 5V
CC
(DC) = 2V
REF
REF
0
1
2
3
4
5
6
7
8
9
10
(AC) = 0.2V
P-P
SECONDS
CODE = FULL SCALE
2609 G30
1k
10k
100k
1M
FREQUENCY (Hz)
2609 G29
Short-Circuit Output Current
vs VOUT (Sinking)
Short-Circuit Output Current
vs VOUT (Sourcing)
50
40
30
20
0
V = 5.5V
CC
V = 5.6V
REF
V = 5.5V
CC
V = 5.6V
REF
CODE = 0
SWEPT 0V TO V
CODE = FULL-SCALE
SWEPT V TO 0V
–10
–20
–30
V
V
OUT
CC
OUT
CC
10
0
–40
–50
0
2
3
4
5
6
1
0
2
3
4
5
6
1
1V/DIV
1V/DIV
2609 G31
2609 G32
26091929fb
ꢀ0
LTC2609/LTC2619/LTC2629
pin Functions
GND (Pin 1): Analog Ground.
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance pin while data is shifted in and is an
open-drainN-channeloutputduringacknowledgment.SDA
REFLO (Pin 2): Reference Low. The voltage at this pin
sets the zero-scale (ZS) voltage of all DACs. This pin can
be raised up to 1V above ground at V = 5V or 100mV
CC
requires a pull-up resistor or current source to V .
CC
above ground at V = 3V.
CC
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V , GND
CC
REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage
2
or leave it floating to select an I C slave address for the
Inputs for each DAC. REFx sets the full-scale voltage of
part (Table 1).
the DACs. REFLO ≤ REFx ≤ V .
CC
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V , GND
CC
V
to V
(Pins 4, 5, 13, 14): DAC Analog Voltage
OUTA
OUTD
2
or leave it floating to select an I C slave address for the
Outputs. The output range is from REFLO to REFx.
part (Table 1).
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V , GND
CC
V
(Pin 16): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V.
2
CC
CC
or leave it floating to select an I C slave address for the
part (Table 1).
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to V .
CC
26091929fb
ꢀꢀ
LTC2609/LTC2619/LTC2629
Block Diagram
2
1
16
REFLO
GND
V
CC
REFA
REFD
15
3
4
V
V
OUTD
OUTA
DAC A
DAC B
DAC D
DAC C
14
V
OUTB
V
OUTC
5
6
13
REFC
12
REFB
CONTROL
LOGIC
32-BIT SHIFT REGISTER
CA0
11
CA1
10
CA2
SCL
SDA
8
9
ADDRESS
DECODE
LOGIC
2
I C
INTERFACE
7
2609 BD
26091929fb
ꢀꢁ
LTC2609/LTC2619/LTC2629
test circuits
Test Circuit 1
Test Circuit 2
V
DD
R /R /R
INH INL INF
100Ω
/V
CAn
CAn
V
IH(CAn) IL(CAn)
GND
2609 TC
timing Diagram
SDA
t
f
t
SU(DAT)
t
t
t
r
t
t
t
t
BUF
f
LOW
HD(STA)
SP
r
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
S
S
P
S
HD(DAT)
2609 F01
ALL VOLTAGE LEVELS REFER TO V
AND V
LEVELS
IH(MIN)
IL(MAX)
Figure 1
26091929fb
ꢀꢂ
LTC2609/LTC2619/LTC2629
operation
Power-On Reset
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero-scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619-1/LTC2629-1setthevoltageoutputstomid-scale
when power is first applied.
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
2
usingthestandard2-wireI Cinterface.TheTimingDiagram
Forsomeapplications,downstreamcircuitsareactivedur-
ingDACpower-upandmaybesensitivetononzerooutputs
from the DAC during this time. The LTC2609/LTC2619/
LTC2629 contain circuitry to reduce the power-on glitch;
furthermore, the glitch amplitude can be made arbitrarily
small by reducing the ramp rate of the power supply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
duringpower-on. SeePower-OnResetGlitchintheTypical
Performance Characteristics section.
(Figure 1) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
thesepull-upresistorsisdependentonthepowersupplyand
2
2
can be obtained from the I C specifications. For an I C bus
operatinginthefastmode,anactivepull-upwillbenecessary
if the bus capacitance is greater than 200pF. The V power
CC
shouldnotberemovedfromtheLTC2609/LTC2619/LTC2629
2
2
when the I C bus is active to avoid loading the I C bus lines
through the internal ESD protection diodes.
Power Supply Sequencing
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629.TheLTC2609/LTC2619/LTC2629donotrespond
to a read from the master.
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REFx ≤ V + 0.3V (see Absolute
CC
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V (Pin 16) is
CC
The START (S) and STOP (P) Conditions
in transition. The REFx pins can be clamped to stay below
the maximum voltage by using Schottky diodes as shown
in Figure 2, thereby easing sequencing constraints.
Whenthebusisnotinuse,bothSCLandSDAmustbehigh.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
V
CC
16
V
CC
LTC2609/
LTC2619/
LTC2629
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
3
REFA
REFB
REFC
REFD
REFA
REFB
REFC
REFD
6
12
15
2609 F02
2
another I C device.
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
Acknowledge
Transfer Function
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releasestheSDAline(HIGH)duringtheAcknowledgeclock
The digital-to-analog transfer function is:
k
N
VOUT(IDEAL)
=
[REFx – REFLO] + REFLO
2
pulse. The slave-receiver must pull down the SDA bus line
26091929fb
ꢀꢃ
LTC2609/LTC2619/LTC2629
operation
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2609/LTC2619/LTC2629 respond to a write by a
master in this manner. The LTC2609/LTC2619/LTC2629
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2609, LTC2619 and
LTC2629 parts to be accomplished with one 3-byte write
2
transaction on the I C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
Chip Address
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximumcapacitiveloadallowedontheaddresspins(CA0,
CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are floating.
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V , GND or float. This results
CC
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Write Word Protocol
Table 1. Slave Address Map
CA2
GND
CA1
GND
CA0
GND
SA6 SA5 SA4 SA3 SA2 SA1 SA0
The master initiates communication with the LTC2609/
LTC2619/LTC2629withaSTARTconditionanda7-bitslave
address followed by the Write bit (W) = 0. The LTC2609/
LTC2619/LTC2629 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data.TheLTC2609/LTC2619/LTC2629acknowledgeseach
byte of data by pulling the SDA line low at the 9th clock of
eachdatabytetransmission.Afterreceivingthreecomplete
bytesofdata,theLTC2609/LTC2619/LTC2629executesthe
command specified in the 24-bit input word.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
GND
FLOAT
GND
GND
V
CC
GND
FLOAT
GND
GND
FLOAT FLOAT
FLOAT
GND
V
CC
GND
V
V
V
GND
CC
CC
CC
GND
FLOAT
GND
V
CC
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
FLOAT
V
CC
If more than three data bytes are transmitted after a valid
7-bitslaveaddress,theLTC2609/LTC2619/LTC2629donot
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
FLOAT FLOAT
GND
FLOAT FLOAT FLOAT
FLOAT FLOAT
V
CC
FLOAT
FLOAT
FLOAT
V
CC
V
CC
V
CC
GND
The format of the three data bytes is shown in Figure 3.
The first byte of the input word consists of the 4-bit com-
mand and 4-bit DAC address. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629
respectively).AtypicalLTC2609writetransactionisshown
in Figure 4.
FLOAT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
FLOAT
GND
V
CC
FLOAT
GND
FLOAT FLOAT
FLOAT
V
CC
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
V
V
V
GND
CC
CC
CC
FLOAT
V
CC
GLOBAL ADDRESS
26091929fb
ꢀꢄ
LTC2609/LTC2619/LTC2629
operation
Write Word Protocol for LTC2609/LTC2619/LTC1629
W
A
1STDATABYTE
A
2NDDATABYTE
A
3RDDATABYTE
A
P
S
SLAVEADDRESS
INPUT WORD
Input Word (LTC2609)
C3
C1
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C2
C0
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
Input Word (LTC2619)
C3
C1
A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
C2
C0
1ST DATA BYTE
2ND DATA BYTE
3RD DATA BYTE
Input Word (LTC2629)
C3
C1
D11 D10 D9 D8 D7 D6 D5 D4
2ND DATA BYTE
D2 D1 D0
D3
X
X
X
C2
C0 A3 A2 A1 A0
2609 F03
1ST DATA BYTE
3RD DATA BYTE
Figure 3
Power-Down Mode
Table 2
COMMAND*
C3 C2 C1 C0
Forpower-constrainedapplications,power-downmodecan
be used to reduce the supply current whenever less than
four outputs are needed. When in power-down, the buffer
amplifiers, bias circuits and reference inputs are disabled,
and draw essentially zero current. The DAC outputs are
put into a high impedance state, and the output pins are
passively pulled to REFLO through individual 90k resis-
tors. Input- and DAC-register contents are not disturbed
during power down.
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
ADDRESS (n)*
A3 A2 A1 A0
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combi-
nation with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply current is reduced by
approximately1/4foreachDACpowereddown. Theeffec-
tive resistance at REFx (Pins 3, 6, 12 and 15) are at high
impedance(typically>1GΩ)whenthecorrespondingDACs
are powered down. Normal operation can be resumed by
executing any command which includes a DAC update,
as shown in Table 2.
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
All DACs
*Command and address codes not shown are reserved and should not be used.
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than four DACs are in a powered-down state prior to
theupdatecommand, thepower-updelaytimeis5µs. Ifon
the other hand, all four DACs are powered down, then the
26091929fb
ꢀꢅ
LTC2609/LTC2619/LTC2629
operation
main bias generation circuit block has been automatically
shut down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power-up delay time is
The PC board should have separate areas for the analog
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
12µs (for V = 5V) or 30µs (for V = 3V).
CC
CC
Voltage Output
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
2.7V).
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shielditfromnoise.Analoggroundshouldbeacontinuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
permilliampereofforcedloadcurrentchangeisexpressed
in LSB/mA.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground.ResistancefromtheGNDpintosystemstarground
should be as low as possible. When a zero-scale DAC
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.035Ω when driving a load well away from
the rails.
voltage of zero is desired, REFLO (Pin 2) should
output
be connected to system star ground.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure4b.Similarly,limitingcanoccurnearfull-scalewhen
The amplifier is stable driving capacitive loads of up to
1000pF.
the REF pins are tied to V . If REFx = V and the DAC
CC
CC
full-scale error (FSE) is positive, the output for the highest
codes limits at V as shown in Figure 4c. No full-scale
CC
Board Layout
limiting can occur if REFx is less than V – FSE.
CC
TheexcellentloadregulationandDCcrosstalkperformance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
26091929fb
ꢀꢆ
LTC2609/LTC2619/LTC2629
operation
26091929fb
ꢀꢇ
LTC2609/LTC2619/LTC2629
operation
26091929fb
ꢀꢈ
LTC2609/LTC2619/LTC2629
typical application
Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters
V
REF
REFA
JP3
REFB
JP4
REFC
JP5
REFD
JP6
ADC REF
JP7
1
3
5
A
B
2
4
6
1
3
5
A
B
2
4
6
1
3
5
A
B
2
4
6
1
3
5
A
B
2
4
6
1
3
5
A
B
2
4
6
C1
0.1µF
V
C
C
C
C
C
CC
V
CC
5V
REF
16
4.096V
2.048V
REF
REF
V
CC
LTC2609CGN
11
10
7
4
E2
E3
E4
E5
E6
E7
E8
E9
CA0
CA1
CA2
V
V
OUTA
OUTA
3
REFA
REFA
5
V
V
OUTB
OUTB
6
REFB
REFB
13
12
14
15
V
V
OUTC
OUTC
REFC
REFC
9
8
SDA
SCL
V
V
OUTD
OUTD
2
I C
REFD
REFD
E10
E11
REFLO GND
V
V
GND
GND
REF
CC
C5
0.1µF
2
1
C4
0.1µF
JP1 REFLO
C3
100pF
R5
7.5k
EXT
EXT REFLO
REFLO
R8
22Ω
3
JP2
ON/OFF
GND
V
CC
7
4
2
8
DISABLE
ADC
MUXOUT ADCIN FSSET
V
V
LTC2428CG
CH0
CC CC
V
V
V
5V
REF
IN
IN
IN
9
LT1790ACS6-5
6
5
10 CH1
11 CH2
12 CH3
13 CH4
14 CH5
15 CH6
17 CH7
4
3
R6
23
V
V
OUT
IN
C7
C6
CSADC
7.5k
20
25
19
21
24
CS
1µF
0.1µF
NC
NC
CSMUX
SCK
CLK
DIN
SD0
F0
6.3V
8-CHANNEL
MUX
20-BIT
ADC
+
GND GND
SCK
MOSI
MISO
SPI
BUS
–
1
2
26
4.096V
5
ZSSET
REF
LT1790ACS6-4.096
R7
7.5k
6
4
GND GND GND GND GND GND GND
16 18 22 27 28
V
V
OUT
IN
C9
1µF
6.3V
C8
0.1µF
1
6
3
5
2609 TA02
NC
NC
GND GND
1
2
2.048V
REF
LT1790ACS6-2.048
6
4
V
V
OUT
IN
C11
1µF
6.3V
C10
0.1µF
3
5
NC
NC
GND GND
1
2
26091929fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢁ0
LTC2609/LTC2619/LTC2629
revision history
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/09 Update Manufacturer’s Information on Typical Application
Revise Receiver Input Hysteresis Conditions
Revise Block Diagram
1
3
7
Revise Figure 1.
8
Update Manufacturer’s Information on Figure 10
Update Tables 1 and 3
10
12
B
3/10
Revised C- and I-Grade Temperature Ranges in Order Information Section
2
26091929fb
ꢁꢀ
LTC2609/LTC2619/LTC2629
package Description
GN Package
16-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 p.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 p.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 p .004
(0.38 p 0.10)
s 45o
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
relateD parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.096V
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
OUT
CC
LTC1654
Dual 14-Bit Rail-to-Rail V
DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
= 5V(3V), Low Power, Deglitched
OUT
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1821
Single 16-Bit V
DACs with Serial Interface in SO-8
V
CC
OUT
Parallel 5V/3V 16-Bit V
DACs
Low Power, Deglitched, Rail-to-Rail V
OUT
OUT
Octal 10/8-Bit V
DACs in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
Parallel 16-Bit Voltage Output DAC
Octal 16-/14-/12-Bit V DACs in 16-Lead SSOP
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610
LTC2620
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
LTC2601/LTC2611
LTC2621
Single 16-/14-/12-Bit V
DACs in 10-Lead DFN
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
LTC2602/LTC2612
LTC2622
Dual 16-/14-/12-Bit V
DACs in 8-Lead MSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
LTC2604/LTC2614
LTC2624
Quad 16-/14-/12-Bit V
Octal 16-/14-/12-Bit V
DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
OUT
OUT
2
LTC2605/LTC2615
LTC2625
DACs with I C Interface in 16-Lead SSOP 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output
2
LTC2606/LTC2616
LTC2626
Single 16-/14-/12-Bit V
DACs in 10-Lead DFN with I C Interface 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output
OUT
26091929fb
LT 0310 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢁꢁ
●
●
LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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