LTC2630AHSC6-HM10#TRPBF [Linear]
IC SERIAL INPUT LOADING, 4.4 us SETTLING TIME, 10-BIT DAC, PDSO6, LEAD FREE, PLASTIC, EIAJ, MO-203AB, SC-70, 6 PIN, Digital to Analog Converter;
| 型号： | LTC2630AHSC6-HM10#TRPBF |
| 厂家： | 
Linear |
| 描述： | IC SERIAL INPUT LOADING, 4.4 us SETTLING TIME, 10-BIT DAC, PDSO6, LEAD FREE, PLASTIC, EIAJ, MO-203AB, SC-70, 6 PIN, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2630
Single 12-/10-/8-Bit
Rail-to- Rail DACs with 10ppm/°C
Reference in SC70
Features
Description
The LTC®2630 is a family of 12-, 10-, and 8-bit voltage-
output DACs with an integrated, high-accuracy, low-drift
reference in a 6-lead SC70 package. It has a rail-to-rail
output buffer and is guaranteed monotonic.
n
Integrated Precision Reference
2.5V Full Scale 10ppm/°C (LTC2630-L)
4.096V Full Scale 10ppm/°C (LTC2630-H)
n
Maximum INL Error: 1 LSB (LTC2630A-12)
n
Low Noise: 0.7mV , 0.1Hz to 200kHz
P-P
The LTC2630-L has a full-scale output of 2.5V, and
operates from a single 2.7V to 5.5V supply. The
LTC2630-Hhasafull-scaleoutputof4.096V,andoperates
from a 4.5V to 5.5V supply. Each DAC can also operate in
supply asreferencemode, which sets the full-scale output
to the supply voltage.
n
n
n
n
n
n
n
n
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Guaranteed Monotonic over Temperature
Selectable Internal Reference or Supply as Reference
2.7V to 5.5V Supply Range (LTC2630-L)
Low Power Operation: 180µA at 3V
Power Down to 1.8µA Maximum (C and I Grades)
Power-on Reset to Zero or Mid-Scale Options
SPI Serial Interface
The parts use a simple SPI/MICROWIRE™ compatible
3-wire serial interface which operates at clock rates up
to 50MHz.
Double-Buffered Data Latches
Tiny 6-Lead SC70 Package
The LTC2630 incorporates a power-on reset circuit. Op-
tions are available for reset to zero or reset to mid-scale
after power-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178 and 7414561.
applications
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Mobile Communications
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Process Control and Industrial Automation
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Automatic Test Equipment
Portable Equipment
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Automotive
Block Diagram
Integral Nonlinearity (LTC2630A-LZ12)
V
CC
INTERNAL
REFERENCE
1.0
V
CC
V
FS
= 3V
= 2.5V
SDI
0.5
0
CONTROL
DECODE LOGIC
RESISTOR
DIVIDER
24-BIT
SCK
SHIFT
REGISTER
DACREF
DAC
–0.5
–1.0
CS/LD
V
OUT
INPUT
REGISTER
DAC
REGISTER
2048
3072
0
4095
1024
CODE
GND
2630 TA03
2630 BD
2630ff
1
LTC2630
aBsolute maximum ratings
pin conFiguration
(Notes 1, 2)
TOP VIEW
Supply Voltage (V ) ...................................–0.3V to 6V
CC
CS/LD 1
SCK 2
SDI 3
6 V
OUT
CS/LD, SCK, SDI ..........................................–0.3V to 6V
5 GND
V
OUT
..................................–0.3V to min(V + 0.3V, 6V)
CC
4 V
CC
Operating Temperature Range
LTC2630C................................................ 0°C to 70°C
LTC2630I.............................................–40°C to 85°C
LTC2630H (Note 3)............................–40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
SC6 PACKAGE
6-LEAD PLASTIC SC70
T
= 150°C (Note 6), θ = 300°C/W
JA
JMAX
orDer inFormation
LTC2630
A
C
SC6 –L
M
12
#TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
SC6 = 6-Lead SC70
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = 1 LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2630ff
2
LTC2630
proDuct selection guiDe
PART NUMBER
LTC2630A-LM12
LTC2630A-LZ12
LTC2630A-HM12
LTC2630A-HZ12
LTC2630-LM12
LTC2630-LM10
LTC2630-LM8
LTC2630-LZ12
LTC2630-LZ10
LTC2630-LZ8
PART MARKING*
LCZB
V
WITH INTERNAL REFERENCE POWER-ON RESET TO CODE RESOLUTION
V
MAXIMUM INL
1LSB
FS
CC
2.5V • (4095/4096)
2.5V • (4095/4096)
4.096V • (4095/4096)
4.096V • (4095/4096)
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Zero
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
10-Bit
8-Bit
2.7V–5.5V
2.7V–5.5V
4.5V–5.5V
4.5V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
LCSB
1LSB
LCWR
LCZC
Mid-Scale
Zero
1LSB
1LSB
LCZB
Mid-Scale
Mid-Scale
Mid-Scale
Zero
2LSB
LCZF
1LSB
LCYW
LCSB
0.5LSB
2LSB
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
12-Bit
10-Bit
8-Bit
LCZD
Zero
1LSB
LCYV
Zero
0.5LSB
2LSB
LTC2630-HM12
LTC2630-HM10
LTC2630-HM8
LTC2630-HZ12
LTC2630-HZ10
LTC2630-HZ8
LCWR
LCZH
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Zero
12-Bit
10-Bit
8-Bit
1LSB
LCYY
0.5LSB
2LSB
LCZC
12-Bit
10-Bit
8-Bit
LCZG
Zero
1LSB
LCYX
Zero
0.5LSB
*The temperature grade is identified by a label on the shipping container.
2630ff
3
LTC2630
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
LTC2630-8
LTC2630-10
LTC2630-12
LTC2630A-12
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
l
l
l
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
Monotonicity
VCC = 3V, Internal Ref. (Note 4)
DNL
INL
Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4)
0.5
0.5
1
1
2
1
1
LSB
LSB
mV
Integral Nonlinearity
Zero Scale Error
Offset Error
VCC = 3V, Internal Ref. (Note 4)
VCC = 3V, Internal Ref., Code = 0
VCC = 3V, Internal Ref. (Note 5)
VCC = 3V, Internal Ref. (Note 5)
0.05 0.5
0.2
0.5
0.5
10
1
0.5
0.5
10
0.5
0.5
0.5
10
ZSE
VOS
0.5
0.5
10
5
5
5
5
5
5
5
5
mV
VOSTC VOS Temperature
Coefficient
µV/°C
l
FSE
Full Scale Error
VCC = 3V, Internal Ref.
0.2 0.8
0.2 0.8
0.2 0.8
0.2 0.8
%FSR
VFSTC
Full Scale Voltage
Temperature
Coefficient
VCC = 3V, Internal Ref. (Note 10)
C-Grade
I-Grade
H-Grade
10
10
10
10
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
ppm/°C
Load Regulation
Internal Ref., Mid-Scale,
l
l
V
CC = 3V 10%, –5mA ≤ IOUT ≤ 5mA
0.008 0.016
0.008 0.016
0.03 0.064
0.03 0.064
0.13 0.256
0.13 0.256
0.13 0.256 LSB/mA
0.13 0.256 LSB/mA
V
CC = 5V 10%, –10mA ≤ IOUT ≤ 10mA
DC Output Impedance Internal Ref., Mid-Scale,
CC = 3V 10%, –5mA ≤ IOUT ≤ 5mA
CC = 5V 10%, –10mA ≤ IOUT ≤ 10mA
ROUT
l
l
V
V
0.08 0.156
0.08 0.156
0.08 0.156
0.08 0.156
0.08 0.156
0.08 0.156
0.08 0.156
0.08 0.156
Ω
Ω
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT
DAC Output Span
Supply as Reference
Internal Reference
0V to VCC
0V to 2.5
V
V
PSR
ISC
Power Supply Rejection
VCC = 3V 10% or 5V 10%
–80
dB
Short Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero Scale; VOUT Shorted to VCC
Full Scale; VOUT Shorted to GND
l
l
27
–28
50
–50
mA
mA
Power Supply
l
VCC
ICC
Power Supply Voltage
For Specified Performance
2.7
5.5
V
l
l
l
l
Supply Current (Note 7)
VCC = 3V, Supply as Reference
160
180
180
190
220
240
250
260
µA
µA
µA
µA
V
V
V
CC = 3V, Internal Reference
CC = 5V, Supply as Reference
CC = 5V, Internal Reference
l
l
ISD
Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
CC = 5V, H-Grade
0.36
0.36
1.8
5
µA
µA
V
Digital I/O
l
l
VIH
Digital Input High Voltage
VCC = 3.6V to 5.5V
CC = 2.7V to 3.6V
2.4
2.0
V
V
V
l
l
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
CC = 2.7V to 4.5V
0.8
0.6
V
V
V
l
l
ILK
Digital Input Leakage
VIN = GND to VCC
(Note 8)
1
µA
pF
CIN
Digital Input Capacitance
2.5
2630ff
4
LTC2630
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN
TYP
MAX
UNITS
tS
Settling Time
VCC = 3V (Note 9)
0.39% ( 1LSB at 8 Bits)
0.098% ( 1LSB at 10 Bits)
0.024% ( 1LSB at 12 Bits)
3.2
3.9
4.4
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
1.0
500
2
V/µs
pF
At Mid-Scale Transition
nV•s
en
Output Voltage Noise Density
At f = 1kHz, Supply as Reference
At f = 10kHz, Supply as Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Supply as Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Supply as Reference
0.1Hz to 200kHz, Internal Reference
20
20
650
700
µVP-P
µVP-P
µVP-P
µVP-P
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 8).
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER
CONDITIONS
MIN
4
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
l
l
t1
t2
t3
t4
t5
t6
t7
t10
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
4
ns
9
ns
SCK Low Time
9
ns
CS/LD Pulse width
10
7
ns
SCK High to CS/LD High
CS/LD Low to SCK High
CS/LD High to SCK Positive Edge
SCK Frequency
ns
7
ns
7
ns
50% Duty Cycle
50
MHz
2630ff
5
LTC2630
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
LTC2630-8
LTC2630-10
LTC2630-12
LTC2630A-12
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
l
l
l
l
l
l
8
8
10
10
12
12
12
12
Bits
Bits
Monotonicity
VCC = 5V, Internal Ref. (Note 4)
DNL
INL
Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4)
0.5
0.5
1
1
2
1
1
LSB
LSB
mV
Integral Nonlinearity
Zero Scale Error
Offset Error
VCC = 5V, Internal Ref. (Note 4)
VCC = 5V, Internal Ref., Code = 0
VCC = 5V, Internal Ref. (Note 5)
VCC = 5V, Internal Ref. (Note 5)
0.05 0.5
0.2
0.5
0.5
10
1
0.5
0.5
10
0.5
0.5
0.5
10
ZSE
VOS
0.5
0.5
10
5
5
5
5
5
5
5
5
mV
VOSTC VOS Temperature
Coefficient
µV/°C
l
FSE
Full Scale Error
VCC = 5V, Internal Ref.
0.2 0.8
0.2 0.8
0.2 0.8
0.2
0.8 %FSR
VFSTC
Full Scale Voltage
Temperature
Coefficient
VCC = 5V, Internal Ref. (Note 10)
C-Grade
I-Grade
H-Grade
10
10
10
10
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
ppm/°C
l
l
Load Regulation
V
CC = 5V 10%, Internal Ref.,
0.006 0.01
0.025 0.04
0.10 0.16
0.10 0.16
LSB/
mA
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
ROUT
DC Output Impedance VCC = 5V 10%, Internal Ref.,
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
0.1 0.156
0.1 0.156
0.1 0.156
0.1 0.156
Ω
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT
DAC Output Span
Supply as Reference
Internal Reference
0V to VCC
0V to 4.096
V
V
PSR
ISC
Power Supply Rejection
VCC = 5V 10%
–80
dB
Short Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero Scale; VOUT Shorted to VCC
Full Scale; VOUT Shorted to GND
l
l
27
–28
50
–50
mA
mA
Power Supply
l
VCC
ICC
Power Supply Voltage
For Specified Performance
4.5
2.4
5.5
V
l
l
Supply Current (Note 7)
VCC = 5V, Supply as Reference
180
200
260
280
µA
µA
V
CC = 5V, Internal Reference
l
l
ISD
Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
CC = 5V, H-Grade
0.36
0.36
1.8
5
µA
µA
V
Digital I/O
l
l
l
l
VIH
VIL
ILK
CIN
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage
V
V
0.8
1
VIN = GND to VCC
(Note 8)
µA
pF
Digital Input Capacitance
2.5
2630ff
6
LTC2630
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN
TYP
MAX
UNITS
tS
Settling Time
VCC = 5V (Note 9)
0.39% ( 1LSB at 8 Bits)
0.098% ( 1LSB at 10 Bits)
0.024% ( 1LSB at 12 Bits)
3.7
4.4
4.8
µs
µs
µs
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
1.0
500
2.4
V/µs
pF
At Mid-Scale Transition
nV•s
en
Output Voltage Noise Density
At f = 1kHz, Supply as Reference
At f = 10kHz, Supply as Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
210
200
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Supply as Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Supply as Reference
0.1Hz to 200kHz, Internal Reference
20
20
650
750
µVP-P
µVP-P
µVP-P
µVP-P
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 8).
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER
CONDITIONS
MIN
4
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
l
l
t1
t2
t3
t4
t5
t6
t7
t10
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
4
ns
9
ns
SCK Low Time
9
ns
CS/LD Pulse width
10
7
ns
SCK High to CS/LD High
CS/LD Low to SCK High
CS/LD High to SCK Positive Edge
SCK Frequency
ns
7
ns
7
ns
50% Duty Cycle
50
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: High temperatures degrade operating lifetimes. Operating lifetime
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7: Digital inputs at 0V or V
.
CC
is derated at temperatures greater than 105°C.
Note 8: Guaranteed by design and not production tested.
Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kW in parallel with 100pF to GND.
Note 10: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
N
Note 4: Linearity and monotonicity are defined from code k to code 2 –1,
L
N
where N is the resolution and k is given by k = 0.016 • (2 / V ), rounded
L
L
FS
to the nearest whole code. For V = 2.5V and N = 12, k = 26 and linearity
FS
L
is defined from code 26 to code 4,095. For V = 4.096V and
FS
N = 12, k = 16 and linearity is defined from code 16 to code 4,095.
L
Note 5: Inferred from measurement at code 16 (LTC2630-12), code 4
(LTC2630-10) or code 1 (LTC2630-8).
2630ff
7
LTC2630
typical perFormance characteristics
LTC2630-LM12/-LZ12 (VFS = 2.5V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
0.5
V
CC
= 3V
V
= 3V
CC
0.5
0
0
–0.5
–1.0
–0.5
–1.0
2048
3072
2048
3072
0
4095
0
4095
1024
1024
CODE
CODE
2630 G01
2630 G02
Full-Scale Output Voltage
vs Temperature
INL vs Temperature
DNL vs Temperature
1.0
0.5
1.0
0.5
2.52
2.51
2.50
2.49
2.48
V
= 3V
V
= 3V
V
= 3V
CC
CC
CC
INL (POS)
DNL (POS)
DNL (NEG)
0
0
INL (NEG)
–0.5
–0.5
–1.0
–1.0
50
100
50
100
50
100
125 150
–50 –25
25
75
125 150
–50 –25
25
75
125 150
–50 –25
25
75
0
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2630 G03
2630 G04
2630 G05
Settling to 1LSB
Settling to 1LSB
3/4 SCALE TO 1/4 SCALE STEP
= 3V, V = 2.5V
V
CC
L
FS
R
= 2k, C = 100pF
L
AVERAGE OF 256 EVENTS
CS/LD
2V/DIV
V
OUT
1LSB/DIV
4.4µs
3.6µs
V
OUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
= 3V, V = 2.5V
V
CC
FS
CS/LD
2V/DIV
R
= 2k, C = 100pF
L
L
AVERAGE OF 256 EVENTS
2µs/DIV
2µs/DIV
2630 G07
2630 G06
2630ff
8
LTC2630
typical perFormance characteristics
LTC2630-HM12/-HZ12 (VFS = 4.096V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
0.5
V
CC
= 5V
V
CC
= 5V
0.5
0
0
–0.5
–1.0
–0.5
–1.0
2048
3072
2048
3072
0
4095
0
4095
1024
1024
CODE
CODE
2630 G08
2630 G09
Full-Scale Output Voltage
vs Temperature
INL vs Temperature
DNL vs Temperature
4.115
4.105
4.095
4.085
4.075
1.0
0.5
1.0
0.5
V
= 5V
V
= 5V
V
= 5V
CC
CC
CC
INL (POS)
DNL (POS)
DNL (NEG)
0
0
INL (NEG)
–0.5
–0.5
–1.0
–1.0
50
100
125 150
–50 –25
25
75
50
100
50
100
0
–50 –25
25
75
125 150
–50 –25
25
75
125 150
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2630 G12
2630 G10
2630 G11
Settling to 1LSB
Settling to 1LSB
CS/LD
2V/DIV
V
OUT
1LSB/DIV
4.8µs
4.0µs
V
OUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
= 5V, V = 4.096V
1/4 SCALE TO 3/4 SCALE STEP
V
CC
FS
V
= 5V, V = 4.096V
CS/LD
2V/DIV
CC
FS
R
= 2k, C = 100pF
L
L
R
L
= 2k, C = 100pF
L
AVERAGE OF 256 EVENTS
AVERAGE OF 256 EVENTS
2µs/DIV
2µs/DIV
2630 G14
2630 G13
2630ff
9
LTC2630
typical perFormance characteristics
LTC2630-10
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
0.5
V
CC
V
FS
= 5V
= 4.096V
V
CC
V
FS
= 5V
= 4.096V
0.5
0
0
–0.5
–1.0
–0.5
–1.0
512
768
0
1023
256
512
768
0
1023
256
CODE
CODE
2630 G15
2630 G16
LTC2630-8
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.5
0.50
0.25
0
V
CC
V
FS
= 3V
= 2.5V
V
CC
V
FS
= 3V
= 2.5V
0
–0.5
–1.0
–0.25
–0.50
128
192
128
192
0
255
0
255
64
64
CODE
CODE
2630 G17
2630 G18
LTC2630
Load Regulation
Current Limiting
Offset Error vs Temperature
3
2
1
0
10
8
0.20
0.15
0.10
0.05
0
V
CC
V
CC
V
CC
= 5V (LTC2630-H)
= 5V (LTC2630-L)
= 3V (LTC2630-L)
V
CC
V
CC
V
CC
= 5V (LTC2630-H)
= 5V (LTC2630-L)
= 3V (LTC2630-L)
6
4
2
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
–1
–2
–3
INTERNAL REF.
INTERNAL REF.
CODE = MIDSCALE
CODE = MIDSCALE
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2630 G21
–30
–20
–10
0
10
20
30
–30
–20
–10
0
10 20
30
I
(mA)
I
(mA)
OUT
OUT
2630 G19
2630 G20
2630ff
10
LTC2630
typical perFormance characteristics
LTC2630
Power-On Reset Glitch
Mid-Scale-Glitch Impulse
Large-Signal Response
LTC2630-L
INTERNAL REF
V
CC
CS/LD
5V/DIV
2V/DIV
LTC2630-H12, V = 5V:
CC
2.4nV-s TYP
0.5V/DIV
V
OUT
ZERO-SCALE
5mV/DIV
V
OUT
LTC2630-L12, V = 3V:
CC
2.0nV-s TYP
2mV/DIV
V
= V = 5V
CC
FS
1/4 SCALE TO 3/4 SCALE
200µs/DIV
2µs/DIV
2µs/DIV
2630 G24
2630 G23
2630 G22
Headroom at Rails
vs Output Current
Noise Voltage vs Frequency
0.1Hz to 10Hz Voltage Noise
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
500
400
300
200
100
0
CODE = MIDSCALE
5V SOURCING
V
= 4V, V = 2.5V
CC FS
CODE = MIDSCALE
3V (LTC2630-L) SOURCING
LTC2630-H
10µV/DIV
(V = 5V)
CC
LTC2630-L
5V SINKING
3V (LTC2630-L) SINKING
(V = 4V)
CC
1k
10k
100k
1s/DIV
100
1M
0
1
2
3
4
5
6
7
8
9
10
2630 G27
FREQUENCY (Hz)
I
(mA)
OUT
2630 G26
2630 G25
Exiting Power-Down to Mid-Scale
Supply Current vs Logic Voltage
1.0
0.8
0.6
0.4
0.2
SWEEP SCK, SDI, CS/LD
BETWEEN 0V AND V
CC
CS/LD
2V/DIV
V
= 5V
CC
V
OUT
0.5V/DIV
V
= 3V
CC
(LTC2630-L)
LTC2630-H
0
4µs/DIV
0
1
2
3
4
5
2630 G28
LOGIC VOLTAGE (V)
2630 G29
2630ff
11
LTC2630
pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed.
V
(Pin 4): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V
CC CC
(LTC2630-L) or 4.5V ≤ V ≤ 5.5V (LTC2630-H). Also
CC
used as the reference input when the part is programmed
to operate in supply as reference mode. Bypass to GND
with a 0.1µF capacitor.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
GND (Pin 5): Ground.
V
OUT
(Pin 6): DAC Analog Voltage Output.
SDI (Pin 3): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2630acceptsinputwordlengthsofeither24or32bits.
Block Diagram
V
CC
INTERNAL
REFERENCE
SDI
CONTROL
DECODE LOGIC
RESISTOR
DIVIDER
24-BIT
SHIFT
REGISTER
SCK
DACREF
DAC
CS/LD
V
OUT
INPUT
REGISTER
DAC
REGISTER
GND
2630 BD
2630ff
12
LTC2630
timing Diagram
t
1
t
6
t
t
t
4
2
3
SCK
SDI
1
2
3
23
24
t
10
t
t
7
5
CS/LD
2630 F01
Figure 1. Serial Interface Timing
operation
The LTC2630 is a family of single voltage output DACs in
6-lead SC70 packages. Each DAC can operate rail-to-rail
referencedtotheinputsupply, orwithitsfull-scalevoltage
set by an integrated reference. Twelve combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero
or mid-scale), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2630 is controlled using a 3-wire SPI/
MICROWIRE compatible interface.
Transfer Function
The digital-to-analog transfer function is
k
VOUT(IDEAL)
=
V
REF
N
2
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and V is either 2.5V
(LTC2630-L) or 4.096V (LTC2630-H) in internal refer-
ence mode, and V in Supply as reference mode.
REF
Power-On Reset
CC
The LTC2630-HZ/-LZ clear the output to zero scale when
power is first applied, making system initialization con-
sistent and repeatable.
Table 1. Command Codes
Command*
C3 C2 C1 C0
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2630
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zero
scale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
0
0
1
Write to Input Register
Update (Power up) DAC Register
Write to and Update (Power up) DAC Register
Power down
Select Internal Reference (Power-on Reset Default)
Select Supply as Reference (V
= V )
CC
REF
*Command codes not shown are reserved and should not be used.
The LTC2630-HM/-LM provide an alternative reset, set-
ting the output to mid-scale when power is first applied.
2630ff
13
LTC2630
operation
INPUT WORD (LTC2630-12)
COMMAND
4 DON'T-CARE BITS
DATA (12 BITS + 4 DON'T-CARE BITS)
C3 C2 C1 C0
X
X
X
X
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
X
X
X
MSB
LSB
INPUT WORD (LTC2630-10)
COMMAND
4 DON'T-CARE BITS
DATA (10 BITS + 6 DON'T-CARE BITS)
C3 C2 C1 C0
X
X
X
X
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
INPUT WORD (LTC2630-8)
COMMAND
4 DON'T-CARE BITS
DATA (8 BITS + 8 DON'T-CARE BITS)
C3 C2 C1 C0
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
X
X
X
2630 F02
Figure 2. Command and Data Input Format
Serial Interface
The command (C3-C0) assignments are shown in Table 1.
The first three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the first two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
TheCS/LDinputisleveltriggered. Whenthisinputistaken
low, it acts as a chip-select signal, enabling the SDI and
SCK buffers and the input shift register. Data (SDI input)
is transferred at the next 24 rising SCK edges. The 4-bit
command, C3-C0, is loaded first; then 4 don’t-care bits;
and finally the 16-bit data word. The data word comprises
the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, fol-
lowed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and
-8 respectively; see Figure 2). Data can only be transferred
to the device when the CS/LD signal is low, beginning on
the first rising edge of SCK. SCK may be high or low at
the falling edge of CS/LD. The rising edge of CS/LD ends
the data transfer and causes the device to execute the
command specified in the 24-bit input sequence. The
complete sequence is shown in Figure 3a.
While the minimum input sequence is 24-bits, it may
optionally be extended to 32-bits to accommodate micro-
processors that have a minimum word width of 16-bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits are
transferred to the device first, followed by the 24-bit se-
quence described. Figure 3b shows the 32-bit sequence.
2630ff
14
LTC2630
operation
The 16-bit data word is ignored for all commands that do
The DAC can also operate in supply as reference mode
not include a Write operation.
using command 0111. In this mode, V supplies the
CC
DAC’sreferencevoltageandthesupplycurrentisreduced.
Power-Down Mode
Voltage Output
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DACoutputisnotneeded.Wheninpower-down,thebuffer
amplifier, bias circuit, and reference circuit are disabled
and draw essentially zero current. The DAC output is put
intoahigh-impedancestate,andtheoutputpinispassively
pulled to ground through a 200kΩresistor. Input and DAC
register contents are not disturbed during power-down.
The LTC2630’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8µA
maximum when the DAC is powered down.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 1. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifier
circuits are re-enabled. The power-up delay time is 18µs
for settling to 12-bits.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Charac-
teristics section.
Reference Modes
Forapplicationswhereanaccurateexternalreferenceisnot
available, the LTC2630 has a user-selectable, integrated
reference. The LTC2630-LM and LTC2630-LZ provide a
full-scale output of 2.5V. The LTC2630-HM and LTC2630-
HZ provide a full-scale output of 4.096V.
The amplifier is stable driving capacitive loads of up to
500pF.
The internal reference can be useful in applications where
the supply voltage is poorly regulated. Internal Reference
mode can be selected by using command 0110, and is
the power-on default.
2630ff
15
LTC2630
operation
Rail-to-Rail Output Considerations
the LTC2630 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2630 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
SincetheanalogoutputoftheDACcannotgobelowground,
it may limit for the lowest codes as shown in Figure 4b.
Similarly, limiting can occur near full scale when using the
supply as reference. If V = V and the DAC full-scale
FS
CC
error (FSE) is positive, the output for the highest codes
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2630 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
limits at V , as shown in Figure 4. No full-scale limiting
CC
can occur if V is less than V –FSE.
FS
CC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
ThePCboardshouldhaveseparateareasfortheanalogand
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
2630ff
16
LTC2630
operation
Optoisolated 4mA to 20mA Process Controller
additional current through Q1. Note that at the maximum
loop voltage of 80V, Q1 will dissipate 1.6W when I
20mA and must have an appropriate heat sink.
=
OUT
Figure 5 shows how to use an LTC2630HZ to make an
optoisolated, digitally-controlled 4mA to 20mA transmit-
ter. The transmitter circuitry, including optoisolation, is
powered by the loop voltage which has a wide range of
5.4V to 80V. The 5V output of the LT®3010-5 is used to
set the 4mA offset current and V
control the 0mA to 16mA signal current. The supply cur-
rent for the regulator, DAC, and op amp is well below
R
and R
are the closest 0.1% values to ideal
OFFSET
GAIN
for controlling a 4mA to 20mA output as the digital input
varies from zero scale to full scale. Alternatively, R
OFFSET
is used to digitally
can be a 365k, 1% resistor in series with a 20k trim pot
OUT
and R
can be a 75.0k, 1% resistor in series with a 5k
GAIN
trim pot. The optoisolators shown will limit the speed of
the serial bus; the 6N139 is an alternative that will allow
higher data rates.
the 4mA budget at zero scale. R senses the total loop
current, which includes the quiescent supply current and
S
CS/LD
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
12
D8
13
D7
14
D6
15
D5
16
D4
17
D3
18
D2
19
D1
20
D0
21
22
23
24
C3
C2
C1
C0
X
X
X
X
D11 D10 D9
X
X
X
X
2630 F03a
COMMAND WORD
4 DON’T-CARE BITS
DATA WORD
24-BIT INPUT WORD
Figure 3a. 24-Bit Load Sequence (Minimum Input Word)
LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);
LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
CS/LD
SCK
1
2
3
4
5
6
7
8
9
10
C2
11
C1
12
C0
13
14
15
16
17
18
19
20
D8
21
D7
22
D6
23
D5
24
D4
25
D3
26
D2
27
D1
28
D0
29
30
31
32
SDI
X
X
X
X
X
X
X
X
C3
X
X
X
X
D11 D10 D9
X
X
X
X
8 DON’T-CARE BITS
COMMAND WORD
4 DON’T-CARE BITS
DATA WORD
2630 F03b
32-BIT INPUT WORD
Figure 3b. 32-Bit Load Sequence
LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);
LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
2630ff
17
LTC2630
operation
2630ff
18
LTC2630
typical application
12-Bit, 2.7V to 5.5V Single Supply, Voltage Output DAC
2.7V TO 5.5V
0.1µF
V
CC
SDI
OUTPUT
µP
LTC2630-LZ12
GND
SCK
V
0V TO 2.5V OR
OUT
0V TO V
CC
CS/LD
2630 TA01
2630ff
19
LTC2630
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.15 – 1.35
(NOTE 4)
1.80 – 2.40
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.15 – 0.30
6 PLCS (NOTE 3)
0.65 BSC
0.10 – 0.40
0.80 – 1.00
0.00 – 0.10
REF
1.00 MAX
GAUGE PLANE
0.15 BSC
0.26 – 0.46
SC6 SC70 1205 REV B
0.10 – 0.18
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
2630ff
20
LTC2630
revision history (Revision history begins at Rev F)
REV
DATE
DESCRIPTION
PAGE NUMBER
F
06/12 Corrected units on parameter V
from mV/°C to µV/°C
6
OSTC
2630ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC2630
typical application
V
LOOP
5.4V TO 80V
R
OFFSET
374k
LT3010-5
0.1%
IN
OUT
+
SHDN SENSE
GND
1µF
1µF
R
76.8k
0.1%
GAIN
V
CC
SDI
FROM
OPTO-
ISOLATED
INPUTS
LTC2630-HZ
V
OUT
SCK
+
–
1k
Q1
2N3440
LTC2054
CS/LD
3.01k
1000 F
P
10k
R
S
5V
10Ω
I
OPTO-ISOLATORS
500Ω
OUT
10k
SDI
2630 TA02
SCK
CS/LD
4N28
SDI
SCK
CS/LD
Figure 5. An Optoisolated 4mA to 20mA Process Controller
relateD parts
PART NUMBER
LTC1660/LTC1665
LTC1663
DESCRIPTION
Octal 10-/8-Bit V
COMMENTS
DACs in 16-Pin Narrow SSOP
V
CC
V
CC
V
CC
V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
= 2.7V to 5.5V, 60µA, Internal reference, SMBus Interface
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
Single 10-Bit V
DAC in SOT-23
OUT
LTC1664
Quad 10-Bit V
DAC in 16-Pin Narrow SSOP
OUT
2
LTC1669
Single 10-Bit V
DAC in SOT-23
= 2.7V to 5.5V, 60µA, Internal reference, I C Interface
OUT
LTC1821
Parallel 16-Bit Voltage Output DAC
Octal 16-/14-/12-Bit V
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610/LTC2620
DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2601/LTC2611/LTC2621
LTC2602/LTC2612/LTC2622
LTC2604/LTC2614/LTC2624
LTC2631
Single 16-/14-/12-Bit V
DACs in 10-Lead DFN
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
Dual 16-/14-/12-Bit V
DACs in 8-Lead MSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
Quad 16-/14-/12-Bit V
DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
2
Single 12-/10-/8-Bit I C V
DACs with
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
OUT
2
10ppm/°C Reference in ThinSOT
Selectable External Ref. Mode, Rail-to-Rail Output, I C Interface
LTC2640
Single 12-/10-/8-Bit SPI V DACs with
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Selectable External Ref. Mode, Rail-to-Rail Output, SPI Interface
OUT
10ppm/°C Reference in ThinSOT
2630ff
LT 0612 REV F • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
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LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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