LTC2656CFE-L12PBF [Linear]
Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; 八通道16位/ 12位轨至轨DAC和10ppm的/ ° C（最大值）参考
| 型号： | LTC2656CFE-L12PBF |
| 厂家： | 
Linear |
| 描述： | Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference |
| 文件： | 总24页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2656
Octal 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
FEATURES
DESCRIPTION
The LTC®2656 is a family of octal 16-/12-bit rail-to-rail
DACs with a precision integrated reference. The DACs have
built-in high performance, rail-to-rail, output buffers and
are guaranteed monotonic.The LTC2656-L has a full-scale
output of 2.5V with the integrated 10ppm/°C reference and
operates from a single 2.7V to 5.5V supply. The LTC2656-H
has a full-scale output of 4.096V with the integrated refer-
enceandoperatesfroma4.5Vto5.5Vsupply.EachDACcan
also operate with an external reference, which sets the DAC
full-scaleoutputtotwotimestheexternalreferencevoltage.
n
Precision 10ppm/°C Max Reference
n
Maximum INL Error: 4LSꢀ at 16 ꢀits
n
Guaranteed Monotonic over Temperature
n
Selectable Internal or External Reference
n
2.7V to 5.5V Supply Range (LTC2656-L)
n
Integrated Reference ꢀuffers
n
Ultralow Crosstalk ꢀetween DACs(<1nV•s)
n
Power-On-Reset to Zero-Scale/Mid-scale
n
Asynchronous LDAC Update Pin
n
Tiny 20-Lead 4mm × 5mm QFN and 20-Lead
Thermally Enhanced TSSOP Packages
™
These DACs communicate via a SPI/MICROWIRE com-
patible4-wireserialinterfacewhichoperatesatclockrates
up to 50MHz. The LTC2656 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
APPLICATIONS
n
Mobile Communications
n
Process Control and Industrial Automation
n
tied to V , the DACs reset to mid-scale.
Instrumentation
Automatic Test Equipment
CC
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 6891433.
n
Automotive
BLOCK DIAGRAM
REFCOMP
REFIN/OUT
INTERNAL REFERENCE
REF
REF
GND
V
CC
REFLO
V
DAC A
REF
DAC H
REF
V
V
V
V
OUTA
OUTH
OUTG
OUTF
OUTE
INL vs Code
4
3
V
OUTꢀ
DAC G
REF
2
DAC ꢀ
REF
1
0
–1
–2
–3
–4
V
OUTC
DAC C
REF
DAC F
REF
DAC A
DAC ꢀ
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
128
16384
32768
CODE
49152
65535
V
OUTD
DAC E
DAC D
2656 TA01
POWER-ON RESET
PORSEL
SDO
CS/LD
CONTROL LOGIC
DECODE
SCK
SDI
32-ꢀIT SHIFT REGISTER
CLR
LDAC
2656 ꢀD
2656f
1
LTC2656
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltage (V ) ................................... –0.3V to 6V
Maximum Junction Temperature........................... 150°C
Storage Temperature Range.......................–65 to 150°C
Lead Temperature (Soldering, 10 sec)
CC
CS/LD, SCK, SDI, LDAC, CLR, REFLO.......... –0.3V to 6V
V
to V
................. –0.3V to Min(V + 0.3V, 6V)
OUTA
OUTH CC
REFIN/OUT, REFCOMP ...... –0.3V to Min(V + 0.3V, 6V)
FE Package ....................................................... 300°C
CC
PORSEL, SDO................... –0.3V to Min(V + 0.3V, 6V)
CC
Operating Temperature Range
LTC2656C ................................................ 0°C to 70°C
LTC2656I.............................................. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
REFLO
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GND
V
V
20 19 18 17
OUTA
CC
V
V
OUTꢀ
OUTH
V
1
2
3
4
5
6
16
15
14
13
V
V
V
V
OUTꢀ
OUTH
OUTG
OUTF
OUTE
REFCOMP
V
V
V
REFCOMP
OUTG
OUTF
OUTE
V
V
OUTC
OUTC
21
21
V
V
OUTD
OUTD
REFIN/OUT
12 PORSEL
REFIN/OUT
LDAC
PORSEL
CLR
LDAC
11 CLR
CS/LD
SDO
7
8
9 10
SCK 10
SDI
FE PACKAGE
20-LEAD PLASTIC TSSOP
UFD PACKAGE
20-LEAD (4mm s 5mm) PLASTIC QFN
T
= 150°C, θ = 38°C/W, θ = 10°C/W
JA JC
JMAX
T
= 150°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST ꢀE SOLDERED TO PCꢀ
EXPOSED PAD (PIN 21) IS GND, MUST ꢀE SOLDERED TO PCꢀ
2656f
2
LTC2656
PRODUCT SELECTOR GUIDE
LTC2656 B
C
UFD -L
16
#TR PBF
LEAD FREE DESIGNATOR
PꢀF = Lead Free
TAPE AND REEL
TR = Tape and Reel
RESOLUTION
16 = 16-ꢀit
12 = 12-ꢀit
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
UFD = 20-Lead (4mm × 5mm) Plastic QFN
FE = 20-Lead Thermally Enhanced TSSOP
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
ELECTRICAL GRADE (OPTIONAL)
ꢀ = 4LSꢀ Maximum INL (16-ꢀit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2656f
3
LTC2656
ORDER INFORMATION
PART
MARKING*
TEMPERATURE
RANGE
LEAD FREE FINISH
TAPE AND REEL
PACKAGE DESCRIPTION
MAXIMUM INL
LTC2656ꢀCFE-L16#PꢀF
LTC2656ꢀIFE-L16#PꢀF
LTC2656ꢀCFE-L16#TRPꢀF
LTC2656ꢀIFE-L16#TRPꢀF
LTC2656FE-L16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C
LTC2656FE-L16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C
4
4
LTC2656ꢀCUFD-L16#PꢀF LTC2656ꢀCUFD-L16#TRPꢀF 56L16
LTC2656ꢀIUFD-L16#PꢀF LTC2656ꢀIUFD-L16#TRPꢀF 56L16
0°C to 70°C
–40°C to 85°C
4
4
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
LTC2656ꢀCFE-H16#PꢀF LTC2656ꢀCFE-H16#TRPꢀF LTC2656FE-H16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C
LTC2656ꢀIFE-H16#PꢀF LTC2656ꢀIFE-H16#TRPꢀF LTC2656FE-H16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C
4
4
LTC2656ꢀCUFD-H16#PꢀF LTC2656ꢀCUFD-H16#TRPꢀF 56H16
LTC2656ꢀIUFD-H16#PꢀF LTC2656ꢀIUFD-H16#TRPꢀF 56H16
0°C to 70°C
–40°C to 85°C
4
4
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
LTC2656CFE-L12#PꢀF
LTC2656IFE-L12#PꢀF
LTC2656CFE-L12#TRPꢀF
LTC2656IFE-L12#TRPꢀF
LTC2656FE-L12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C
LTC2656FE-L12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C
1
1
LTC2656CUFD-L12#PꢀF LTC2656CUFD-L12#TRPꢀF 56L12
0°C to 70°C
–40°C to 85°C
1
1
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
LTC2656IUFD-L12#PꢀF
LTC2656IUFD-L12#TRPꢀF
56L12
LTC2656CFE-H12#PꢀF
LTC2656IFE-H12#PꢀF
LTC2656CFE-H12#TRPꢀF
LTC2656IFE-H12#TRPꢀF
LTC2656FE-H12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C
LTC2656FE-H12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C
1
1
LTC2656CUFD-H12#PꢀF LTC2656CUFD-H12#TRPꢀF 56H12
LTC2656IUFD-H12#PꢀF LTC2656IUFD-H12#TRPꢀF 56H12
0°C to 70°C
–40°C to 85°C
1
1
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on
the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2656f
4
LTC2656
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2656B-L16/LTC2656-L12 (internal reference = 1.25V)
LTC2656-12
LTC2656B-16
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
l
l
12
12
16
16
ꢀits
ꢀits
Monotonicity
(Note 3)
(Note 3)
DNL
INL
Differential Nonlinearity
0.1
0.5
0.5
1
0.3
2
1
4
LSꢀ
Integral Nonlinearity (Note 3)
Load Regulation
V
CC
= 5.5V, V = 2.5V
LSꢀ
REF
V
= 5V 10ꢁ, Internal Reference, Mid-Scale,
0.04 0.125
0.6
2
LSꢀ/mA
CC
–15mA ≤ I
≤ 15mA
OUT
l
V
= 3V 10ꢁ, Internal Reference, Mid-Scale,
0.06 0.25
1
4
3
LSꢀ/mA
CC
–7.5mA ≤ I
≤ 7.5mA
OUT
l
l
ZSE
Zero-Scale Error
Offset Error
1
3
1
1
2
mV
mV
V
OS
V
= 1.25V (Note 4)
REF
1
2
2
V
OS
Temperature Coefficient
2
μV/°C
ꢁFSR
ppm/°C
l
GE
Gain Error
0.02 0.1
1
0.02 0.1
1
Gain Temperature Coefficient
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
0 to 2.5
0 to 2 • V
MAX
UNITS
V
DAC Output Span
Internal Reference
External Reference = V
V
V
OUT
EXTREF
EXTREF
PSR
Power Supply Rejection
DC Output Impedance
V
V
10ꢁ
–80
dꢀ
Ω
CC
l
R
= 5V 10ꢁ, Internal Reference, Mid-Scale,
≤ 15mA
0.04
0.15
0.15
OUT
CC
–15mA ≤ I
OUT
l
V
= 3V 10ꢁ, Internal Reference, Mid-Scale,
0.04
Ω
CC
–7.5mA ≤ I
≤ 7.5mA
OUT
DC Crosstalk (Note 5)
Due to Full-Scale Output Change
Due to Load Current Change
Due to Powering Down (per Channel)
1.5
2
1
μV
μV/mA
μV
I
SC
Short-Circuit Output Current (Note 6)
V
= 5.5V, V
= 2.75V
EXTREF
CC
l
l
Code: Zero Scale, Forcing Output to V
20
20
65
65
mA
mA
CC
Code: Full Scale, Forcing Output to GND
V
= 2.7V, V = 1.35V
CC
EXTREF
l
l
Code: Zero Scale, Forcing Output to V
10
10
40
40
mA
mA
CC
Code: Full Scale, Forcing Output to GND
Reference
Reference Output Voltage
1.248
1.25
1.252
10
V
Reference Temperature Coefficient
C-Grade (Note 7)
I-Grade (Note 7)
2
2
ppm/°C
ppm/°C
Reference Line Regulation
V
V
V
V
10ꢁ
–80
3
dꢀ
mA
CC
CC
CC
CC
l
l
Reference Short-Circuit Current
REFCOMP Pin Short-Circuit Current
Reference Load Regulation
= 5.5V, Forcing Output to GND
= 5.5V, Forcing Output to GND
5
60
40
200
μA
= 3V 10ꢁ or 5V 10ꢁ, I
Sourcing
= 100μA
mV/mA
OUT
Reference Output Voltage Noise Density
C
= C
= 0.1μF at f = 1kHz
30
nV/√Hz
REFCOMP
REFIN/OUT
2656f
5
LTC2656
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2656B-L16/LTC2656-L12 (internal reference = 1.25V)
SYMBOL PARAMETER
Reference Input Range
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
External Reference Mode (Note 13)
0.5
V
/2
CC
Reference Input Current
0.001
40
1
μA
Reference Input Capacitance (Note 9)
pF
Power Supply
l
V
Positive Supply Voltage
Supply Current (Note 8)
For Specified Performance
2.7
5.5
V
CC
l
l
l
l
I
V
CC
V
CC
V
CC
V
CC
= 5V, Internal Reference On
= 5V, Internal Reference Off
= 3V, Internal Reference On
= 3V, Internal Reference Off
3.1
2.7
3.0
2.6
4.25
3.7
3.8
3.2
mA
mA
mA
mA
CC
l
I
Supply Current in Shutdown Mode
(Note 8)
V
= 5V
3
μA
SHDN
CC
Digital I/O
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 3.6V to 5.5V
= 2.7V to 3.6V
2.4
2.0
V
V
IH
CC
CC
l
l
V
V
CC
V
CC
= 4.5V to 5.5V
= 2.7V to 4.5V
0.8
0.6
V
V
IL
l
l
l
l
V
V
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
Load Current = –100μA
Load Current = 100μA
V
–0.4
CC
V
V
OH
0.4
1
OL
I
V
IN
= GND to V
CC
μA
pF
LK
C
IN
Digital Input Capacitance (Note 9)
8
AC Performance
t
S
Settling Time (Note 10)
0.024ꢁ ( 1LSꢀ at 12 ꢀits)
0.0015ꢁ ( 1LSꢀ at 16 ꢀits)
4.2
8.9
μs
μs
Settling Time for 1LSꢀ Step
0.024ꢁ ( 1LSꢀ at 12 ꢀits)
0.0015ꢁ ( 1LSꢀ at 16 ꢀits)
2.2
4.9
μs
μs
Voltage Output Slew Rate
Capacitive Load Driving
1.8
1000
3
V/μs
pF
Glitch Impulse (Note 11)
DAC-to-DAC Crosstalk (Note 12)
At Mid-Scale Transition, V = 3V
nV•s
nV•s
CC
Due to Full-Scale Output Change,
2
C
= C
= No Load
REFCOMP
REFOUT
Multiplying ꢀandwidth
150
kHz
e
n
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
85
80
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Internal Reference
8
600
μV
μV
P-P
P-P
2656f
6
LTC2656
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2656B-H16/LTC2656-H12 (internal reference = 2.048V)
LTC2656-12
LTC2656B-16
SYMBOL PARAMETER
DC Performance
Resolution
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNITS
l
l
l
l
l
12
12
16
16
ꢀits
ꢀits
Monotonicity
(Note 3)
(Note 3)
DNL
INL
Differential Nonlinearity
0.1
0.5
0.5
1
0.3
2
1
4
LSꢀ
Integral Nonlinearity (Note 3)
Load Regulation
V
V
= 5.5V, V = 2.5V
LSꢀ
CC
REF
= 5V 10ꢁ, Internal Reference, Mid-Scale,
0.04 0.125
0.6
2
LSꢀ/mA
CC
–15mA ≤ I
≤ 15mA
OUT
l
l
ZSE
Zero-Scale Error
Offset Error
1
3
1
1
3
mV
mV
V
OS
V
REF
= 2.048V (Note 4)
1
2
2
V
Temperature Coefficient
2
2
μV/°C
ꢁFSR
ppm/°C
OS
l
GE
Gain Error
0.02
1
0.1
0.02
1
0.1
Gain Temperature Coefficient
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OUT
DAC Output Span
Internal Reference
External Reference = V
0 to 4.096
0 to 2 • V
V
V
EXTREF
EXTREF
PSR
Power Supply Rejection
DC Output Impedance
V
V
10ꢁ
–80
dꢀ
Ω
CC
l
R
= 5V 10ꢁ, Internal Reference, Midscale,
≤ 15mA
0.04
0.15
OUT
CC
–15mA ≤ I
OUT
DC Crosstalk (Note 5)
Due to Full-Scale Output Change
Due to Load Current Change
Due to Powering Down (per Channel)
1.5
2
1
μV
μV/mA
μV
I
SC
Short-Circuit Output Current (Note 6)
V
= 5.5V, V
= 2.75V
EXTREF
CC
l
l
Code: Zero Scale, Forcing Output to V
20
20
65
65
mA
mA
CC
Code: Full Scale, Forcing Output to GND
Reference
Reference Output Voltage
2.044
2.048
2.052
10
V
Reference Temperature Coefficient
C-Grade (Note 7)
I-Grade (Note 7)
2
2
ppm/°C
ppm/°C
Reference Line Regulation
V
V
V
V
C
10ꢁ
–80
3
dꢀ
mA
CC
l
l
Reference Short-Circuit Current
REFCOMP Pin Short-Circuit Current
Reference Load Regulation
= 5.5V, Forcing Output to GND
= 5.5V, Forcing Output to GND
5
CC
60
40
35
200
μA
CC
= 5V 10ꢁ, I
= 100μA Sourcing
mV/mA
nV/√Hz
V
CC
OUT
Reference Output Voltage Noise Density
Reference Input Range
= C
= 0.1μF at f = 1kHz
REFCOMP
REFIN/OUT
l
l
l
External Reference Mode (Note 13)
0.5
V
/2
CC
Reference Input Current
0.001
40
1
μA
Reference Input Capacitance (Note 9)
pF
2656f
7
LTC2656
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2656B-H16/LTC2656-H12 (internal reference = 2.048V)
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Positive Supply Voltage
Supply Current (Note 8)
For Specified Performance
4.5
5.5
V
CC
l
l
I
V
CC
V
CC
= 5V, Internal Reference On
= 5V, Internal Reference Off
3.3
3.0
4.25
3.7
mA
mA
CC
l
I
Supply Current in Shutdown Mode
(Note 8)
V
= 5V
3
μA
SHDN
CC
Digital I/O
l
l
l
l
l
l
V
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
V
V
= 4.5V to 5.5V
= 4.5V to 5.5V
2.4
V
V
IH
CC
0.8
IL
CC
Load Current = –100μA
Load Current = 100μA
V
–0.4
CC
V
OH
OL
0.4
1
V
I
V
IN
= GND to V
CC
μA
pF
LK
C
Digital Input Capacitance (Note 9)
8
IN
AC Performance
t
S
Settling Time (Note 10)
0.024ꢁ ( 1LSꢀ at 12 ꢀits)
0.0015ꢁ ( 1LSꢀ at 16 ꢀits)
4.6
7.9
μs
μs
Settling Time for 1LSꢀ Step
0.024ꢁ ( 1LSꢀ at 12 ꢀits)
0.0015ꢁ ( 1LSꢀ at 16 ꢀits)
2.0
3.8
μs
μs
Voltage Output Slew Rate
Capacitive Load Driving
1.8
1000
6
V/μs
pF
Glitch Impulse (Note 11)
DAC-to-DAC Crosstalk (Note 12)
At Mid-Scale Transition, V = 5V
nV•s
nV•s
CC
Due to Full-Scale Output Change,
3
C
= C
= No Load
REFCOMP
REFOUT
Multiplying ꢀandwidth
150
kHz
e
n
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
85
80
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Internal Reference
12
650
μV
μV
P-P
P-P
2656f
8
LTC2656
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTC2656B-L16/LTC2656-L12/LTC2656B-H16/LTC2656-H12 (see Figure 1).
SYMBOL PARAMETER
= 2.7V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SDI Valid to SCK Setup
4
4
ns
ns
ns
ns
ns
ns
ns
1
SDI Valid to SCK Hold
2
3
4
5
6
7
8
SCK High Time
9
SCK Low Time
9
CS/LD Pulse Width
10
7
LSꢀ SCK High to CS/LD High
CS/LD Low to SCK High
SDO Propagation Delay from SCK Falling Edge
7
C
V
V
= 10pF
LOAD
l
l
= 4.5V to 5.5V
= 2.7V to 4.5V
20
45
ns
ns
CC
CC
l
l
l
l
l
t
t
t
t
CLR Pulse Width
20
7
ns
ns
9
CS/LD High to SCK Positive Edge
LDAC Pulse Width
10
12
13
15
200
ns
CS/LD High to LDAC High or Low Transition
SCK Frequency
ns
50ꢁ Duty Cycle
50
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 8: Digital inputs at 0V or V
.
CC
Note 9: Guaranteed by design and not production tested.
Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND.
Note 2: All voltages are with respect to GND.
Note 3: Linearity and monotonicity are defined from code kL to code
N
2 – 1, where N is the resolution and kL is the lower end code for which
Note 11: V = 5V, internal reference mode. DAC is stepped 1LSꢀ
CC
no output limiting occurs. For V = 2.5V and N = 16, kL = 128 and
REF
between half scale and half scale – 1LSꢀ. Load is 2k in parallel with 200pF
to GND.
Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output
linearity is defined from code 128 to code 65535. For V = 2.5V and
REF
N = 12, kL = 8 and linearity is defined from code 8 to code 4,095.
Note 4: Inferred from measurement at code 128 (LTC2656-16) or code 8
(LTC2656-12).
of one DAC due to a full-scale change at the output of another DAC. It is
measured with V = 5V and using internal reference, with the measured
CC
Note 5: DC crosstalk is measured with V = 5V and using internal
CC
DAC at mid-scale.
reference with the measured DAC at mid-scale.
Note 13: Gain error specification may be degraded for reference input
voltages less than 1V. See Gain Error vs Reference Input Voltage curve in
the Typical Performance Characteristics section.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
2656f
9
LTC2656
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
LTC2656-L16
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.5
4
3
4
3
V
= 3V
V
= 3V
CC
CC
2
2
INL (POS)
INL (NEG)
1
1
0
0
0
–1
–2
–3
–4
–1
–2
–3
–4
–0.5
–1.0
32768
CODE
49152
30 50
32768
CODE
128
65535
–50 –30
128
16384
49152
65535
16384
–10 10
70 90
110 130
TEMPERATURE (°C)
2656 G02
2656 G03
2656 G01
DNL vs Temperature
REFOUT Voltage vs Temperature
1.253
1.252
1.251
1.250
1.249
1.248
1.247
1.0
0.5
V
= 3V
V
= 3V
CC
CC
DNL (POS)
DNL (NEG)
0
–0.5
–1.0
30 50
–50 –30 –10 10
70 90 110 130
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
2656 G04
2656 G05
Settling to 1LSB Rising
Settling to 1LSB Falling
3/4 SCALE TO 1/4
SCALE STEP
CS/LD
3V/DIV
V
= 3V, V = 2.5V
CC
FS
R
= 2k, C = 200pF
L
L
V
OUT
AVERAGE OF 2048
EVENTS
100μV/DIV
8.7μs
8.9μs
V
OUT
100μV/DIV
1/4 SCALE TO 3/4
SCALE STEP
V
= 3V, V = 2.5V
CC
L
FS
CS/LD
3V/DIV
R
= 2k, C = 200pF
L
AVERAGE OF 2048
EVENTS
2μs/DIV
2μs/DIV
2656 G06
2656 G07
2656f
10
LTC2656
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
LTC2656-H16
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL vs Temperature
1.0
0.5
4
3
4
3
V
= 5V
V
= 5V
V
= 5V
CC
CC
CC
2
2
INL (POS)
INL (NEG)
1
1
0
0
0
–1
–2
–3
–4
–1
–2
–3
–4
–0.5
–1.0
32768
CODE
49152
–50 –30
30 50
32768
CODE
128
65535
–10 10
70 90
110 130
128
16384
49152
65535
16384
TEMPERATURE (°C)
2656 G09
2656 G10
2656 G08
DNL vs Temperature
REFOUT Voltage vs Temperature
1.0
0.5
2.054
2.052
2.050
2.048
2.046
2.044
2.042
V
= 5V
V
= 5V
CC
CC
DNL (POS)
DNL (NEG)
0
–0.5
–1.0
30 50
–50 –30 –10 10
70 90 110 130
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
2656 G11
2656 G12
Settling to 1LSB Rising
Settling to 1LSB Falling
CS/LD
5V/DIV
6.1μs
V
OUT
250μV/DIV
3/4 SCALE TO 1/4
SCALE STEP
7.9μs
V
= 5V, V = 4.096V
V
CC
FS
OUT
R
= 2k, C = 200pF
L
250μV/DIV
L
AVERAGE OF 2048
EVENTS
1/4 SCALE TO
R = 2k, C = 200pF
L L
CS/LD
5V/DIV
3/4 SCALE STEP AVERAGE OF 2048
V
CC
V
FS
= 5V,
= 4.096V
EVENTS
2μs/DIV
2μs/DIV
2656 G13
2656 G14
2656f
11
LTC2656
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
LTC2656-12
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Settling to 1LSB (12 Bit) Rising
1.0
0.5
1.0
0.5
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 2.048V
= 2.048V
CS/LD
5V/DIV
4.6μs
0
0
V
OUT
1mV/DIV
–0.5
–1.0
–0.5
–1.0
1/4 SCALE TO
R = 2k, C = 200pF
L L
3/4 SCALE STEP AVERAGE OF 2048
V
V
= 5V,
= 4.095V
EVENTS
CC
FS
2048
3072
2048
3072
2μs/DIV
8
4095
8
4095
1024
1024
2656 G17
CODE
CODE
2656 G15
2656 G16
LTC2656-16
Headroom at Rails vs
Output Current
Load Regulation
Current Limiting
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.20
0.15
0.10
0.05
0
V
V
= 5V (LTC2656-H)
= 3V (LTC2656-L)
V
CC
V
CC
= 5V (LTC2656-H)
= 3V (LTC2656-L)
CC
CC
5V SOURCING
6
INTERNAL REF.
CODE = MID-SCALE
INTERNAL REF.
CODE = MID-SCALE
3V SOURCING
(LTC2656-L)
4
2
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
5V
SINKING
3V SINKING
(LTC2656-L)
–50 –40 –30 –20 –10
0
10 20 30 40 50
(mA)
0
1
2
3
4
I
5
6
7
8
9
10
–50 –40 –30 –20 –10
0
10 20 30 40 50
(mA)
I
(mA)
I
OUT
OUT
OUT
2656 G18
2656 G20
2656 G19
Offset Error vs Temperature
Zero-Scale Error vs Temperature
Gain Error vs Temperature
3.0
2.5
64
48
1.00
0.75
0.50
0.25
0
32
2.0
16
1.5
1.0
0
–16
–32
–48
–64
–0.25
–0.50
–0.75
–1.00
0.5
0
30 50
TEMPERATURE (°C)
–50 –30 –10 10
70 90 110 130
90 110
130
30 50
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
–50 –30 –10 10
70 90 110 130
TEMPERATURE (°C)
2656 G23
2656 G22
3656 G21
2656f
12
LTC2656
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
LTC2656-16
Offset Error vs Reference Input
Gain Error vs Reference Input
ICC Shutdown vs VCC
2.0
64
48
450
400
350
300
250
200
150
100
50
V
= 5.5V
V
= 5.5V
CC
CC
OFFSET ERROR OF 8 CHANNELS
GAIN ERROR OF 8 CHANNELS
1.5
1.0
32
0.5
16
0
0
–0.5
–1.0
–1.5
–2.0
–16
–32
–48
–64
0
1.5
REFERENCE VOLTAGE (V)
1.5
REFERENCE VOLTAGE (V)
0.5
1.0
2.0
2.5
0.5
1.0
2.0
2.5
2.5
3.0
3.5
4.0
(V)
5.5
4.5
5.0
V
CC
2656 G24
2656 G25
2656 G26
Supply Current vs Logic Voltage
Hardware CLR to Mid-Scale
Hardware CLR to Zero-Scale
4.0
3.6
3.2
2.8
2.4
2.0
V
V
= 5V
REF
CODE = FULL-SCALE
CC
SWEEP SCK, SDI, CS/LD
= 2.048V
ꢀETWEEN 0V AND V
CC
V
V
OUT
OUT
1V/DIV
1V/DIV
V
= 5V
CC
V
V
= 5V
REF
CODE = FULL-SCALE
CC
(LTC2656-H)
= 2.048V
CLR
5V/DIV
CLR
5V/DIV
V
= 3V
CC
(LTC2656-L)
0
1
2
3
4
5
1μs/DIV
1μs/DIV
2656 G29
2656 G28
LOGIC VOLTAGE (V)
2656 G27
Mid-Scale Glitch Impulse
Multiplying Bandwidth
Large-Signal Response
8
6
4
2
CS/LD
5V/DIV
0
V
OUT
–2
V
V
= 5V, 6nV•s TYP
CC
V
1V/DIV
OUT
(LTC2656-H16)
5mV/DIV
–4
–6
= 3V, 3nV•s TYP
CC
V
V
V
= 5V
REF(DC)
REF(AC)
CC
–8
V
(LTC2656-L16)
OUT
= 2V
V
V
= 5V
REF
ZERO-SCALE TO FULL-SCALE
CC
5mV/DIV
= 0.2V
= 2.048V
–10
–12
P-P
CODE = FULL-SCALE
2μs/DIV
1k
10k
100k
1M
2.5μs/DIV
2656 G32
2656 G31
FREQUENCY (Hz)
2656 G30
2656f
13
LTC2656
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
LTC2656
DAC-to-DAC Crosstalk (Dynamic)
Power-On Reset Glitch
Power-On Reset to Mid-Scale
LTC2656-H
ONE DAC
SWITCH 0-FS
2V/DIV
V
CC
V
CC
2V/DIV
2V/DIV
LTC2656-H16, V = 5V, 3nV•s TYP
CC
C
= C
= NO LOAD
REFOUT
REFCOMP
V
OUT
2mV/DIV
V
OUT
ZERO-SCALE
LTC2656-H16, V = 5V, <1nV•s TYP
CC
V
10mV/DIV
OUT
C
= C
= 0.1μF
REFOUT
REFCOMP
1V/DIV
V
OUT
2mV/DIV
2μs/DIV
200μs/DIV
250μs/DIV
2656 G32
2656 G34
2656 G35
Reference 0.1Hz to 10Hz
Voltage Noise
Noise Voltage vs Frequency
0.1Hz to 10Hz Voltage Noise
1200
1000
800
600
400
200
0
V
= 5V
V
C
= 1.25V
= C
CC
V
= 5V, V = 2.5V
CC FS
REFOUT
REFCOMP
CODE = MID-SCALE
INTERNAL REF
= 0.1μF
REFOUT
CODE = MID-SCALE
INTERNAL REF
C
= C
= 0.1μF
REFCOMP
REFOUT
C
= C
= 0.1μF
REFCOMP
REFOUT
2μV/DIV
5μV/DIV
LTC2656-H
LTC2656-L
10
1
100
1k
10k 100k
1M
1 SEC/DIV
1 SEC/DIV
2656 G38
2656 G37
FREQUENCY (Hz)
2656 G36
2656f
14
LTC2656
PIN FUNCTIONS (TSSOP/QFN)
REFLO (Pin 1/Pin 19): Reference Low Pin. The voltage
at this pin sets the zero-scale voltage of all DACs. REFLO
should be tied to GND.
SCK (Pin 10/Pin 8): Serial Interface Clock Input. CMOS
and TTL compatible.
SDI (Pin 11/Pin 9): Serial Interface Data Input. Data is
applied to SDI for transfer to the device at the rising edge
of SCK (Pin 10). The LTC2656 accepts input word lengths
of either 24 or 32 bits.
V
to V
(Pins 2, 3, 5, 6, 15, 16, 17, 18/Pins
OUTA
OUTH
20, 1, 3, 4, 13, 14, 15, 16): DAC Analog Voltage Out-
puts. The output range is 0V to 2 times the voltage at the
REFIN/OUT pin.
SDO (Pin 12/Pin 10): Serial Interface Data Output. This
pin is used for daisy-chain operation. The serial output
of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32
SCK rising edges before being output at the next falling
edge. This pin is continuously driven and does not go high
impedance when CS/LD is taken active high.
REFCOMP (Pin 4/Pin 2): Internal Reference Compensa-
tion Pin. For low noise and reference stability, tie a 0.1μF
capacitor to GND. Connect REFCOMP to GND to allow the
use of external reference at start-up.
REFIN/OUT (Pin 7/Pin 5): This pin acts as the internal
reference output in internal reference mode and acts as
the reference input pin in external reference mode. When
acting as an output, the nominal voltage at this pin is
1.25V for L options and 2.048V for H options. For low
noise and reference stability tie a capacitor from this pin
CLR (Pin 13/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causestheDACvoltageoutputstodropto0VifthePORSEL
pin is tied to GND. If the PORSEL pin is tied to V , a logic
CC
to GND. This capacitor value must be ≤C
, where
low at CLR sets all registers to mid-scale code and causes
REFCOMP
C
is the capacitance tied to the REFCOMP pin. In
the DAC voltage outputs to go to mid-scale.
REFCOMP
external reference mode, the allowable reference input
PORSEL (Pin 14/Pin 12): Power-On Reset Select Pin. If
voltage range is 0.5V to V /2.
CC
tied to GND, the DAC resets to zero-scale at power-up. If
LDAC (Pin 8/Pin 6): Asynchronous DAC Update Pin. If
CS/LDishigh,afallingedgeonLDACimmediatelyupdates
the DAC register with the contents of the input register
(similar to a software update). If CS/LD is low when LDAC
goes low, the DAC register is updated after CS/LD returns
high. A low on the LDAC pin powers up the DAC outputs.
All the software power-down commands are ignored if
LDAC is low when CS/LD goes high.
tied to V , the DAC resets to mid-scale at power-up.
CC
V
(Pin 19/Pin 17): Supply Voltage Input. For -L op-
CC
tions, 2.7V ≤ V ≤ 5.5V and for -H options, 4.5V ≤ V
CC
CC
≤ 5.5V.
GND (Pin 20/Pin 18): Ground.
ExposedPad(Pin21/Pin21):Ground. Mustbesoldered
to PCꢀ Ground.
CS/LD (Pin 9/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specified command (see Table 1)
is executed.
2656f
15
LTC2656
BLOCK DIAGRAM
REFCOMP
REFIN/OUT
INTERNAL REFERENCE
REF
REF
GND
V
CC
REFLO
V
DAC A
REF
DAC H
REF
V
V
V
V
OUTA
OUTH
OUTG
OUTF
OUTE
V
DAC G
REF
DAC ꢀ
REF
OUTꢀ
V
DAC C
REF
DAC F
REF
OUTC
V
OUTD
DAC E
DAC D
POWER-ON RESET
PORSEL
SDO
CS/LD
CONTROL LOGIC
DECODE
SCK
SDI
32-ꢀIT SHIFT REGISTER
CLR
LDAC
2656 ꢀD
TIMING DIAGRAMS
t
1
t
t
2
t
t
4
6
3
SCK
1
2
3
23
24
t
10
SDI
t
t
7
5
CS/LD
t
8
SDO
t
t
12
13
LDAC
Figure 1a
2656 F01a
CS/LD
t
13
LDAC
2656 F01b
Figure 1b
2656f
16
LTC2656
OPERATION
The LTC2656 is a family of octal voltage output DACs in
20-lead 4mm × 5mm QFN and in 20-lead thermally en-
hancedTSSOPpackages.EachDACcanoperaterail-to-rail
in external reference mode, or with its full-scale voltage
set by an integrated reference. Four combinations of ac-
curacy (16-bit and 12-bit), and full-scale voltage (2.5V or
4.096V) are available. The LTC2656 is controlled using a
4-wire SPI/MICROWIRE compatible interface.
supply turn-on and turn-off sequences, when the voltage
at V is in transition.
CC
Transfer Function
The digital-to-analog transfer function is:
⎛
⎞
k
VOUT(IDEAL)
=
• 2 • V – VREFLO + V
(
)
REF
REFLO
⎜
⎝
⎟
⎠
N
2
where k is the decimal equivalent of the binary DAC input
Power-On Reset
code, N is the resolution of the DAC, and V is the volt-
REF
TheLTC2656-L/LTC2656-Hcleartheoutputtozeroscaleif
thePORSELpinistiedtoGND,whenpowerisfirstapplied,
makingsysteminitializationconsistentandrepeatable.For
some applications, downstream circuits are active during
DAC power-up and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2656 contains
circuitrytoreducethepower-onglitch.Theanalogoutputs
typicallyriselessthan10mVabovezeroscaleduringpower
on if the power supply is ramped to 5V in 1ms or more.
In general, the glitch amplitude decreases as the power
supply ramp time is increased. See Power-On Reset Glitch
in the Typical Performance Characteristics.
age at the REFIN/OUT pin. The resulting DAC output span
is 0V to 2 • V , as it is necessary to tie REFLO to GND.
REF
V
is nominally 1.25V for LTC2656-L and 2.048V for
LTC2656-H, in internal reference mode.
REF
Table 1. Command and Adress Codes
COMMAND*
C3 C2 C1 C0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All
Write to and Update (Power Up) n
Power Down n
Power Down Chip (All DACs and Reference)
Select Internal Reference (Power-Up Reference)
Alternatively, if the PORSEL pin is tied to V , the
CC
LTC2656-L/ LTC2656-H sets the output to mid-scale when
Select External Reference (Power-Down
Reference)
power is first applied.
1
1
1
1
No Operation
Power Supply Sequencing and Start-Up
ADDRESS (n)*
A3 A2 A1 A0
For the LTC2656 family of parts, the internal reference is
powered up at start-up by default. If an external reference
is to be used, the REFCOMP pin must be hardwired to
GND. Having REFCOMP hardwired to GND at power up
will cause the REFIN/OUT pin to become high impedance
and will allow for the use of an external reference at start-
up. However in this configuration, the internal reference
will still be on even though it is disconnected from the
REFIN/OUT pin and will draw supply current. In order
to use external reference after power-up, the command
Select External Reference (0111b) should be used to turn
the internal reference off (see Table 1.)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
DAC A
DAC ꢀ
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
*Command and address codes not shown are reserved and should not
be used.
Serial Interface
TheCS/LDinputisleveltriggered. Whenthisinputistaken
low, it acts as a chip-select signal, powering on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The voltage at REFIN/OUT should be kept within the range
– 0.3V ≤ REFIN/OUT ≤ V + 0.3V if the external reference
CC
is to be used (see Absolute Maximum Ratings). Particular
care should be taken to observe these limits during power
2656f
17
LTC2656
OPERATION
The 4-bit command, C3-C0, is loaded first; followed by the
4-bitDACaddress, A3-A0;andfinallythe16-bitdataword.
For the LTC2656-16 the data word comprises the 16-bit
input code, ordered MSꢀ-to-LSꢀ. For the LTC2656-12 the
data word comprizes the 12-bit input code, ordered MSꢀ-
to-LSꢀ, followed by four don’t care bits. Data can only be
transferred to the LTC2656 when the CS/LD signal is low.
TherisingedgeofCS/LDendsthedatatransferandcauses
thedevicetocarryouttheactionspecifiedinthe24-bitinput
word. The complete sequence is shown in Figure 2a.
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. ꢀecause of this, the devices can be addressed and
controlledindividuallybysimplyconcatenatingtheirinput
words; the first instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
first device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16- or 12-bit input code,
and is converted to an analog voltage at the DAC output.
The update operation also powers up the selected DAC
if it had been in power-down mode. The data path and
registers are shown in the ꢀlock Diagram.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever
less than eight DAC outputs are needed. When in power
down, the buffer amplifiers, bias circuits and integrated
reference circuits are disabled and draw essentially zero
current. The DAC outputs are put into a high impedance
state, and the output pins are passively pulled to ground
through individual 80k resistors. Input- and DAC-register
contents are not disturbed during power down.
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits must be transferred to the device first,
followed by the 24-bit word as just described. Figure 2b
showsthe32-bitsequence.The32-bitwordisrequiredfor
daisy-chainoperation,andisalsoavailabletoaccommodate
microprocessorsthathaveaminimumwordwidthof16bits
(2bytes).The16-bitdatawordisignoredforallcommands
that do not include a write operation.
Any channel or combination of DAC channels can be put
into power-down mode by using command 0100b in
combination with the appropriate DAC address, (n). The
integrated reference is automatically powered down when
external reference is selected using command 0111b. In
addition, all the DAC channels and the integrated refer-
ence together can be put into power-down mode using
power-down chip command 0101b. For all power-down
commands the 16-bit data word is ignored.
Daisy-Chain Operation
TheserialoutputoftheshiftregisterappearsattheSDOpin.
Data transferred to the device from the SDI input is delayed
32 SCK rising edges before being output at the next SCK
falling edge. The SDO pin is continuously driven and does
not go high impedance when CS/LD is taken active high.
Normal operation resumes by executing any command
which includes a DAC update, in software as shown in
Table 1 or by taking the asynchronous LDAC pin low. The
selected DAC is powered up as its voltage output is up-
dated. When a DAC which is in a powered-down state is
poweredupandupdated,normalsettlingisdelayed.Ifless
than eight DACs are in a powered-down state prior to the
update command, the power-up delay time is 12μs. If, on
TheSDOoutputcanbeusedtofacilitatecontrolofmultiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDIandCS/LD). Sucha“daisy-chain”seriesisconfigured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
the other hand, all eight DACs and the integrated reference
2656f
18
LTC2656
OPERATION
2656f
19
LTC2656
OPERATION
are powered down, then the main bias generation circuit
block has been automatically shut down in addition to the
individual DAC amplifiers and integrated reference. In this
case, the power-up delay time is 14μs. The power up of
the integrated reference depends on the command that
powered it down. If the reference is powered down using
theselectexternalreferencecommand(0111b),thenitcan
only be powered back up using select internal reference
command(0110b). Howeverifthereferencewaspowered
down using power-down chip command (0101b), then in
addition to select internal reference command (0110b),
any command that powers up the DACs will also power
up the integrated reference.
reference. The LTC2656-L has a 1.25V reference that pro-
vides a full-scale DAC output of 2.5V. The LTC2656-H has
a 2.048V reference that provides a full-scale DAC output
of 4.096V. ꢀoth references exhibit a typical temperature
drift of 2ppm/°C. Internal reference mode can be selected
by using command 0110b, and is the power-on default. A
bufferisneedediftheinternalreferenceisrequiredtodrive
external circuitry. For reference stability and low noise, it
is recommended that a 0.1μF capacitor be tied between
REFCOMP and GND. In this configuration, the internal
referencecandriveupto0.1μFcapacitiveloadwithoutany
stability problems. In order to ensure stable operation, the
capacitive load on the REFIN/OUT pin should not exceed
the capacitive load on the REFCOMP pin.
Asynchronous DAC Update Using LDAC
The DAC can also operate in external reference mode us-
ing command 0111b. In this mode, the REFIN/OUT pin
acts as an input that sets the DAC’s reference voltage. The
input is high impedance and does not load the external
reference source. The acceptable voltage range at this
In addition to the update commands shown in Table 1, the
LDAC pin asynchronously updates all the DAC registers
with the contents of the input registers.
If CS/LD is high, a low on the LDAC pin causes all the
DAC registers to be updated with the contents of the
input registers.
pin is 0.5V ≤ REFIN/OUT ≤ V /2. The resulting full-scale
CC
REFIN/OUT
output voltage is 2 • V
. For using external refer-
ence at start-up, see the Power Supply Sequencing and
Start-Up section.
If CS/LD is low, a low going pulse on the LDAC pin before
therisingedgeofCS/LDpowersupalltheDACoutputsbut
does not cause the output to be updated. If LDAC remains
lowaftertherisingedgeofCS/LD,thenLDACisrecognized,
the command specified in the 24-bit word just transferred
is executed and the DAC outputs are updated.
Integrated Reference Buffers
Each of the eight DACs in LTC2656 has its own integrated
high performance reference buffer. The buffers have very
highinputimpedanceanddonotloadthereferencevoltage
source. These buffers shield the reference voltage from
glitchescausedbyDACswitchingandthusminimizeDAC-
to-DACdynamiccrosstalk.TypicallyDAC-to-DACcrosstalk
is less than 3nV•s. ꢀy tying 0.1μF capacitors between
REFCOMP and GND, and also between REFIN/OUT and
GND, this number can be reduced to less than 1nV•s. See
the curve DAC-to-DAC Dynamic Crosstalk in the Typical
Performance Characteristics section.
The DAC outputs are powered up when LDAC is taken
low, independent of the state of CS/LD. The integrated
reference is also powered up if it was powered down us-
ing power-down chip (0101b) command. The integrated
reference will not power up when LDAC is taken low,
if it was powered down using select external reference
(0111b) command.
If LDAC is low at the time CS/LD goes high, it inhibits any
software power-down command (power down n, power-
down chip, select external reference) that was specified
in the input word.
Voltage Outputs
EachoftheLTC2656’seightrail-to-railoutputamplifierscon-
tainedinthesepartshasaguaranteedloadregulationwhen
sourcing or sinking up to 15mA at 5V (7.5mA at 3V).
Reference Modes
For applications where an accurate external reference is
notavailable,theLTC2656hasauser-selectable,integrated
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
2656f
20
LTC2656
OPERATION
load conditions. The measured change in output voltage
permilliampereofforcedloadcurrentchangeisexpressed
in LSꢀ/mA.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shielditfromnoise.Analoggroundshouldbeacontinuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSꢀ/mA to Ohms. The amplifiers’ DC output
impedance is 0.04Ω when driving a load well away from
the rails.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground.TheREFLOpinshouldbeconnectedtothesystem
star ground. Resistance from the REFLO pin to the system
star ground should be as low as possible.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
Since the analog outputs of the device cannot go below
ground, they may limit the lowest codes as shown in Fig-
ure 3b. Similarly, limiting can occur in external reference
Board Layout
TheexcellentloadregulationandDCcrosstalkperformance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
mode near full scale when the REFIN/OUT pin is at V /2.
CC
If V
= V /2 and the DAC full-scale error (FSE)
is positive, the output for the highest codes limits at V
REFIN/OUT
CC
CC
The PC board should have separate areas for the analog
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals
awayfromsensitiveanalogsignalsandfacilitatestheuseof
separatedigitalandanaloggroundplaneswhichhavemini-
mal capacitive and resistive interaction with each other.
are shown in Figure 3c. No full-scale limiting can occur if
≤ (V – FSE)/2.
V
REFIN/OUT
CC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
POSITIVE
FSE
V
REF
= V
CC
V
REF
= V
CC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
2656 F03
(3c)
OUTPUT
VOLTAGE
0
32,768
65,535
INPUT CODE
(3a)
0V
NEGATIVE
OFFSET
INPUT CODE
(3b)
Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (3a) Overall Transfer Function (3b) Effect of
Negative Offset for Codes Near Zero-Scale (3c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2656f
21
LTC2656
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 p0.10
2.74
(.108)
4.50 p0.10
6.40
(.252)
ꢀSC
2.74
(.108)
SEE NOTE 4
0.45 p0.05
1.05 p0.10
0.65 ꢀSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.65
(.0256)
ꢀSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (Cꢀ) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCꢀ METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
2656f
22
LTC2656
PACKAGE DESCRIPTION
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev ꢀ)
0.70 p0.05
2.65 p 0.05
4.50 p 0.05
3.10 p 0.05
1.50 REF
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 ꢀSC
2.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
0.75 p 0.05
1.50 REF
19
4.00 p 0.10
R = 0.05 TYP
(2 SIDES)
20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
2.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD20) QFN 0506 REV ꢀ
0.25 p 0.05
0.200 REF
R = 0.115
TYP
0.50 ꢀSC
0.00 – 0.05
ꢀOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO ꢀE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON ꢀOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL ꢀE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND ꢀOTTOM OF PACKAGE
2656f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2656
TYPICAL APPLICATION
Digitally Controlled Output Voltage 1.1A Supply
V
V
CC
CC
JP2
4
2
3
1
MID-SCALE
ZERO-SCALE
C1
0.1μF
V
IN
C1
0.1μF
C1
0.1μF
R4
7.5k
1.2V TO 36V
IN
LT3080
REFCOMP REFIN/OUT LDAC PORSEL V
CLR
CC
7
8
20
1
3
CS
SCK
SDO
V
V
V
OUTA
OUTꢀ
OUTC
OUTD
V
TO
CONTROL
MICROCONTROLLER
10
9
+
–
4
LTC2656*
SDI
V
13
14
15
16
V
1μF
OUTE
OUT
V
OUTF
V
OUT
V
V
OUTG
OUTH
SET
2.2μF
GND REFLO GND
21
19
18
NOTE: LT3080 MINIMUM LOAD CURRENT
IS 0.5mA
2656 TA02
*PIN NUMꢀERS INDICATED ARE FOR THE QFN PACKAGE
RELATED PARTS
PART NUMBER
LTC1660/LTC1665
LTC1664
DESCRIPTION
COMMENTS
Octal 10-/8-ꢀit V
DACs in 16-Pin Narrow SSOP
V
CC
V
CC
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
= 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
Quad 10-ꢀit V
DAC in 16-Pin Narrow SSOP
OUT
LTC1821
Single 16-ꢀit V
DAC with 1LSꢀ INL, DNL
Parallel Interface, Precision 16-ꢀit Settling in 2ꢂs for 10V Step
OUT
LTC2600/LTC2610/ Octal 16-/14-/12-ꢀit V
LTC2620
DACs in 16-Lead Narrow SSOP
250ꢂA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2601/LTC2611/ Single 16-/14-/12-ꢀit V
LTC2621
DACs in 10-Lead DFN
300ꢂA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2602/LTC2612/ Dual 16-/14-/12-ꢀit V
LTC2622
DACs in 8-Lead MSOP
DACs in 16-Lead SSOP
300ꢂA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
LTC2604/LTC2614/ Quad 16-/14-/12-ꢀit V
LTC2624
250ꢂA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
OUT
OUT
2
LTC2605/LTC2615/ Octal 16-/14-/12-ꢀit V
LTC2625
DACs with I C Interface
250ꢂA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output
270ꢂA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output
250ꢂA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with
2
LTC2606/LTC2616/ Single 16-/14-/12-ꢀit V
LTC2626
DACs with I C Interface
OUT
2
LTC2609/LTC2619/ Quad 16-/14-/12-ꢀit V
LTC2629
DACs with I C Interface
OUT
Separate V Pins for Each DAC
REF
LTC2636
Octal 12-/10-/8-ꢀit V
DACs with 10ppm/°C Reference
125ꢂA per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V
Reference, Rail-to-Rail Output, SPI Interface
OUT
LTC2641/LTC2642
LTC2704
Single 16-/14-/12-ꢀit V
DACs with 1LSꢀ INL, DNL
1LSꢀ (Max) INL, DNL, 3mm x 3mm DFN and MSOP Packages,
120ꢂA Supply Current, SPI Interface
OUT
Quad 16-/14-/12-ꢀit V
1LSꢀ DNL
DACs with 2LSꢀ INL,
DACs with 1LSꢀ INL,
Software Programmable Output Ranges Up to 10V, SPI Interface
OUT
LTC2755
Quad 16-/14-/12-ꢀit I
1LSꢀ DNL
Software Programmable Output Ranges Up to 10V, Parallel Interface
OUT
2656f
LT 0809 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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