LTC2752ACLX-PBF [Linear]
Dual16-Bit SoftSpan IOUT DACs; Dual16位的SoftSpan IOUT DAC的
| 型号： | LTC2752ACLX-PBF |
| 厂家： | 
Linear |
| 描述： | Dual16-Bit SoftSpan IOUT DACs |
| 文件： | 总24页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2752
Dual16-Bit
SoftSpan I DACs
OUT
FeaTures
DescripTion
The LTC®2752 is a dual 16-bit multiplying serial-input,
current-outputdigital-to-analogconverter.Itoperatesfrom
a single 3V to 5V supply and is guaranteed monotonic
over temperature. The LTC2752A provides full 16-bit
performance( 1LSBINLandDNL,max)overtemperature
without any adjustments. This SoftSpan™ DAC offers
six output ranges (up to 1ꢀV) that can be programmed
through the 3-wire SPI serial interface, or pinstrapped for
operation in a single range.
n
Program or Pin-Strap Six Output Ranges
0V to 5V, 0V to 10V, –2.5V to 7.5V, 2.5V, 5V, 10V
n
Maximum 16-Bit INL Error: 1 LSB oꢀer
Temperature
n
Guaranteed Monotonic oꢀer Temperature
n
Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V)
n
Serial Readback of All On-Chip Registers
n
1μA Maximum Supply Current
n
2.7V to 5.5V Single-Supply Operation
n
16-Bit Settling Time: 2µs
Any on-chip register (including DAC output-range set-
tings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
n
Voltage-Controlled Offset and Gain Trims
n
Clear and Power-On-Reset to ꢀV Regardless of
Output Range
48-Pin 7mm × 7mm LQFP Package
n
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to ꢀV regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178.
applicaTions
n
High Resolution Offset and Gain Adjustment
n
Process Control and Industrial Automation
n
Automatic Test Equipment
n
Data Acquisition Systems
Typical applicaTion
Dual 16-Bit VOUT DAC with Software-Selectable Ranges
REFERENCE
5V
+
–
Integral Nonlinearity (INL)
1.0
R
10ꢀ ꢁANꢂE
0.8
FBA
I
–
+
OUT1A
OUT2A
0.6
I
V
OUTA
DAC A
0.4
0.2
V
DD
V
OSADJA
SPI with READBACK
GND
0
LTC2752
R
I
FBB
–0.2
–0.4
–
+
OUT1B
OUT2B
I
V
OUTB
DAC B
–0.6
–0.8
–1.0
V
OSADJB
0
16384
32768
CODE
49152
65535
–
+
2752 TA01b
ALL AMPLIFIERS 1/2 LT1469
REFERENCE
5V
2752 TA01
2752f
ꢀ
LTC2752
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
I
, I
to GND............................................ ꢀ.3V
OUT1X OUT2X
R
, R
, REFX, R , R
, V
,
INX COMX
FBX OFSX OSADJX
GE
to GND ....................................................... 18V
ADJX
V
to GND..................................................–ꢀ.3V to 7V
DD
Digital Inputs to GND................................... –ꢀ.3V to 7V
REFA
REFA
COMA
1
2
3
4
5
6
7
8
9
36 REFB
35 REFB
Digital Outputs to GND ..... –ꢀ.3V to V +ꢀ.3V (max 7V)
Operating Temperature Range
DD
R
34 R
33 GE
32 R
31 R
INB
30 GND
COMB
ADJB
INB
GE
ADJA
R
LTC2752C ................................................ ꢀ°C to 7ꢀ°C
LTC2752I .............................................–4ꢀ°C to 85°C
Maximum Junction Temperature .......................... 15ꢀ°C
Storage Temperature Range ..................–65°C to 15ꢀ°C
Lead Temperature (Soldering, 1ꢀ sec)...................3ꢀꢀ°C
INA
R
INA
GND
I
I
29 I
28 I
OUT2AS
OUT2AF
OUT2BS
OUT2BF
GND 10
CS/LD 11
SDI 12
27 GND
26 LDAC
25 S2
LX PACKAGE
48-LEAD (7mm s 7mm) PLASTIC LQFP
T
JMAX
= 15ꢀ°C, θ = 58°C/W
JA
orDer inForMaTion
LEAD FREE FINISH
LTC2752BCLX#PBF
LTC2752BILX#PBF
LTC2752ACLX#PBF
LTC2752AILX#PBF
PART MARKING*
LTC2752LX
PACKAGE DESCRIPTION
TEMPERATURE RANGE
ꢀ°C to 7ꢀ°C
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
LTC2752LX
–4ꢀ°C to 85°C
ꢀ°C to 7ꢀ°C
LTC2752LX
LTC2752LX
–4ꢀ°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
2752f
ꢁ
LTC2752
elecTrical characTerisTics VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2752B
TYP
LTC2752A
SYMBOL
Static Performance
Resolution
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
l
l
l
l
l
16
16
16
16
Bits
Bits
Monotonicity
DNL
INL
GE
Differential Nonlinearity
Integral Nonlinearity
Gain Error
1
2
ꢀ.2
ꢀ.4
2
1
1
LSB
LSB
All Output Ranges
∆Gain/∆Temp
2ꢀ
12
LSB
Gain Error Temperature
Coefficient
ꢀ.25
ꢀ.25
ppm/°C
l
l
BZE
Bipolar Zero Error
All Bipolar Ranges
12
1
1
8
1
LSB
Bipolar Zero Temperature
Coefficient
ꢀ.15
ꢀ.ꢀ1
ꢀ.15
ppm/°C
Unipolar Zero-Scale Error
Power Supply Rejection
Unipolar Ranges (Note 3)
ꢀ.ꢀ1
LSB
l
l
PSR
V
V
= 5V, 1ꢀ0
= 3V, 1ꢀ0
ꢀ.4
1
ꢀ.ꢀ3
ꢀ.1
ꢀ.2
ꢀ.5
LSB/V
LSB/V
DD
DD
I
I
Leakage Current
T = 25°C
MIN
ꢀ.ꢀ5
2
5
ꢀ.ꢀ5
2
5
nA
nA
LKG
OUT1
A
l
T
to T
MAX
VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Pins
l
l
l
l
l
l
Reference Inverting Resistors
DAC Input Resistance
Feedback Resistors
(Note 4)
16
8
2ꢀ
1ꢀ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
R
R
R
(Notes 5, 6)
(Note 6)
REF
FB
8
1ꢀ
Bipolar Offset Resistors
Offset Adjust Resistors
Gain Adjust Resistors
Output Capacitance
(Note 6)
16
2ꢀ
OFS
R
1ꢀ24
2ꢀ48
128ꢀ
256ꢀ
VOSADJ
R
GEADJ
IOUT1
C
Full-Scale
Zero-Scale
9ꢀ
4ꢀ
Dynamic Performance
Output Settling Time
Span Code = ꢀꢀꢀꢀ, 1ꢀV Step. To ꢀ.ꢀꢀ150 FS
(Note 7)
2
μs
Glitch Impulse
V
DD
V
DD
= 5V (Note 8)
= 3V (Note 8)
2.2
ꢀ.6
nV•s
nV•s
Digital-to-Analog Glitch Impulse
Reference Multiplying BW
(Note 9)
ꢀV to 5V Range, V = 3V
2
1
nV•s
MHz
,
RMS
REF
Code = Full Scale, –3dB BW
Multiplying Feedthrough Error
ꢀV to 5V Range, V
Sine Wave
=
1ꢀV, 1ꢀkHz
ꢀ.4
mV
REF
Analog Crosstalk
(Note 1ꢀ)
–1ꢀ9
–1ꢀ8
13
dB
dB
THD
Total Harmonic Distortion
Output Noise Voltage Density
(Note 11) Multiplying
(Note 12) at I
nV/√Hz
OUT1
2752f
ꢂ
LTC2752
elecTrical characTerisTics VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
l
l
V
Supply Voltage
2.7
5.5
1
V
DD
I
V
Supply Current
Digital Inputs = ꢀV or V
DD
ꢀ.5
μA
DD
DD
Digital Inputs
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
3.3V ≤ V ≤ 5.5V
2.4
2
V
V
IH
DD
2.7V ≤ V < 3.3V
DD
l
l
V
4.5V < V ≤ 5.5V
ꢀ.8
ꢀ.6
V
V
IL
DD
2.7V ≤ V ≤ 4.5V
DD
Hysteresis Voltage
ꢀ.1
V
µA
pF
l
l
I
IN
Digital Input Current
Digital Input Capacitance
V
V
= GND to V
DD
1
6
IN
C
IN
= ꢀV (Note 13)
IN
Digital Outputs
l
l
V
OH
V
OL
Digital Output High Voltage
Digital Output Low Voltage
I
I
= 2ꢀꢀµA, 2.7V ≤ V ≤ 5.5V
V – ꢀ.4
DD
V
V
OH
DD
= 2ꢀꢀµA, 2.7V ≤ V ≤ 5.5V
ꢀ.4
OL
DD
TiMing characTerisTics
The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
= 4.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
l
l
l
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
t
t
SDI Valid to SCK Set-Up
SDI Valid to SCK Hold
SCK High Time
7
7
ns
ns
1
2
11
11
9
ns
3
SCK Low Time
ns
4
CS/LD Pulse Width
ns
5
LSB SCK High to CS/LD High
CS/LD Low to SCK Positive Edge
CS/LD High to SCK Positive Edge
SRO Propagation Delay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/LD High to RFLAG High
SCK Frequency
4
ns
6
4
ns
7
4
ns
8
C
= 1ꢀpF
18
ns
9
LOAD
36
15
ns
1ꢀ
11
12
13
ns
C
C
= 1ꢀpF (Note 13)
= 1ꢀpF (Note 13)
5ꢀ
4ꢀ
4ꢀ
ns
LOAD
ns
LOAD
5ꢀ0 Duty Cycle (Note 14)
MHz
V
DD
= 2.7V to 3.3V
l
l
l
l
l
l
l
t
t
t
t
t
t
t
SDI Valid to SCK Set-Up
SDI Valid to SCK Hold
SCK High Time
9
9
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
15
15
12
5
SCK Low Time
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK Positive Edge
5
2752f
ꢃ
LTC2752
TiMing characTerisTics The l denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
t
t
t
t
t
t
CS/LD High to SCK Positive Edge
SRO Propagation Delay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/LD High to RFLAG high
SCK Frequency
5
8
C
LOAD
= 1ꢀpF
26
ns
9
6ꢀ
2ꢀ
ns
1ꢀ
11
12
13
ns
C
C
= 1ꢀpF (Note 13)
= 1ꢀpF (Note 13)
7ꢀ
6ꢀ
25
ns
LOAD
ns
LOAD
5ꢀ0 Duty Cycle (Note 14)
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 8: Measured at the major carry transition, ꢀV to 5V range. Output
amplifier: LT1468; C = 5ꢀpF.
FB
Note 9. Full-scale transition; REF = ꢀV.
Note 10. Analog Crosstalk is defined as the AC voltage ratio V
/V
,
OUTB REFA
expressed in dB. REFB is grounded, and DAC B is set to ꢀV-5V span and
zero-, mid- or full- scale code. V is a 3V , 1kHz sine wave.
REFA
RMS
Note 3: Calculation from feedback resistance and I
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
leakage current
OUT1
Note 11. REF = 6V
amplifier = LT1469.
Note 12. Calculation from V = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and
B = bandwidth (Hz). ꢀV to 5V Range; zero-, mid-, or full- scale.
at 1kHz. ꢀV to 5V range. DAC code = FS. Output
RMS
n
Note 4: Input resistors measured from R to R
; feedback resistors
INX
COMX
measured from R
to REFX.
COMX
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
and from the specified pin to I
Note 13. Guaranteed by design, not subject to test.
Note 14. When using SRO, maximum SCK frequency f
is limited by
MAX
I
.
OUT2X
OUT1X
SRO propagation delay t as follows:
9
Note 7: Using LT1468 with C
= 27pF. A ꢀ.ꢀꢀ150 settling time
FEEDBACK
1
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
fMAX
=
, where t is the setup time of the receiving device.
S
2 t + t
9
S
2752f
ꢄ
LTC2752
Typical perForMance characTerisTics
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL ꢀs Temperature
1.0
0.8
1.0
0.8
1.0
0.8
10ꢀ RANGE
10ꢀ ꢁRNGE
10ꢀ ꢁRNGE
0.6
0.6
0.6
0.4
0.4
0.4
+INL
–INL
0.2
0.2
0.2
0
0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
20
TEMPERATURE (°C)
40
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
–40
–20
0
60
80
2752 G02
2752 G03
2752 G01
DNL ꢀs Temperature
Gain Error ꢀs Temperature
Bipolar Zero Error ꢀs Temperature
1.0
0.8
8
6
4
2
8
6
4
2
0ꢀ.5ꢁꢁpm°C TꢂP
±0ꢀ25ꢁꢁpm°C TꢂP
10ꢀ RANGE
0.6
0.4
+DNL
–DNL
0.2
0.0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–2
±2ꢀ5ꢃ
±5ꢃ
–4
–6
–8
–4
–6
–8
2ꢀ5ꢃ
±±0ꢃ
5ꢃ
0ꢃ TO 5ꢃ
.0ꢃ
0ꢃ TO ±0ꢃ
–2ꢀ5ꢃ TO 7ꢀ5ꢃ
–2ꢀ5ꢃ TO 7ꢀ5ꢃ
–40
–20
0
20
TEMPERATURE (°C)
40
60
80
–40
–20
0
40
60
80
–20
0
40
20
–40
60
80
20
TEMPERATURE (°C)
TEMPERATURE (°C)
2752 G04
2752 G06
2752 G05
2752f
ꢅ
LTC2752
Typical perForMance characTerisTics
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
INL ꢀs Reference Voltage
DNL ꢀs Reference Voltage
1.0
1.0
0.8
5V RꢀNGꢁ
5V RꢀNGꢁ
0.8
0.6
0.4
0.6
0.4
+DNL
+DNL
–DNL
+INL
–INL
+INL
–INL
0.2
0.0
0.2
0.0
–DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
V(R ) (V)
V(R ) (V)
IN
IN
2752 G08
2752 G07
Multiplying Frequency Response
ꢀs Digital Code
INL ꢀs VDD
DNL ꢀs VDD
1.0
0.8
1.0
ALL BITS ON
D15
D14
D13
D12
D11
D10
D9
0
–20
10V ꢀRNGꢁ
10V ꢀRNGꢁ
0.8
0.6
0.6
0.4
0.4
–40
D8
+INL
–INL
+INL
–INL
D7
0.2
0.2
D6
–60
D5
0.0
0.0
D4
D3
–80
D2
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
D1
D0
–100
–120
–140
0V TO 5V OUTPUT RANGE
LT1468 OUTPUT AMPLIFIER
FEEDBACK
ALL BITS OFF
C
= 15pF
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
100
1k
10k
100k
1M
10M
V
(V)
V
(V)
DD
FREQUENCY (Hz)
DD
2752 G10
2752 G09
2752 G17
2752f
ꢆ
LTC2752
Typical perForMance characTerisTics
VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted.
Supply Current
ꢀs Logic Input Voltage
Logic Threshold
ꢀs Supply Voltage
Supply Current
ꢀs Clock Frequency
5
4
3
2
1
0
100
10
2
1.75
1.5
ALTERNATING ZERO
AND FULL-SCALE
CLR, LDAC, SDI, SCK,
CS/LD TIED TOGETHER
1
RISING
V
= 5V
V
DD
0.1
1.25
1
FALLING
= 3V
DD
0.01
0.001
V
= 5V
DD
3
0.75
0.5
V
= 3V
DD
2
0.0001
0
1
4
5
1
100
10k
1M
100M
2.5
3.5
4
4.5
5
5.5
3
DIGITAL INPUT VOLTAGE (V)
V
(V)
DD
SCK FREQUENCY (Hz)
2752 G11
2752 G12
2752 G13
Settling Full-Scale Step
Midscale Glitch (VDD = 3V)
Midscale Glitch (VDD = 5V)
2.2nV•s TYP
0.6nV•s TYP
CS/LD
5V/DIV
CS/LD
5V/DIV
UPD
5V/DIV
GATED
SETTLING
WAVEFORM
100µV/DIV
(AVERAGED)
V
V
OUT
OUT
5mV/DIV
5mV/DIV
(AVERAGED)
(AVERAGED)
2752 G15
2752 G16
2752 G14
500ns/DIV
500ns/DIV
500ns/DIV
0V TO 5V RANGE
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
LT1468 AMP; C
= 20pF
FEEDBACK
LT1468 OUTPUT AMPLIFIER
0V TO 10V STEP
C
= 50pF
C
= 50pF
FEEDBACK
FEEDBACK
V
t
= –10V; SPAN CODE = 0000
= 1.7µs to 0.0015% (16 BITS)
REF
FALLING MAJOR CARRY TRANSITION.
RISING TRANSITION IS SIMILAR OR BETTER.
FALLING MAJOR CARRY TRANSITION.
SETTLE
RISING TRANSITION IS SIMILAR OR BETTER.
2752f
ꢇ
LTC2752
pin FuncTions
REFA (Pins 1, 2): Feedback Resistor for the DAC A Refer-
ence Inverting Amplifier, and Reference Input for DAC A.
The 2ꢀk feedback resistor is connected internally from
SRO (Pin 14): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clocking
out after the last address bit Aꢀ is clocked in. SRO is an
active output only when the chip is selected (i.e., when
CS/LD is low). Otherwise SRO presents a high impedance
output in order to allow other parts to control the bus.
REFA to R . For normal operation tie this pin to the
COMA
output of the DAC A reference inverting amplifier (see
Typical Applications). Typically –5V; accepts up to 15V.
Pins 1 and 2 are internally shorted together.
V
(Pin16):PositiveSupplyInput;2.7V≤V ≤5.5V. By-
DD
DD
R
(Pin 3): Virtual Ground Point for the DAC A Ref-
pass with a ꢀ.1μF low ESR ceramic capacitor to ground.
COMA
erence Amplifier Inverting Resistors. The 2ꢀk reference
CLR (Pin 19): Asynchronous Clear Input. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
inverting resistors are connected internally from R to
INA
R
COMA
and from R
to REFA, respectively (see Block
COMA
Diagram). For normal operation tie R
to the negative
COMA
RFLAG (Pin 20): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
input of the external reference inverting amplifier (see
Typical Applications).
GE
(Pin 4): Gain Adjust Pin for DAC A. This control
ADJA
DNC (Pin 21): Do not connect this pin.
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LSB is
the same for any output range. See System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S2, S1 and Sꢀ (Pins 25, 24
and 23) to configure all DACs for operation in a single,
fixed output range.
R
(Pins 5, 6): Input Resistor for External Reference
INA
To configure the part for manual span use, tie M-SPAN
Inverting Amplifier. The 2ꢀk input resistor is connected
directly to V . The DAC output range is then set via
DD
internally from R to R . For normal operation tie
INA
COMA
hardware pin strapping of pins S2, S1 and Sꢀ (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
R
to the external positive reference voltage (see Typical
INA
Applications). Either or both of these precision-matched
resistor sets (each set comprising R , R and R
)
EFX
INX COMX
ToconfigurethepartforSoftSpanuse,tieM-SPANdirectly
to GND. The output ranges are then individually control-
lable through the SPI port; and pins S2, S1 and Sꢀ have
no effect.
may be used to invert positive references to provide the
negativevoltagesneededbytheDACs.Typically5V;accepts
up to 15V. Pins 5 and 6 are internally shorted together.
GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to
ground.
See Manual Span Configuration in the Operation section.
M-SPANmustbeconnectedeitherdirectlytoGND(SoftSpan
I
, I
(Pins 8, 9): DAC A Current Output
OUT2AS OUT2AF
configuration) or to V (manual span configuration).
DD
Complement Sense and Force Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Typical Applications section).
S0 (Pin 23): Span Bit ꢀ Input. In Manual Span mode
(M-SPANtiedtoV ),pinsSꢀ,S1andS2arepin-strapped
DD
to select a single fixed output range for all DACs. These
pins should be tied to either GND or V even if they are
DD
CS/LD (Pin 11): Synchronous Chip Select and Load Input
Pin.
unused.
S1(Pin24):SpanBit1Input.InManualSpanmode(M-SPAN
SDI (Pin 12): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK) when CS/LD is low.
tied to V ), pins Sꢀ, S1 and S2 are pin-strapped to select
DD
a single fixed output range for all DACs. These pins should
be tied to either GND or V even if they are unused.
SCK (Pin 13): Serial Clock Input.
DD
2752f
ꢈ
LTC2752
pin FuncTions
S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (M-
Typical Applications). Typically –5V; accepts up to 15V.
Pins 35 and 36 are internally shorted together.
SPAN tied to V ), pins Sꢀ, S1 and S2 are pin-strapped
DD
to select a single fixed output range for all DACs. These
R
(Pins 37, 38): Bipolar Offset Resistor for DAC B.
OFSB
pins should be tied to either GND or V even if they are
DD
These pins provide the translation of the output voltage
unused.
range for bipolar spans. Accepts up to 15V; for normal
LDAC (Pin 26): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
operation tieto the positive referencevoltage at R (Pins
INB
31, 32). Pins 37 and 38 are internally shorted together.
R
(Pins 39, 40): DAC B Feedback Resistor. For normal
FBB
I
, I
(Pins 28, 29): DAC B Current Output
operation tieto the outputofthe I/V converter amplifier for
OUT2BF OUT2BS
Complement Force and Sense Pins. Tie to ground via a
clean, low impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Typical Applications section).
DAC B (see Typical Applications). The DAC output current
fromI
flowsthroughthefeedbackresistortotheR
FBB
OUT1B
pins. Pins 39 and 4ꢀ are internally shorted together.
I
(Pin 41): DAC B Current Output. This pin is a virtual
OUT1B
R
(Pins31,32):InputResistorfortheExternalReference
ground when the DAC is operating and should reside at
ꢀV. For normal operation tie to the negative input of the I/V
converter amplifier for DAC B (see Typical Applications).
INB
Inverting Amplifier. The 2ꢀk input resistor is connected
internally from R to R . For normal operation tie
INB
COMB
R
to the external positive reference voltage (see Typical
INB
V
(Pin 42): DAC B Offset Adjust Pin. This voltage
OSADJB
Applications). Either or both of these precision matched
controlpincanbeusedtonullunipolaroffsetorbipolarzero
error. The offset change expressed in LSB is the same for
anyoutputrange.SeeSystemOffsetandGainAdjustments
in the Operation section. Tie to ground if not used.
resistor sets (each set comprising R , R and R
)
EFX
INX COMX
may be used to invert positive references to provide the
negative voltages needed by the DACs. Typically 5V; ac-
cepts up to 15V. Pins 31 and 32 are internally shorted
together.
V
(Pin 43): DAC A Offset Adjust Pin. This voltage
OSADJA
controlpincanbeusedtonullunipolaroffsetorbipolarzero
error. The offset change expressed in LSB is the same for
anyoutputrange.SeeSystemOffsetandGainAdjustments
in the Operation section. Tie to ground if not used.
GE
(Pin 33): Gain Adjust Pin for DAC B. This control
ADJB
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LSB is
the same for any output range. See System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
I
(Pin 44): DAC A Current Output. This pin is a virtual
OUT1A
ground when the DAC is operating and should reside at
ꢀV. For normal operation tie to the negative input of the I/V
converter amplifier for DAC A (see Typical Applications).
R
(Pin 34): Virtual Ground Point for the DAC B Ref-
COMB
erence Amplifier Inverting Resistors. The 2ꢀk reference
R
(Pins 45, 46): DAC A Feedback Resistor. For normal
inverting resistors are connected internally from R to
FBA
INB
operation tieto the outputofthe I/V converter amplifier for
R
and from R
to REFB, respectively (see Block
COMB
COMB
DAC A (see Typical Applications). The DAC output current
Diagram). For normal operation tie R
to the negative
COMB
fromI
flowsthroughthefeedbackresistortotheR
FBA
input of the external reference inverting amplifier (see
OUT1A
pins. Pins 45 and 46 are internally shorted together.
Typical Applications).
R
(Pins 47, 48): Bipolar Offset Resistor for DAC A.
REFB (Pins 35, 36): Feedback Resistor for the DAC B
Reference Inverting Amplifier, and Reference Input for
DAC B. The 2ꢀk feedback resistor is connected internally
OFSA
This pin provides the translation of the output voltage
range for bipolar spans. Accepts up to 15V; for normal
operation tieto the positive referencevoltage at R (Pins
from REFB to R
. For normal operation tie this pin to
INA
COMB
5, 6). Pins 47 and 48 are internally shorted together.
the output of the DAC B reference inverting amplifier (see
2752f
ꢀ0
LTC2752
block DiagraM
16
V
DD
R
INA
(5, 6)
(31, 32) R
INB
2.56M
2.56M
4
3
33
20k
20k
20k
20k
GE
R
GE
R
ADJA
ADJB
34
COMB
COMA
(35, 36) REFB
REFA (1, 2)
(37, 38) R
OFSB
R
R
I
(47, 48)
OFSA
CODE REGISTERS
CODE REGISTERS
16
3
16
3
(39, 40) R
FBB
(45, 46)
FBA
DAC REG INPUT REG
INPUT REG DAC REG
DAC A
16-BIT WITH
SPAN SELECT
DAC B
16-BIT WITH
SPAN SELECT
44
41
I
OUT1B
OUT1A
SPAN REGISTERS
SPAN REGISTERS
8
9
29
28
42
DAC REG INPUT REG
INPUT REG DAC REG
I
I
I
OUT2BS
OUT2AS
OUT2AF
I
OUT2BF
43
V
V
OSADJB
OSADJA
CONTROL AND READBACK LOGIC
POWER-ON
RESET
GND (7, 10, 15, 17, 18, 27, 30)
M-SPAN
22
S0
23
S1
24
S2
25
RFLAG
CLR
19
CS/LD SDI
11 12
SCK
13
LDAC
26
SRO
20
14
2752 BD
2752f
ꢀꢀ
LTC2752
TiMing DiagraM
t
1
t
6
t
t
t
4
2
3
1
2
31
32
SCK
SDI
t
8
LSB
t
t
7
5
CS/LD
LDAC
SRO
t
11
t
9
Hi-Z
LSB
2752 TD
2752f
ꢀꢁ
LTC2752
operaTion
Output Ranges
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
TheLTC2752isadual,current-output,serial-inputprecision
multiplying DAC with selectable output ranges. Ranges
can either be programmed in software for maximum flex-
ibility—each of the DACs can be programmed to any one
ofsixoutputranges—orhardwiredthroughpin-strapping.
Twounipolarrangesareavailable(ꢀVto5VandꢀVto1ꢀV),
and four bipolar ranges ( 2.5V, 5V, 1ꢀV and –2.5V to
7.5V). These ranges are obtained when an external pre-
cision 5V reference is used. The output ranges for other
reference voltages are easy to calculate by observing that
each range is a multiple of the external reference voltage.
Therangescanthenbeexpressed:ꢀ to 1×,ꢀ to 2×, ꢀ.5×,
1×, 2×, and –ꢀ.5× to 1.5×.
Input and DAC Registers
The LTC2752 has 5 internal registers for each DAC, a total
of 1ꢀ registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers—one set for the
code data, and one for the output range of the DAC—plus
one readback register. Double buffering provides the ca-
pability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Manual Span Configuration
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2752 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to V . The active output range for all DACs is
DD
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
then set via hardware pin strapping of pins S2, S1 and Sꢀ
(rather than through the SPI port); and Write and Update
commands have no effect on the active output span. See
Figure 1 and Table 3.
Note that updates always include both Code and Span
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been changed via a Write operation.
V
DD
V
LTC2752
DD
–
+
DAC A
DAC B
10V
10V
Serial Interface
M-SPAN
S2
When the CS/LD pin is taken low, the data on the SDI
pin is loaded into the shift register on the rising edge of
the clock (SCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2752 is a 4-bit command
word (C3 C2 C1 Cꢀ), followed by a 4-bit address word
(A3 A2 A1 Aꢀ) and 16 data (span or code) bits, MSB first.
Figure 2 shows the SDI input word syntax to use when
S1
–
+
S0
CS/LD SDI SCK
2752 F01
Figure 1. Using M-SPAN to Configure the LTC2752
for Single-Span Operation ( 10V Range Shown)
2752f
ꢀꢂ
LTC2752
operaTion
and Code) is copied into its Readback register and seri-
ally shifted out through the SRO pin. Figure 3 shows the
loading and readback sequences.
writing code or span. If a 32-bit input sequence is used,
the first eight bits must be zeros, followed by the same
sequence as for a 24-bit wide input. Figure 3 shows the
input and readback sequences for both 24-bit and 32-bit
operations.
Inthedatafield(D15-Dꢀ)ofanynon-readinstructioncycle,
SROshiftsoutthecontentsofthebufferthatwasspecified
intheprecedingcommand.This“rollingreadback”default
mode of operation can dramatically reduce the number
of instruction cycles needed, since any command can be
verified during succeeding commands with no additional
overhead. SeeFigure4. Table1showsthestoragelocation
(‘readback pointer’) of the data which will be output from
SRO during the next instruction.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output.The readback data begins after the
command (C3-Cꢀ) and address (A3-Aꢀ) words have been
shifted into SDI. SRO outputs a logic low (when CS/LD
is low) until the readback data begins. For a 24-bit input
sequence, the 16 readback bits are shifted out on the
falling edges of clocks 8-23, suitable for shifting into a
microprocessor on the rising edges of clocks 9-24. For a
32-bit sequence, the bits are shifted out on clocks 16-31;
see Figure 3b.
ForReadcommands,thedataisshiftedoutduringtheRead
instruction itself (on the 16 falling SCK edges immediately
after the last address bit is shifted in on SDI). When check-
ing the span of a DAC using SRO, the span bits are the last
four bits shifted out, corresponding to their sequence and
positions when writing a span. See Figure 3.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
Span Readback in Manual Span Configuration
If a Span DAC register is chosen for readback, SRO re-
sponds by outputting the actual output span; this is true
whethertheLTC2752isconfiguredforSoftSpan(M-SPAN
tied to GND) or manual span (M-SPAN tied to V ) use.
DD
In SoftSpan configuration, SRO outputs the span code
from the Span DAC register (programmed through the
SPI port). In manual span configuration, the active span
is controlled by pins S2, S1 and Sꢀ, so SRO outputs the
logic values of these pins. The span code bits S2, S1 and
Sꢀ always appear in the same order and positions in the
SRO output sequence; see Figure 3.
The codes for the command word (C3-Cꢀ) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-Aꢀ).
Readback
In addition to the Input and DAC registers, each DAC has
one Readback register associated with it. When a Read
command is issued to a DAC, the contents of one of its
four buffers (Input and DAC registers for each of Span
2752f
ꢀꢃ
LTC2752
operaTion
2752f
ꢀꢄ
LTC2752
operaTion
2752f
ꢀꢅ
LTC2752
operaTion
WRITE CODE
DAC A
WRITE CODE
DAC B
WRITE SPAN
DAC C
WRITE SPAN
DAC B
UPDATE
ALL DACs
...
SDI
READ
CODE INPUT
REGISTER DAC A
READ
CODE INPUT
REGISTER DAC B
READ
SPAN INPUT
REGISTER DAC A
READ
SPAN INPUT
REGISTER DAC B
READ
...
SRO
CODE DAC
REGISTER DAC A
2754 F04
Figure 4. Rolling Readback
Table 1. Command Codes
CODE
READBACK POINTER–
CURRENT INPUT WORD W
READBACK POINTER–
NEXT INPUT WORD W
C3
C2
C1
C0
COMMAND
0
+1
ꢀ
ꢀ
1
ꢀ
Write Span DAC n
Write Code DAC n
Update DAC n
Set by Previous Command
Set by Previous Command
Set by Previous Command
Set by Previous Command
Set by Previous Command
Input Span Register DAC n
Input Code Register DAC n
DAC Span Register DAC n
DAC Code Register DAC n
DAC Span Register DAC n
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
ꢀ
ꢀ
1
ꢀ
1
Update All DACs
ꢀ
1
1
ꢀ
Write Span DAC n
Update DAC n
ꢀ
1
1
1
ꢀ
ꢀ
1
ꢀ
ꢀ
1
ꢀ
1
Write Code DAC n
Update DAC n
Set by Previous Command
Set by Previous Command
Set by Previous Command
DAC Code Register DAC n
DAC Span Register DAC n
DAC Code Register DAC n
Write Span DAC n
Update All DACs
Write Code DAC n
Update All DACs
1
1
1
1
1
ꢀ
ꢀ
1
1
1
1
1
ꢀ
ꢀ
1
ꢀ
1
ꢀ
1
1
Read Input Span Register DAC n
Read Input Code Register DAC n
Read DAC Span Register DAC n
Read DAC Code Register DAC n
No Operation
Input Span Register DAC n
Input Code Register DAC n
DAC Span Register DAC n
DAC Code Register DAC n
Set by Previous Command
DAC Code Register DAC n
DAC Span Register DAC A
DAC Span Register DAC A
–
–
System Clear
–
–
Initial Power-Up or Power Interupt
Codes not shown are reserved–do not use
Table 2. Address Codes
Table 3. Span Codes
A3
ꢀ
A2
ꢀ
A1
ꢀ
A0
×
n
DAC A
S3 S2 S1 S0 SPAN
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
ꢀ
1
ꢀ
1
ꢀ
1
Unipolar ꢀV to 5V
Unipolar ꢀV to 1ꢀV
Bipolar –5V to 5V
ꢀ
ꢀ
1
DAC B
×
1
1
1
All DACs (Note 1)
×
Bipolar –1ꢀV to 1ꢀV
Bipolar –2.5V to 2.5V
Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use.
Note 1. If readback is taken using the All DACs address, the LTC2752
defaults to DAC A.
× = Don’t Care.
Codes not shown are reserved–do not use
2752f
ꢀꢆ
LTC2752
operaTion
Examples
a) CS/LD↓ (Note that after power-on, the code in
Input register is zero)
1. Using a 24-bit instruction, load DAC A with the unipolar
range of ꢀV to 1ꢀV, output at zero volts and DAC B with
the bipolar range of 1ꢀV, outputs at zero volts. Note all
DAC outputs should change at the same time.
Clock SDI =
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀ11 ꢀꢀ1ꢀ 1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
b) CS/LD↑
Code Input register- Code of DAC B set to
midscale setting.
a) CS/LD↓
Clock SDI = ꢀꢀ1ꢀ 1111 ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀ11
c) CS/LD↓
b) CS/LD↑
Clock SDI =
Span Input register- Range of all DACs set to
bipolar 1ꢀV.
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀ1ꢀ ꢀꢀ1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀ1ꢀꢀ
Data out on SRO = 1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ Verifies
that Code Input register- DAC B is at midscale
setting.
c) CS/LD↓
Clock SDI = ꢀꢀ1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀ1
d) CS/LD↑
d) CS/LD↑
Span Input register- Range of DAC A set to
unipolar ꢀV to 1ꢀV.
Span Input register- Range of DAC B set to
Bipolar 2.5V range.
e) CS/LD↓
e) CS/LD↓
Clock SDI = ꢀꢀ11 1111 1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
Clock SDI =
ꢀꢀꢀꢀ ꢀꢀꢀꢀ 1ꢀ1ꢀ ꢀꢀ1ꢀ XXXX XXXX XXXX XXXX
Data Out on SRO = ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀ1ꢀꢀ
Verifies that Span Input register- range of DAC B
set to Bipolar 2.5V Range.
CS/LD↑
f) CS/LD↑
Code Input register- Code of all DACs set to
midscale.
g) CS/LD↓
Clock SDI = ꢀꢀ11 ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
f) CS/LD↓
h) CS/LD↑
Clock SDI =
Code Input register- Code of DAC A set to
zero code.
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀ1ꢀꢀ ꢀꢀ1ꢀ XXXX XXXX XXXX XXXX
g) CS/LD↑
i) CS/LD↓
Update DAC B for both Code and Range
Clock SDI = ꢀ1ꢀꢀ 1111 XXXX XXXX XXXX XXXX
h) Alternatively steps f and g could be replaced with
j) CS/LD↑
LDAC
.
Update all DACs for both Code and Range.
System Offset and Reference Adjustments
k) Alternatively steps i and j could be replaced with
LDAC
.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2752, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
2. Using a 32-bit load sequence, load DAC B with bipolar
2.5V and its output at zero volts. Use readback to check
Input register contents before updating the DAC output
(i.e., before copying Input register contents into DAC
register).
2752f
ꢀꢇ
LTC2752
operaTion
The offset adjust pin V
can be used to null unipolar
The V
pins have an input impedance of 1.28MΩ.
OSADJX
OSADJX
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
These pins should be driven with a Thevenin-equivalent
impedance of 1ꢀk or less to preserve the settling perfor-
mance of the LTC2752. They should be shorted to GND
if not used.
–VVOSADJX
∆VOS LSB =
•512
[
]
VRINX
TheGE
pinshaveaninputimpedanceof2.56MΩ, and
ADJX
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
A 5V control voltage applied to V
produces ∆V
=
OSADJX
OS
–512 LSB in any output range, assuming a 5V reference
voltage at R
.
INX
Power-On Reset and Clear
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
When power is first applied to the LTC2752, all DACs
power-up in unipolar 5V mode (S3 S2 S1 Sꢀ = ꢀꢀꢀꢀ). All
internal DAC registers are reset to ꢀ and the DAC outputs
initialize to zero volts.
1
∆V = –( / )V
[ꢀV to 5V, 2.5V spansꢁ
OS
128 OSADJX
1
∆V = –( / )V
[ꢀV to 1ꢀV, 5V, –2.5V to
7.5V spansꢁ
OS
64 OSADJX
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
1
∆V = –( / )V
[ 1ꢀV spanꢁ
OS
32 OSADJX
The gain error adjust pins GE
can be used to null
ADJX
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to ꢀ and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
VGEADJX
VRINX
∆GE=
•512
The gain-error delta is non-inverting for positive reference
voltages.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
Note that this pin compensates the gain by altering the
invertedreferencevoltageV
.Involtageterms,theV
REFX
REFX
delta is inverted and attenuated by a factor of 128.
1
∆V
= –( / )GE
REFX
128
ADJX
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
The nominal input range of these pins is 5V; other volt-
ages of up to 15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
at power-up, system clear, or if the supply V dips below
DD
approximately2V;andstaysasserteduntilanyvalidUpdate
command is executed.
2752f
ꢀꢈ
LTC2752
applicaTions inForMaTion
Op Amp Selection
of op amps to meet the system’s specified error budget.
Select the amplifier from Table 6 and insert the specified
op amp parameters in Table 5. Add up all the errors for
each category to determine the effect the op amp has on
the accuracy of the part. Arithmetic summation gives an
(unlikely) worst-case effect. A root-sum-square (RMS)
summation produces a more realistic estimate.
Because of the extremely high accuracy of the 16-bit
LTC2752, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 4 and 5 contain equations for evaluating the ef-
fects of op amp parameters on the LTC2752’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
Table 4. Coefficients for the Equations of Table 5
OUTPUT RANGE
A1
1.1
2.2
2
A2
2
A3
1
A4
A5
1
5V
1ꢀV
3
ꢀ.5
1
1.5
1.5
2.5
1
5V
2
1
1
1ꢀV
4
4
ꢀ.83
1.4
ꢀ.7
2.5V
1
1
1
Table 6 contains a partial list of Linear Technology preci-
sion op amps recommended for use with the LTC2752.
The easy-to-use design equations simplify the selection
–2.5V to 7.5V
1.9
3
ꢀ.5
1.5
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inꢀerting Amp.
UNIPOLAR
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
BIPOLAR GAIN
ERROR (LSB)
OP AMP
INL (LSB)
5V
DNL (LSB)
5V
OFFSET (LSB)
5V
REF
5V
REF
5V
REF
5V
REF
V
(mV)
(nA)
V
• 3 •
V
• 0.78 •
A3 • V
• 13.1 •
A3 • V
• 19.6 •
V
• 13.1 •
V
I
• 13.1 •
ꢀV
ꢀV
ꢀV
ꢀV
ꢀV
ꢀV
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
OS1
OS1
OS1
OS1
OS1
OS1
OS1
REF
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
ꢀV
I
I
• 0.0003 •
I
• 0.00008 •
I
• 0.13 •
I
• 0.13 •
0
I
• 0.0018 •
• 0.0018 •
ꢀV
ꢀV
B1
B1
B1
B1
B1
B1
ꢁ
B1
ꢁ
ꢀV
ꢀV
ꢀV
ꢁ
ꢁ
ꢁ
ꢁ
REF
16.5
VOL1
1.5
VOL1
131
VOL1
131
VOL1
A
A
(V/mV)
(mV)
A1 •
A2 •
0
0
0
0
A5 •
A5 •
VOL1
ꢁ
ꢁ
ꢀA
0
ꢀA
0
ꢁ
ꢁ
ꢀA
ꢀA
5V
REF
5V
REF
5V
REF
V
A4 • V
• 13.1 •
V
• 26.2 •
V
• 26.2 •
• 0.26 •
OS2
OS2
OS2
OS2
ꢀV
ꢁ
ꢀ
ꢁꢁ
ꢁ
ꢀV
ꢀV
5V
5V
REF
5V
I
B2
(nA)
0
0
0
0
A4 • I • 0.13 •
I
B2
• 0.26 •
I
B2
B2
ꢀ
ꢁꢁ
ꢀV
REF
ꢀV
ꢀV
ꢁ
ꢁ
REF
66
131
A
131
A
(V/mV)
A4 •
VOL2
A
VOL2
VOL2
VOL2
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2752 with Releꢀant Specifications
AMPLIFIER SPECIFICATIONS
VOLTAGE CURRENT
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
t
POWER
SETTLING
V
I
A
VOL
NOISE
NOISE
with LTC2752 DISSIPATION
OS
B
AMPLIFIER
LT1ꢀꢀ1
µV
nA
V/mV
nV/√Hz
pA/√Hz
µs
12ꢀ
12ꢀ
115
19
mW
46
25
2
8ꢀꢀ
1ꢀ
14
14
2.7
5
ꢀ.12
ꢀ.ꢀꢀ8
ꢀ.ꢀꢀ8
ꢀ.3
ꢀ.25
ꢀ.2
ꢀ.16
4.5
22
ꢀ.8
ꢀ.7
ꢀ.75
12.5
9ꢀ
LT1ꢀ97
5ꢀ
ꢀ.35
ꢀ.25
2ꢀ
1ꢀꢀꢀ
15ꢀꢀ
4ꢀꢀꢀ
5ꢀꢀꢀ
2ꢀꢀꢀ
11
LT1112 (Dual)
LT1124 (Dual)
LT1468
6ꢀ
1ꢀ.5/Op Amp
69/Op Amp
117
7ꢀ
75
1ꢀ
ꢀ.6
2
LT1469 (Dual)
125
1ꢀ
5
ꢀ.6
22
9ꢀ
2
123/Op Amp
2752f
ꢁ0
LTC2752
applicaTions inForMaTion
Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on INL and DNL. For
example,fortheLTC2752witha5Vreferencein5Vunipolar
mode, a 25ꢀµV op amp offset will cause a 3.3LSB zero-
scale error and a 3.3LSB gain error; but only ꢀ.75LSB of
INL degradation and ꢀ.2LSB of DNL degradation.
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s apparent INL and DNL performance. If a refer-
ence is chosen with a loose output voltage temperature
coefficient, then the DAC output voltage along its transfer
characteristicwillbeverydependentonambientconditions.
Minimizing the error due to reference temperature coef-
ficient can be achieved by choosing a precision reference
with a low output voltage temperature coefficient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, con-
sult an op amp’s data sheet to find the worst-case V
OS
and I over temperature. Then, plug these numbers into
B
As precision DAC applications move to 16-bit and higher
performance, referenceoutputvoltage noise may contrib-
ute a dominant share of the system’s noise floor. This in
turncandegradesystemdynamicrangeandsignal-to-noise
ratio. Care should be exercised in selecting a voltage refer-
encewithaslowanoutputnoisevoltageaspracticalforthe
system resolution desired. Precision voltage references,
like the LT1236 and LTC6655, produce low output noise in
the ꢀ.1Hz to 1ꢀHz region, well below the 16-bit LSB level
the V and I equations from Table 5 and calculate the
temperature-induced effects.
OS
B
For applications where fast settling time is important, Ap-
plicationNote74,ComponentandMeasurementAdvances
Ensure16-BitDACSettlingTime,offersathoroughdiscus-
sion of 16-bit DAC settling time and op amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2752 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2752
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2752 with Releꢀant Specifications
INITIAL
TOLERANCE
TEMPERATURE 0.1Hz to 10Hz
REFERENCE
DRIFT
NOISE
LT1ꢀ19A-5,
LT1ꢀ19A-1ꢀ
ꢀ.ꢀ50 Max
ꢀ.ꢀ50 Max
ꢀ.ꢀ750 Max
5ppm/°C Max
12µV
P-P
LT1236A-5,
LT1236A-1ꢀ
5ppm/°C Max
1ꢀppm/°C Max
3µV
P-P
There are three primary error sources to consider
when selecting a precision voltage reference for 16-bit
applications:outputvoltageinitialtolerance,outputvoltage
temperature coefficient and output voltage noise.
LT146ꢀA-5,
LT146ꢀA-1ꢀ
2ꢀµV
12µV
P-P
LT179ꢀA-2.5
ꢀ.ꢀ50 Max
ꢀ.ꢀ50 Max
1ꢀppm/°C Max
5ppm/°C Max
P-P
LTC6652A-2.ꢀ48
LTC6652A-2.5
LTC6652A-3
2.1ppm
2.1ppm
2.1ppm
2.2ppm
2.3ppm
2.8ppm
P-P
P-P
P-P
P-P
P-P
P-P
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
( ꢀ.ꢀ50),minimizesthegainerrorcausedbythereference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
LTC6652A-3.3
LTC6652A-4.ꢀ96
LTC6652A-5
LT6655A-25,
LT6655A-5
ꢀ.ꢀ250 Max
2ppm/°C Max
ꢀ.25ppm
P-P
2752f
ꢁꢀ
LTC2752
applicaTions inForMaTion
in 5V or 1ꢀV full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
The best strategy here is to tie the pins to the star ground
planebymultipleviaslocateddirectlyunderneaththepart.
Alternatively, the pins may be routed to the star ground
point if necessary; join the force and sense pins together
at the part and route one trace for each channel of no more
than 12ꢀ squares of 1oz. copper.
Grounding
As with any high resolution converter, clean grounding
is important. A low impedance analog ground plane is
necessary, as are star grounding techniques. Keep the
board layer used for star ground continuous to minimize
ground resistances; that is, use the star-ground concept
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Typical Applications). Note, however,
that the voltage offset of the ground buffer amp directly
contributes to the effects on accuracy specified in Table
without using separate star traces. The I
pins are
OUT2
of particular concern; INL will be degraded by the code
dependent currents carried by the I and I
5 under V . The combined effects of the offsets can be
OS1
OUT2XF
OUT2XS
calculated by substituting the total offset from I
to
OUT1X
pins if voltage drops to ground are allowed to develop.
I
for V
in the equations.
OUT2XS
OS1
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
8
8
I
OUT2AS
I
OUT2AS
200Ω
200Ω
–
2
–
2
9
6
9
6
I
I
1000pF
LT1012
OUT2AF
LT1468
OUT2AF
1
2
3
+
+ 3
ZETEX
1
BAT54S
ZETEX*
BAT54S
3
2
3
*SCHOTTKY BARRIER DIODE
LTC2752
V
REF
5V
47, 48 R
5, 6 R
OFSA
INA
R
45, 46
FBA
15pF
+ 3
–
1
2
1/2 LT1469
4 GE
3 R
ADJA
I
I
44
OUT1A
1
–
2
V
DAC A
1/2 LT1469
3 +
OUTA
COMA
8, 9
43
150pF
OUT2A
V
1, 2 REFA
OSADJA
–
+
DAC B
2752 F05
Figure 5. Optional Circuits for Driꢀing IOUT2 from GND with a Force/Sense Amplifier
2752f
ꢁꢁ
LTC2752
package DescripTion
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # ꢀ5-ꢀ8-176ꢀ Rev Ø)
7.15 – 7.25
5.50 REF
9.00 BSC
7.00 BSC
48
48
1
2
SEE NOTE: 4
1
2
0.50 BSC
9.00 BSC
7.00 BSC
5.50 REF
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
11° – 13°
1.35 – 1.45 MAX
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
1.00 REF
0.50
BSC
0.09 – 0.20
0.17 – 0.27
0.05 – 0.15
LX48 LQFP 0907 REVØ
0.45 – 0.75
SECTION A – A
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
2752f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢁꢂ
LTC2752
Typical applicaTion
Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply
15V
7
LT1012A
6
+
–
3
2
4
5V REFERENCE
2
6
–15V
C1
IN
OUT
15V
100pF
C6
10µF
C7
10µF
C2
0.1µF
15V
LT1236-5
4
10k
26
10k
19
7
LT1991
16
47, 48
5, 6
3
1, 2
450k
1
7
V
LDAC CLR
R
R
INA
R
COMA
REFA
DD
OFSA
450k
–
+
10
1
45, 46
V
REF
4
43
33
42
CC
6
R
FBA
GE
V
ADJA
C3
27pF
2
3
8
9
4
V
OUTA
OUTB
OUTC
CS2
CS/LD
SDI
450k
15V
7
OSADJA
6
5
V
V
V
–
+
2
3
44
SPI BUS SDI
SCK
4
I
I
GE
OUT1A
6
ADJB
V
V
DACA
DACB
SCK
OUT
8, 9
–15V
OUTD
V
OUT2A
OSADJB
LT1468
4
10
1
GND
10, 11
6
6
6
–15V
LT1991
LTC2634-MSELMX12
39, 40
R
FBB
LTC2752
C4
27pF
10
1
15V
22
23
24
25
LT1991
LT1991
–
+
2
3
41
M-SPAN
S0
7
4
I
I
OUT1B
6
OUT
28, 29
OUT2B
LT1468
10
1
S1
–15V
7, 10, 15, 17, 18, 27, 30
S2
GND
R
R
R
COMB
OFSB
INB
CS/LD SDI SCK SRO
11 12 13 14
REFB
2752 TA02
37, 38 31, 32 34
35, 36
C5
100pF
15V
7
CS1
SDI SCK SRO
SPI BUS
+
–
3
2
6
LT1012A
4
–15V
relaTeD parTs
PART NUMBER
LTC2757
LTC2754
LTC2751
LTC2753
LTC2755
LTC159ꢀ
LTC1592
DESCRIPTION
Single Parallel 18-Bit I
COMMENTS
SoftSpan DAC
1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package
1LSB INL/DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package
1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm QFN-48 Package
1LSB INL/DNL, Software-Selectable Ranges, 9mm × 9mm QFN-64 Package
ꢀ.5LSB INL/DNL 2-Quadrant, 16-Pin Narrow SO and PDIP Packages
1LSB INL/DNL, Software-Selectable Ranges, 16-Lead SSOP Package
1LSB INL/DNL, Integrated 4-Quadrant Resistors, 28-Lead SSOP Package
1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers
OUT
Quad Serial 16-Bit/12-Bit I
SoftSpan DACs
OUT
Single Parallel 16-Bit/14-Bit/12-Bit I
Dual Parallel 16-Bit/14-Bit/12-Bit I
SoftSpan DAC
OUT
SoftSpan DACs
SoftSpan DACs
OUT
Quad Parallel 16-Bit/14-Bit/12-Bit I
OUT
Dual Serial 12-Bit Multiplying I
DAC
OUT
Single Serial 16-Bit/14-Bit/12-Bit I
SoftSpan DAC
OUT
LTC1591/LTC1597 Single Parallel 16-Bit/14-Bit I
DACs
OUT
LTC27ꢀ4
References
LTC6655
LT1ꢀ27
Quad Serial 16-Bit/14-Bit/12-Bit V
SoftSpan DACs
OUT
Precision Reference
Precision Reference
Precision Reference
ꢀ.ꢀ250 Maximum Tolerance, ꢀ.25ppm ꢀ.1Hz to 1ꢀHz Noise
P-P
2ppm/°C Maximum Drift
LT1236A-5
Amplifiers
LT1ꢀ12
ꢀ.ꢀ50 Maximum Tolerance, 1ppm ꢀ.1Hz to 1ꢀHz Noise
P-P
Precision Operational Amplifier
Precision Operational Amplifier
25µV Max Offset, 1ꢀꢀpA Max Bias Current, ꢀ.5µV Noise, 38ꢀµA Supply
Current
P-P
LT1ꢀꢀ1
25µV Max Offset, ꢀ.3µV Noise, High Output Drive
P-P
LT1468/LT1469
Single/Dual 16-Bit Accurate Op-Amp
9ꢀMHz GBW, 22V/μs Slew Rate, ꢀ.3µV Noise
P-P
2752f
LT 0510 • PRINTED IN USA
Linear Technology Corporation
163ꢀ McCarthy Blvd., Milpitas, CA 95ꢀ35-7417
ꢁꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(4ꢀ8) 432-19ꢀꢀ FAX: (4ꢀ8) 434-ꢀ5ꢀ7 www.linear.com
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