LTC2753CUK-14#TRPBF_技术文档

LTC2753

Dual Current Output

12-/14-/16-Bit SoftSpan

DACs with Parallel I/O

FEATURES

DESCRIPTION

The LTC^®2753 is a family of dual 12-, 14-, and 16-bit

multiplying parallel-input, current-output DACs. These

DACs operate from a single 2.7V to 5.5V supply and are all

guaranteedmonotonicovertemperature.TheLTC2753A-16

provides 16-bit performance ( 1LꢀS ꢁIL and DILꢂ over

temperature without any adjustments. These ꢀoftꢀpan™

DACs offer six output ranges—two unipolar and four

bipolar—that can be programmed through the parallel

interface, or pinstrapped for operation in a single range.

■

Six Programmable Output Ranges

Unipolar: 0V to 5V, 0V to 10V

Bipolar: ±5V, ±10V, ±±25V, –±25V to 725V

■

Maximum 16-Bit INL Error: ±1 LSB oꢀer Temperature

■

Low 1μA (Maximum) Supply Current

■

Guaranteed Monotonic oꢀer Temperature

■

Low Glitch Impulse 1nV•s

■

2.7V to 5.5V ꢀingle ꢀupply Operation

■

2μs ꢀettling Time to 1 LꢀS

■

Parallel ꢁnterface with Readback of All Registers

TheLTC2753DACsuseabidirectionalinput/outputparallel

interface that allows readback of any on-chip register. A

power-on reset circuit resets the DAC outputs to 0V when

power is initially applied. A logic low on the CLR pin asyn-

chronously clears the DACs to 0V in any output range.

■

Asynchronous CLR Pin Clears DAC Outputs to 0V in

Any Output Range

Power-On Reset to 0V

48-Pin 7mm × 7mm QFI Package

■

The parts are speciﬁed over commercial and industrial

temperature ranges.

APPLICATIONS

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

ꢀoftꢀpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

■

High Resolution Offset and Gain Adjustment

■

Process Control and ꢁndustrial Automation

■

Automatic Test Equipment

■

Data Acquisition ꢀystems

TYPICAL APPLICATION

Dual 16-Bit V_OUTDAC with Software-Selectable Ranges

LTC±753-16 Integral Nonlinearity (INL)

LTC2753-16

R

47

2

V

REF

5V

OFꢀA

1.0

R

V

= 5V

REF

±10V RANGE

ꢁI

DD

46

R

ꢁ

FSA

15pF

0.8

0.6

= 5V

+

–

45

4

–

OUT1A

R1

R2

1/2 LT1469

0.4

R

1

COM

V

1/2 LT1469

+

DAC A

OUTA

ꢁ

0.2

OUT2A

150pF

0.0

REFA 48

REFS 39

44

43

R

VOꢀA

VOꢀS

–0.2

–0.4

–0.6

–0.8

–1.0

32

ꢁ

+

OUT2S

25°C

90°C

–45°C

V

1/2 LT1469

–

DAC S

OUTS

42

41

OUT1S

15pF

R

40

OFꢀS

R

0

16384

32768

CODE

49152

65535

FSS

3

2753 TA01

ꢀPAI ꢁ/O

DATA ꢁ/O

ꢁ/O PORT

16

2753 TA01b

2753f

1

LTC2753

ABSOLUTE MAXIMUM RATINGS

(Notes 1, ±)

Operating Temperature Range

ꢁ

, ꢁ

, R

to GID ................................. 0.3V

OUT1X OUT2X COM

LTC2753C..................................................... 0°C to 70°C

LTC2753ꢁ.................................................. –40°C to 85°C

Maximum Junction Temperature........................... 125°C

ꢀtorage Temperature Range................... –65°C to 150°C

R

, R , R

, R , REF to GID ................... 15V

VOꢀX FSX OFꢀX ꢁI X

V

to GID.................................................. –0.3V to 7V

DD

Digital ꢁnputs and Digital ꢁ/O

to GID ..........................–0.3V to V +0.3V (max 7Vꢂ

DD

PIN CONFIGURATION

48 47 46 45 44 43 42 41 40 39 38 37

R

UPD

READ

D/ꢀ

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

27

26

25

R

UPD

READ

D/ꢀ

R

UPD

READ

D/ꢀ

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

27

26

25

COM

R

ꢁI

R

ꢁI

ꢀ2

ꢁ

ꢀ0

ꢁ

ꢀ0

ꢁ

ꢀ0

OUT2A

GID

OUT2A

GID

OUT2A

GID

ꢁ

OUT2S

D11

D10

D9

D8

D7

GID

IC

D13

D12

D11

D10

D9

GID

IC

D0

D15

D14

D13

D12

D11

D10

D9

GID

IC

D0

D1

D2

49

10

11

12

10

11

12

10

11

12

D6

D5

D8

D7

D1

D3

13 14 15 16 17 18 19 20 21 22 23 24

LTC2753-12 UK PACKAGE

48-LEAD (7mm × 7mmꢂ PLAꢀTꢁC QFI

LTC2753-14 UK PACKAGE

48-LEAD (7mm × 7mmꢂ PLAꢀTꢁC QFI

LTC2753-16 UK PACKAGE

48-LEAD (7mm × 7mmꢂ PLAꢀTꢁC QFI

T

= 125°C, θ = 29°C/W

JA

T

= 125°C, θ = 29°C/W

T

= 125°C, θ = 29°C/W

JMAX JA

JMAX

JA

EXPOꢀED PAD (PꢁI 49ꢂ ꢁꢀ GID, MUꢀT SE ꢀOLDERED TO PCS

ORDER INFORMATION

LEAD FREE FINISH

LTC2753CUK-12#PSF

LTC2753ꢁUK-12#PSF

LTC2753CUK-14#PSF

LTC2753ꢁUK-14#PSF

TAPE AND REEL

PART MARKING*

LTC2753UK-12

LTC2753UK-14

LTC2753UK-16

PACKAGE DESCRIPTION

48-Lead (7mm × 7mmꢂ Plastic QFI

TEMPERATURE RANGE

LTC2753CUK-12#TRPSF

LTC2753ꢁUK-12#TRPSF

LTC2753CUK-14#TRPSF

LTC2753ꢁUK-14#TRPSF

0°C to 70°C

48-Lead (7mm × 7mmꢂ Plastic QFI

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

LTC2753SCUK-16#PSF LTC2753SCUK-16#TRPSF

LTC2753SꢁUK-16#PSF LTC2753SꢁUK-16#TRPSF

LTC2753ACUK-16#PSF LTC2753ACUK-16#TRPSF

LTC2753AꢁUK-16#PSF LTC2753AꢁUK-16#TRPSF

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2753f

2

LTC2753

ELECTRICAL CHARACTERISTICS ^V_DD= 5V, V_REF= 5V unless otherwise speciﬁed2 The ● denotes the

speciﬁcations which apply oꢀer the full operating temperature range, otherwise speciﬁcations are at T_A= ±5°C2

LTC±753-1± LTC±753-14 LTC±753B-16

MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

LTC±753A-16

SYMBOL PARAMETER

Static Performance

Resolution

CONDITIONS

MIN TYP

●

12

14

16

Sits

LꢀS

Monotonicity

DIL

ꢁIL

GE

Differential

1

2

1

5

1

2

0.2

0.4

4

1

Ionlinearity

●

ꢁntegral

Ionlinearity

LꢀS

Gain Error

All Output

Ranges

0.5

0.6

0.2

0.5

1.5

0.6

0.5

20

14

GE

Gain Error Temp-

erature Coefﬁcient

ΔGain/ΔTemp

0.6

0.5

0.6

2

ppm/°C

LꢀS

TC

●

SZE

SZꢀ

Sipolar Zero Error All Sipolar

Ranges

1

3

12

8

Sipolar Zero Temp-

erature Coefﬁcient

0.5

ppm/°C

LꢀS/V

nA

TC

●

PꢀR

Power ꢀupply

Rejection

V

= 5V, 10ꢃ

= 3V, 10ꢃ

0.025

0.06

0.1

0.25

0.4

1

0.03

0.1

0.2

0.5

DD

ꢁ

Leakage

T = 25°C

0.05

2

5

0.05

2

5

0.05

2

5

0.05

2

5

LKG

OUT1

A

●

Current

T

to T

MꢁI MAX

C

ꢁOUT1

Output

Capacitance

Full-ꢀcale

Zero ꢀcale

75

45

75

45

75

45

75

45

pF

V_DD= 5V, V_REF= 5V unless otherwise speciﬁed2 The ● denotes speciﬁcations that apply oꢀer the full operating temperature range,

otherwise speciﬁcations are at T_A= ±5°C2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resistances (Note 3)

R1, R2

●

Reference ꢁnverting Resistors

DAC ꢁnput Resistance

Feedback Resistor

(Iote 4ꢂ

16

8

20

10

kΩ

R

REF

FS

(Iote 3ꢂ

8

10

Sipolar Offset Resistor

Offset Adjust Resistor

16

800

20

OFꢀ

R

VOꢀ

1000

Dynamic Performance

Output ꢀettling Time

0V to 10V Range, 10V ꢀtep. To 0.0015ꢃ Fꢀ

(Iote 5ꢂ

2

ꢄs

Glitch ꢁmpulse

(Iote 6ꢂ

(Iote 7ꢂ

1

nV•s

mV

Digital-to-Analog Glitch ꢁmpulse

Multiplying Feedthrough Error

0V to 10V Range, V = 10V, 10kHz

ꢀine Wave

0.5

REF

THD

Total Harmonic Distortion

(Iote 8ꢂ Multiplying

–110

13

dS

Output Ioise Voltage Density

(Iote 9ꢂ at ꢁ

nV/√Hz

OUT1

2753f

3

LTC2753

ELECTRICAL CHARACTERISTICS ^V_DD= 5V, V_REF= 5V unless otherwise speciﬁed2 The ● denotes the

speciﬁcations which apply oꢀer the full operating temperature range, otherwise speciﬁcations are at T_A= ±5°C2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

●

V

ꢀupply Voltage

2.7

5.5

1

V

DD

ꢁ

DD

ꢀupply Current, V

Digital ꢁnputs = 0V or V

DD

0.5

ꢄA

DD

Digital Inputs

●

V

Digital ꢁnput High Voltage

Digital ꢁnput Low Voltage

3.3V ≤ V ≤ 5.5V

2.4

2

V

ꢁH

DD

2.7V ≤ V < 3.3V

DD

●

V

4.5V < V ≤ 5.5V

0.8

0.6

V

ꢁL

DD

2.7V ≤ V ≤ 4.5V

DD

●

ꢁ

Digital ꢁnput Current

V

= GID to V

DD

1

6

μA

pF

ꢁI

C

Digital ꢁnput Capacitance

V

= 0V (Iote 10ꢂ

ꢁI

Digital Outputs

●

V

ꢁ

= 200μA

V – 0.4

DD

V

OH

OL

OH

0.4

OL

TIMING CHARACTERISTICS

The ● denotes speciﬁcations that apply oꢀer the full operating temperature range,

otherwise speciﬁcations are at T_A= ±5°C2

SYMBOL PARAMETER

= 425V to 525V

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

Write and Update Timing

●

t

ꢁ/O Valid to WR Rising Edge ꢀet-Up

ꢁ/O Valid to WR Rising Edge Hold

7

ns

1

2

WR Pulse Width Low

15

0

3

UPD Pulse Width High

4

UPD Falling Edge to WR Falling Edge

WR Rising Edge to UPD Rising Edge

D/ꢀ Valid to WR Falling Edge ꢀet-Up Time

WR Rising Edge to D/ꢀ Valid Hold Time

A1-A0 Valid to WR Falling Edge ꢀetup Time

WR Rising Edge to A1-A0 Valid Hold Time

A1-A0 Valid to UPD Rising Edge ꢀetup Time

UPD Falling Edge to A1-A0 Valid Hold Time

Io Data ꢀhoot-Through

(Iote 10ꢂ

5

0

6

7

8

5

9

0

10

11

12

9

7

Readback Timing

●

t

13

t

14

t

15

t

26

t

27

WR Rising Edge to READ Rising Edge

READ Falling Edge to WR Falling Edge

READ Rising Edge to ꢁ/O Propagation Delay

A1-A0 Valid to READ Rising Edge ꢀetup Time

READ Falling to A1-A0 Valid Hold Time

7

ns

(Iote 10ꢂ

20

C = 10pF

L

40

20

0

(Iote 10ꢂ

2753f

4

LTC2753

TIMING CHARACTERISTICS ^The● denotes speciﬁcations that apply oꢀer the full operating temperature range,

otherwise speciﬁcations are at T_A= ±5°C2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ns

●

t

UPD Valid to ꢁ/O Propagation Delay

D/ꢀ Valid to READ Rising Edge

READ Rising Edge to UPD Rising Edge

UPD Falling Edge to READ Falling Edge

READ Falling Edge to UPD Rising Edge

ꢁ/O Sus Hi-Z to READ Rising Edge

READ Falling Edge to ꢁ/O Sus Active

C = 10pF

L

26

17

18

19

20

22

23

24

(Iote 10ꢂ

Io Update

(Iote 10ꢂ

7

0

ns

0

ns

7

ns

0

ns

20

ns

CLR Timing

●

t

25

CLR Pulse Width Low

15

ns

V

DD

= ±27V to 323V

Write and Update Timing

●

t

ꢁ/O Valid to WR Rising Edge ꢀet-Up

ꢁ/O Valid to WR Rising Edge Hold

15

30

0

ns

1

2

WR Pulse Width Low

3

UPD Pulse Width High

4

UPD Falling Edge to WR Falling Edge

WR Rising Edge to UPD Rising Edge

D/ꢀ Valid to WR Falling Edge ꢀet-Up Time

WR Rising Edge to D/ꢀ Valid Hold Time

A1-A0 Valid to WR Falling Edge ꢀetup Time

WR Rising Edge to A1-A0 Valid Hold Time

A1-A0 Valid to UPD Rising Edge ꢀetup Time

UPD Falling Edge to A1-A0 Valid Hold Time

Io Data ꢀhoot-Through

(Iote 10ꢂ

5

0

6

7

8

7

9

0

10

11

12

15

Readback Timing

●

t

13

t

14

t

15

t

26

t

27

t

17

t

18

t

19

t

20

WR Rising Edge to Read Rising Edge

Read Falling Edge to WR Falling Edge

Read Rising Edge to ꢁ/O Propagation Delay

A1-A0 Valid to READ Rising Edge ꢀetup Time

READ Falling to A1-A0 Valid Hold Time

UPD Valid to ꢁ/O Propagation Delay

D/ꢀ Valid to Read Rising Edge

10

35

ns

(Iote 10ꢂ

C = 10pF

L

53

43

35

0

(Iote 10ꢂ

C = 10pF

L

(Iote 10ꢂ

Io Update

12

0

Read Rising Edge to UPD Rising Edge

UPD Falling Edge to Read Falling Edge

0

2753f

5

LTC2753

TIMING CHARACTERISTICS ^The● denotes speciﬁcations that apply oꢀer the full operating temperature range,

otherwise speciﬁcations are at T_A= ±5°C2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

= ±27V to 323V

DD

●

t

READ Falling Edge to UPD Rising Edge

ꢁ/O Sus Hi-Z to Read Rising Edge

Read Falling Edge to ꢁ/O Sus Active

(Iote 10ꢂ

10

0

ns

22

23

24

35

CLR Timing

●

t

CLR Pulse Width Low

20

ns

25

Note 1: ꢀtresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

basis. ꢀee Application Iote 74, Component and Measurement Advances

Ensure 16-Sit DAC ꢀettling Time.

Note 6: Measured at the major carry transition, 0V to 5V range. Output

ampliﬁer: LT1469; C = 27pF.

FS

Note ±: Continuous operation above the speciﬁed maximum operating

junction temperature may impair device reliability.

Note 3: Secause of the proprietary ꢀoftꢀpan switching architecture, the

measured resistance looking into each of the speciﬁed pins is constant for

Note 72 Full-scale transition; REF = 0V.

Note 82 REF = 6V

at 1kHz. 0V to 5V range. DAC code = Fꢀ. Output

RMꢀ

ampliﬁer = LT1469.

Note 92 Calculation from V = √4kTRS, where k = 1.38E-23 J/°K

n

all output ranges if the ꢁ

and ꢁ

pins are held at ground.

OUT1X

OUT2X

(Soltzmann constantꢂ, R = resistance (Ωꢂ, T = temperature (°Kꢂ, and S =

bandwidth (Hzꢂ.

Note 102 Guaranteed by design. Iot production tested.

Note 4: R1 is measured from R to R

; R2 is measured from REFA to

ꢁI

COM

R

.

COM

Note 5: Using LT1469 with C

= 15pF. A 0.0015ꢃ settling time

FEEDSACK

of 1.7ꢄs can be achieved by optimizing the time constant on an individual

2753f

6

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= ±5°C, unless otherwise noted2}

LTC±753-16

INL ꢀs Temperature

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

1.0

0.8

V

= 5V

REF

V = 5V

DD

V = 5V

REF

V

= 5V

DD

REF

= 5V

±10V RANGE

10V RAIGE

0.6

0.4

+ꢁIL

–ꢁIL

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

32768

CODE

65535

–40

–20

0

20

40

80

0

16384

32768

CODE

49152

65535

0

16384

49152

60

TEMPERATURE (°Cꢂ

2753 G01

2753 G02

2753 G04

Gain Error ꢀs Temperature

DNL ꢀs Temperature

Bipolar Zero ꢀs Temperature

1.0

0.8

16

12

8

6

4

2

0

2

4

6

8

V

= 5V

V

= 5V

V

= 5V

DD

REF

DD

REF

DD

REF

10V RAIGE

0.6

0.4

0.5ppm/°C (TYPꢂ

0.6ppm/°C (TYPꢂ

4

0.2

+DIL

–DIL

0.0

0

–0.2

–0.4

–0.6

–0.8

–1.0

–4

–8

–12

–16

20

TEMPERATURE (°Cꢂ

40

80

–40

–20

0

20

40

60

80

–40

–20

0

60

–40

–20

0

20

40

60

80

TEMPERATURE (°Cꢂ

2753 G07

2753 G05

2753 G06

INL ꢀs V_REF

DNL ꢀs V_REF

1.0

0.8

V

= 5V

V

= 5V

DD

0.8

0.6

5V RAIGE

0.6

0.4

+ꢁIL

–ꢁIL

+ꢁIL

–ꢁIL

0.2

+DIL

–DIL

+DIL

–DIL

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–10 –8 –6

4

2

0

2

4

6

8

10

–10 –8 –6

4

2

0

2

4

6

8

10

V

(Vꢂ

V

(Vꢂ

REF

2753 G08

2751 G09

2753f

7

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= ±5°C, unless otherwise noted2}

LTC±753-16

Multiplying Frequency Response

ꢀs Digital Code

INL ꢀs V_DD

Settling 0V to 10V

1.0

0.8

ALL SꢁTꢀ OI

0

–20

D15

D14

D13

D12

D11

D10

D9

UPD

0.6

5V/DꢁV

0.4

+ꢁIL

–ꢁIL

–40

0.2

D8

D7

D6

D5

D4

D3

GATED

ꢀETTLꢁIG

WAVEFORM

250μV/DꢁV

0.0

–60

–0.2

–0.4

–0.6

–0.8

–1.0

–80

D2

D1

D0

UIꢁPOLAR 5V OUTPUT RAIGE

LT1469 OUTPUT AMPLꢁFꢁER

FEEDSACK

2753 G10

–100

–120

500ns/DꢁV

UꢀꢁIG LT1469 AMP

C

= 15pF

ALL SꢁTꢀ OFF

C

= 12pF

FEEDSACK

100

1k

10k

100k

1M

10M

2.5

3

3.5

4

4.5

5

5.5

0V TO 10V ꢀTEP

FREQUEICY (Hzꢂ

V

(Vꢂ

DD

2751 G09b

2753 G10a

LTC±753-14

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

V

= 5V

V

= 5V

DD

REF

DD

REF

±10V RANGE

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

4096

8192

12288

16383

0

4096

8192

12288

16383

CODE

2753 G12

2753 G11

LTC±753-1±

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.8

1.0

0.8

V

= 5V

V

= 5V

DD

REF

DD

REF

±10V RANGE

10V RAIGE

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1024

2048

3072

4095

2048

4095

0

1024

3072

CODE

2753 G13

2753 G14

2753f

8

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= ±5°C, unless otherwise noted2}

LTC±753-1±, LTC±753-14, LTC±753-16

Supply Current ꢀs

Logic Input Voltage

Midscale Glitch

20

15

10

5

UPD

5V/DꢁV

1nV•ꢀ (TYPꢂ

V

= 5V

DD

V

OUT

2mV/DꢁV

2753 G15

500ns/DꢁV

UꢀꢁIG AI LT1469

= 27pF

V

= 3V

DD

V

= 5V

REF

0V TO 5V RAIGE

DD

0

= 5V

C

FEEDSACK

0

1

2

3

4

5

DꢁGꢁTAL ꢁIPUT VOLTAGE (Vꢂ

2753 G16

Logic Threshold

ꢀs Supply Voltage

Supply Current

ꢀs Update Frequency

2

1.75

1.5

10

1

RꢁꢀꢁIG

0.1

1.25

1

FALLꢁIG

0.01

0.001

V

= 5V

DD

V

= 3V

0.75

0.5

DD

0.0001

2.5

3.5

4

4.5

5

5.5

3

10

100

1k

10k

100k

1M

V

(Vꢂ

DD

UPDATE FREQUEICY (Hzꢂ

2753 G18

2753 G17

2753f

9

LTC2753

PIN FUNCTIONS

R

COM

(Pin 1): Center Tap Point for the Reference ꢁnverting

output range. When conﬁgured for single-span operation,

the output range is set via hardware pin strapping. The

inputandDACregistersofthespanꢁ/Oportaretransparent

and do not respond to write or update commands.

Resistors.The20kreferenceinvertingresistorsR1andR2

are connected internally from R to R and from R

to REFA, respectively (see Slock Diagramꢂ. For normal

ꢁI

COM

operation tie R to the negative input of the external

reference inverting ampliﬁer (see Typical Applicationsꢂ.

COM

Toconﬁgurethepartforsingle-spanuse,tieMꢀPAIdirectly

to V . ꢁf MꢀPAI is instead connected to GID (ꢀoftꢀpan

DD

conﬁgurationꢂ, the output ranges are set and veriﬁed by

usingwrite, updateandreadoperations. ꢀeeManualꢀpan

Conﬁguration in the Operation section. MꢀPAI must be

connectedeitherdirectlytoGID(ꢀoftꢀpanconﬁgurationꢂ

R (Pin ±): ꢁnput Resistor R1 of the Reference ꢁnverting

Resistors.The20kresistorR1isconnectedinternallyfrom

IN

R to R

ꢁI

. For normal operation tie R to the external

COM

ꢁI

reference voltage V . Typically 5V; accepts up to 15V.

REF

or V (single-span conﬁgurationꢂ.

DD

S± (Pin 3): ꢀpan ꢁ/O Sit 2. Pins ꢀ0, ꢀ1 and ꢀ2 are used

to program and to read back the output ranges of the

DACs.

D0-D± (Pins ±±-±4): LTC±753-1± Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D0 is the LꢀS.

I

(Pin 4): DAC A Current Output Complement. Tie

to ground.

OUT±A

D0-D4 (Pins ±±-±6): LTC±753-14 Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D0 is the LꢀS.

ꢁ

OUT2A

GND(Pin5):ꢀhieldGround,providesnecessaryshielding

for ꢁ . Tie to ground.

OUT2A

D0-D6 (Pins ±±-±8): LTC±753-16 Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D0 is the LꢀS.

D3-D11 (Pins 6-14): LTC±753-1± Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D11 is the MꢀS.

NC (Pins ±5-30): LTC±753-1± Only2 Io ꢁnternal Connection.

NC (Pins ±7-30): LTC±753-14 Only2 Io ꢁnternal Connection.

D5-D13 (Pins 6-14): LTC±753-14 Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D13 is the MꢀS.

NC (Pins ±9, 30): LTC±753-16 Only2 Io ꢁnternal Con-

nection.

D7-D15 (Pins 6-14): LTC±753-16 Only2 DAC ꢁnput/Output

Data Sits. These ꢁ/O pins set and read back the DAC code.

D15 is the MꢀS.

GND(Pin31):ꢀhieldGround,providesnecessaryshielding

for ꢁ

. Tie to ground.

OUT2S

I

(Pin 3±): DAC S Current Output Complement. Tie

to ground.

V

(Pin 15): Positive ꢀupply ꢁnput 2.7V ≤ V ≤ 5.5V.

DD

OUT±B

DD

ꢁ

Requires a 0.1μF bypass capacitor to GID.

OUT2S

S0 (Pin 33): ꢀpan ꢁ/O Sit 0. Pins ꢀ0, ꢀ1 and ꢀ2 are used to

NC (Pin 16): Io ꢁnternal Connection.

program and to read back the output range of the DACs.

A1 (Pin 17): DAC Address Sit 1. ꢀee Table 3.

A0 (Pin 18): DAC Address Sit 0. ꢀee Table 3.

GND (Pin 19): Ground. Tie to ground.

D/S (Pin 34): Data/ꢀpan ꢀelect. This pin is used to select

the data ꢁ/O pins or the span ꢁ/O pins (D0 to D15 or ꢀ0

to ꢀ2, respectivelyꢂ, along with their respective dedicated

registers, for write or read operations. Update operations

ignore D/ꢀ, since all updates affect both data and span

registers. For single-span operation, tie D/ꢀ to ground.

CLR (Pin ±0): Asynchronous Clear. When CLR is taken

to a logic low, the data registers are reset to the zero-volt

code for the present output range (V

= 0Vꢂ.

OUT

READ (Pin 35): Read Pin. When READ is asserted high,

the data ꢁ/O pins (D0-D15ꢂ or span ꢁ/O pins (ꢀ0-ꢀ2ꢂ

MSPAN(Pin±1):ManualꢀpanControlPin.MꢀPAIisused

to conﬁgure the LTC2753 for operation in a single, ﬁxed

2753f

10

LTC2753

PIN FUNCTIONS

output the contents of the selected register (see Table

1ꢂ. For single-span operation, readback of the span ꢁ/O

pins is disabled.

0V. For normal operation tie to the negative input of the ꢁ/V

converter ampliﬁer for DAC S (see Typical Applicationsꢂ.

R

VOSB

(Pin 43): DAC S Offset Adjust. Iominal input range

UPD (Pin 36): Update and Suffer ꢀelect Pin. When READ

is held low and UPD is asserted high, the contents of the

addressed DAC’s input registers (both data and spanꢂ are

copiedintotheirrespectiveDACregisters.Theoutputofthe

DAC is updated, reﬂecting the new DAC register values.

is 5V.Theimpedancelookingintothispinis1Mtoground.

ꢁf not used, tie R to ground.

VOꢀS

R

(Pin 44): DAC A Offset Adjust. Iominal input range

VOSA

is 5V.Theimpedancelookingintothispinis1Mtoground.

ꢁf not used, tie R to ground.

VOꢀA

When READ is held high, the update function is disabled

and the UPD pin functions as a buffer selector—logic low

to select the input register, high to select the DAC register.

ꢀee Readback in the Operation section.

I

(Pin 45): DAC A Current Output. This pin is a virtual

OUT1A

ground when the DAC is operating and should reside at

0V. For normal operation tie to the negative input of the ꢁ/V

converter ampliﬁer for DAC A (see Typical Applicationsꢂ.

WR(Pin37):ActiveLowWritePin. AWriteoperationcop-

ies the data present on the data or span ꢁ/O pins (D0-D15

or ꢀ0-ꢀ2, respectivelyꢂ into the associated input register.

When READ is high, the Write function is disabled.

R

(Pin 46): DAC A Feedback Resistor. For normal

FBA

operation tie to the output of the ꢁ/V converter ampliﬁer

for DAC A (see Typical Applicationsꢂ. The DAC output

current from ꢁ

to the RFSA pin. The impedance looking into this pin is

10k to ground.

ﬂows through the feedback resistor

OUT1A

S1 (Pin 38): ꢀpan ꢁ/O Sit 1. Pins ꢀ0, ꢀ1 and ꢀ2 are used

to program and to read back the output ranges of the

DACs.

R

(Pin 47): Sipolar Offset Ietwork for DAC A. This

OFSA

REFB(Pin39):ReferenceꢁnputforDACS.Theimpedance

looking into this pin is 10k to ground. For normal opera-

tion tie to the output of the reference inverting ampliﬁer.

Typically –5V; accepts up to 15V.

pin provides the translation of the output voltage range for

bipolar spans. Accepts up to 15V; for normal operation

tie to the positive reference voltage at R (Pin 2ꢂ. The

impedance looking into this pin is 20k to ground.

ꢁI

R

(Pin 40): Sipolar Offset Ietwork for DAC S. This

OFSB

REFA (Pin 48): Reference ꢁnput for DAC A, and connec-

tion for internal reference inverting resistor R2. The 20k

pinprovidesthetranslationoftheoutputvoltagerangefor

bipolar spans. Accepts up to 15V; for normal operation

resistorR2isconnectedinternallyfromR

toREFA.For

COM

tie to the positive reference voltage at R (Pin 2ꢂ. The

impedance looking into this pin is 20k to ground.

ꢁI

normal operation tie this pin to the output of the reference

invertingampliﬁer(seeTypicalApplicationsꢂ.Typically–5V;

accepts up to 15V. The impedance looking into this pin

R

FBB

(Pin 41): DAC S Feedback Resistor. For normal

operation tie to the output of the ꢁ/V converter ampliﬁer

for DAC S (see Typical Applicationsꢂ. The DAC output

is 10k to ground (R and R

ﬂoatingꢂ.

ꢁI

COM

Exposed Pad (Pin 49): Ground. The Exposed Pad must

be soldered to the PCS.

current from ꢁ

ﬂows through the feedback resistor

OUT1S

to the R

pin. The impedance looking into this pin is

FSS

10k to ground.

I

(Pin 4±): DAC S Current Output. This pin is a virtual

OUT1B

ground when the DAC is operating and should reside at

2753f

11

LTC2753

BLOCK DIAGRAM

R

ꢁI

R

REFA R

R

COM

OFꢀA FSA

2

1

48

47

46

R1

R2

16

3

DATA ꢁ /O

ꢁ/O

6-14, 22-28

PORT

16

3

DATA ꢁIPUT

REGꢁꢀTER

DATA DAC

REGꢁꢀTER

45

ꢁ

OUT1A

DAC A

16-SꢁT WꢁTH

ꢀPAI ꢀELECT

ꢀPAI ꢁ /O

3, 38, 33

ꢁ/O

PORT

4

OUT2A

ꢀPAI ꢁIPUT

REGꢁꢀTER

ꢀPAI DAC

REGꢁꢀTER

3

16

3

44

17

18

R

VOꢀA

VOꢀS

A1

DAC

43

42

ADDREꢀꢀ

16

3

DATA ꢁIPUT

REGꢁꢀTER

DATA DAC

REGꢁꢀTER

A0

ꢁ

OUT1S

OUT2S

DAC S

16-SꢁT WꢁTH

ꢀPAI ꢀELECT

32

ꢁ

ꢀPAI ꢁIPUT

REGꢁꢀTER

ꢀPAI DAC

REGꢁꢀTER

COITROL LOGꢁC

35

37

36

34

20

21

39

40

41

2753 SD

READ WR UPD D/ꢀ CLR

MꢀPAI

REFS R

R

OFꢀS FSS

2753f

12

LTC2753

TIMING DIAGRAMS

Write, Update and Clear Timing

t

3

t

1

t

2

WR

DATA/ꢀPAI ꢁ/O

ꢁIPUT

VALꢁD

t

4

t

6

5

UPD

t

8

7

9

D/ꢀ

VALꢁD

t

11

t

12

10

ADDREꢀꢀ

A1 - A0

VALꢁD

t

25

CLR

2753 TD01

Readback Timing

READ

t

14

24

13

t

WR

23

DATA/ꢀPAI ꢁ/O

ꢁIPUT

t

15

DATA/ꢀPAI ꢁ/O

OUTPUT

VALꢁD

t

27

26

17

ADDREꢀꢀ

A1-A0

t

20

t

19

t

22

UPD

t

18

D/ꢀ

VALꢁD

2753 TD02

2753f

13

LTC2753

OPERATION

Output Ranges

Loading the span input register is accomplished similarly,

holding the D/ꢀ pin high and bringing the WR pin low. The

span and data register structures are the same except for

thenumberofparallelbits—thespanregistershave3bits,

while the data registers have 12, 14, or 16.

TheLTC2753isadualcurrent-output, parallel-inputpreci-

sionmultiplyingDACwithsoftware-programmableoutput

ranges. ꢀoftꢀpan provides two unipolar output ranges

(0V to 5V and 0V to 10Vꢂ, and four bipolar ranges ( 2.5V,

5V, 10V and –2.5V to 7.5Vꢂ. These ranges are obtained

when an external precision 5V reference is used. When

a reference voltage of 2V is used, the ꢀoftꢀpan ranges

become: 0V to 2V, 0V to 4V, 1V, 2V, 4V and –1V to 3V.

The output ranges are linearly scaled for references other

than 2V and 5V.

To make both registers transparent for ﬂowthrough

mode, tie WR low and UPD high. However, this defeats

the deglitcher operation and output glitch impulse may

increase. The deglitcher is activated on the rising edge

of the UPD pin.

The interface also allows the use of the input and DAC

registers in a master-slave, or edge-triggered, conﬁgura-

tion. This mode of operation occurs when WR and UPD

are tied together and driven by a single clock signal. The

data bits are loaded into the input register on the falling

edge of the clock and then loaded into the DAC register

on the rising edge.

Digital Section

The LTC2753 has 4 internal registers for each DAC, a total

of 8 registers (see Slock Diagramꢂ. Each DAC channel has

twosetsofdouble-bufferedregisters—onesetforthedata,

and one set for the span (output rangeꢂ of the DAC. The

double-bufferedfeatureprovidesthecapabilitytosimulta-

neously update the span and code, which allows smooth

voltage transitions when changing output ranges. ꢁt also

permits the simultaneous updating of multiple DACs.

ꢁt is possible to control both data and span on one 16-bit

wide data bus by allowing span pins ꢀ2 to ꢀ0 to share

bus lines with the data LꢀSs (D2 to D0ꢂ. Io write or read

operation includes both span and data, so there cannot

be a conﬂict.

Each set of double-buffered registers comprises an input

registerandaDACregister. Theinputregistersareholding

buffers—when data is loaded into an input register via a

write operation, the DAC outputs are not affected.

The asynchronous clear pin resets both DACs to 0V in any

output range. CLR resets all data registers, while leaving

the span registers undisturbed.

The contents of a DAC register, on the other hand, di-

rectly control the DAC output voltage or output range.

The contents of the DAC registers are changed by copying

the contents of an input register into its associated DAC

register via an update operation.

V

DD

LTC2753-16

V

DD

DAC A

DAC S

MꢀPAI

ꢀ2

Write and Update Operations

ꢀ1

The data input register of the addressed DAC is loaded

directly from a 16-bit microprocessor bus by holding the

D/ꢀ pin low and pulsing the WR pin low (write operationꢂ.

The DAC register is loaded by pulsing the UPD pin high

(update operationꢂ, which copies the data held in the input

register into the DAC register. Iote that updates always

include both data and span; but the DAC register values

willnotchangeunlesstheinputregistervalueshaveprevi-

ously been changed via a write operation.

ꢀ0

D/ꢀ

WR

UPD READ A1

A0

2753 F01

16

DATA ꢁ/O

Figure 12 Using MSPAN to Conﬁgure the LTC±753 for Single-Span

Operation (±10V Range)2

2753f

14

LTC2753

OPERATION

These devices also have a power-on reset that initializes

the D/ꢀ pin. The selected ꢁ/O port’s pins become logic

outputs during readback, while the unselected ꢁ/O port’s

pins remain high-impedance inputs.

both DACs to V

= 0V in any output range. The DACs

OUT

power up in the 0V-5V range if the part is in ꢀoftꢀpan

conﬁguration;formanualspan(seeManualꢀpanConﬁgu-

rationbelowꢂ,bothDACspowerupinthemanually-chosen

range at the appropriate code.

With the DAC channel and ꢁ/O port selected, assert READ

high and select the desired input or DAC register using the

UPD pin. Iote that UPD is a two function pin—the update

function is only available when READ is low. When READ

is high, the update function is disabled and the UPD pin

instead selects the input or DAC register for readback.

Table 1 shows the readback functions for the LTC2753.

Manual Span Conﬁguration

Multipleoutputrangesarenotneededinsomeapplications.

ToconﬁguretheLTC2753forsingle-spanoperation,tiethe

MꢀPAI pin to V and the D/ꢀ pin to GID. The desired

DD

Table 12 Write, Update and Read Functions

output range is then speciﬁed by the span ꢁ/O pins (ꢀ0,

READ D/S WR UPD

SPAN I/O

DATA I/O

ꢀ1 and ꢀ2ꢂ as usual, but the pins are programmed by ty-

0

1

-

Write to ꢁnput Register

ing directly to GID or V (see Figure 1 and Table 2ꢂ. ꢁn

DD

Write/Update

(Transparentꢂ

this conﬁguration, both DAC channels will initialize to the

chosen output range at power-up, with V

= 0V.

OUT

0

1

0

1

0

1

-

When conﬁgured for manual span operation, span pin

readback is disabled.

Update DAC Register Update DAC Register

Write to ꢁnput Register

-

Write/Update

(Transparentꢂ

Readback

0

1

0

1

X

0

1

0

1

0

1

-

The contents of any one of the 8 interface registers can

be read back from the ꢁ/O ports.

Update DAC register Update DAC Register

-

Read ꢁnput Register

Theꢁ/Opinsaregroupedintotwoports:dataandspan.The

data ꢁ/O port comprises pins D0-D11, D0-D13 or D0-D15

(LTC2753-12, LTC2753-14 or LTC2753-16, respectivelyꢂ.

The span ꢁ/O port comprises pins ꢀ0, ꢀ1 and ꢀ2 for all

parts.

-

Read DAC Register

Read ꢁnput Register

Read DAC Register

-

X = Don’t Care

The most common readback task is to check the contents

of an input register after writing to it, before updating the

new data to the DAC register. To do this, hold UPD low

and assert READ high. The contents of the selected port’s

input register are output to its ꢁ/O pins.

Each DAC channel has a set of data registers that are

controlled and read back from the data ꢁ/O port; and a set

of span registers that are controlled and read back from

the span ꢁ/O port. The register structure is shown in the

Slock Diagram.

To read back the contents of a DAC register, hold UPD low

and assert READ high, then bring UPD high to select the

DACregister. ThecontentsoftheselectedDACregisterare

output by the selected port’s ꢁ/O pins. Iote: if no update is

desiredafterthereadbackoperation,UPDmustbereturned

low before bringing READ low; otherwise the UPD pin will

revert to its primary function and update the DAC.

A readback operation is initiated by asserting READ to

logic high after selecting the desired DAC channel and ꢁ/O

port.Theꢁ/Opins,whicharehigh-impedancedigitalinputs

when READ is low, selectively change to low-impedance

logic outputs during readback.

ꢀelect the DAC channel with address pins A1 and A0, and

select the ꢁ/O port (data or spanꢂ to be read back with

2753f

15

LTC2753

OPERATION

System Offset Adjustment

Table ±2 Span Codes

S±

0

S1

0

S0

0

SPAN

Many systems require compensation for overall system

Unipolar 0V to 5V

Unipolar 0V to 10V

Sipolar –5V to 5V

Sipolar –10V to 10V

Sipolar –2.5V to 2.5V

Sipolar –2.5V to 7.5V

offset. The R

and R

offset adjustment pins are

VOꢀA

VOꢀS

0

1

provided for this purpose. For noise immunity and ease

of adjustment, the control voltage is attenuated to the

DAC output:

0

1

0

1

0

V

= –0.01 • V(R

ꢂ [0V to 5V, 2.5V spansꢅ

Oꢀ

VOꢀX

1

0

1

= –0.02 • V(R

spansꢅ

ꢂ [0V to 10V, 5V, –2.5V to 7.5V

Oꢀ

VOꢀX

Codes not shown are reserved and should not be used.

Table 32 Address Codes

V

= –0.04 • V(R ꢂ [ 10V spanꢅ

VOꢀX

Oꢀ

DAC CHANNEL

A1

0

A0

0

The nominal input range of this pin is 5V; other reference

voltages of up to 15V may be used if needed. The R

A

S

VOꢀX

0

1

pins have an input impedance of 1MΩ. To preserve the

settling performance of the LTC2753, drive this pin with a

Thevenin-equivalent impedance of 10k or less. ꢀhort any

ALL*

1

Codes not shown are reserved and should not be used.

*ꢁf readback is taken using the All DACs address, the LTC2753 defaults to

DAC A.

unused system offset adjustment pins to ꢁ

.

OUT2

2753f

16

LTC2753

OPERATION—EXAMPLES

1. Load 5V range with the output at 0V. Iote that since span and code are updated together, the output, if started at

0V, will stay there. The 16-Sit DAC code is shown in hex for compactness.

WR

ꢀPAI ꢁ/O

ꢁIPUT

010

DATA ꢁ/O

ꢁIPUT

8000

H

UPD

UPDATE

( 5V RAIGE, V

= 0Vꢂ

OUT

D/ꢀ

READ = LOW

2753 TD03

2. Load 10V range with the output at 5V, changing to –5V.

WR

ꢀPAI ꢁ/O

ꢁIPUT

011

DATA ꢁ/O

ꢁIPUT

C000

4000

H

UPD

UPDATE (5Vꢂ

UPDATE (–5Vꢂ

D/ꢀ

READ = LOW

2753 TD04

3. Write and update midscale code in 0V to 5V range (V

and DAC registers before updating.

= 2.5Vꢂ using readback to check the contents of the input

OUT

WR

Hꢁ-Z

DATA ꢁ/O

ꢁIPUT

8000

H

Hꢁ-Z

DATA ꢁ/O

OUTPUT

8000

0000

H

ꢁIPUT REGꢁꢀTER

DAC REGꢁꢀTER

UPD

UPDATE (2.5Vꢂ

D/ꢀ

READ

2753 TD05

2753f

17

LTC2753

APPLICATIONS INFORMATION

Op Amp Selection

programmed in a unipolar or bipolar output range. These

are the changes the op amp can cause to the ꢁIL, DIL,

unipolaroffset,unipolargainerror,bipolarzeroandbipolar

gain error. Tables 4 and 5 can also be used to determine

the effects of op amp parameters on the LTC2753-14

and the LTC2753-12. However, the results obtained from

Tables 4 and 5 are in 16-bit LꢀSs. Divide these results

by 4 (LTC2753-14ꢂ and 16 (LTC2753-12ꢂ to obtain the

correct LꢀS sizing.

Secause of the extremely high accuracy of the 16-bit

LTC2753-16, careful thought should be given to op amp

selection in order to achieve the exceptional performance

of which the part is capable. Fortunately, the sensitivity of

ꢁIL and DIL to op amp offset has been greatly reduced

compared to previous generations of multiplying DACs.

Tables 4 and 5 contain equations for evaluating the effects

of op amp parameters on the LTC2753’s accuracy when

Table 6 contains a partial list of LTC precision op amps

recommended for use with the LTC2753. The easy-to-use

designequationssimplifytheselectionofopampstomeet

the system’s speciﬁed error budget. ꢀelect the ampliﬁer

from Table 6 and insert the speciﬁed op amp parameters

in Table 5. Add up all the errors for each category to de-

termine the effect the op amp has on the accuracy of the

part.Arithmeticsummationgivesan(unlikelyꢂworst-case

effect. A root-sum-square (RMꢀꢂ summation produces a

more realistic estimate.

Table 42 Variables for Each Output Range That Adjust the

Equations in Table 5

OUTPUT RANGE

A1

1.1

2.2

2

A±

2

A3

1

A4

A5

1

5V

10V

3

0.5

1

1.5

2.5

1

5V

2

1

10V

4

0.83

1.4

0.7

2.5V

1

–2.5V to 7.5V

1.9

3

0.5

1.5

Table 52 Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1)2 Subscript 1

Refers to Output Amp, Subscript ± Refers to Reference Inꢀerting Amp2

UNIPOLAR

OFFSET (LSB)

BIPOLAR ZERO

ERROR (LSB)

UNIPOLAR GAIN

ERROR (LSB)

BIPOLAR GAIN

ERROR (LSB)

OP AMP

INL (LSB)

DNL (LSB)

5V

REF

5V

REF

5V

REF

5V

REF

5V

REF

5V

REF

V

(mVꢂ

V

• 3.2 •

V

• 0.82 •

A3 • V

Oꢀ1

• 13.2 •

A3 • V

• 19.8 •

V

• 13.2 •

V

ꢁ

• 13.2 •

Oꢀ1

)

⁽V

Oꢀ1

5V

ꢁ

(nAꢂ

ꢁ

• 0.0003 •

ꢁ

• 0.00008 •

ꢁ

S1

• 0.13 •

ꢁ

S1

• 0.13 •

ꢁ

S1

• 0.0018 •

⁽V

S1

)

⁽V

)

REF

₍16.5k₎

1.5k

VOL1

131k

VOL1

131k

VOL1

A

VOL1

(V/Vꢂ

(mVꢂ

A1 •

A2 •

0

A5 •

0

A5 •

)

A

⁽A

)

⁽A

VOL1

5V

V

0

A4 • V

• 13.1 •

V

• 26.2 •

V

• 26.2 •

Oꢀ2

⁽V

)

⁽V

(

))

)

REF

5V

REF

5V

REF

5V

⁽V

ꢁ

(mVꢂ

A4 • ꢁ • 0.13 •

ꢁ

• 0.26 •

ꢁ

S2

• 0.26 •

131k

S2

(

⁽V

)

⁽V

REF

66k

VOL2

131k

⁽A

A

(V/Vꢂ

A4 •

VOL2

⁽A

)

⁽A

)

VOL2

Table 62 Partial List of LTC Precision Ampliﬁers Recommended for Use with the LTC±753 with Releꢀant Speciﬁcations

AMPLIFIER SPECIFICATIONS

VOLTAGE CURRENT

SLEW

RATE

V/μs

GAIN BANDWIDTH

PRODUCT

MHz

t

POWER

SETTLING

V

I

A

VOL

NOISE

with LTC±753 DISSIPATION

OS

B

AMPLIFIER

LT1001

μV

nA

V/mV

nV/√Hz

pA/√Hz

μs

120

115

19

mW

46

25

2

800

10

14

2.7

5

0.12

0.008

0.3

0.25

0.2

0.16

4.5

22

0.8

0.7

0.75

12.5

90

LT1097

50

0.35

0.25

20

1000

1500

4000

5000

2000

11

LT1112 (Dualꢂ

LT1124 (Dualꢂ

LT1468

60

10.5/Op Amp

69/Op Amp

117

70

75

10

0.6

2

LT1469 (Dualꢂ

125

10

5

0.6

22

90

2

123/Op Amp

2753f

18

LTC2753

APPLICATIONS INFORMATION

Op amp offset will contribute mostly to output offset and

gain error, and has minimal effect on ꢁIL and DIL. For

example, for the LTC2753-16 with a 5V reference in 5V

unipolar mode, a 250μV op amp offset will cause a 3.3LꢀS

zero-scale error and a 3.3LꢀS gain error; but only 0.8LꢀS

of ꢁIL degradation and 0.2LꢀS of DIL degradation.

A reference’s output voltage temperature coefﬁcient af-

fects not only the full-scale error, but can also affect the

circuit’s apparent ꢁIL and DIL performance. ꢁf a refer-

ence is chosen with a loose output voltage temperature

coefﬁcient, then the DAC output voltage along its transfer

characteristicwillbeverydependentonambientconditions.

Minimizing the error due to reference temperature coef-

ﬁcient can be achieved by choosing a precision reference

with a low output voltage temperature coefﬁcient and/or

tightly controlling the ambient temperature of the circuit

to minimize temperature gradients.

While not directly addressed by the simple equations in

Tables 4 and 5, temperature effects can be handled just as

easily for unipolar and bipolar applications. First, consult

an op amp’s data sheet to ﬁnd the worst-case V and ꢁ

Oꢀ

S

over temperature. Then, plug these numbers in the V

Oꢀ

As precision DAC applications move to 16-bit and higher

performance, reference output voltage noise may con-

tribute a dominant share of the system’s noise ﬂoor. This

in turn can degrade system dynamic range and signal-to-

noise ratio. Care should be exercised in selecting a voltage

reference with as low an output noise voltage as practi-

cal for the system resolution desired. Precision voltage

references, like the LT1236, produce low output noise in

the 0.1Hz to 10Hz region, well below the 16-bit LꢀS level

in 5V or 10V full-scale systems. However, as the circuit

bandwidths increase, ﬁltering the output of the reference

may be required to minimize output noise.

and ꢁ equations from Table 5 and calculate the tempera-

ture-induced effects.

S

For applications where fast settling time is important, Ap-

plicationIote74,ComponentandMeasurementAdvances

Ensure16-SitDACꢀettlingTime,offersathoroughdiscus-

sion of 16-bit DAC settling time and op amp selection.

Precision Voltage Reference Considerations

Much in the same way selecting an operational ampliﬁer

for use with the LTC2753 is critical to the performance of

the system, selecting a precision voltage reference also

requires due diligence. The output voltage of the LTC2753

is directly affected by the voltage reference; thus, any

voltage reference error will appear as a DAC output volt-

age error.

Table 72 Partial List of LTC Precision References Recommended

for Use with the LTC±753 with Releꢀant Speciﬁcations

INITIAL

TOLERANCE

TEMPERATURE

DRIFT

021Hz to 10Hz

NOISE

REFERENCE

LT1019A-5,

LT1019A-10

0.05ꢃ

0.075ꢃ

0.05ꢃ

5ppm/°C

10ppm/°C

12μV

P-P

There are three primary error sources to consider when

selecting a precision voltage reference for 16-bit appli-

cations: output voltage initial tolerance, output voltage

temperature coefﬁcient and output voltage noise.

LT1236A-5,

LT1236A-10

3μV

P-P

LT1460A-5,

LT1460A-10

20μV

P-P

ꢁnitial reference output voltage tolerance, if uncorrected,

generates a full-scale error term. Choosing a reference

with low output voltage initial tolerance, like the LT1236

( 0.05ꢃꢂ,minimizesthegainerrorcausedbythereference;

however, a calibration sequence that corrects for system

zero- and full-scale error is always recommended.

LT1790A-2.5

12μV

2753f

19

LTC2753

APPLICATIONS INFORMATION

Grounding

pin to star ground. This minimizes the voltage drop from

this pin to ground caused by the code dependent current

ﬂowing to ground. When the resistance of this circuit

board trace becomes greater than 1Ω, a force/sense am-

pliﬁer conﬁguration should be used to drive this pin (see

Figure 2ꢂ. This preserves the excellent accuracy (1LꢀS

ꢁIL and DILꢂ of the LTC2753-16.

As with any high resolution converter, clean grounding is

important. A low impedance analog ground plane and star

grounding techniques should be used. ꢁ

must be tied

OUT2

to the star ground with as low a resistance as possible.

When it is not possible to locate star ground close to

ꢁ

, a low resistance trace should be used to route this

OUT2

2753f

20

LTC2753

APPLICATIONS INFORMATION

ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE

4,32

ꢁ

OUT2

200Ω

–

2

–

+

2

3

6

1000pF

LT1468

1

2

6

+ ³

ꢁ

LT1001

OUT2

ZETEX

SAT54ꢀ

1

2

3

ZETEX*

SAT54ꢀ

3

*ꢀCHOTTKY SARRꢁER DꢁODE

V

REF

5V

LTC2753-16

46

R

47

2

OFꢀA

R

ꢁ

FSA

R

ꢁI

15pF

+ ³

45

–

1

OUT1A

2

3

1/2 LT1469

1

–

R

COM

1

2

DAC A

V

OUTA

1/2 LT1469

+

4

ꢁ

OUT2A

150pF

REFA 48

44

R

VOꢀA

2753 F02

Figure ±2 Optional Circuits for Driꢀing I_OUT±from GND with a Force/Sense Ampliﬁer2

2753f

21

LTC2753

TYPICAL APPLICATIONS

Dual 16-Bit V_OUTDAC with Software-Selectable Ranges

V

REF

5V

LTC2753-16

46

R

47

2

OFꢀA

R

ꢁ

FSA

R

ꢁI

15pF

C2

+ ³

45

4

–

R1

R2

OUT1A

2

3

1

1/2 LT1469

1

–

R

1

2

COM

DAC A

V

OUTA

1/2 LT1469

+

ꢁ

OUT2A

150pF

C1*

REFA 48

REFS 39

44

43

32

R

VOꢀA

VOꢀS

ꢁ

+

5

6

OUT2S

7

V

OUTS

DAC S

1/2 LT1469

–

42

41

ꢁ

OUT1S

15pF

C3

R

OFꢀS

40

R

FSS

16

2753 F03

DATA ꢁ/O

D15 - D0

ꢁ/O PORT

3

ꢀPAI ꢁ/O

ꢀ2 - ꢀ0

WR UPD READ D/ꢀ CLR MꢀPAI A1, A0

37 36 35 34 20 21 17, 18

WR UPD READ D/ꢀ CLR ADDREꢀꢀ

*FOR MULTꢁPLYꢁIG APPLꢁCATꢁOIꢀ C1 = 15pF

2753f

22

LTC2753

PACKAGE DESCRIPTION

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

0.70 ±0.05

5.15 ± 0.05

5.50 REF

6.10 ±0.05 7.50 ±0.05

(4 SIDES)

5.15 ± 0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 ± 0.05

R = 0.115

TYP

7.00 ± 0.10

(4 SIDES)

R = 0.10

TYP

47 48

0.40 ± 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1

CHAMFER

C = 0.35

5.15 ± 0.10

5.50 REF

(4-SIDES)

5.15 ± 0.10

(UK48) QFN 0406 REV C

0.200 REF

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

2753f

ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2753

TYPICAL APPLICATION

Offset and Gain Trim Circuits2 Powering V_DDfrom LT10±7 Ensures Quiet Supply

OFFꢀET

TRꢁM A

OFFꢀET

TRꢁM S

+

V

ꢁI

OUT

U3

LT1027

+

2

6

5

2

1

V

C13

10μF

8

2

3

2

R1

10k

1

2

R3

10k

TRꢁM

R2

10k

–

3

C20

10μF

GID

4

U2A

1

LT^®1469

1

C23

0.1μF

+

C22

0.001μF

4

GAꢁI

TRꢁM

–

V

C1

30pF

15

47

40

2

1

48

39

46

6

7

8

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

V

R

OFꢀA

R

OFꢀS

R

ꢁI

R

COM

REFA REFS

R

FSA

DD

–

45

9

6

5

ꢁ

OUT1A

10

11

12

13

14

22

23

24

25

26

27

28

U4S

LT1469

7

1

V

OUTA

4

+

OUT2A

44

DATA ꢁ/O

R

U1

LTC2753-16

VOꢀA

VOꢀS

43

32

R

+

8

V

+

3

2

D4

D3

D2

D1

ꢁ

OUT2S

U4A

OUTS

LT1469

42

–

ꢁ

OUT1S

D0

–

4

V

3

38

33

ꢀ2

ꢀ1

ꢀ0

ꢀPAI ꢁ/O

C2

30pF

R

FSS

D/ꢀ READ UPD WR CLR

34 35 36 37 20

MꢀPAI GID GID GID GID

21 31 19 49

5

41

2753 TA03

D/ꢀ READ UPD WR CLR

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

1ppm/°C Maximum Drift

LT1027

Precision Reference

LT1236A-5

LT1468

0.05ꢃ Maximum Tolerance, 1ppm 0.1Hz to 10Hz Ioise

90MHz GSW, 22V/μs ꢀlew Rate

16-Sit Accurate Op-Amp

Dual 16-Sit Accurate Op-Amp

LT1469

90MHz GSW, 22V/μs ꢀlew Rate

LTC1588/LTC1589/ ꢀerial 12-/14-/16-Sit ꢁ

LTC1592

ꢀingle DAC

ꢀoftware-ꢀelectable (ꢀoftꢀpanꢂ Ranges, 1LꢀS ꢁIL, DIL, 16-Lead ꢀꢀOP Package

OUT

LTC1591/LTC1597 Parallel 14-/16-Sit ꢁ

ꢀingle DAC

ꢁntegrated 4-Quadrant Resistors

OUT

LTC1821

Parallel 16-Sit V

ꢀingle DAC

1LꢀS ꢁIL, DIL, 0V to 10V, 0V to –10V, 10V Output Ranges

OUT

LTC2601/LTC2611/ ꢀerial 12-/14-/16-Sit V

LTC2621

ꢀingle DACs

ꢀingle DACs, ꢀPꢁ-Compatible, ꢀingle ꢀupply, 0V to 5V Outputs in 3mm × 3mm

DFI-10 Package

OUT

2

LTC2606/LTC2616/ ꢀerial 12-/14-/16-Sit V

LTC2626

ꢀingle DACs

ꢀingle DACs, ꢁ C-Compatible, ꢀingle ꢀupply, 0V to 5V Outputs in 3mm × 3mm

OUT

DFI-10 Package

LTC2641/LTC2642 ꢀerial 12-/14-/16-Sit Unbuffered V

DACs

ꢀingle

2LꢀS ꢁIL, 1LꢀS DIL, 1μs ꢀettling, Tiny MꢀOP-10, 3mm × 3mm DFI-10

Packages

OUT

LTC2704

LTC2751

ꢀerial 12-/14-/16-Sit V

Quad DACs

ꢀoftware-ꢀelectable (ꢀoftꢀpanꢂ Ranges, ꢁntegrated Ampliﬁers, 2LꢀS ꢁIL

OUT

Parallel 12-/14-/16-Sit ꢁ

ꢀingle DACs

ꢀoftꢀpan

1LꢀS ꢁIL, DIL, ꢀoftware-ꢀelectable (ꢀoftꢀpanꢂ Ranges, 5mm × 7mm

QFI-38 Package

OUT

2753f

LT 1007 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Slvd., Milpitas, CA 95035-7417

24

●

(408ꢂ 432-1900 FAX: (408ꢂ 434-0507 www.linear.com


型号：	LTC2753CUK-14#TRPBF
厂家：	Linear
描述：	LTC2753 - Dual Current Output 12-/14-/16-Bit SoftSpan DACs with Parallel I/O; Package: QFN; Pins: 48; Temperature Range: 0°C to 70°C
文件：	总24页 (文件大小：281K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2753CUK-14#TRPBF [Linear]

相关型号：

LTC2753CUK-14PBF

LTC2753IUK-12#TRPBF

LTC2753IUK-12PBF

LTC2753IUK-14#PBF

LTC2753IUK-14#TRPBF

LTC2753IUK-14PBF

LTC2753UK-12

LTC2753UK-14

LTC2753UK-16

LTC2754

LTC2754-12

LTC2754ACUKG-16