LTC2754AIUKG-16PBF [Linear]
Quad 12-/16-Bit SoftSpan IOUT DACs; 四核12位/ 16位的SoftSpan IOUT DAC的
| 型号： | LTC2754AIUKG-16PBF |
| 厂家： | 
Linear |
| 描述： | Quad 12-/16-Bit SoftSpan IOUT DACs |
| 文件： | 总28页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2754
Quad 12-/16-Bit
SoftSpan I DACs
OUT
FEATURES
DESCRIPTION
TheLTC®2754isafamilyofquad12- and16-bitmultiplying
serial-input, current-output digital-to-analog converters.
They operate from a single 3V to 5V supply and are guar-
anteed monotonic over temperature. The LTC2754A-16
provides full 16-bit performance ( 1LꢀS ꢁIL and ꢂIL,
max) over temperature without any adjustments. These
ꢀoftꢀpan™ ꢂACs offer six output ranges (up to 1ꢃV) that
canbeprogrammedthroughthe3-wireꢀPꢁserialinterface,
or pinstrapped for operation in a single range.
n
Program or Pin-Strap Six Output Ranges
0V to 5V, 0V to 10V, –2.5V to 7.5V, 2.5V, 5V, 10V
n
Maximum 16-Bit INL Error: 1 LSB oꢀer
Temperature
Guaranteed Monotonic oꢀer Temperature
n
n
Low Glitch Impulse 0.26nV•s (3V), 1.25nV•s (5V)
n
Serial Readback of All On-Chip Registers
n
Low 1μA Maximum ꢀupply Current
n
2.7V to 5.5V ꢀingle-ꢀupply Operation
n
16-Sit ꢀettling Time: 2ꢄs
The content of any on-chip register (including ꢂAC out-
put-range settings) can be verified in just one instruction
cycle; and if you change any register, that register will be
automatically read back during the next instruction cycle.
n
Voltage-Controlled Offset and Gain Trims
n
Clear and Power-On-Reset to ꢃV Regardless of
Output Range
52-Pin 7mm × 8mm QFI Package
n
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the ꢂAC outputs to ꢃV regardless of output range.
APPLICATIONS
■
High Resolution Offset and Gain Adjustment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Process Control and ꢁndustrial Automation
■
Automatic Test Equipment
ꢂata Acquisition ꢀystems
Protected by U.S. Patents, including 5481178.
■
TYPICAL APPLICATION
Quad 16-Bit VOUT DAC with Software-Selectable Ranges
V
REFA
V
REFS
+
–
+
–
LTC2754-16 Integral
Nonlinearity (INL)
V
ꢂꢂ
1.ꢃ
ꢃ.8
V
V
= 5V
= 5V
1ꢃV RAIGE
ꢂꢂ
REF
V
V
OꢀAꢂJS
OUT2S
OꢀAꢂJA
ꢁ
ꢃ.6
ꢁ
ꢁ
+
–
+
–
OUT2A
V
V
V
OUTS
OUTA
ꢃ.4
ꢁ
ꢂAC A
ꢂAC ꢂ
ꢂAC S
OUT1A
OUT1S
R
FSA
R
ꢃ.2
FSS
ꢃ
ꢀPꢁ with REAꢂSACK
LTC2754-16
R
R
FSC
FSꢂ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
ꢁ
ꢁ
ꢁ
–
+
–
+
OUT1ꢂ
OUT2ꢂ
OUT1C
OUT2C
V
OUTC
ꢁ
OUTꢂ
ꢂAC C
V
V
OꢀAꢂJC
OꢀAꢂJꢂ
ꢃ
16384
32768
COꢂE
49152
65535
–
+
–
+
ALL AMPLꢁFꢁERꢀ 1/2 LT1469
2754 Gꢃ1
V
REFꢂ
V
REFC
2754 TAꢃ1
2754f
1
LTC2754
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VꢁEW
ꢁ
, ꢁ
to GIꢂ............................................ ꢃ.3V
OUT1X OUT2X
R
, R
, REFX, R , R
, V
,
ꢁIX COMX
FSX OFꢀX OꢀAꢂJX
GE
V
to GIꢂ........................................................ 18V
AꢂJX
52 51 5ꢃ 49 48 47 46 45 44 43 42 41
to GIꢂ..................................................–ꢃ.3V to 7V
ꢂꢂ
GE
ꢁ
1
2
4ꢃ GE
AꢂJS
AꢂJA
ꢂigital ꢁnputs and
R
ꢁIA
39
38
37
R
ꢁIS
ꢁ
3
Outputs to GIꢂ ................ –ꢃ.3V to V +ꢃ.3V (max 7V)
OUT2A
GIꢂ
OUT2S
GIꢂ
ꢂꢂ
4
Operating Temperature Range
CS/Lꢂ
ꢀꢂꢁ
5
36 LDAC
ꢀ2
35
LTC2754C ................................................ ꢃ°C to 7ꢃ°C
LTC2754ꢁ..............................................–4ꢃ°C to 85°C
Maximum Junction Temperature........................... 15ꢃ°C
ꢀtorage Temperature Range...................–65°C to 15ꢃ°C
6
ꢀCK
7
34 ꢀ1
53
ꢀRO
8
33 ꢀꢃ
ꢀROGIꢂ
9
32 M-ꢀPAI
31 RFLAG
3ꢃ CLR
V
1ꢃ
ꢂꢂ
GIꢂ 11
ꢁ
12
13
14
29
28
ꢁ
OUT2C
OUT2ꢂ
R
R
ꢁIC
ꢁIꢂ
GE
27 GE
AꢂJC
AꢂJꢂ
15 16 17 18 19 2ꢃ 21 22 23 24 25 26
UKG PACKAGE
52-LEAꢂ (7mm s 8mm) PLAꢀTꢁC QFI
T
= 15ꢃ°C, θ = 29°C/W
JA
JMAX
EXPOꢀEꢂ PAꢂ (PꢁI 53) ꢁꢀ GIꢂ, MUꢀT SE ꢀOLꢂEREꢂ TO PCS
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC2754UKG-12
LTC2754UKG-12
PACKAGE DESCRIPTION
TEMPERATURE RANGE
ꢃ°C to 7ꢃ°C
LTC2754CUKG-12#PSF
LTC2754ꢁUKG-12#PSF
LTC2754CUKG-12#TRPSF
LTC2754ꢁUKG-12#TRPSF
52-Lead (7mm × 8mm) Plastic QFI
52-Lead (7mm × 8mm) Plastic QFI
52-Lead (7mm × 8mm) Plastic QFI
52-Lead (7mm × 8mm) Plastic QFI
52-Lead (7mm × 8mm) Plastic QFI
52-Lead (7mm × 8mm) Plastic QFI
–4ꢃ°C to 85°C
ꢃ°C to 7ꢃ°C
LTC2754SCUKG-16#PSF LTC2754SCUKG-16#TRPSF LTC2754UKG-16
LTC2754SꢁUKG-16#PSF LTC2754SꢁUKG-16#TRPSF LTC2754UKG-16
LTC2754ACUKG-16#PSF LTC2754ACUKG-16#TRPSF LTC2754UKG-16
LTC2754AꢁUKG-16#PSF LTC2754AꢁUKG-16#TRPSF LTC2754UKG-16
–4ꢃ°C to 85°C
ꢃ°C to 7ꢃ°C
–4ꢃ°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2754f
2
LTC2754
ELECTRICAL CHARACTERISTICS VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2754-12
TYP
LTC2754B-16
TYP
LTC2754A-16
TYP
SYMBOL
Static Performance
Resolution
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
●
●
●
12
12
16
16
16
16
Sits
Sits
LꢀS
Monotonicity
ꢂIL
ꢂifferential
Ionlinearity
1
1
ꢃ.2
1
●
●
ꢁIL
GE
ꢁntegral Ionlinearity
1
2
2
ꢃ.4
2
1
LꢀS
LꢀS
Gain Error
All Output Ranges
ΔGain/ΔTemp
ꢃ.5
1
2ꢃ
12
Gain Error Temp-
erature Coefficient
1
1
ppm/°C
●
SZE
Sipolar Zero Error
All Sipolar Ranges
ꢃ.2
ꢃ.5
1
12
1
8
LꢀS
Sipolar Zero Temp-
erature Coefficient
ꢃ.5
ꢃ.5
ppm/°C
●
●
PꢀR
Power ꢀupply
Rejection
V
ꢂꢂ
V
ꢂꢂ
= 5V, 1ꢃ0
= 3V, 1ꢃ0
ꢃ.ꢃ25
ꢃ.ꢃ6
ꢃ.4
1
ꢃ.ꢃ3
ꢃ.1
ꢃ.2
ꢃ.5
LꢀS/V
LꢀS/V
ꢁ
ꢁ
Leakage Current T = 25°C
ꢃ.ꢃ5
2
5
ꢃ.ꢃ5
2
5
ꢃ.ꢃ5
2
5
nA
nA
LKG
OUT1
A
●
T
to T
MAX
MꢁI
VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Pins
●
●
●
●
●
●
Reference ꢁnverting Resistors
ꢂAC ꢁnput Resistance
Feedback Resistors
(Iote 4)
16
8
2ꢃ
1ꢃ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
R
R
R
REF
(Iote 3)
(Iote 3)
8
1ꢃ
FS
Sipolar Offset Resistors
Offset Adjust Resistors
Gain Adjust Resistors
Output Capacitance
16
2ꢃ
OFꢀ
R
1ꢃ24
2ꢃ48
128ꢃ
256ꢃ
VOꢀAꢂJ
R
GEAꢂJ
ꢁOUT1
C
Full-ꢀcale
Zero-ꢀcale
75
45
Dynamic Performance
Output ꢀettling Time
ꢃV to 1ꢃV Range, 1ꢃV ꢀtep. To ꢃ.ꢃꢃ150 Fꢀ
(Iote 5)
2
μs
Glitch ꢁmpulse
V
V
= 5V (Iote 6)
= 3V (Iote 6)
1.25
ꢃ.26
nV•s
nV•s
ꢂꢂ
ꢂꢂ
ꢂigital-to-Analog Glitch ꢁmpulse
Reference Multiplying SW
(Iote 7)
ꢃV to 5V Range, V = 3V
2
2
nV•s
MHz
,
RMꢀ
REF
Code = Full ꢀcale, –3dS SW
Multiplying Feedthrough Error
ꢃV to 5V Range, V = 1ꢃV, 1ꢃkHz
ꢃ.5
mV
REF
ꢀine Wave
Analog Crosstalk
(Iote 8)
–1ꢃ9
–11ꢃ
13
dS
dS
THꢂ
Total Harmonic ꢂistortion
Output Ioise Voltage ꢂensity
(Iote 9) Multiplying
(Iote 1ꢃ) at ꢁ
nV/√Hz
OUT1
2754f
3
LTC2754
ELECTRICAL CHARACTERISTICS VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes the
specifications which apply oꢀer the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
●
●
V
ꢀupply Voltage
2.7
5.5
1
V
ꢂꢂ
ꢁ
ꢂꢂ
ꢀupply Current, V
ꢂigital ꢁnputs = ꢃV or V
ꢂꢂ
ꢃ.5
μA
ꢂꢂ
Digital Inputs
●
●
V
ꢂigital ꢁnput High Voltage
ꢂigital ꢁnput Low Voltage
3.3V ≤ V ≤ 5.5V
2.4
2
V
V
ꢁH
ꢂꢂ
2.7V ≤ V < 3.3V
ꢂꢂ
●
●
V
4.5V < V ≤ 5.5V
ꢃ.8
ꢃ.6
V
V
ꢁL
ꢂꢂ
2.7V ≤ V ≤ 4.5V
ꢂꢂ
Hysteresis Voltage
ꢃ.1
V
ꢄA
pF
●
●
ꢁ
ꢂigital ꢁnput Current
ꢂigital ꢁnput Capacitance
V
V
= GIꢂ to V
ꢂꢂ
1
6
ꢁI
ꢁI
C
= ꢃV (Iote 11)
ꢁI
ꢁI
Digital Outputs
●
●
V
OH
V
OL
ꢁ
ꢁ
= 2ꢃꢃꢄA
= 2ꢃꢃꢄA
2.7V ≤ V ≤ 5.5V
V – ꢃ.4
ꢂꢂ
V
V
OH
ꢂꢂ
2.7V ≤ V ≤ 5.5V
ꢃ.4
OL
ꢂꢂ
TIMING CHARACTERISTICS
The ● denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
= 4.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
●
●
●
●
●
●
●
●
●
●
●
●
●
●
t
t
t
t
t
t
t
t
t
t
t
t
t
ꢀꢂꢁ Valid to ꢀCK ꢀet-Up
ꢀꢂꢁ Valid to ꢀCK Hold
ꢀCK High Time
7
7
ns
ns
1
2
11
11
9
ns
3
ꢀCK Low Time
ns
4
CS/Lꢂ Pulse Width
ns
5
LꢀS ꢀCK High to CS/Lꢂ High
CS/Lꢂ Low to ꢀCK Positive Edge
CS/Lꢂ High to ꢀCK Positive Edge
ꢀRO Propagation ꢂelay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/Lꢂ High to RFLAG High
ꢀCK Frequency
4
ns
6
4
ns
7
4
ns
8
C
= 1ꢃpF
18
ns
9
LOAꢂ
36
15
ns
1ꢃ
11
12
13
ns
C
C
= 1ꢃpF (Iote 11)
= 1ꢃpF (Iote 11)
5ꢃ
4ꢃ
4ꢃ
ns
LOAꢂ
ns
LOAꢂ
5ꢃ0 ꢂuty Cycle (Iote 12)
MHz
V
= 2.7V to 3.3V
DD
●
●
●
●
●
●
t
t
t
t
t
t
ꢀꢂꢁ Valid to ꢀCK ꢀet-Up
ꢀꢂꢁ Valid to ꢀCK Hold
ꢀCK High Time
9
9
ns
ns
ns
ns
ns
ns
1
(Iote 11)
2
3
4
5
6
C = 1ꢃpF
L
15
15
12
5
ꢀCK Low Time
CS/Lꢂ Pulse Width
LꢀS ꢀCK High to CS/Lꢂ High
2754f
4
LTC2754
TIMING CHARACTERISTICS The ● denotes specifications that apply oꢀer the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
5
TYP
MAX
UNITS
ns
●
●
●
●
●
●
●
●
t
t
t
t
t
t
t
CS/Lꢂ Low to ꢀCK Positive Edge
CS/Lꢂ High to ꢀCK Positive Edge
ꢀRO Propagation ꢂelay
CLR Pulse Width Low
LDAC Pulse Width Low
CLR Low to RFLAG Low
CS/Lꢂ High to RFLAG high
ꢀCK Frequency
7
5
ns
8
C
LOAꢂ
= 1ꢃpF
26
ns
9
6ꢃ
2ꢃ
ns
1ꢃ
11
12
13
ns
C
C
= 1ꢃpF (Iote 11)
= 1ꢃpF (Iote 11)
7ꢃ
6ꢃ
25
ns
LOAꢂ
ns
LOAꢂ
5ꢃ0 ꢂuty Cycle (Iote 12)
MHz
Note 1: ꢀtresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7. Full-scale transition; REF = ꢃV.
Note 8. Analog Crosstalk is defined as the AC voltage ratio V
/V
,
OUTS REFA
expressed in dS. REFS is grounded, and ꢂAC S is set to ꢃV-5V span and
zero-, mid- or full- scale code. V is a 3V , 1kHz sine wave. Crosstalk
REFA
RMꢀ
Note 2: Continuous operation above the specified maximum operating
between other ꢂAC channels is similar or better.
junction temperature may impair device reliability.
Note 9. REF = 6V at 1kHz. ꢃV to 5V range. ꢂAC code = Fꢀ. Output
RMꢀ
Note 3: Secause of the proprietary ꢀoftꢀpan switching architecture, the
amplifier = LT1469.
measured resistance looking into each of the specified pins is constant for
Note 10. Calculation from V = √4kTRB, where k = 1.38E-23 J/°K
(Soltzmann constant), R = resistance (Ω), T = temperature (°K), and S =
bandwidth (Hz). ꢃV to 5V Range; zero-, mid-, or full- scale.
n
all output ranges if the ꢁ
and ꢁ
pins are held at ground.
OUT1X
OUT2X
Note 4: ꢁnput resistors measured from R to R
; feedback resistors
ꢁIX
COMX
measured from R
to REFX.
COMX
Note 11. Guaranteed by design, not subject to test.
Note 5: Using LT1469 with C
= 15pF. A ꢃ.ꢃꢃ150 settling time
FEEꢂSACK
Note 12. When using ꢀRO, maximum ꢀCK frequency f
is limited by
MAX
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. ꢀee Application Iote 74, Component and Measurement Advances
Ensure 16-Sit ꢂAC ꢀettling Time.
ꢀRO propagation delay t as follows:
9
⎛
⎞
1
⎜
⎜
⎝
⎟
⎟
⎠
fMAX
=
Note 6: Measured at the major carry transition, ꢃV to 5V range. Output
2 t + t
, where t is the setup time of the receiving device.
ꢀ
(
)
9
S
amplifier: LT1469; C = 27pF.
FS
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2754-16
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL ꢀs Temperature
1.ꢃ
ꢃ.8
1.ꢃ
ꢃ.8
1.ꢃ
ꢃ.8
V
V
= 5V
= 5V
V
V
= 5V
= 5V
V
V
= 5V
= 5V
ꢂꢂ
REF
ꢂꢂ
REF
1ꢃV RAIGE
ꢂꢂ
REF
1ꢃV RAIGE
1ꢃV RAIGE
ꢃ.6
ꢃ.6
ꢃ.6
ꢃ.4
ꢃ.4
ꢃ.4
+ꢁIL
–ꢁIL
ꢃ.2
ꢃ.2
ꢃ.2
ꢃ
ꢃ
ꢃ.ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
ꢃ
16384
32768
COꢂE
49152
65535
ꢃ
16384
32768
COꢂE
49152
65535
–4ꢃ
–2ꢃ
ꢃ
2ꢃ
4ꢃ
6ꢃ
8ꢃ
TEMPERATURE (°C)
2754 Gꢃ3
2754 Gꢃ1
2754 Gꢃ2
2754f
5
LTC2754
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2754-16
DNL ꢀs Temperature
Bipolar Zero ꢀs Temperature
Gain Error ꢀs Temperature
1.ꢃ
ꢃ.8
8
6
4
2
16
12
8
V
V
= 5V
= 5V
V
V
= 5V
= 5V
ꢂꢂ
REF
V
V
= 5V
= 5V
ꢂꢂ
REF
1ꢃV RAIGE
ꢂꢂ
REF
1ꢃV RAIGE
1ꢃV RAIGE
ꢃ.6
ꢃ.4
4
ꢃ.2
+ꢂIL
–ꢂIL
ꢃ.5ppm/°C (TYP)
1ppm/°C (TYP)
ꢃ.ꢃ
ꢃ
ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–2
–4
–4
–6
–8
–8
–12
–16
–4ꢃ
–2ꢃ
ꢃ
2ꢃ
4ꢃ
6ꢃ
8ꢃ
–4ꢃ
–2ꢃ
ꢃ
4ꢃ
2ꢃ
6ꢃ
8ꢃ
–2ꢃ
ꢃ
4ꢃ
2ꢃ
–4ꢃ
6ꢃ
8ꢃ
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2754 Gꢃ4
2754 Gꢃ5
2754 Gꢃ6
INL ꢀs VREF
DNL ꢀs VREF
1.ꢃ
ꢃ.8
1.ꢃ
ꢃ.8
ꢃ.6
ꢃ.4
ꢃ.2
ꢃ.ꢃ
V
= 5V
V
= 5V
ꢂꢂ
ꢂꢂ
5V RAIGE
5V RAIGE
ꢃ.6
ꢃ.4
+ꢁIL
+ꢁIL
–ꢁIL
ꢃ.2
+ꢂIL
–ꢂIL
+ꢂIL
–ꢂIL
ꢃ.ꢃ
–ꢁIL
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–1ꢃ –8 –6
4
2
ꢃ
2
4
6
8
1ꢃ
–1ꢃ –8 –6
4
2
ꢃ
2
4
6
8
1ꢃ
V
(V)
V
(V)
REF
REF
2754 Gꢃ7
2754 Gꢃ8
Multiplying Frequency Response
ꢀs Digital Code
INL ꢀs VDD
1.ꢃ
ꢃ.8
ALL SꢁTꢀ OI
ꢃ
–2ꢃ
ꢂ15
ꢂ14
ꢂ13
ꢂ12
ꢂ11
ꢂ1ꢃ
ꢂ9
ꢃ.6
ꢃ.4
+ꢁIL
–4ꢃ
ꢃ.2
ꢂ8
ꢂ7
ꢃ.ꢃ
–6ꢃ
ꢂ6
ꢂ5
ꢂ4
ꢂ3
–ꢁIL
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–8ꢃ
ꢂ2
ꢂ1
ꢂꢃ
UIꢁPOLAR 5V OUTPUT RAIGE
LT1469 OUTPUT AMPLꢁFꢁER
FEEꢂSACK
–1ꢃꢃ
–12ꢃ
C
= 8.2pF
ALL SꢁTꢀ OFF
2.5
3
3.5
4
4.5
5
5.5
1ꢃꢃ
1k
1ꢃk
1ꢃꢃk
1M
1ꢃM
FREQUEICY (Hz)
V
(V)
ꢂꢂ
2754 Gꢃ9
2754 G1ꢃ
2754f
6
LTC2754
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LTC2754-12
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.ꢃ
ꢃ.8
1.ꢃ
ꢃ.8
V
V
= 5V
= 5V
V
V
= 5V
= 5V
ꢂꢂ
REF
1ꢃV RAIGE
ꢂꢂ
REF
1ꢃV RAIGE
ꢃ.6
ꢃ.6
ꢃ.4
ꢃ.4
ꢃ.2
ꢃ.2
ꢃ
ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
–ꢃ.2
–ꢃ.4
–ꢃ.6
–ꢃ.8
–1.ꢃ
ꢃ
1ꢃ24
2ꢃ48
3ꢃ72
4ꢃ95
ꢃ
1ꢃ24
2ꢃ48
3ꢃ72
4ꢃ95
COꢂE
COꢂE
2754 G11
2754 G12
LTC2754
Supply Current
ꢀs Logic Input Voltage
Logic Threshold
Supply Current
ꢀs Supply Voltage
ꢀs Clock Frequency
5
4
3
2
1
ꢃ
2
1ꢃꢃ
CLR, LDAC, ꢀꢂꢁ, ꢀCK,
Cꢀ/LD TꢁEꢂ TOGETHER
1.75
1.5
1.25
1
1ꢃ
RꢁꢀꢁIG
1
V
= 5V
V
ꢂꢂ
ꢃ.1
= 3V
ꢂꢂ
FALLꢁIG
ꢃ.ꢃ1
ꢃ.ꢃꢃ1
V
= 5V
ꢂꢂ
3
ꢃ.75
ꢃ.5
V
= 3V
ꢂꢂ
2
ꢃ.ꢃꢃꢃ1
ꢃ
1
4
5
2.5
3.5
4
4.5
5
5.5
3
1
1ꢃꢃ
1ꢃk
1M
1ꢃꢃM
V
(V)
ꢂꢁGꢁTAL ꢁIPUT VOLTAGE (V)
ꢀCK FREQUEICY (Hz)
ꢂꢂ
2754 G14
2754 G13
2754 G15
Settling 0V to 10V
Midscale Glitch
Midscale Glitch
CS/Lꢂ
2V/ꢂꢁV
CS/Lꢂ
5V/ꢂꢁV
CS/Lꢂ
5V/ꢂꢁV
ꢃ.26nV•s TYP
1.25nV•s TYP
GATEꢂ
ꢀETTLꢁIG
WAVEFORM
25ꢃꢄV/ꢂꢁV
V
OUT
V
5mV/ꢂꢁV
OUT
5mV/ꢂꢁV
2754 G17
2754 G17
2754 G16
5ꢃꢃns/ꢂꢁV
UꢀꢁIG LT1469 AMP
C = 12pF
FEEꢂSACK
V
V
= 5V
= 5V
5ꢃꢃns/ꢂꢁV
V
V
= 3V
REF
5ꢃꢃns/ꢂꢁV
ꢂꢂ
REF
5V RAIGE
ꢂꢂ
= 5V
5V RAIGE
LT1468 OUTPUT AMPLꢁFꢁER
= 27pF
LT1468 OUTPUT AMPLꢁFꢁER
= 27pF
ꢃV TO 1ꢃV ꢀTEP
C
C
FEEꢂSACK
FEEꢂSACK
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER
2754f
7
LTC2754
PIN FUNCTIONS
GE
(Pin1): Gain Adjust Pin for ꢂAC A. This control
Applications).Anyoralloftheseprecision-matchedresis-
torsets(EachsetcomprisingRꢁIX,RCOMX andREFX)may
be used to invert one or more positive reference voltages
to the negative voltages needed by the ꢂACs. Typically
5V; accepts up to 15V.
ADJA
pin can be used to null gain error or to compensate for
reference errors. Iominal adjustment range is 512 LꢀS
(LTC2754-16)foravoltageinputrangeof V
(i.e., 5V
RꢁIA
for a 5V reference input). Tie to ground if not used.
R
(Pin 2): ꢁnput Resistor for Reference ꢁnverting
GE
(Pin 14): Gain Adjust Pin for ꢂAC ꢂ. This control
INA
ADJD
Amplifier. The 2ꢃk input resistor is connected internally
from R to R . For normal operation tie R to the
pin can be used to null gain error or to compensate for
reference errors. Iominal adjustment range is 512 LꢀS
ꢁIA
COMA
ꢁIA
externalreferencevoltageV
Any or all of these precision-matched resistor sets (Each
set comprising R , R and REFX) may be used to
invertoneormorepositivereferencevoltagestothenega-
tive voltages needed by the ꢂACs. Typically 5V; accepts
up to 15V.
(seeTypicalApplications).
(LTC2754-16)foravoltageinputrangeof V
for a 5V reference input). Tie to ground if not used.
(i.e., 5V
REFA
RꢁIꢂ
ꢁIX COMX
R
COMD
(Pin 15): Center Tap Point for Reference Amplifier
ꢁnverting Resistors. The 2ꢃk reference inverting resistors
are connected internally from R to R and from
ꢁIꢂ
COMꢂ
R
COMꢂ
to REFꢂ, respectively (see Slock ꢂiagram). For
I
(Pin 3): ꢂAC A Current Output Complement. Tie
to ground.
normaloperationtieR
tothenegativeinputofexternal
OUT2A
COMꢂ
ꢁ
reference inverting amplifier (see Typical Applications).
OUT2A
GND (Pin 4): Ground; provides shielding for ꢁ
. Tie
REFD(Pin16):ꢁnvertedReferenceVoltageforꢂACꢂ,with
OUT2A
to ground.
internal connection to the reference inverting resistor. The
2ꢃk resistor is connected internally from REFꢂ to R
.
COMꢂ
CS/LD (Pin 5): ꢀynchronous Chip ꢀelect and Load Pin.
For normal operation tie this pin to the output of reference
invertingamplifier(seeTypicalApplications).Typically–5V;
accepts up to 15V. The impedance looking into this pin
SDI (Pin 6): ꢀerial ꢂata ꢁnput. ꢂata is clocked in on the
rising edge of the serial clock (ꢀCK) when CS/Lꢂ is low.
is 1ꢃk to ground (R and R
floating).
COMꢂ
ꢁIꢂ
SCK (Pin 7): ꢀerial Clock.
R
(Pin 17): Sipolar Offset Ietwork for ꢂAC ꢂ. This
OFSD
SRO (Pin 8): ꢀerial Readback Output. ꢂata is clocked out
on the falling edge of ꢀCK. Readback data begins clocking
out after the last address bit Aꢃ is clocked in. ꢀRO is an
active output only when the chip is selected (i.e., when
CS/Lꢂislow). OtherwiseꢀROpresentsahigh-impedance
output in order to allow other parts to control the bus.
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to 15V; for normal operation
tie to the positive reference voltage at R (Pin 13). The
impedance looking into this pin is 2ꢃk to ground.
ꢁIꢂ
R
(Pin 18): ꢂAC ꢂ Feedback Resistor. For normal
FBD
operation tie to the output of the ꢁ/V converter amplifier
for ꢂAC ꢂ (see Typical Applications). The ꢂAC output
SROGND (Pin 9): Ground pin for ꢀRO. Tie to ground.
V
(Pin10):Positiveꢀupplyꢁnput;2.7V≤V ≤5.5V.Sy-
ꢂꢂ
DD
current from ꢁ
flows through the feedback resistor
OUT1ꢂ
pass with a ꢃ.1μF low-EꢀR ceramic capacitor to ground.
to the R
pin. The impedance looking into this pin is
FSꢂ
1ꢃk to ground.
GND (Pin 11): Ground. Tie to ground.
I
(Pin 19): ꢂAC ꢂ Current Output. This pin is a
OUT1D
I
(Pin 12): ꢂAC ꢂ Current Output Complement. Tie
OUT2D
virtual ground when the ꢂAC is operating and should
reside at ꢃV. For normal operation tie to the negative
input of the ꢁ/V converter amplifier for ꢂAC ꢂ (see Typi-
cal Applications).
ꢁ
to ground.
OUT2ꢂ
RIND (Pin 13): ꢁnput Resistor for Reference ꢁnverting
Amplifier. The 2ꢃk input resistor is connected inter-
nally from RꢁIꢂ to RCOMꢂ. For normal operation tie RꢁIꢂ
to the external reference voltage VREFꢂ (see Typical
2754f
8
LTC2754
PIN FUNCTIONS
V
(Pin 20): ꢂAC ꢂ Offset Adjust Pin. This control
GE
(Pin 27): Gain Adjust Pin for ꢂAC C. This control
OSADJD
ADJC
pin can be used to null unipolar offset or bipolar zero error.
Theoffsetvoltagedeltaisinvertedandattenuatedsuchthat
pin can be used to null gain error or to compensate for
reference errors. Iominal adjustment range is 512 LꢀS
a 5V control voltage applied to V
-512 LꢀS (LTC2754-16) in any output range (assumes a
5V reference voltage at R ). Tie to ground if not used.
produces ΔV
=
(LTC2754-16)foravoltageinputrangeof V
for a 5V reference input). Tie to ground if not used.
(i.e., 5V
OꢀAꢂJꢂ
Oꢀ
RꢁIC
ꢁIꢂ
R
INC
(Pin 28): ꢁnput Resistor for Reference ꢁnverting
V
(Pin 21): ꢂAC C Offset Adjust Pin. This control
Amplifier. The 2ꢃk input resistor is connected internally
from R to R . For normal operation tie R to the
OSADJC
pincanbeusedtonullunipolaroffsetorbipolarzeroerror.
Theoffsetvoltagedeltaisinvertedandattenuatedsuchthat
ꢁIC
COMC
ꢁIC
external reference voltage V
(see Typical Applica-
REFC
a 5V control voltage applied to V
-512 LꢀS (LTC2754-16) in any output range (assumes a
5V reference voltage at R ). Tie to ground if not used.
produces ΔV
=
tions). Any or all of these precision-matched resistor
sets (Each set comprising R , R and R ) may be
OꢀAꢂJC
Oꢀ
ꢁIX COMX
EFX
used to invert one or more positive reference voltages to
the negative voltages needed by the ꢂACs. Typically 5V;
accepts up to 15V.
ꢁIC
I
(Pin 22): ꢂAC C Current Output. This pin is a virtual
OUT1C
ground when the ꢂAC is operating and should reside at
ꢃV. For normal operation tie to the negative input of the ꢁ/V
converter amplifier for ꢂAC C (see Typical Applications).
I
ꢁ
(Pin 29): ꢂAC C Current Output Complement. Tie
to ground.
OUT2C
OUT2C
R
(Pin 23): ꢂAC C Feedback Resistor. For normal
CLR (Pin 30): Asynchronous Clear Pin. When this pin is
low, all ꢂAC registers (both code and span) are cleared to
zero. All ꢂAC outputs are cleared to zero volts.
FBC
operation tie to the output of the ꢁ/V converter amplifier
for ꢂAC C (see Typical Applications). The ꢂAC output
current from ꢁ
flows through the feedback resistor
OUT1ꢂ
RFLAG (Pin 31): Reset Flag Pin. An active low output is
asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
to the R
pin. The impedance looking into this pin is
FSC
1ꢃk to ground.
R
(Pin 24): Sipolar Offset Ietwork for ꢂAC C. This
OFSC
M-SPAN (Pin 32): Manual ꢀpan Control Pin. M-ꢀPAI is
used in conjunction with pins ꢀ2, ꢀ1 and ꢀꢃ (Pins 33, 34
and 35) to configure all ꢂACs for operation in a single,
fixed output range.
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to 15V; for normal operation
tie to the positive reference voltage at R (Pin 28). The
ꢁIC
impedance looking into this pin is 2ꢃk to ground.
To configure the part for manual-span use, tie M-ꢀPAI
REFC(Pin25):ꢁnvertedReferenceVoltageforꢂACC, with
directly to V . The active output range is then set via
ꢂꢂ
internal connection to the reference inverting resistor. The
hardware pin strapping of pins ꢀ2, ꢀ1 and ꢀꢃ (rather than
through the ꢀPꢁ port); and Write and Update commands
have no effect on the active output span.
2ꢃk resistor is connected internally from REFC to R
.
COMC
For normal operation tie this pin to the output of reference
invertingamplifier(seeTypicalApplications).Typically–5V;
accepts up to 15V. The impedance looking into this pin
To configure the part for ꢀoftꢀpan use, tie M-ꢀPAI di-
rectly to GIꢂ. The output ranges are then individually and
dynamically controllable through the ꢀPꢁ port; and pins
ꢀ2, ꢀ1 and ꢀꢃ have no effect.
is 1ꢃk to ground (R and R
floating).
COMC
ꢁIC
R
(Pin 26): Center Tap Point for Reference Amplifier
COMC
ꢁnverting Resistors. The 2ꢃk reference inverting resistors
are connected internally from R to R and from
ꢀee ‘Manual ꢀpan Configuration’ in the Operation sec-
tion. M-ꢀPAI must be connected either directly to
ꢁIC
COMC
R
to REFC, respectively (see Slock ꢂiagram). For
COMC
GIꢂ (ꢀoftꢀpan configuration) or to V (manual-span
normaloperationtieR
tothenegativeinputofexternal
ꢂꢂ
COMC
configuration).
reference inverting amplifier (see Typical Applications).
2754f
9
LTC2754
PIN FUNCTIONS
S0 (Pin 33): ꢀpan Sit ꢃ. ꢁn Manual ꢀpan mode (M-ꢀPAI
2ꢃk resistor is connected internally from REFS to R
.
COMS
tied to V ), Pins ꢀꢃ, ꢀ1 and ꢀ2 are pin-strapped to select
For normal operation tie this pin to the output of reference
invertingamplifier(seeTypicalApplications).Typically–5V;
accepts up to 15V. The impedance looking into this pin
ꢂꢂ
a single fixed output range for all ꢂACs. These pins should
be tied to either GIꢂ or V even if they are unused.
ꢂꢂ
is 1ꢃk to ground (R and R
floating).
COMS
ꢁIS
S1 (Pin 34): ꢀpan Sit 1. ꢁn Manual ꢀpan mode (M-ꢀPAI
tied to V ), Pins ꢀꢃ, ꢀ1 and ꢀ2 are pin-strapped to select
R
(Pin 43): Sipolar Offset Ietwork for ꢂAC S. This
OFSB
ꢂꢂ
a single fixed output range for all ꢂACs. These pins should
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to 15V; for normal operation
be tied to either GIꢂ or V even if they are unused.
ꢂꢂ
tie to the positive reference voltage at R (Pin 39). The
impedance looking into this pin is 2ꢃk to ground.
ꢁIS
S2 (Pin 35): ꢀpan Sit 2. ꢁn Manual ꢀpan mode (M-ꢀPAI
tied to V ), Pins ꢀꢃ, ꢀ1 and ꢀ2 are pin-strapped to select
ꢂꢂ
a single fixed output range for all ꢂACs. These pins should
R
(Pin 44): ꢂAC S Feedback Resistor. For normal
FBB
be tied to either GIꢂ or V even if they are unused.
operation tie to the output of the ꢁ/V converter amplifier
for ꢂAC S (see Typical Applications). The ꢂAC output
ꢂꢂ
LDAC (Pin 36): Asynchronous ꢂAC Load ꢁnput. When
LDAC is a logic low, all ꢂACs are updated (CS/Lꢂ must
be high).
current from ꢁ
flows through the feedback resistor
OUT1S
to the R
pin. The impedance looking into this pin is
FSS
1ꢃk to ground.
GND (Pin 37): Ground; provides shielding for ꢁ
to ground.
. Tie
OUT2S
I
(Pin 45): ꢂAC S Current Output. This pin is a virtual
OUT1B
ground when the ꢂAC is operating and should reside at
ꢃV. For normal operation tie to the negative input of the ꢁ/V
converter amplifier for ꢂAC S (see Typical Applications).
I
ꢁ
(Pin 38): ꢂAC S Current Output Complement. Tie
to ground.
OUT2B
OUT2S
R
(Pin 39): ꢁnput Resistor for Reference ꢁnverting
V
(Pin 46): ꢂAC S Offset Adjust Pin. This control
INB
OSADJB
Amplifier. The 2ꢃk input resistor is connected internally
pincanbeusedtonullunipolaroffsetorbipolarzeroerror.
Theoffset-voltagedeltaisinvertedandattenuatedsuchthat
from R to R
external reference voltage V
tions). Any or all of these precision-matched resistor sets
(Each set comprising R , R and REFX) may be
used to invert one or more positive reference voltages to
the negative voltages needed by the ꢂACs. Typically 5V;
accepts up to 15V.
. For normal operation tie R to the
ꢁIS
ꢁIS
COMS
(see Typical Applica-
a 5V control voltage applied to V
produces ΔV
=
REFS
OꢀAꢂJS
Oꢀ
–512 LꢀS (LTC2754-16) in any output range (assumes a
5V reference voltage at R ). Tie to ground if not used.
ꢁIX
COMX
ꢁIS
V
(Pin 47): ꢂAC A Offset Adjust Pin. This control
OSADJA
pincanbeusedtonullunipolaroffsetorbipolarzeroerror.
Theoffset-voltagedeltaisinvertedandattenuatedsuchthat
GE
(Pin 40): Gain Adjust Pin for ꢂAC S. This control
a 5V control voltage applied to V
produces ΔV
=
ADJB
OꢀAꢂJA
Oꢀ
pin can be used to null gain error or to compensate for
reference errors. Iominal adjustment range is 512 LꢀS
–512 LꢀS (LTC2754-16) in any output range (assumes a
5V reference voltage at R ). Tie to ground if not used.
ꢁIA
(LTC2754-16)foravoltageinputrangeof V
for a 5V reference input). Tie to ground if not used.
(i.e., 5V
RꢁIS
I
(Pin 48): ꢂAC A Current Output. This pin is a virtual
OUT1A
ground when the ꢂAC is operating and should reside at
ꢃV. For normal operation tie to the negative input of the ꢁ/V
converter amplifier for ꢂAC A (see Typical Applications).
R
(Pin 41): Center Tap Point for Reference Amplifier
COMB
ꢁnverting Resistors. The 2ꢃk reference inverting resistors
are connected internally from R to R and from
ꢁIS
COMS
R
(Pin 49): ꢂAC A Feedback Resistor. For normal
FBA
R
to REFS, respectively (see Slock ꢂiagram). For
COMS
operation tie to the output of the ꢁ/V converter amplifier
for ꢂAC A (see Typical Applications). The ꢂAC output
normaloperationtieR
tothenegativeinputofexternal
COMS
reference inverting amplifier (see Typical Applications).
current from ꢁ
flows through the feedback resistor
OUT1A
REFB(Pin42):ꢁnvertedReferenceVoltageforꢂACS, with
internal connection to the reference inverting resistor. The
to the R
pin. The impedance looking into this pin is
FSA
1ꢃk to ground.
2754f
10
LTC2754
PIN FUNCTIONS
R
(Pin 50): Sipolar Offset Ietwork for ꢂAC A. This
accepts up to 15V. The impedance looking into this pin
OFSA
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to 15V; for normal operation
is 1ꢃk to ground (R and R
floating).
COMA
ꢁIA
R
(Pin 52): Center Tap Point for Reference Amplifier
COMA
tie to the positive reference voltage at R (Pin 2). The
impedance looking into this pin is 2ꢃk to ground.
ꢁIA
ꢁnverting Resistors. The 2ꢃk reference inverting resistors
are connected internally from R to R and from
ꢁIA
COMA
REFA(Pin51):ꢁnvertedReferenceVoltageforꢂACA, with
R
to REFA, respectively (see Slock ꢂiagram). For
COMA
internal connection to the reference inverting resistor. The
normaloperationtieR
tothenegativeinputofexternal
COMA
2ꢃk resistor is connected internally from REFA to R
.
reference inverting amplifier (see Typical Applications).
COMA
For normal operation tie this pin to the output of reference
invertingamplifier(seeTypicalApplications).Typically–5V;
Exposed Pad (Pin 53): Ground. The Exposed Pad must
be soldered to the PCS.
BLOCK DIAGRAM
V
ꢂꢂ
10
R
R
ꢁIS
2
1
39
40
41
ꢁIA
2.56M
2.56M
GE
R
GE
R
2ꢃk
2ꢃk
2ꢃk
2ꢃk
AꢂJA
AꢂJS
52
COMA
COMS
LTC2754-16
REFA
REFS
51
50
49
48
42
43
44
45
R
OFꢀA
R
R
ꢁ
OFꢀS
FSS
ꢂATA REGꢁꢀTERꢀ
ꢂATA REGꢁꢀTERꢀ
16
3
16
3
R
FSA
ꢂAC REG ꢁIPUT REG
ꢁIPUT REG ꢂAC REG
ꢂAC A
16-SꢁT WꢁTH
ꢀPAI ꢀELECT
ꢂAC S
16-SꢁT WꢁTH
ꢀPAI ꢀELECT
ꢁ
ꢁ
OUT1A
OUT2A
OUT1S
OUT2S
ꢀPAI REGꢁꢀTERꢀ
ꢀPAI REGꢁꢀTERꢀ
ꢁ
3
38
ꢂAC REG ꢁIPUT REG
ꢁIPUT REG ꢂAC REG
V
V
V
V
47
20
46
21
OꢀAꢂJA
OꢀAꢂJS
OꢀAꢂJC
OꢀAꢂJꢂ
ꢂATA REGꢁꢀTERꢀ
ꢂATA REGꢁꢀTERꢀ
16
3
16
3
ꢂAC REG ꢁIPUT REG
ꢁIPUT REG ꢂAC REG
ꢂAC ꢂ
16-SꢁT WꢁTH
ꢀPAI ꢀELECT
ꢂAC C
16-SꢁT WꢁTH
ꢀPAI ꢀELECT
ꢁ
ꢁ
12
19
29
22
OUT2ꢂ
OUT2C
OUT1C
ꢀPAI REGꢁꢀTERꢀ
ꢀPAI REGꢁꢀTERꢀ
ꢁ
ꢁ
OUT1ꢂ
ꢂAC REG ꢁIPUT REG
ꢁIPUT REG ꢂAC REG
R
R
R
18
17
16
23
24
25
FSꢂ
FSC
R
OFꢀꢂ
OFꢀC
REFꢂ
REFC
POWER-OI
REꢀET
2ꢃk
2ꢃk
2ꢃk
2ꢃk
R
R
15
14
13
26
27
28
COMꢂ
COMC
2.56M
2.56M
GE
AꢂJꢂ
GE
R
AꢂJC
COITROL AIꢂ REAꢂSACK LOGꢁC
R
ꢁIꢂ
ꢁIC
4, 11, 37
GIꢂ
32
35 34 33
31
30
5
6
7
36
8
9
2754 Sꢂ
M-ꢀPAI ꢀ2 ꢀ1 ꢀꢃ
RFLAG
CLR
CS/Lꢂ ꢀꢂꢁ ꢀCK LDAC ꢀRO
ꢀROGIꢂ
2754f
11
LTC2754
TIMING DIAGRAMS
t
1
t
6
t
t
t
4
2
3
1
2
31
32
ꢀCK
ꢀꢂꢁ
t
8
LꢀS
t
t
7
5
CS/Lꢂ
LDAC
ꢀRO
t
11
t
9
Hi-Z
LꢀS
2754 Tꢂ
OPERATION
Output Ranges
V
V
ꢂꢂ
ꢂꢂ
The LTC2754 is a quad, current-output, serial-input preci-
sionmultiplyingꢂACwithselectableoutputranges.Ranges
can either be programmed in software for maximum
flexibility—each of the four ꢂACs can be programmed
to any one of six output ranges—or hardwired through
pin-strapping. Two unipolar ranges are available (ꢃV to 5V
and ꢃV to 1ꢃV), and four bipolar ranges ( 2.5V, 5V, 1ꢃV
and –2.5V to 7.5V). These ranges are obtained when an
external precision 5V reference is used. When a reference
voltage of 2V is used, the ranges become: ꢃV to 2V, ꢃV to
4V, 1V, 2V, 4V and –1V to 3V. The output ranges are
linearly scaled for other reference voltages.
LTC2754-16
–
+
ꢂAC A
1ꢃV
M-ꢀPAI
ꢀ2
ꢀ1
–
+
ꢂAC S
ꢂAC C
ꢂAC ꢂ
1ꢃV
1ꢃV
1ꢃV
ꢀꢃ
–
+
–
+
CS/Lꢂ ꢀꢂꢁ ꢀCK
Manual Span Configuration
2754 Fꢃ1
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2754 to operate in a single span
without additional operational overhead, tie the M-ꢀPAI
Figure 1. Using M-SPAN to Configure the LTC2754
for Single-Span Operation ( 10V Range Shown).
pin directly to V . The active output range for all four
ꢂꢂ
ꢂACs is then set via hardware pin strapping of pins ꢀ2,
ꢀ1 and ꢀꢃ (rather than through the ꢀPꢁ port); and Write
and Update commands have no effect on the active output
span. ꢀee Figure 1 and Table 3.
Tie the M-ꢀPAI pin to ground for normal ꢀoftꢀpan
operation.
2754f
12
LTC2754
OPERATION
Input and DAC Registers
data begins. For a 24-bit input sequence, the 16 readback
bits are shifted out on the falling edges of clocks 8-23,
suitable for shifting into a microprocessor on the rising
edges of clocks 9-24. For a 32-bit sequence, the bits are
shifted out on clocks 16-31; see Figure 3b.
The LTC2754 has 5 internal registers for each ꢂAC, a total
of 2ꢃ registers (see Slock ꢂiagram). Each ꢂAC channel
has two sets of double-buffered registers—one set for the
code data, and one for the output range of the ꢂAC—plus
one readback register. ꢂouble buffering provides the ca-
pability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. ꢁt also permits the simultaneous
updating of multiple ꢂACs.
WhenCS/Lꢂishigh,theꢀROpinpresentsahighimpedance
(three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all ꢂACs are updated with code and span data
(data in the ꢁnput buffers is copied into the ꢂAC buffers).
CS/Lꢂ must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All ꢂACs”
serial input command.
Each set of double-buffered registers comprises an ꢁnput
register and a ꢂAC register.
ꢁnput register: The Write operation shifts data from the
ꢀꢂꢁ pin into a chosen ꢁnput register. The ꢁnput registers
are holding buffers; Write operations do not affect the
ꢂAC outputs.
The codes for the command word (C3-Cꢃ) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-Aꢃ).
ꢂAC register: The Update operation copies the contents
of an ꢁnput register to its associated ꢂAC register. The
contents of a ꢂAC register directly updates the associated
ꢂAC output voltage or output range.
Readback
ꢁn addition to the ꢁnput and ꢂAC registers, each ꢂAC has
one Readback register associated with it. When a Read
command is issued to a ꢂAC, the contents of one of its
four buffers (ꢁnput and ꢂAC registers for each of ꢀpan
and Code) is copied into its Readback register and seri-
ally shifted out through the ꢀRO pin. Figure 3 shows the
loading and readback sequences.
Iote that updates always include both ꢂata and ꢀpan
registers; but the values held in the ꢂAC registers will
only change if the associated ꢁnput register values have
previously been changed via a Write operation.
Serial Interface
ꢁnthedatafield(ꢂ15-ꢂꢃ)ofanynon-readinstructioncycle,
ꢀROshiftsoutthecontentsofthebufferthatwasspecified
intheprecedingcommand.This“rollingreadback”default
mode of operation can dramatically reduce the number
of instruction cycles needed, since any command can be
verified during succeeding commands with no additional
overhead. ꢀeeFigure4. Table1showsthestoragelocation
(‘readback pointer’) of the data which will be output from
ꢀRO during the next instruction.
When the CS/Lꢂ pin is taken low, the data on the ꢀꢂꢁ
pin is loaded into the shift register on the rising edge of
the clock (ꢀCK pin). The minimum (24-bit wide) loading
sequence required for the LTC2754 is a 4-bit command
word (C3 C2 C1 Cꢃ), followed by a 4-bit address word
(A3 A2 A1 Aꢃ) and 16 data (span or code) bits, MꢀS first.
Figure 2 shows the ꢀꢂꢁ input word syntax to use when
writing code or span. ꢁf a 32-bit input sequence is used,
the first eight bits must be zeros, followed by the same
sequence as for a 24-bit wide input. Figure 3 shows the
input and readback sequences for both 24-bit and 32-bit
operations.
ForReadcommands,thedataisshiftedoutduringtheRead
instruction itself (on the 16 falling ꢀCK edges immediately
afterthelastaddressbitisshiftedinonꢀꢂꢁ).Whenchecking
the span of a ꢂAC using ꢀRO, the span bits are the last
four bits shifted out, corresponding to their sequence and
positions when writing a span. ꢀee Figure 3.
When CS/Lꢂ is low, the ꢀRO pin (ꢀerial Readback Output)
is an active output.The readback data begins after the
command (C3-Cꢃ) and address (A3-Aꢃ) words have been
shiftedintoꢀꢂꢁ.ꢀROoutputsalogiclowuntilthereadback
2754f
13
LTC2754
OPERATION
Table 1. Command Codes
CODE
READBACK POINTER–
CURRENT INPUT WORD W
READBACK POINTER–
NEXT INPUT WORD W
C3
C2
C1
C0
COMMAND
0
+1
ꢃ
ꢃ
1
ꢃ
Write ꢀpan ꢂAC n
Write Code ꢂAC n
Update ꢂAC n
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢁnput ꢀpan Register ꢂAC n
ꢁnput Code Register ꢂAC n
ꢂAC ꢀpan Register ꢂAC n
ꢂAC Code Register ꢂAC A
ꢂAC ꢀpan Register ꢂAC n
ꢃ
ꢃ
1
1
ꢃ
1
ꢃ
ꢃ
ꢃ
1
ꢃ
1
Update All ꢂACs
ꢃ
1
1
ꢃ
Write ꢀpan ꢂAC n
Update ꢂAC n
ꢃ
1
1
1
ꢃ
ꢃ
1
ꢃ
ꢃ
1
ꢃ
1
Write Code ꢂAC n
Update ꢂAC n
ꢀet by Previous Command
ꢀet by Previous Command
ꢀet by Previous Command
ꢂAC Code Register ꢂAC n
ꢂAC ꢀpan Register ꢂAC n
ꢂAC Code Register ꢂAC n
Write ꢀpan ꢂAC n
Update All ꢂACs
Write Code ꢂAC n
Update All ꢂACs
1
1
1
1
1
ꢃ
ꢃ
1
1
1
1
1
ꢃ
ꢃ
1
ꢃ
1
ꢃ
1
1
Read ꢁnput ꢀpan Register ꢂAC n
Read ꢁnput Code Register ꢂAC n
Read ꢂAC ꢀpan Register ꢂAC n
Read ꢂAC Code Register ꢂAC n
Io Operation
ꢁnput ꢀpan Register ꢂAC n
ꢁnput Code Register ꢂAC n
ꢂAC ꢀpan Register ꢂAC n
ꢂAC Code Register ꢂAC n
ꢀet by Previous Command
ꢂAC Code Register ꢂAC n
ꢂAC ꢀpan Register ꢂAC A
ꢂAC ꢀpan Register ꢂAC A
–
–
ꢀystem Clear
–
–
ꢁnitial Power-Up or Power ꢁnterupt
Codes not shown are reserved–do not use
Table 2. Address Codes
Table 3. Span Codes
A3
ꢃ
A2
ꢃ
A1
ꢃ
A0
×
n
ꢂAC A
S3 S2 S1 S0 SPAN
ꢃ
ꢃ
ꢃ
ꢃ
1
1
ꢃ
ꢃ
1
1
ꢃ
ꢃ
ꢃ
1
ꢃ
1
ꢃ
1
Unipolar ꢃV to 5V
×
×
×
×
×
×
ꢃ
ꢃ
1
ꢂAC S
Unipolar ꢃV to 1ꢃV
Sipolar –5V to 5V
×
ꢃ
1
ꢃ
ꢂAC C
×
ꢃ
1
1
ꢂAC ꢂ
Sipolar –1ꢃV to 1ꢃV
Sipolar –2.5V to 2.5V
Sipolar –2.5V to 7.5V
×
1
1
1
All ꢂACs (Iote 1)
×
Codes not shown are reserved–do not use.
Note 1. ꢁf readback is taken using the All ꢂACs address, the LTC2754
defaults to ꢂAC A.
× = ꢂon’t Care.
Codes not shown are reserved–do not use.
× = ꢂon’t Care.
2754f
14
LTC2754
OPERATION
Readback in M-Span Configuration
2. Using a 32-bit load sequence, load ꢂAC C with bipolar
2.5V and its output at zero volts. Use readback to check
ꢁnput register contents before updating the ꢂAC output
(i.e., before copying ꢁnput register contents into ꢂAC
register).
ꢁf the part is in M-ꢀpan configuration and a ꢂAC ꢀpan
register is specified for readback, then the data shifted out
of ꢀRO will reflect the actual active span. The hardware-
configured output range is therefore software detectable
and available for use in programming.
a) CS/Lꢂ↓ (Iote that after power-on, the code in
ꢁnput register is zero)
Examples
Clock ꢀꢂꢁ = ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃ11 ꢃ1ꢃꢃ 1ꢃꢃꢃ ꢃꢃꢃꢃ
ꢃꢃꢃꢃ ꢃꢃꢃꢃ
1. Using a 24-bit instruction, load ꢂAC A with the unipolar
range of ꢃV to 1ꢃV, output at zero volts and all other ꢂACs
with the bipolar range of 1ꢃV, outputs at zero volts. Iote
all ꢂAC outputs should change at the same time.
b) CS/Lꢂ↑
ꢁnput register- Code of ꢂAC C set to midscale
setting.
a) CS/Lꢂ↓
c) CS/Lꢂ↓
Clock ꢀꢂꢁ = ꢃꢃ1ꢃ 1111 ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃ11
Clock ꢀꢂꢁ = ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃ1ꢃ ꢃ1ꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ
ꢃꢃꢃꢃ ꢃ1ꢃꢃ
b) CS/Lꢂ↑
ꢂata out on ꢀRO = 1ꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ Verifies
that ꢁnput register- Code ꢂAC C is at midscale
setting.
ꢁnput register- Range of all ꢂACs set to bipolar
1ꢃV.
c) CS/Lꢂ↓
d) CS/Lꢂ↑
Clock ꢀꢂꢁ = ꢃꢃ1ꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃ1
ꢁnput register- Range of ꢂAC C set to Sipolar
2.5V range.
d) CS/Lꢂ↑
ꢁnput register- Range of ꢂAC A set to unipolar ꢃV
to 1ꢃV.
e) CS/Lꢂ↓
Clock ꢀꢂꢁ = ꢃꢃꢃꢃ ꢃꢃꢃꢃ 1ꢃ1ꢃ ꢃ1ꢃꢃ xxxx xxxx
xxxx xxxx
e) CS/Lꢂ↓
Clock ꢀꢂꢁ = ꢃꢃ11 1111 1ꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ
ꢂata Out on ꢀRO = ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃ1ꢃꢃ
Verifies that ꢁnput register- range of ꢂAC C set to
Sipolar 2.5V Range.
f) CS/Lꢂ↑
ꢁnput register- Code of all ꢂACs set to midscale.
CS/Lꢂ↑
g) CS/Lꢂ↓
f) CS/Lꢂ↓
Clock ꢀꢂꢁ = ꢃꢃ11 ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃꢃꢃꢃ
Clock ꢀꢂꢁ = ꢃꢃꢃꢃ ꢃꢃꢃꢃ ꢃ1ꢃꢃ ꢃ1ꢃꢃ xxxx xxxx
xxxx xxxx
h) CS/Lꢂ↑
ꢁnput register- Code of ꢂAC A set to zero code.
g) CS/Lꢂ↑
i) CS/Lꢂ↓
Update ꢂAC C for both Code and Range
Clock ꢀꢂꢁ = ꢃ1ꢃꢃ 1111 XXXX XXXX XXXX XXXX
h) Alternatively steps f and g could be replaced with
j) CS/Lꢂ↑
LDAC
.
Update all ꢂACs for both Code and Range.
k) Alternatively steps i and j could be replaced with
LDAC
.
2754f
15
LTC2754
OPERATION
System Offset and Reference Adjustments
The V
pins have an input impedance of 1.28MΩ.
OꢀAꢂJX
These pins should be driven with a Thevenin-equivalent
impedance of 1ꢃk or less to preserve the settling
performance of the LTC2754. They should be shorted to
GIꢂ if not used.
The LTC2754 has individual offset- and gain- adjust pins
(V
and GE
, respectively) for each of its four
OꢀAꢂJX
AꢂJX
ꢂACs.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2754, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
TheGE
pinshaveaninputimpedanceof2.56MΩ, and
AꢂJX
are intended for use with fixed reference voltages only.
TheyshouldbeshortedtoGIꢂifnotused. ꢁfthereference
inverting resistors are not used for that channel, then
GE
, R
and R should all be shorted to REFX.
AꢂJX COMX ꢁIX
The offset adjust pins V
can be used to null
OꢀAꢂJX
unipolar offset or bipolar zero error. The offset-voltage
delta is inverted and attenuated such that a 5V control
Power-On Reset and Clear
When power is first applied to the LTC2754, all ꢂACs
power-up in unipolar 5V mode (ꢀ3 ꢀ2 ꢀ1 ꢀꢃ = ꢃꢃꢃꢃ). All
internal ꢂAC registers are reset to ꢃ and the ꢂAC outputs
initialize to zero volts.
voltage applied to V
produces ΔV = –512 LꢀS
OꢀAꢂJX
Oꢀ
(LTC2754-16) in any output range (assumes a 5V refer-
ence voltage at R ).
ꢁIX
ꢁn voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
ꢁf the part is configured for manual span operation, all four
ꢂACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
ΔV = –(1/128)V
[ꢃV to 5V, 2.5V spansꢅ
Oꢀ
OꢀAꢂJX
OꢀAꢂJX
ΔV = –(1/64)V
[ꢃV to 1ꢃV, 5V, –2.5V to 7.5V
Oꢀ
spansꢅ
When the CLR pin is taken low, a system clear results.
The ꢂAC buffers are reset to ꢃ and the ꢂAC outputs are
all reset to zero volts. The ꢁnput buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed ꢂACs to their respective
previous states.
ΔV = –(1/32)V
[ 1ꢃV spanꢅ
Oꢀ
OꢀAꢂJX
The gain error adjust pins GE
can be used to null
AꢂJX
gain error or to compensate for reference errors. Iominal
adjustment range is 512 LꢀS (LTC2754-16) for a volt-
age input range of V
(i.e., 5V for a 5V reference
RꢁIX
ꢁf CLR is asserted during an instruction, i.e., when CS/Lꢂ
is low, the instruction is aborted. ꢁntegrity of the relevant
ꢁnput buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
input). The gain-error delta is non-inverting for positive
reference voltages.
Iote that these pins compensate the gain by altering the
invertedreferencevoltageV
.ꢁnvoltageterms,theV
REFX
REFX
delta is inverted and attenuated by a factor of 128.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
ΔV = –(1/128)GE
REFX
AꢂJX
at power-up, system clear, or if the supply V dips below
ꢂꢂ
The nominal input range of these pins is 5V; other volt-
ages of up to 15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the performance of which the part is capable.
approximately2V;andstaysasserteduntilanyvalidUpdate
command is executed.
2754f
16
LTC2754
OPERATION
2754f
17
LTC2754
OPERATION
2754f
18
LTC2754
OPERATION
WRꢁTE ꢂATA
ꢂAC A
WRꢁTE ꢂATA
ꢂAC S
WRꢁTE ꢂATA
ꢂAC C
WRꢁTE ꢂATA
ꢂAC ꢂ
UPꢂATE
ALL ꢂACs
...
ꢀꢂꢁ
REAꢂ
REAꢂ
REAꢂ
REAꢂ
REAꢂ
...
ꢀRO
ꢁIPUT ꢂATA
ꢁIPUT ꢂATA
ꢁIPUT ꢂATA
ꢁIPUT ꢂATA
ꢂAC ꢂATA
REGꢁꢀTER ꢂAC A
REGꢁꢀTER ꢂAC S
REGꢁꢀTER ꢂAC C
REGꢁꢀTER ꢂAC ꢂ
REGꢁꢀTER ꢂAC A
2754 Fꢃ4
Figure 4. Rolling Readback
2754f
19
LTC2754
APPLICATIONS INFORMATION
Op Amp Selection
in 16-bit LꢀSs. ꢂivide these results by 16 to obtain the
correct LꢀS sizing.
Secause of the extremely high accuracy of the 16-bit
LTC2754-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
ꢁIL and ꢂIL to op amp offset has been greatly reduced
compared to previous generations of multiplying ꢂACs.
Table 6 contains a partial list of LTC precision op amps
recommended for use with the LTC2754. The easy-to-use
designequationssimplifytheselectionofopampstomeet
Table 4. Coefficients for the Equations in Table 5
OUTPUT RANGE
A1
1.1
2.2
2
A2
2
A3
1
A4
A5
1
Tables 4 and 5 contain equations for evaluating the effects
of op amp parameters on the LTC2754’s accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the ꢁIL, ꢂIL,
unipolaroffset,unipolargainerror,bipolarzeroandbipolar
gain error. Tables 4 and 5 can also be used to determine
the effects of op amp parameters on the LTC2754-12.
However, the results obtained from Tables 4 and 5 are
5V
1ꢃV
3
ꢃ.5
1
1.5
1.5
2.5
1
5V
2
1
1
1ꢃV
4
4
ꢃ.83
1.4
ꢃ.7
2.5V
1
1
1
–2.5V to 7.5V
1.9
3
ꢃ.5
1.5
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inꢀerting Amp.
UNIPOLAR
OFFSET (LSB)
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
BIPOLAR GAIN
ERROR (LSB)
OP AMP
INL (LSB)
DNL (LSB)
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
REF
V
(mV)
V
• 3.2 •
V
• ꢃ.82 •
A3 • V
• 13.2 •
A3 • V
• 19.8 •
V
• 13.2 •
V
• 13.2 •
Oꢀ1
)
)
)
)
)
)
)
)
(V
(V
(V
(V
(V
(V
Oꢀ1
Oꢀ1
Oꢀ1
Oꢀ1
Oꢀ1
Oꢀ1
5V
5V
5V
5V
5V
5V
ꢁ
(nA)
ꢁ
• ꢃ.ꢃꢃꢃ3 •
ꢁ
• ꢃ.ꢃꢃꢃꢃ8 •
ꢁ
• ꢃ.13 •
ꢁ
S1
• ꢃ.13 •
ꢃ
ꢁ
• ꢃ.ꢃꢃ18 •
ꢁ
• ꢃ.ꢃꢃ18 •
(V
(V
S1
S1
S1
S1
S1
S1
)
(V
(V
(V
(V
)
)
)
REF
REF
REF
REF
REF
REF
( 16.5k)
1.5k
VOL1
131k
VOL1
131k
VOL1
A
VOL1
(V/V)
(mV)
A1 •
A2 •
ꢃ
ꢃ
ꢃ
ꢃ
A5 •
A5 •
)
A
(A
)
)
(A
(A
VOL1
5V
5V
5V
V
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
A4 • V
• 13.1 •
V
• 26.2 •
V
• 26.2 •
Oꢀ2
Oꢀ2
Oꢀ2
Oꢀ2
(V
)
(V
(V
(
))
))
)
REF
REF
REF
5V
5V
REF
5V
REF
ꢁ
(mV)
A4 • ꢁ • ꢃ.13 •
ꢁ
• ꢃ.26 •
ꢁ
S2
• ꢃ.26 •
131k
S2
S2
S2
(
(V
REF
(V
)
)
(V
66k
VOL2
131k
(A
A
VOL2
(V/V)
A4 •
(A
)
(A
)
)
VOL2
VOL2
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2754 with Releꢀant Specifications
AMPLIFIER SPECIFICATIONS
t
VOLTAGE CURRENT
SLEW
RATE
V/μs
GAIN BANDWIDTH
PRODUCT
MHz
POWER
SETTLING
V
I
A
VOL
NOISE
NOISE
with LTC2755 DISSIPATION
OS
B
AMPLIFIER
LT1ꢃꢃ1
μV
nA
V/mV
nV/√Hz
pA/√Hz
μs
12ꢃ
12ꢃ
115
19
mW
46
25
2
8ꢃꢃ
1ꢃ
14
14
2.7
5
ꢃ.12
ꢃ.ꢃꢃ8
ꢃ.ꢃꢃ8
ꢃ.3
ꢃ.25
ꢃ.2
ꢃ.16
4.5
22
ꢃ.8
ꢃ.7
ꢃ.75
12.5
9ꢃ
LT1ꢃ97
5ꢃ
ꢃ.35
ꢃ.25
2ꢃ
1ꢃꢃꢃ
15ꢃꢃ
4ꢃꢃꢃ
5ꢃꢃꢃ
2ꢃꢃꢃ
11
LT1112 (ꢂual)
LT1124 (ꢂual)
LT1468
6ꢃ
1ꢃ.5/Op Amp
69/Op Amp
117
7ꢃ
75
1ꢃ
ꢃ.6
2
LT1469 (ꢂual)
125
1ꢃ
5
ꢃ.6
22
9ꢃ
2
123/Op Amp
2754f
20
LTC2754
APPLICATIONS INFORMATION
the system’s specified error budget. ꢀelect the amplifier
from Table 6 and insert the specified op amp parameters
in Table 5. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part.Arithmeticsummationgivesan(unlikely)worst-case
effect. A root-sum-square (RMꢀ) summation produces a
more realistic estimate.
applications:outputvoltageinitialtolerance,outputvoltage
temperature coefficient and output voltage noise.
ꢁnitial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
( ꢃ.ꢃ50),minimizesthegainerrorcausedbythereference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on ꢁIL and ꢂIL. For
example, for the LTC2754-16 with a 5V reference in 5V
unipolar mode, a 25ꢃꢄV op amp offset will cause a 3.3LꢀS
zero-scale error and a 3.3LꢀS gain error; but only ꢃ.8LꢀS
of ꢁIL degradation and ꢃ.2LꢀS of ꢂIL degradation.
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s apparent ꢁIL and ꢂIL performance. ꢁf a refer-
ence is chosen with a loose output voltage temperature
coefficient, then the ꢂAC output voltage along its transfer
characteristicwillbeverydependentonambientconditions.
Minimizing the error due to reference temperature coef-
ficient can be achieved by choosing a precision reference
with a low output voltage temperature coefficient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, con-
sult an op amp’s data sheet to find the worst-case V
Oꢀ
and ꢁ over temperature. Then, plug these numbers into
S
the V and ꢁ equations from Table 5 and calculate the
Oꢀ
S
temperature-induced effects.
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2754 with Releꢀant Specifications
For applications where fast settling time is important, Ap-
plicationNote74,“ComponentandMeasurementAdvances
Ensure16-BitDACSettlingTime,”offersathoroughdiscus-
sion of 16-bit DAC settling time and op amp selection.
INITIAL
TOLERANCE
TEMPERATURE 0.1Hz to 10Hz
REFERENCE
DRIFT
NOISE
LT1ꢃ19A-5,
LT1ꢃ19A-1ꢃ
ꢃ.ꢃ50
ꢃ.ꢃ50
ꢃ.ꢃ750
5ppm/°C
12ꢄV
P-P
LT1236A-5,
LT1236A-1ꢃ
5ppm/°C
3ꢄV
P-P
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2754 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2754
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a ꢂAC output volt-
age error.
LT146ꢃA-5,
LT146ꢃA-1ꢃ
1ꢃppm/°C
2ꢃꢄV
12ꢄV
P-P
LT179ꢃA-2.5
ꢃ.ꢃ50
ꢃ.ꢃ50
1ꢃppm/°C
5ppm/°C
P-P
LTC6652A-2.ꢃ48
LTC6652A-2.5
LTC6652A-3
2.1ppm
2.1ppm
2.1ppm
2.2ppm
2.3ppm
2.8ppm
P-P
P-P
P-P
P-P
P-P
P-P
LTC6652A-3.3
LTC6652A-4.ꢃ96
LTC6652A-5
There are three primary error sources to consider
when selecting a precision voltage reference for 16-bit
2754f
21
LTC2754
APPLICATIONS INFORMATION
As precision ꢂAC applications move to 16-bit and higher
performance, referenceoutputvoltagenoisemaycontrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practi-
cal for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the ꢃ.1Hz to 1ꢃHz region, well below the 16-bit LꢀS level
in 5V or 1ꢃV full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
When it is not possible to locate star ground close to
, a low resistance trace should be used to route this
ꢁ
OUT2
pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code-dependent current
flowing to ground. When the resistance of this circuit
board trace becomes greater than 1Ω, a force/sense am-
plifier configuration should be used to drive this pin (see
Figure 5). This preserves the excellent accuracy (1LꢀS
ꢁIL and ꢂIL) of the LTC2754-16.
Layout
Figures 6, 7, 8, and 9 show the layout for the LTC2754
evaluation board, ꢂC1546. This shows how to route the
digital signals around the device without interfering with
the reference and output op amps. Complete demo board
documentation is available in the ꢂC1546 “Quick ꢀtart
Guide.”
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
groundingtechniquesshouldbeused. ꢁ
mustbetied
OUT2X
to the star ground with as low a resistance as possible.
2754f
22
LTC2754
APPLICATIONS INFORMATION
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
3, 12, 29, 38
ꢁ
OUT2
2ꢃꢃΩ
2ꢃꢃ7
–
+
2
3
–
2
6
ꢁ
LT1ꢃꢃ1
OUT2
6
1ꢃꢃꢃpF
LT1468
1
2
1
2
+ 3
ZETEX
SAT54ꢀ
ZETEX*
SAT54ꢀ
3
3
*ꢀCHOTTKY SARRꢁER ꢂꢁOꢂE
V
REF
5V
LTC2754-16
49
R
5ꢃ
OFꢀA
R
FSA
R
2
ꢁIA
15pF
+ 3
1
GE
AꢂJA
48
ꢁ
–
1
OUT1A
OUT2A
2
3
1/2 LT1469
1
R
–
52
2
COMA
V
OUTA
ꢂAC A
1/2 LT1469
3
ꢁ
+
15ꢃpF
V
51
47
OꢀAꢂJA
REFA
–
+
ꢂAC S
ꢂAC C
ꢂAC ꢂ
–
+
–
+
2754 Fꢃ5
Figure 5. Optional Circuits for Driꢀing IOUT2 from GND with a Force/Sense Amplifier.
2754f
23
LTC2754
APPLICATIONS INFORMATION
2754 Fꢃ6
Figure 6. LTC2754 Eꢀaluation Board DC1546. Layer 1, Top Layer (Component Side)
2754 Fꢃ7
Figure 7. LTC2754 Eꢀaluation Board DC1546. Layer 2, GND Plane
2754f
24
LTC2754
APPLICATIONS INFORMATION
2754 Fꢃ8
Figure 8. LTC2754 Eꢀaluation Board DC1546. Layer 3, Power Traces
2754 Fꢃ9
Figure 9. LTC2754 Eꢀaluation Board DC1546. Layer 4, Bottom Layer (Solder Side)
2754f
25
LTC2754
TYPICAL APPLICATION
Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply
15ꢃpF
15ꢃpF
+
+
V
V
–
–
2
3 +
6
8
8
7
1
5 +
4
4
–
–
V
R
V
5V
2
6
5
+
ꢁI
OUT
LT1236-5
V
1ꢃ
39
41
2
52
42
REFS
43
44
51
REFA
5ꢃ
OFꢀA
49
1ꢃꢄF
1ꢃꢄF
ꢃ.1ꢄF
27pF
TRꢁM
V
R
R
R
R
R
FSS
R
R
FSA
ꢂꢂ
ꢁIS RCOMS ꢁIA
COMA
OFꢀS
GIꢂ
4
1ꢃk
1ꢃk
1ꢃk
+
V
V
3ꢃ
31
5
48
3
6
–
5 +
8
CLR
ꢁ
ꢁ
OUT1A
7
V
V
V
OUTꢂ
OUTS
OUTC
RFLAG
CS/Lꢂ
ꢀꢂꢁ
OUT2A
4
–
CS1
47
6
V
27pF
TO LT1991
ꢀꢂꢁ
ꢀCK
ꢀꢂO
CS2
OꢀAꢂJA
7
ꢀCK
+
8
V
ꢀRO
–
2
3 +
45
38
8
ꢁ
ꢁ
OUT1S
7
36
5V
LDAC
OUT2S
4
–
V
ꢃ.1ꢄF
ꢃ.1ꢄF
46
V
27pF
TO LT1991
OꢀAꢂJS
11
1
LTC2754
1ꢃk
REF
V
CC
7
8
9
2
3
4
5
12
13
14
15
Tꢃ
+
CS/Lꢂ
ꢀCK
ꢀꢂꢁ
V
OUTA
OUTS
OUTC
V
AꢂꢂꢁTꢁOIAL
OFFꢀET AꢂJUꢀT
CꢁRCUꢁTꢀ
–
6
5 +
22
29
V
V
V
8
32
35
34
33
ꢁ
OUT1C
7
M-ꢀPAI
ꢀ2
ꢁ
OUT2C
LT1469
4
OUTꢂ
LTC2636
–
V
OUTE
V
Tꢃ
ꢀ1
21
V
OUTF
OUTG
OUTH
1ꢃ
6
V
OꢀAꢂJC
AꢂꢂꢁTꢁOIAL
GAꢁI AꢂJUꢀT
CꢁRCUꢁTꢀ
TO LT1991
CLR
LDAC
V
V
27pF
ꢀꢃ
GIꢂ
16
+
V
V
–
19
2
8
ꢁ
ꢁ
OUT1ꢂ
OUT2ꢂ
1
V
3 +
OUTA
12
2ꢃ
4
LT1469
–
V
OꢀAꢂJꢂ
+
GE
GE
GE
GE
GIꢂ GIꢂ GIꢂ GIꢂ ꢀROGIꢂ R
R
R
R
REFC R
25
R
REFꢂ
R
R
AꢂJA
1
AꢂJS
4ꢃ
AꢂJC
27
AꢂJꢂ
14
ꢁIC COMC ꢁIꢂ COMꢂ
OFꢀC FSC
OFꢀꢂ FSꢂ
V
7
4
11 37 53
9
28
26
13
15
24
23 16 17 18
LT1991
45ꢃk
5ꢃk
8
M9
M3
M1
P1
TO LT1991s
5V
15ꢃpF
15ꢃk
4ꢄF
9
1ꢃ
1
+
+
45ꢃk
45ꢃk
–
+
V
V
V
15ꢃpF
OUT
6
5
–
3 +
–
2
3 +
2
8
8
7
45ꢃk
4ꢄF
15ꢃk
5ꢃk
2
4
4
LT1469
LT1469
P3
–
–
V
REF
3
2754 TAꢃ2
P9
4
7
–
V
+
V
LT1991
5ꢃk
45ꢃk
4ꢄF
8
9
M9
M3
M1
P1
15ꢃk
45ꢃk
45ꢃk
–
+
1ꢃ
1
OUT
REF
6
5
45ꢃk
4ꢄF
15ꢃk
5ꢃk
2
P3
3
P9
4
–
V
2754f
26
LTC2754
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC ꢂWG # ꢃ5-ꢃ8-1729 Rev Ø)
7.50 p0.05
6.10 p0.05
5.50 REF
(2 SIDES)
0.70 p0.05
6.45 p0.05
6.50 REF
(2 SIDES)
7.10 p0.05 8.50 p0.05
5.41 p0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 p 0.05
7.00 p 0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45oC
CHAMFER
6.45 p0.10
8.00 p 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 p0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 p 0.05
TOP VIEW
SIDE VIEW
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 p 0.05
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2754f
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2754
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1ꢃ27
Precision Reference
Precision Reference
16-Sit Accurate Op-Amp
ꢂual 16-Sit Accurate Op-Amp
1ppm/°C Maximum ꢂrift
LT1236A-5
LT1468
ꢃ.ꢃ50 Maximum Tolerance, 1ppm ꢃ.1Hz to 1ꢃHz Ioise
9ꢃMHz GSW, 22V/ꢄs ꢀlew Rate
LT1469
9ꢃMHz GSW, 22V/ꢄs ꢀlew Rate
LTC1588/LTC1589/ ꢀerial 12-/14-/16-Sit ꢁ
LTC1592
ꢀingle ꢂAC
ꢀoftware-ꢀelectable (ꢀoftꢀpan) Ranges, 1LꢀS ꢁIL, ꢂIL, 16-Lead ꢀꢀOP Package
OUT
LTC1591/LTC1597 Parallel 14-/16-Sit ꢁ
ꢀingle ꢂAC
ꢁntegrated 4-Quadrant Resistors
OUT
LTC27ꢃ4
LTC2751
ꢀerial 12-/14-/16-Sit V
Quad ꢂACs
ꢀoftware-ꢀelectable (ꢀoftꢀpan) Ranges, ꢁntegrated Amplifiers, 1LꢀS ꢁIL
OUT
Parallel 12-/14-/16-Sit ꢁ
ꢀingle ꢂAC
ꢀoftꢀpan
1LꢀS ꢁIL, ꢂIL, ꢀoftware-ꢀelectable (ꢀoftꢀpan) Ranges, 5mm ꢆ 7mm
QFI-38 Package
OUT
LTC2753
LTC2755
Parallel 12-/14-16-Sit ꢁ
ꢂACs
ꢀoftꢀpan ꢂual
ꢀoftꢀpan Quad
1LꢀS ꢁIL, ꢂIL, ꢀoftware-ꢀelectable (ꢀoftꢀpan) Ranges, 7mm ꢆ 7mm
QFI-48 Package
OUT
Parallel 12-/14-/16-Sit ꢁ
ꢂACs
1LꢀS ꢁIL, ꢂIL, ꢀoftware-ꢀelectable (ꢀoftꢀpan) Ranges, 9mm ꢆ 9mm
QFI-64 Package
OUT
2754f
LT 0609 • PRINTED IN USA
LinearTechnology Corporation
163ꢃ McCarthy Slvd., Milpitas, CA 95ꢃ35-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(4ꢃ8) 432-19ꢃꢃ FAX: (4ꢃ8) 434-ꢃ5ꢃ7 www.linear.com
相关型号：
©2020 ICPDF网 联系我们和版权申明