LTC2846 [Linear]
3.3V Software-Selectable Multiprotocol Transceiver with Termination; 3.3V软件可选的多协议收发器与终止
| 型号： | LTC2846 |
| 厂家： | 
Linear |
| 描述： | 3.3V Software-Selectable Multiprotocol Transceiver with Termination |
| 文件： | 总24页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2846
3.3V Software-Selectable
Multiprotocol Transceiver
with Termination
U
FEATURES
DESCRIPTIO
The LTC®2846 is a 3-driver/3-receiver multiprotocol trans-
ceiver with on-chip cable termination. When combined with
the LTC2844 or LTC2845, this chip set forms a complete
software-selectable DTE or DCE interface port that supports
the RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21
protocols. All necessary cable termination is provided inside
the LTC2846. The LTC2846 has a boost regulator that takes
in a 3.3V input and switches at 1.2MHz, allowing the use of
tiny,lowcostcapacitorsandinductors2mmorlessinheight.
■
Software-Selectable Transceiver Supports:
RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21
■
Operates from Single 3.3V Supply
■
TUV Rheinland of North America Inc. Certified NET1,
NET2 and TBR2 Compliant, Report No.:
TBR2/050101/02, TBR2/051501/02
■
1.2MHz Boost Switching Regulator for 3.3V to 5V
Conversion
On-Chip Cable Termination
■
■
Complete DTE or DCE Port with LTC2844 or LTC2845
The 5V output drives an internal charge pump that requires
only five space-saving surface mounted capacitors. The
LTC2846 is available in a 36-lead SSOP surface mount
package.
■
Small Footprint
■
Available in 36-Lead SSOP (0.209 Wide) Package
U
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Data Networking
■
CSU and DSU
■
Data Routers
U
TYPICAL APPLICATIO
Complete DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL
CTS
DSR
DCD
DTR
RTS
TXC
SCTE
TXD
RXD
RXC
LTC2846
LTC2844
D3
D4
D2
D1
D3
D2
T
D1
T
R4
R3
R2
R1
R3
T
R2
T
R1
T
18
13
5
22
6
10
8
23 20 19
4
1
7
16
3
9
17
12 15 11
24 14
2
DB-25 CONNECTOR
2846 TA01
sn2846 2846fs
1
LTC2846
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC Voltage.............................................. –0.3V to 6.5V
VIN Voltage .............................................. –0.3V to 6.5V
Input Voltage
Transmitters ........................... –0.3V to (VCC + 0.3V)
Receivers............................................... –18V to 18V
Logic Pins .............................. –0.3V to (VCC + 0.3V)
Output Voltage
Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V)
Receivers................................. –0.3V to (VIN + 0.3V)
VEE........................................................ –10V to 0.3V
VDD ....................................................... –0.3V to 10V
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output.......................................... Indefinite
VEE.................................................................. 30 sec
SW Voltage ............................................... –0.4V to 36V
FB Voltage ............................................... –0.3V to 2.5V
Current into FB Pin .............................................. ±1mA
SHDN Voltage ........................................... –0.3V to 10V
Operating Temperature Range
ORDER PART
NUMBER
TOP VIEW
NC
1
2
3
4
5
6
7
8
9
36 SW
35 FB
LTC2846CG
LTC2846IG
BOOST
SWITCHING
REGULATOR
PGND
V
IN
34 SGND
+
SHDN
33 C2
–
–
C1
32 C2
+
C1
31 V
EE
CHARGE PUMP
V
30 GND
DD
V
29 D1 A
28 D1 B
27 D2 A
26 D2 B
25 D3/R1 A
24 D3/R1 B
23 R2 A
22 R2 B
21 R3 A
20 R3 B
19 DCE/DTE
CC
D1
D1
D2
D3
T
T
D2 10
D3 11
R1 12
R2 13
R3 14
M0 15
M1 16
T
T
T
R1
R2
R3
V
17
IN
M2 18
LTC2846C ............................................... 0°C to 70°C
LTC2846I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 90°C/W, θJC = 35°C/W
*θJA SOLDERED TO A CIRCUIT BOARD IS TYPICALLY 60°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER
Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
Supply Current (DCE Mode,
CC
RS530, RS530-A, X.21 Modes, No Load
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode
V.28 Mode, No Load
V.28 Mode, Full Load
14
100
126
20
35
300
mA
mA
mA
mA
mA
µA
CC
All Digital Pins = GND or V )
●
●
130
170
IN
●
●
75
900
No-Cable Mode
P
V
Internal Power Dissipation (DCE Mode)
Positive Charge Pump Output Voltage
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, Full Load
V.28 Mode, Full Load
550
775
200
mW
mW
mW
D
+
V.11 or V.28 Mode, No Load
V.35 Mode
V.28 Mode, with Load
●
●
●
8
7
8
9.3
8.0
8.7
6.5
V
V
V
V
V.28 Mode, with Load, I = 10mA
DD
sn2846 2846fs
2
LTC2846
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
V
Negative Charge Pump Output Voltage
V.28 Mode, No Load
V.28 Mode, Full Load
V.35 Mode
RS530, RS530-A, X.21 Modes, Full Load
–9.6
–8.5
–6.5
–6.0
V
V
V
V
●
●
●
–7.5
–5.5
–4.5
f
t
Charge Pump Oscillator Frequency
Charge Pump Rise Time
500
2
kHz
ms
OSC
r
No-Cable Mode/Power-Off to Normal Operation
Logic Inputs and Outputs
V
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
D1, D2, D3, M0, M1, M2, DCE/DTE
SHDN
●
●
2.0
2.4
V
V
IH
V
D1, D2, D3, M0, M1, M2, DCE/DTE
SHDN
0.8
0.5
V
V
IL
I
D1, D2, D3
M0, M1, M2, DCE/DTE = GND
●
●
●
±10
–120
±10
±0.1
32
µA
µA
µA
µA
µA
IN
–30
–75
M0, M1, M2, DCE/DTE = V
SHDN = GND
IN
SHDN = 3V
16
3
V
V
Output High Voltage
I = –3mA
O
●
●
●
2.7
V
V
OH
OL
Output Low Voltage
I = 1.6mA
O
0.2
0.4
I
I
Output Short-Circuit Current
Three-State Output Current
0V ≤ V ≤ V
IN
±50
mA
OSR
OZR
O
M0 = M1 = M2 = V , V = GND
●
●
–30
–85
–160
±10
µA
µA
IN
O
M0 = M1 = M2 = V , V = V
IN
O
IN
V.11 Driver
V
V
Open Circuit Differential Output Voltage
Loaded Differential Output Voltage
R = 1.95k (Figure 1)
●
± 5
V
ODO
ODL
L
R = 50Ω (Figure 1)
0.5V
±2
0.67V
ODO
V
V
L
ODO
R = 50Ω (Figure 1)
L
●
●
∆V
Change in Magnitude of Differential
Output Voltage
R = 50Ω (Figure 1)
L
0.2
V
OD
V
Common Mode Output Voltage
R = 50Ω (Figure 1)
●
●
3
V
V
OC
L
∆V
Change in Magnitude of Common Mode
Output Voltage
R = 50Ω (Figure 1)
L
0.2
OC
I
I
Short-Circuit Current
V
= GND
±150
±100
mA
SS
OZ
OUT
Output Leakage Current
V
and V ≤ 0.25V, Power Off or
●
± 1
µA
A
B
No-Cable Mode or Driver Disabled
t , t
Rise or Fall Time
(Figures 2, 13)
●
●
●
●
2
15
15
0
15
40
40
3
25
65
65
12
ns
ns
ns
ns
ns
r
f
PLH
PHL
t
t
Input to Output Rising
Input to Output Falling
(Figures 2, 13)
(Figures 2, 13)
∆t
Input to Output Difference, t
Output to Output Skew
– t
(Figures 2, 13)
PLH
PHL
t
(Figures 2, 13)
3
SKEW
sn2846 2846fs
3
LTC2846
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
–0.2
100
TYP
MAX
UNITS
V.11 Receiver
V
Input Threshold Voltage
Input Hysteresis
–7V ≤ V ≤ 7V
●
●
●
0.2
40
V
mV
Ω
TH
CM
∆V
TH
–7V ≤ V ≤ 7V
15
103
15
50
50
4
CM
R
IN
Input Impedance
–7V ≤ V ≤ 7V (Figure 3)
CM
t , t
Rise or Fall Time
C = 50pF (Figures 4, 14)
L
ns
ns
ns
ns
r
f
PLH
PHL
t
t
Input to Output Rising
Input to Output Falling
Input to Output Difference, t
C = 50pF (Figures 4, 14)
L
●
●
●
90
90
25
C = 50pF (Figures 4, 14)
L
∆t
– t
PHL
C = 50pF (Figures 4, 14)
L
0
PLH
V.35 Driver
V
Differential Output Voltage
Open Circuit, R = 1.95k (Figure 5)
●
±1.2
±0.66
V
V
OD
L
With Load, –4V ≤ V ≤ 4V (Figure 6)
±0.44
±0.55
CM
V
V
, V
Single-Ended Output Voltage
Transmitter Output Offset
Open Circuit, R = 1.95k (Figure 5)
●
●
●
●
●
●
±1.2
±0.6
–13
13
V
V
OA OB
L
R = 50Ω (Figure 5)
L
OC
I
I
I
Transmitter Output High Current
Transmitter Output Low Current
V , V = 0V
–9
9
–11
11
±1
100
150
5
mA
mA
µA
Ω
OH
A
B
V , V = 0V
OL
OZ
A
B
Transmitter Output Leakage Current
V
and V ≤ 0.25V
±100
150
A
B
R
R
Transmitter Differential Mode Impedance
Transmitter Common Mode Impedance
Rise or Fall Time
50
OD
OC
–2V ≤ V ≤ 2V (Figure 7)
135
165
Ω
CM
t , t
(Figures 8, 13)
(Figures 8, 13)
(Figures 8, 13)
(Figures 8, 13)
(Figures 8, 13)
ns
ns
ns
ns
ns
r
f
PLH
PHL
t
t
Input to Output
●
●
●
15
15
35
35
0
65
65
16
Input to Output
∆t
Input to Output Difference, t
Output to Output Skew
– t
PLH PHL
t
4
SKEW
V.35 Receiver
V
Differential Receiver Input Threshold Voltage
Receiver Input Hysteresis
Receiver Differential Mode Impedance
Receiver Common Mode Impedance
Rise or Fall Time
–2V ≤ V ≤ 2V (Figure 9)
●
●
●
–0.2
0.2
40
V
mV
Ω
TH
CM
∆V
–2V ≤ V ≤ 2V (Figure 9)
15
103
150
15
TH
CM
R
R
–2V ≤ V ≤ 2V
90
110
165
ID
IC
CM
–2V ≤ V ≤ 2V (Figure 10)
135
Ω
CM
t , t
r
C = 50pF (Figures 4, 14)
L
ns
ns
ns
ns
f
t
t
Input to Output
C = 50pF (Figures 4, 14)
L
●
●
●
50
90
90
25
PLH
PHL
Input to Output
C = 50pF (Figures 4, 14)
L
50
∆t
Input to Output Difference, t
Output Voltage
– t
PHL
C = 50pF (Figures 4, 14)
L
0
4
PLH
V.28 Driver
V
Open Circuit
R = 3k (Figure 11)
L
●
●
±10
V
V
O
±5
±8.5
I
Short-Circuit Current
Power-Off Resistance
V
= GND
●
●
±150
mA
SS
OUT
R
–2V < V < 2V, Power Off
or No-Cable Mode
300
4
Ω
OZ
O
SR
Slew Rate
R = 7k, C = 0 (Figures 11, 15)
●
●
●
30
2.5
2.5
V/µs
µs
L
L
t
t
Input to Output
Input to Output
R = 3k, C = 2500pF (Figures 11, 15)
1.5
1.5
PLH
PHL
L
L
R = 3k, C = 2500pF (Figures 11, 15)
µs
L
L
sn2846 2846fs
4
LTC2846
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V.28 Receiver
V
V
Input Low Threshold Voltage
Input High Threshold Voltage
Receiver Input Hysteresis
Receiver Input Impedance
Rise or Fall Time
(Figure 12)
(Figure 12)
(Figure 12)
●
●
●
●
0.8
V
V
THL
TLH
2
0
3
∆V
0.05
5
0.3
7
V
TH
R
–15V ≤ V ≤ 15V
kΩ
ns
ns
ns
IN
A
t , t
r
C = 50pF (Figures 12, 16)
L
15
f
t
t
Input to Output
C = 50pF (Figures 12, 16)
L
●
●
60
300
300
PLH
PHL
Input to Output
C = 50pF (Figures 12, 16)
L
160
Boost Switching Regulator (Note 4)
V
V
Operating Voltage
Feedback Voltage
FB Pin Bias Current
3
3.3
1.255
120
3.6
1.280
360
V
V
IN
●
●
1.230
FB
I
I
V
= 1.255V
nA
FB
FB
Quiescent Current
Quiescent Current in Shutdown
V
SHDN
V
SHDN
= 2.4V, Not Switching
= 0V, V = 3V
4.2
0.01
6
1
mA
µA
Q
IN
∆V
f
Reference Line Regulation
Switching Frequency
Maximum Duty Cycle
Switch Current Limit
3V ≤ V ≤ 3.6V
0.01
1.2
0.05
1.6
%/V
MHz
%
FB(LR)
IN
●
●
0.85
82
1
DC
MAX
90
I
(Note 5)
1.2
2
1
A
LIM
V
Switch V
I
SW
= 900mA
= 5V
350
0.01
mV
µA
SAT
CESAT
I
Switch Leakage Current
V
SW
LEAK
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 3: All typicals are given for V = 5V, V = 3.3V, C
= C = 10µF,
VCC VIN
CC
IN
C
= 1µF, C
= 3.3µF and T = 25°C.
VEE A
VDD
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 4: The Boost Regulator is specified for V = 3V unless otherwise
noted.
Note 5: Current limit guaranteed by design and/or correlation to static test.
IN
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V.11 Mode ICC vs Data Rate
V.35 Mode ICC vs Data Rate
V.28 Mode ICC vs Data Rate
60
55
50
45
40
35
30
150
145
140
135
130
125
120
170
160
150
140
T
= 25°C
T
= 25°C
T
= 25°C
A
A
A
130
120
110
100
90
10
20
40
60
80 100
100
1000
10
100
1000
10000
10
10000
DATA RATE (kBd)
DATA RATE (kBd)
DATA RATE (kBd)
2846 G06
2846 G04
2846 G05
sn2846 2846fs
5
LTC2846
TYPICAL PERFOR A CE CHARACTERISTICS
U W
V.11 Mode ICC vs Temperature
V.35 Mode ICC vs Temperature
V.28 Mode ICC vs Temperature
128.0
127.5
127.0
126.5
126.0
125.5
125.0
124.5
124.0
123.5
123.0
110
105
100
95
37.5
37.0
36.5
36.0
35.5
35.0
34.5
34.0
90
85
80
33.5
–40
0
20
40
60
80 100
–20
40
TEMPERATURE (°C)
80 100
–20
0
40
60
80 100
–40 –20
0
20
60
–40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
2846 G08
2846 G07
3846 G09
Boost Switching Regulator
Oscillator Frequency
vs Temperature
Boost Switching Regulator SHDN
Pin Current vs Voltage
Boost Switching Regulator
Current Limit vs Duty Cycle
1.30
1.25
1.20
1.15
1.10
1.05
1.4
1.2
40
35
30
25
T
A
= 25°C
1.0
0.8
0.6
0.4
0.2
T
= 100°C
T
= 25°C
A
A
20
15
10
5
0
0
–40 –20
0
20
40
60
80 100
1
2
4
50
DUTY CYCLE (%)
70
80
0
5
6
10 20
30
40
60
3
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
2846 G12
2846 G10
2846 G11
Efficiency vs Load Current
90
85
80
75
70
65
60
55
50
T
= 25°C
A
V
= 3.3V
IN
0
50 100 150 200 250 300 350 400 450 500
LOAD CURRENT (mA)
2846 TA01b
sn2846 2846fs
6
LTC2846
U
U
U
PI FU CTIO S
NC (Pin 1): No Connect.
M2 (Pin 18): TTL Level Mode Select Input 2 with Pull-Up
to VIN. See Table 1.
PGND (Pin 2): Boost Switching Regulator Power Ground.
Tie PGND to SGND.
DCE/DTE (Pin 19): TTL Level Mode Select Input with
Pull-Up to VIN. See Table 1.
VIN (Pin 3): Input Supply Pin. Input supply to boost
switching regulator. 3V ≤VIN ≤ 3.6V. Bypass with a 10µF
capacitor to ground.
R3 B (Pin 20): Receiver 3 Noninverting Input.
R3 A (Pin 21): Receiver 3 Inverting Input.
R2 B (Pin 22): Receiver 2 Noninverting Input.
R2 A (Pin 23): Receiver 2 Inverting Input.
SHDN (Pin 4): Boost Switching Regulator Shutdown Pin.
Tie to 2.4V or more to enable regulator. Ground to shut
down.
C1– (Pin 5): Capacitor C1 Negative Terminal. Connect a
D3/R1 B (Pin 24): Receiver 1 Noninverting Input and
Driver 3 Noninverting Output.
1µF capacitor between C1+ and C1–.
C1+ (Pin 6): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1+ and C1–.
D3/R1 A (Pin 25): Receiver 1 Inverting Input and Driver 3
Inverting Output.
D2 B (Pin 26): Driver 2 Noninverting Output.
D2 A (Pin 27): Driver 2 Inverting Output.
D1 B (Pin 28): Driver 1 Noninverting Output.
D1 A (Pin 29): Driver 1 Inverting Output.
GND (Pin 30): Transceiver Ground.
VDD (Pin 7): Generated Positive Supply Voltage for
V.28. Connect a 1µF capacitor to ground.
VCC (Pin 8): Input Supply Pin. Input supply to trans-
ceiver. 4.75V≤ VCC ≤5.25V. Connect to output of switch-
ing regulator.
D1 (Pin 9): TTL Level Driver 1 Input.
D2 (Pin 10): TTL Level Driver 2 Input.
D3 (Pin 11): TTL Level Driver 3 Input.
VEE (Pin31):GeneratedNegativeSupplyVoltage.Connect
a 3.3µF capacitor to GND.
C2– (Pin 32): Capacitor C2 Negative Terminal. Connect a
R1 (Pin 12): CMOS Level Receiver 1 Output with Pull-Up
to VIN when Three-Stated.
1µF capacitor between C2+ and C2–.
C2+ (Pin 33): Capacitor C2 Positive Terminal. Connect a
1µF capacitor between C2+ and C2–.
R2 (Pin 13): CMOS Level Receiver 2 Output with Pull-Up
to VIN when Three-Stated.
SGND(Pin34):BoostSwitchingRegulatorSignalGround.
Tie PGND to SGND.
R3 (Pin 14): CMOS Level Receiver 3 Output with Pull-Up
to VIN when Three-Stated.
FB (Pin 35): Boost Switching Regulator Feedback Pin.
Reference voltage is 1.255V. Connect resistive divider tap
here. Minimize trace area at FB.
M0 (Pin 15): TTL Level Mode Select Input 0 with Pull-Up
to VIN. See Table 1.
M1 (Pin 16): TTL Level Mode Select Input 1 with Pull-Up
SW (Pin 36): Boost Switching Regulator Switch Pin.
Connect inductor/diode here. Minimize trace area at this
pin to reduce EMI.
to VIN. See Table 1.
VIN (Pin17):InputSupplyPin.Inputsupplytotransceiver.
3V ≤VIN ≤ 3.6V. Connect to Pin 3.
sn2846 2846fs
7
LTC2846
W
BLOCK DIAGRA
BOOST SWITCHING REGULATOR
GND SW
SW
2
3
4
36
35
34
PGND
V
FB
FB
V
IN
IN
SHDNGND
SGND
SHDN
CHARGE PUMP
–
–
+
+
C1
C1
C1
V
C2
C2
V
C2
5
6
7
33
32
31
+
+
–
–
C1
C2
V
V
DD
DD
EE
EE
V
8
V
GND
30 GND
29 D1A
CC
CC
50Ω
S1
D1
9
D1
S2
125Ω
50Ω
D1B
28
27 D2A
50Ω
S1
D2 10
D2
D3
S2
125Ω
50Ω
D2B
26
D3 11
DCE/DTE 19
R1 12
25 D3/R1 A
20k
20k
10k
6k
51.5Ω
S3
S1
S2
125Ω
10k
20k
51.5Ω
24 D3/R1 B
R1
R2A
23
6k
S3
10k
51.5Ω
S2
R2 13
R2
125Ω
10k
20k
51.5Ω
R2B
R3A
22
21
20k
10k
6k
S3
51.5Ω
51.5Ω
S2
R3 14
R3
125Ω
V
17
15
IN
10k
20k
M0
R3B
20
MODE
SELECTION
LOGIC
2846 BD
M1 16
M2 18
sn2846 2846fs
8
LTC2846
TEST CIRCUITS
C
L
R
R
L
B
A
100pF
B
A
D
D
R
L
V
OD
100Ω
C
L
V
OC
L
100pF
2846 F02
2846 F01
Figure 1. V.11 Driver DC Test Circuit
Figure 2. V.11 Driver AC Test Circuit
I
B
B
R
B
I
A
R
C
A
L
A
+
= ±7V
V
CM
–
2(V – V )
B
A
R
=
IN
I
B
– I
2846 F04
A
2846 F03
Figure 3. Input Impedance Test Circuit
Figure 4. V.11, V.35 Receiver AC Test Circuit
V
OB
V
OB
50Ω
50Ω
R
R
50Ω
50Ω
50Ω
50Ω
50Ω
L
125Ω
125Ω
125Ω
125Ω
V
OD
50Ω
V
OC
+
L
V
V
CM
= ±2V
CM
–
2846 F05
2846 F06
2846 F07
V
OA
V
OA
Figure 5. V.35 Driver Open-Circuit Test
Figure 6. V.35 Driver Test Circuit
Figure 7. V.35 Driver Common Mode
Impedance Test Circuit
51.5Ω
125Ω
50Ω
50Ω
50Ω
125Ω
125Ω
+
+
V
CM
= ±2V
V
50Ω
TH
–
–
51.5Ω
+
2846 F08
V
CM
–
2846 F09
2846 F10
Figure 8. V.35 Driver AC Test Circuit
Figure 9. V.35 Receiver DC Test Circuit
Figure 10. Receiver Common Mode
Impedance Test Circuit
D
A
A
R
R
C
V
A
C
L
L
L
2846 F11
2846 F12
Figure 11. V.28 Driver Test Circuit
Figure 12. V.28 Receiver Test Circuit
sn2846 2846fs
9
LTC2846
W
U
ODE SELECTIO
Table 1
Mode Name M2 M1 M0 DCE/ D1,2 D3
DTE
D1
D2
D3
R1
R2
R3
R1
R2,R3
V
V
EE
DD
(Note 3) (Note 3) (Note 4) (Note 5)
(Note 2)
(Note 2)
(Note 2)
A
B
A
B
A
B
A
B
A
B
A
B
Not Used
(Default V.11)
RS530A
RS530
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
TTL
TTL
TTL
TTL
TTL
TTL
TTL
X
X
X
X
X
X
X
X
X
V.11 V.11 V.11 V.11
V.11 V.11 V.11 V.11
V.11 V.11 V.11 V.11
V.11 V.11 V.11 V.11
V.35 V.35 V.35 V.35
V.11 V.11 V.11 V.11
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V
V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V
V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V
V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V
–6V
–6V
–6V
X.21
–6V
V.35
V.35 V.35 V.35 V.35 V.35 V.35 CMOS CMOS
8V
–6.5V
–6V
RS449/V.36
V.28/RS232
No Cable
V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V
V.28
Z
Z
Z
V.28
Z
Z
Z
V.28 30k V.28 30k V.28 30k CMOS CMOS 8.7V –8.5V
30k 30k 30k 30k 30k 30k
Z
Z
4.7V
0.3V
Not Used
(Default V.11)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11
TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11
TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11
TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11
TTL TTL V.35 V.35 V.35 V.35 V.35 V.35 30k 30k V.35 V.35 V.35 V.35
TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11
Z
Z
Z
Z
Z
Z
Z
Z
CMOS 9.3V
CMOS 9.3V
CMOS 9.3V
CMOS 9.3V
–6V
–6V
RS530A
RS530
–6V
X.21
–6V
V.35
CMOS
8V
–6.5V
–6V
RS449/V.36
V.28/RS232
No Cable
CMOS 9.3V
TTL TTL V.28
Z
Z
V.28
Z
Z
Z
V.28
Z
Z
Z
30k 30k V.28 30k V.28 30k
30k 30k 30k 30k 30k 30k
CMOS 8.7V –8.5V
4.7V 0.3V
X
X
Z
Z
Note 1: Driver inputs are TTL level compatible.
Note2:Unusedreceiverinputsareterminatedwith30ktoground. Inaddition, R2andR3arealways
terminated by a 103Ω differential impedence (see Block Diagram on page 8).
Note 4: VDD values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25°C with LTC2846
under full load for each mode.
Note 5: VEE values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25°C with LTC2846
under full load for each mode.
Note 3: Receiver Outputs are CMOS level compatible and have a weak pull up to VIN when Z.
U
W
W
SWITCHI G TI E WAVEFOR S
3V
f = 1MHz : t ≤ 10ns : t ≤ 10ns
r
f
1.5V
1.5V
D
0V
t
t
PHL
PLH
V
O
90%
90%
10%
B – A
50%
50%
10%
–V
O
1/2 V
O
t
t
f
r
A
V
O
B
t
t
2846 F13
SKEW
SKEW
Figure 13. V.11, V.35 Driver Propagation Delays
V
B – A
OD2
f = 1MHz : t ≤ 10ns : t ≤ 10ns
INPUT
r
f
0V
t
0V
–V
OD2
t
PLH
PHL
V
R
OH
OUTPUT
1.65V
1.65V
V
OL
2846 F14
Figure 14. V.11, V.35 Receiver Propagation Delays
sn2846 2846fs
10
LTC2846
U
W
W
SWITCHI G TI E WAVEFOR S
3V
1.5V
t
1.5V
D
0V
PHL
3V
t
PLH
V
O
3V
SR =
2846 F15
6V
f
6V
r
0V
0V
SR =
–3V
A
t
t
–3V
–V
O
t
t
r
f
Figure 15. V.28 Driver Propagation Delays
V
IH
1.5V
A
1.5V
V
IL
t
PHL
t
PLH
V
R
OH
1.65V
2846 F16
1.65V
V
OL
Figure 16. V.28 Receiver Propagation Delays
W U U
U
APPLICATIO S I FOR ATIO
Mode Selection
Overview
The interface protocol is selected using the mode select
pins M0, M1 and M2 (see Table 1).
The LTC2846 consists of a boost switching regulator, a
charge pump and a 3-driver/3-receiver transceiver. The
boost switching regulator generates a 5V VCC from the
3.3V input at VIN to power the charge pump and trans-
ceiver. The charge pump generates the VDD and VEE
supplies. The LTC2846’s VCC, VDD and VEE supplies can
be used to power a companion chip like the LTC2844 or
LTC2845. The receiver outputs are driven between 0V and
VIN to interface with 3.3V logic.
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, the drivers and receivers will
operateinV.28(RS232)electricalmode. Fortheclockand
data signals, the drivers and receivers will operate in V.35
electrical mode. The DCE/DTE pin will configure the port
for DCE mode when high, and DTE when low.
The LTC2846 and LTC2844 form a complete software-
selectable DTE or DCE interface port that supports the
RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21
protocols. Cable termination is provided on-chip, elimi-
nating the need for discrete termination designs.
Theinterfaceprotocolmaybeselectedsimplybyplugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon-
nected (1) or wired to ground (0) in the cable as shown in
Figure 18. The internal pull-up current sources will ensure
a binary 1 when a pin is left unconnected.
A complete DCE-to-DTE interface operating in EIA530
modeisshowninFigure17. TheLTC2846halfofeachport
is used to generate and appropriately terminate the clock
and data signals. The LTC2844 is used to generate the
control signals along with LL (Local Loopback).
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VIN.
sn2846 2846fs
11
LTC2846
W U U
U
APPLICATIO S I FOR ATIO
DTE
DCE
SERIAL
CONTROLLER
LTC2846
LTC2846
SERIAL
CONTROLLER
103Ω
103Ω
R3
D1
D2
D3
TXD
TXD
TXD
SCTE
R2
R1
SCTE
SCTE
D3
TXC
RXC
RXD
R1
103Ω
103Ω
103Ω
TXC
RXC
RXD
TXC
RXC
R2
R3
D2
D1
RXD
LTC2844
R3
LTC2844
D1
RTS
DTR
RTS
DTR
RTS
DTR
D2
D3
R2
R1
D3
DCD
DSR
R1
R2
R3
DCD
DSR
DCD
DSR
D2
D1
CTS
LL
CTS
LL
CTS
LL
D4
R4
R4
D4
2846 F17
Figure 17. Complete Multiprotocol Interface in EIA530 Mode
When the cable is removed, leaving all mode pins uncon-
nected, the LTC2846/LTC2844 will enter no-cable mode.
In this mode the LTC2846/LTC2844 supply current drops
to less than 900µA and the LTC2846/LTC2844 driver out-
puts are forced into a high impedance state. At the same
time, the R2 and R3 receivers of the LTC2846 are differ-
entially terminated with 103Ω and the other receivers on
the LTC2846 and LTC2844 are terminated with 30kΩ to
ground.
Cable Termination
Traditional implementations used expensive relays to
switch resistors or required the user to change termina-
tion modules every time a new interface standard was
sn2846 2846fs
12
LTC2846
W U U
APPLICATIO S I FOR ATIO
U
(DATA)
CONNECTOR
15
16
18
19
M0
LTC2846
M1
M2
NC
NC
DCE/DTE
CABLE
14
13
12
11
DCE/DTE
M2
LTC2844
M1
M0
2846 F18
(DATA)
Figure 18. Single Port DCE V.35 Mode Selection in the Cable
BALANCED
INTERCONNECTING
CABLE
selected. Switching the terminations with FETs is difficult
because the FETs must remain off when the signal voltage
is beyond the supply voltage. Alternatively, custom cables
may contain termination in the cable head or route signals
to various terminations on the board.
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
A
A'
The LTC2846/LTC2844 chip set solves the cable termina-
tion switching problem by automatically providing the
appropriate termination and switching on-chip for the
V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35
electrical protocols.
2846 F19
C
C'
Figure 19. Typical V.10 Interface
V.10 (RS423) Interface
I
Z
3.25mA
All V.10 drivers and receivers necessary for the RS449,
EIA530, EIA530-A, V.36 and X.21 protocols are imple-
mented on the LTC2844 or LTC2845.
A typical V.10 unbalanced interface is shown in Figure 19.
A V.10 single-ended generator with output A and ground
C is connected to a differential receiver with input A' con-
nected to A, and ground C' connected via the signal return
to ground C. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 20.
–10V
–3V
V
Z
3V
10V
The V.10 receiver configuration in the LTC2844 and
LTC2845 is shown in Figure 21. In V.10 mode, switch S3
inside the LTC2844 and LTC2845 is turned off. The
noninverting input is disconnected inside the LTC2844
2846 F20
–3.25mA
Figure 20. V.10 Receiver Input Impedance
sn2846 2846fs
13
LTC2846
W U U
U
APPLICATIO S I FOR ATIO
A
A
'
A'
LTC2844
LTC2846
R5
20k
R5
20k
R1
R8
6k
R8
6k
51.5Ω
R6
10k
R6
10k
RECEIVER
RECEIVER
S3
S1
S2
S3
R3
124Ω
R7
10k
R7
10k
R2
51.5Ω
R4
20k
R4
20k
B
B'
B'
C'
C'
2846 F23
2846 F21
GND
GND
Figure 21. V.10 Receiver Configuration
Figure 23. V.11 Receiver Configuration
termination impedance to the cable as shown in Figure
231. The LTC2844 and LTC2845 only handle control
signals, so no termination other than their V.11 receivers’
30k input impedance is necessary.
BALANCED
INTERCONNECTING
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
A
A'
V.28 (RS232) Interface
100Ω
MIN
A typical V.28 unbalanced interface is shown in Figure 24.
A V.28 single-ended generator with output A and ground
C is connected to a single-ended receiver with input A
connected to A and ground C
return to ground C.
B
C
B'
C'
2846 F22
'
' connected via the signal
Figure 22. Typical V.11 Interface
and LTC2845 receivers and connected to ground. The
cable termination is then the 30k input impedance to
ground of the LTC2844 and LTC2845 V.10 receiver.
BALANCED
INTERCONNECTING
CABLE
LOAD
GENERATOR
CABLE
TERMINATION
RECEIVER
V.11 (RS422) Interface
A
A'
A typical V.11 balanced interface is shown in Figure 22. A
V.11 differential generator with outputs A and B and
ground C is connected to a differential receiver with input
2846 F24
C
C'
A' connected to A, input B' connected to B, and ground C'
Figure 24. Typical V.28 Interface
connected via the signal return to ground C. The V.11
interface has a differential termination at the receiver end
that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is essen-
tial to prevent reflections from corrupting the data. The
receiver inputs must also be compliant with the imped-
ance curve shown in Figure 20.
A
'
LTC2846
R5
R1
R8
6k
20k
51.5Ω
R6
RECEIVER
10k
S3
S1
S2
R3
124Ω
R7
10k
R2
51.5Ω
R4
20k
B
'
In V.11 mode, all switches are off except S1 of the
LTC2846’s receivers which connects a 103Ω differential
2846 F25
GND
C
'
1Actually, there is no switch S1 in receivers R2 and R3. However, for simplicity, all termination
networks on the LTC2846 can be treated identically if it is assumed that an S1 switch exists and is
always closed on the R2 and R3 receivers.
Figure 25. V.28 Receiver Configuration
sn2846 2846fs
14
LTC2846
W U U
APPLICATIO S I FOR ATIO
U
In V.28 mode, S3 is closed inside the LTC2846/LTC2844
which connects a 6k (R8) impedance to ground in parallel
with 20k (R5) plus 10k (R6) for a combined impedance of
5k as shown in Figure 25. Proper termination is only pro-
videdwhentheBinputofthereceiversisfloating, sinceS1
of the LTC2846’s R2 and R3 receivers remains on in V.28
mode1. The noninverting input is disconnected inside the
LTC2846/LTC2844 receiver and connected to a TTL level
reference voltage to give a 1.4V receiver trip point.
100Ω ±10Ω, and the impedance between shorted termi-
nals (A and B ) and ground (C') must be 150Ω ±15Ω.
'
'
InV.35mode,bothswitchesS1andS2insidetheLTC2846
are on, connecting a T network impedance as shown in
Figure 27. The 30k input impedance of the receiver is
placed in parallel with the T network termination, but does
not affect the overall input impedance significantly.
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground (C) must be 150Ω ±15Ω.
V.35 Interface
A typical V.35 balanced interface is shown in Figure 26. A
V.35 differential generator with outputs A and B and
ground C is connected to a differential receiver with input
No-Cable Mode
The no-cable mode (M0 = M1 = M2 = 1) is intended for
the case when the cable is disconnected from the con-
nector. The charge pump, bias circuitry, drivers and
receiversareturnedoff, thedriveroutputsareforcedinto
a high impedance state, and theVCC supply current to the
transceiver drops to less than 300µA while its VIN supply
current drops to less than 10µA. Note that the LTC2846’s
A' connected to A, input B' connected to B, and ground C'
connected via the signal return to ground C. The V.35
interface requires a T or delta network termination at the
receiver end and the generator end. The receiver differen-
tial impedance measured at the connector must be
BALANCED
R2andR3receiverscontinuetobeterminatedbya103
differential impedance.
Ω
INTERCONNECTING
CABLE
GENERATOR
LOAD
CABLE
TERMINATION
RECEIVER
Charge Pump
A'
A
The LTC2846 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 28. A voltage
doubler generates about 8V on VDD and a voltage inverter
generatesabout–7.5VonVEE.Three1µFsurfacemounted
tantalumorceramiccapacitorsarerequiredforC1, C2and
C3. The VEE capacitor C4 should be a minimum of 3.3µF.
All capacitors are 16V and should be placed as close as
possible to the LTC2846 to reduce EMI.
50Ω
50Ω
125Ω
125Ω
50Ω
50Ω
B
'
B
C
C'
2846 F26
Figure 26. Typical V.35 Interface
A
'
LTC2846
R5
20k
R1
51.5Ω
R8
6k
7
6
5
8
33
32
31
30
+
–
V
C2
C2
DD
+
R6
RECEIVER
C2
C3
1µF
10k
1µF
S1
S2
S3
C1
C1
V
R3
124Ω
C1
1µF
LTC2846
–
V
EE
C4
3.3µF
R7
10k
R2
51.5Ω
R4
20k
+
B
'
GND
5V
CC
C5
10µF
2846 F27
GND
C
'
2846 F28
Figure 27. V.35 Receiver Configuration
Figure 28. Charge Pump
sn2846 2846fs
15
LTC2846
W U U
U
APPLICATIO S I FOR ATIO
Switching Regulator
The switching regulator has a switch current limit of 1A.
This current limit protects the switch as well as the exter-
nal components connected to the switching regulator.
ThecircuitasshowninFigure29canprovideupto480mA
at 5V to drive the LTC2846’s transceiver as well as its
companionchipintheDTE-DCEinterface. Initsshutdown
mode with the SHDN pin at 0V, the boost switching
regulator draws less than 10µA.
The high speed operation of the boost switching regulator
demands careful attention to board layout. Figure 30
shows the recommended component placement.
Ferrite core inductors should be used to obtain the best
efficiency, as core losses at 1.2MHz are much lower for
ferritecoresthanforcheaperpowdered-irontypes.Choose
an inductor that can handle at least 1A without saturating,
and ensure that the inductor has a low DCR (copper wire
resistance) to minimize I2R power losses.
Receiver Fail-Safe
All LTC2846/LTC2844 receivers feature fail-safe opera-
tion in all modes. If the receiver inputs are left floating or
areshortedtogetherbyaterminationresistor, thereceiver
output will always be forced to a logic high.
Use low ESR capacitors for the output to minimize output
ripple voltage. Multilayer ceramic capacitors are an excel-
lent choice, as they have extremely low ESR and are
available in very small packages. Ceramic capacitors also
make a good choice for the input decoupling capacitor,
and should be placed as close as possible to the switching
regulator. Solid tantalum or OS-CON capacitors can be
used but they will occupy more board area than a ceramic
and will have a higher ESR.
DTE vs DCE Operation
The DCE/DTE pin acts as an enable for Driver 3/Receiver 1
in the LTC2846, and Driver 3/Receiver 1 and Receiver 4/
Driver 4 in the LTC2844.
The LTC2846/LTC2844 can be configured for either DTE
or DCE operation in one of two ways: a dedicated DTE or
DCE port with a connector of appropriate gender or a port
with one connector that can be configured for DTE or DCE
operationbyreroutingthesignalstotheLTC2846/LTC2844
using a dedicated DTE cable or dedicated DCE cable.
ASchottkydiodeisrecommendedforusewiththeswitch-
ing regulator. The ON Semiconductor MBR0520 is a very
good choice.
A dedicated DTE port using a DB-25 male connector is
showninFigure31.Theinterfacemodeisselectedbylogic
outputs from the controller or from jumpers to either VIN
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 32.
To set the output voltage, select the values of R1 and R2
according to the following equation.
R1 = R2[(5V/1.255V) – 1]
A good value for R2 is 4.3k which sets the current in the
resistor divider chain to 1.255V/4.3k = 292µA.
V
CC
GND
L1
V
D1
IN
5.6µH
V
CC
V
IN
5V
3.3V
C5
480mA
3
36
SW
R1
R2
V
D1
R1
13k
C6
10µF
L1
IN
C6
BOOST
SWITCHING
REGULATOR
SHDN
C5
10µF
35
4
SHDN
FB
R2
4.3k
GND
2, 34
SHUTDOWN
2846 F30
C5,C6: TAIYO YUDEN X5R JMK316BJ106ML
D1: ON SEMICONDUCTOR MBR0520
L1: SUMIDA CR43-5R6
2846 F29
Figure 29. Boost Switching Regulator
Figure 30. Suggested Layout
sn2846 2846fs
16
LTC2846
U
TYPICAL APPLICATIO S
A port with one DB-25 connector, that can be configured
for either DTE or DCE operation is shown in Figure 33. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to Pins 2 and 14 via the
LTC2846’s Driver 1. In DCE mode, Driver 1 now routes the
RXD signal to Pins 2 and 14.
PRT refers to the power dissipated by each driver in a
receiver termination on the far end of the cable while ND is
the number of drivers. Conversely, current from the far
end drivers dissipate power NR • PRT in the internal
receiver termination where NR is the number of receivers.
LTC2846 Power Dissipation
Consider an LTC2846 in X.21, DCE mode (three V.11
drivers and two V.11 receivers). From the Electrical Char-
acteristics Table, ICC at no load = 14mA, ICC at full load =
100mA. Each receiver termination is 100Ω (RRT) and
current going into each receiver termination = (100mA –
14mA)/3 = 28.7mA (IRT).
Multiprotocol Interface with RL, LL, TM
and a DB-25 Connector
IftheRL,LLandTMsignalsareimplemented,therearenot
enough drivers and receivers available in the LTC2846/
LTC2844. In Figure 34, the required control signals are
handled by the LTC2845. The LTC2845 has an additional
single-endeddriver/receiverpairthatcanhandletwomore
optional control signals such as TM and RL.
PRT = (IRT)2 • RRT
(2)
From Equation (2), PRT = 82.4mW and from Equation (1),
DC power dissipation PDISS(2846) = 125% • (5V • 100mA)
– 3 • 82.4mW + 2 • 82.4mW = 543mW.
Cable-Selectable Multiprotocol Interface
A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 35. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected by
the cable by wiring M0 (connector Pin 18) and M1 (con-
nector Pin 21) and DCE/DTE (connector Pin 25) to ground
(connector Pin 7) or letting them float. If M0, M1 or
DCE/DTE is floating, internal pull-up current sources will
pull the signals to VIN. The select bit M2 is floating, and
therefore, internally pulled high. When the cable is pulled
out, the interface will go into the no-cable mode.
Consider the above example running at a baud rate of
10MBd. From the Typical Characteristic for “V.11 Mode
ICC vs Data Rate,” the ICC at 10MBd is 160mA. ICC
increases with baud rate due to driver transient dissipa-
tion. From Equation (1), AC power dissipation PDISS(2846)
= 125% • (5V • 160mA) –3 • 82.4mW + 2 • 82.4mW =
918mW.
LTC2845 Power Dissipation
If a LTC2845 is used to form a complete DCE port with the
LTC2846, it will be running in the X.21 mode (three V.11
drivers and two V.10 drivers, two V.11 receivers and two
V.10 receivers, all with internal 30k termination). In addi-
tion to VCC, it uses the VDD and VEE outputs from the
LTC2846. Negligible power is dissipated in the large
internal receiver termination of the LTC2845 so the NR •
PRT termofEquation(1)canbeomitted.ThusEquation(1)
is modified as follows:
Power Dissipation Calculations
TheLTC2846takesina3.3Vsupplyandproducesa5VVCC
with an internal switcher at approximately 80% efficiency.
VDD andVEE areinturnproducedfromVCC withaninternal
charge pump at approximately 80% and 70% efficiency
respectively. Current drawn internally from VDD or VEE
translates directly into a higher ICC. The LTC2846 dissi-
pates power according to the equation:
PDISS(2845) = (VCC • ICC) + (VDD • IDD)
PDISS(2846) = 125% • (VCC • ICC)
– ND • PRT + NR • PRT
(1)
sn2846 2846fs
17
LTC2846
U
TYPICAL APPLICATIO S
+ (VEE • IEE) – ND • PRT
(3)
79mW and V.10 PRT = 49.6mW.
Since power is drawn from the supplies of the LTC2846
(VCC, VDD and VEE) at less than 100% efficiency, the
LTC2846 dissipates extra power to source PDISS(2845) and
From Equation (3), PDISS(2845) = 5V • (110mA – 23mA) +
(8V • 0.3mA) + 5.5V • 23mA – 3 • 79mW – 2 • 49.6mW =
228mW. SincetheLTC2845runsslowcontrolsignals, the
ACpowerdissipationcanbeassumedtobeequaltotheDC
power dissipation.
PRT
:
PDISS1(2846) = 125% • (VCC • ICC) + 125% • 125%
• (VDD • IDD) + 125% • 143% • (VEE • IEE)
– PDISS(2845) – ND • PRT
TheextrapowerdissipatedintheLTC2846duetoLTC2845
is given by Equation(4), PDISS1(2846) = 25% • (5V • 87mA)
+ 56% • (8V • 0.3mA) + 79% • (5.5V • 23mA) = 210mW.
So for an X.21 DCE port running at 10MBd, the LTC2846
dissipates approximately 918mW + 210mW = 1128mW
while the LTC2845 dissipates 228mW.
= 25% • (VCC • ICC) + 56% • (VDD • IDD)
+ 79% • (VEE • IEE)
(4)
From the LTC2845 Electrical Characteristics Table, for
VCC = 5V, VDD = 8V and VEE = – 5.5V:
Compliance Testing
I
I
I
I
I
I
at no load
2.7mA
110mA
2mA
CC
CC
EE
at full load with all drivers high
at no load
The LTC2846/LTC2844 and LTC2846/LTC2845 chipsets
have been tested by TUV Rheinland of North America Inc.
and passed the NET1, NET2 and TBR2 requirements.
Copies of the test reports are available from LTC or TUV
Rheinland of North America Inc.
at full load with both V.10 drivers low
at no load
23mA
0.3mA
0.3mA
EE
DD
DD
at full load
The title of the reports are Test Report No.:
TBR2/051501/02 and TBR2/050101/02
The V.11 drivers are driven between VCC and GND while
the V.10 drivers are driven between VCC and VEE. Assume
that the V.11 driver outputs are high and V.10 driver
outputs low. Current going into each 100Ω V.11 receiver
termination = (110mA – 2.7mA) – 23mA/3 = 28.1mA.
Current going into each 450Ω V.10 receiver termination =
The address of TUV Rheinland of North America Inc. is:
TUV Rheinland of North America Inc.
1775, Old Highway 8 NW, Suite 107
St. Paul, MN 55112
Tel. (651) 639-0775
Fax (651) 639-0873
23mA – 2mA/2 = 10.5mA. From Equation (2), V.11 PRT
=
sn2846 2846fs
18
LTC2846
U
TYPICAL APPLICATIO S
D1
L1
MBR0520
5.6µH
V
V
IN
3.3V
CC
5V
3
36
C6
R1
10µF
13k
BOOST
SWITCHING
REGULATOR
4
7
5
35
33
C5
10µF
SHDN
R2
4.3k
C2
1µF
C3
1µF
32
31
C1
CHARGE
PUMP
6
8
1µF
C4
V
+
3.3µF
CC
30
29
5V
LTC2846
2
TXD A (103)
9
TXD
D1
D2
D3
T
T
T
14
24
28
27
TXD B
SCTE A (113)
10
11
SCTE
11
26
SCTE B
25
15
TXC A (114)
12
13
14
TXC
RXC
RXD
R1
R2
R3
24
23
12
17
TXC B
RXC A (115)
T
T
22
21
9
3
RXC B
RXD A (104)
16
7
20
15
16
18
19
RXD B
SG
M0
M1
M2
17
1
V
IN
SHIELD
DCE/DTE
3.3V
V
CC
C7
1µF
C8
1µF
DB-25 MALE
CONNECTOR
28
27
1
2
V
V
EE
GND
CC
C9
1µF
V
DD
26
4
RTS A (105)
RTS B
3
4
5
RTS
D1
D2
D3
25
24
23
19
20
23
DTR A (108)
DTR B
DTR
LTC2844
8
10
6
22
21
20
19
6
7
8
DCD A (109)
DCD B
R1
R2
R3
R4
DCD
DSR
CTS
LL
DSR A (107)
22
DSR B
5
18
17
CTS A (106)
CTS B
13
10
9
16
18
LL A (141)
D4
11
12
13
14
15
V
IN
3.3V
M0
M1
M2
M0
M1
M2
V
IN
C10
1µF
DCE/DTE
2846 F31
Figure 31. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
sn2846 2846fs
19
LTC2846
U
TYPICAL APPLICATIO S
D1
MBR0520
L1
5.6µH
V
V
CC
5V
IN
3.3V
3
36
C6
R1
10µF
13k
BOOST
SWITCHING
REGULATOR
4
7
5
35
33
C5
10µF
SHDN
R2
4.3k
C2
C3
1µF
1µF
32
31
C1
1µF
CHARGE
PUMP
6
8
C4
V
CC
5V
+
3.3µF
30
29
LTC2846
3
RXD A (104)
9
RXD
D1
D2
D3
T
T
T
16
17
28
27
RXD B
RXC A (115)
10
11
RXC
9
26
RXC B
25
15
TXC A (114)
12
13
14
TXC
SCTE
TXD
R1
R2
R3
24
23
12
24
TXC B
SCTE A (113)
T
T
22
21
11
2
SCTE B
TXD A (103)
14
7
20
15
16
18
19
TXD B
M0
M1
M2
SGND (102)
17
1
V
IN
3.3V
SHIELD (101)
DCE/DTE
NC
V
CC
C7
1µF
C8
1µF
DB-25 FEMALE
CONNECTOR
28
27
1
2
V
V
EE
GND
CC
C9
1µF
V
DD
26
5
CTS A (106)
CTS B
3
4
5
CTS
D1
D2
D3
25
24
23
13
6
DSR A (107)
DSR B
22
DSR
LTC2844
8
10
20
23
22
21
20
19
6
7
8
DCD A (109)
DCD B
R1
R2
R3
R4
DCD
DTR
RTS
LL
DTR A (108)
DTR B
4
18
17
RTS A (105)
RTS B
19
10
9
16
18
LL A (141)
D4
11
12
13
14
15
V
IN
3.3V
M0
M1
M2
M0
M1
M2
V
IN
C10
1µF
NC
DCE/DTE
2846 F32
Figure 32. Controller-Selectable DCE Port with DB-25 Connector
sn2846 2846fs
20
LTC2846
U
TYPICAL APPLICATIO S
D1
L1
MBR0520
5.6µH
V
V
IN
3.3V
CC
5V
3
36
C6
R1
10µF
13k
BOOST
SWITCHING
REGULATOR
4
7
5
35
33
C5
10µF
SHDN
R2
4.3k
C2
1µF
C3
1µF
32
31
C1
1µF
CHARGE
PUMP
6
8
C4
V
+
3.3µF
CC
30
29
5V
DTE
DCE
LTC2846
2
TXD A
RXD A
9
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
D1
D2
D3
T
T
T
14
24
28
27
TXD B
RXD B
SCTE A RXC A
10
11
11
26
SCTE B RXC B
15
25
TXC A
TXC A
12
13
14
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R1
R2
R3
12
17
24
23
TXC B
TXC B
RXC A
SCTE A
T
T
22
21
9
3
SCTE B
TXD A
RXC B
RXD A
16
7
20
TXD B
RXD B
SG
15
16
18
19
M0
M1
M2
17
1
V
IN
3.3V
SHIELD
DCE/DTE
V
CC
C7
1µF
C8
1µF
DB-25
CONNECTOR
28
27
1
2
V
V
EE
GND
CC
C9
1µF
V
DD
26
4
RTS A
CTS A
3
4
5
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
D1
D2
D3
25
24
23
19
20
RTS B
DTR A
DTR B
CTS B
DSR A
DSR B
23
LTC2844
8
10
6
22
21
20
19
DCD A
DCD B
DSR A
DCD A
DCD B
DTR A
6
7
8
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
R1
R2
R3
R4
22
DSR B
CTS A
CTS B
DTR B
RTS A
RTS B
5
18
17
13
10
9
16
18
LL A
LL A
D4
11
12
13
14
15
V
IN
3.3V
M0
M1
M0
M1
M2
V
IN
C10
1µF
M2
DCE/DTE
DCE/DTE
2846 F33
Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
sn2846 2846fs
21
LTC2846
U
TYPICAL APPLICATIO S
D1
MBR0520
L1
5.6µH
V
V
CC
5V
IN
3.3V
3
36
C6
R1
10µF
13k
BOOST
SWITCHING
REGULATOR
4
7
5
35
33
C5
10µF
SHDN
R2
4.3k
C2
C3
1µF
1µF
32
31
C1
1µF
CHARGE
PUMP
6
8
C4
V
+
3.3µF
CC
30
29
5V
LTC2846
DTE
TXD A
DCE
RXD A
2
9
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
D1
D2
D3
T
T
T
14
24
28
27
TXD B
RXD B
SCTE A RXC A
10
11
26
11
SCTE B RXC B
25
15
TXC A
TXC B
RXC A
TXC A
TXC B
SCTE A
12
13
14
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R1
R2
R3
12
17
24
23
T
T
9
3
22
21
RXC B
RXD A
SCTE B
TXD A
20
16
7
RXD B
SG
TXD B
15
16
18
19
M0
M1
M2
1
SHIELD
17
V
IN
3.3V
DCE/DTE
V
CC
C7
1µF
5V
C8
1µF
36
35
DB-25
CONNECTOR
1, 19
2
V
CC
V
EE
GND
C9
1µF
V
DD
34
4
19
20
RTS A
CTS A
CTS B
DSR A
DSR B
3
4
5
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
D1
D2
D3
33
32
RTS B
DTR A
DTR B
23
31
LTC2845
8
30
29
28
27
DCD A
DCD B
DSR A
DCD A
DCD B
DTR A
6
7
R1
R2
R3
10
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
6
22
DSR B
CTS A
DTR B
RTS A
26
5
13
18
8
9
DTE_CTS/DCE_RTS
DTE_LL/DCE_RI
DTE_RI/DCE_LL
25
24
CTS B
LL
RTS B
RI
D4
R4
10
23
*
RI
LL
25
21
17
18
22
21
DTE_TM/DCE_RL
DTE_RL/DCE_TM
R5
TM
RL
RL
TM
D5
11
12
13
14
20
15
V
IN
M0
M1
M0
M1
M2
V
IN
3.3V
*OPTIONAL
C10
1µF
D4ENB
2846 F34
M2
16
NC
DCE/DTE
R4EN
DCE/DTE
Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector
sn2846 2846fs
22
LTC2846
U
TYPICAL APPLICATIO S
D1
L1
MBR0520
5.6µH
V
V
IN
3.3V
CC
5V
3
36
C6
R1
10µF
13k
BOOST
SWITCHING
REGULATOR
4
7
5
35
33
C5
10µF
SHDN
R2
4.3k
C2
1µF
C3
32
31
1µF
C1
1µF
CHARGE
PUMP
6
8
C4
V
+
3.3µF
CC
30
29
5V
DTE
DCE
LTC2846
2
TXD A
RXD A
9
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
D1
D2
D3
T
T
T
14
24
28
27
TXD B
RXD B
RXC A
SCTE A
10
11
11
26
SCTE B
RXC B
25
15
TXC A
TXC A
12
13
14
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
R1
R2
R3
12
17
24
23
TXC B
RXC A
TXC B
SCTE A
T
T
9
3
22
21
SCTE B
TXD A
RXC B
RXD A
16
7
20
RXD B
SG
15
16
18
19
TXD B
M0
M1
M2
NC
1
17
V
IN
3.3V
SHIELD
DCE/DTE
DB-25
CONNECTOR
V
CC
C7
1µF
C8
1µF
25
21
18
28
27
DCE/DTE
1
2
V
V
EE
GND
CC
C9
1µF
M1
M0
V
DD
26
4
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
3
4
5
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
D1
D2
D3
25
24
23
19
20
23
LTC2844
8
10
6
22
21
20
19
6
7
8
DCD A
DCD B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
R1
R2
R3
R4
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
22
5
18
17
RTS A
RTS B
CTS A
CTS B
13
CABLE WIRING FOR MODE SELECTION
10
9
16
MODE
V.35
RS449, V.36
RS232
PIN 18
PIN 7
NC
PIN 21
PIN 7
PIN 7
NC
D4
11
12
13
14
15
PIN 7
V
IN
3.3V
M0
M1
M2
V
IN
C10
1µF
CABLE WIRING FOR
DTE/DCE SELECTION
NC
MODE
DTE
DCE
PIN 25
PIN 7
NC
DCE/DTE
2846 F35
Figure 35. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
sn2846 2846fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC2846
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
(.002)
NOTE:
G36 SSOP 0802
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
RELATED PARTS
PART NUMBER
LTC1321
DESCRIPTION
COMMENTS
Dual RS232/RS485 Transceiver
Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs
Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs
4-Driver/4-Receiver for Data and Clock Signals
LTC1334
Single 5V RS232/RS485 Multiprotocol Transceiver
Software-Selectable Multiprotocol Transceiver
Software-Selectable Cable Terminator
Single Supply V.35 Transceiver
LTC1343
LTC1344A
LTC1345
Perfect for Terminating the LTC1543 (Not Needed with LTC1546)
3-Driver/3-Receiver for Data and Clock Signals
LTC1346A
LTC1543
Dual Supply V.35 Transceiver
3-Driver/3-Receiver for Data and Clock Signals
Software-Selectable Multiprotocol Transceiver
Terminated with LTC1344A for Data and Clock Signals, Companion to
LTC1544 or LTC1545 for Control Signals
LTC1544
LTC1545
Software-Selectable Multiprotocol Transceiver
Software-Selectable Multiprotocol Transceiver
Companion to LTC1546 or LTC1543 for Control Signals Including LL
5-Driver/5-Receiver Companion to LTC1546 or LTC1543
for Control Signals Including LL, TM and RL
LTC1546
LTC2844
LTC2845
Software-Selectable Multiprotocol Transceiver
3.3V Software-Selectable Multiprotocol Transceiver
3.3V Software-Selectable Multiprotocol Transceiver
3-Driver/3-Receiver with Termination for Data and Clock Signals
Companion to LTC2846 for Control Signals Including LL
5-Driver/5-Receiver Companion to LTC2846 for Control Signals
Including LL, TM and RL
sn2846 2846fs
LT/TP 0503 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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