LTC2919CDDB-2.5#TRPBF [Linear]
暂无描述;LTC2919
Precision Triple/Dual Input
UV, OV and Negative
Voltage Monitor
U
DESCRIPTIO
FEATURES
The LTC®2919 is a triple/dual input monitor intended for a
variety of system monitoring applications. Polarity selec-
tion and a buffered reference output allow the LTC2919 to
monitor positive and negative supplies for undervoltage
(UV) and overvoltage (OV) conditions.
■
Two Low Voltage Adjustable Inputs (0.5V)
■
Accurate UVLO Provides a Third Monitor Input
■
Open-Drain RST, OUT1 and OUT2 Outputs
Pin Selectable Input Polarity Allows Negative, UV
■
and OV Monitoring
Guaranteed Threshold Accuracy: 1.5ꢀ
■
The two adjustable inputs have a nominal 0.5V threshold,
featuring tight 1.5% threshold accuracy over the entire
operating temperature range. Glitch filtering ensures out-
puts operate reliably without false triggering. An accurate
threshold at the V pin provides a third input supply
monitor for a 2.5V, 3.3V or 5V supply.
■
6.5V Shunt Regulator for High Voltage Operation
■
Low 50μA Quiescent Current
■
Buffered 1V Reference for Negative Supply Offset
■
Input Glitch Rejection
Adjustable Reset Timeout Period
CC
■
■
Selectable Internal Timeout Saves Components
■
■
Two independent output pins indicate the status of each
adjustable input. A third common output provides a
configurable reset timeout that may be set by an accu-
rate internal 200ms timer, programmed with an external
capacitor, or disabled for a fast response. A three-state
input pin sets the input polarity of each adjustable input
without requiring any external components.
Outputs Guaranteed Low With V = 0.5V
CC
Space Saving 10-Lead 3mm × 2mm DFN and MSOP
Packages
U
APPLICATIO S
■
Desktop and Notebook Computers
■
Network Servers
The LTC2919 provides a highly versatile, precise, space-
conscious, micropower solution for supply monitoring.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 6949965, 7292076.
■
Core, I/O Monitor
Automotive
■
U
TYPICAL APPLICATIO
3.3V UV/OV (Window) Monitor Application with
200ms Internal Timeout (3.3V Logic Out)
SEL Pin Connection for Input Polarity
Combinations
3.3V
POLARITY
0.1μF
V
CC
453k
10k
ADJ1
+
ADJ2
+
SEL PIN
LTC2919–2.5
10k
ADJ1
OUT1
OUT2
RST
UV
V
CC
10k
10.7k
76.8k
REF
OV
FAULT
OPEN
GND
ADJ2
SEL
+
–
TMR
–
–
GND
2919 TA01a
2919f
1
LTC2919
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Terminal Voltages
Operating Temperature Range
V
(Note 3)............................................. –0.3V to 6V
LTC2919C ................................................ 0°C to 70°C
LTC2919I..............................................–40°C to 85°C
LTC2919H .......................................... –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
CC
OUT1, OUT2, RST................................. –0.3V to 7.5V
ADJ1, ADJ2 .......................................... –0.3V to 7.5V
TMR, SEL..................................–0.3V to (V + 0.3V)
CC
Terminal Currents
I
I
(Note 3)...................................................... 10mA
REF
CC
.................................................................... 1mA
MSOP-10.......................................................... 300°C
PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
10
9
SEL
ADJ1
ADJ2
TMR
REF
TOP VIEW
V
SEL
CC
OUT1
OUT2
RST
1
2
3
4
5
10 ADJ1
CC
V
9
8
7
6
ADJ2
TMR
REF
11
8
OUT1
OUT2
RST
7
GND
6
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
DDB PACKAGE
10-LEAD (3mm × 2mm) PLASTIC DFN
T
= 150°C, θ = 120°C/W
JA
JMAX
T
= 150°C, θ = 76°C/W
JA
JMAX
EXPOSED PAD (PIN 11) MAY BE LEFT OPEN OR TIED TO GND
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LDGT
LDGT
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2919CDDB-2.5#PBF
LTC2919IDDB-2.5#PBF
LTC2919HDDB-2.5#PBF
LTC2919CDDB-3.3#PBF
LTC2919IDDB-3.3#PBF
LTC2919HDDB-3.3#PBF
LTC2919CDDB-5#PBF
LTC2919IDDB-5#PBF
LTC2919HDDB-5#PBF
LTC2919CMS-2.5#PBF
LTC2919IMS-2.5#PBF
LTC2919HMS-2.5#PBF
LTC2919CMS-3.3#PBF
LTC2919IMS-3.3#PBF
LTC2919HMS-3.3#PBF
LTC2919CMS-5#PBF
LTC2919IMS-5#PBF
LTC2919CDDB-2.5#TRPBF
LTC2919IDDB-2.5#TRPBF
LTC2919HDDB-2.5#TRPBF
LTC2919CDDB-3.3#TRPBF
LTC2919IDDB-3.3#TRPBF
LTC2919HDDB-3.3#TRPBF
LTC2919CDDB-5#TRPBF
LTC2919IDDB-5#TRPBF
LTC2919HDDB-5#TRPBF
LTC2919CMS-2.5#TRPBF
LTC2919IMS-2.5#TRPBF
LTC2919HMS-2.5#TRPBF
LTC2919CMS-3.3#TRPBF
LTC2919IMS-3.3#TRPBF
LTC2919HMS-3.3#TRPBF
LTC2919CMS-5#TRPBF
LTC2919IMS-5#TRPBF
LTC2919HMS-5#TRPBF
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
LDGT
LDMW
LDMW
LDMW
LDMX
LDMX
LDMX
LTDGS
LTDGS
LTDGS
LTDMT
LTDMT
LTDMT
LTDMV
LTDMV
LTDMV
–40°C to 85°C
–40°C to 125°C
LTC2919HMS-5#PBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2919f
2
LTC2919
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V (LTC2919-2.5), VCC = 3.3V (LTC2919-3.3), VCC = 5V
(LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = floating, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.5
TYP
MAX
UNITS
●
●
V
Operating Supply Voltage
RST, OUT1, OUT2 in Correct State
V
V
CC(MIN)
V
V
Shunt Regulation Voltage
Input Current
I
CC
= 1mA, I = 0
6.0
6.5
7.1
CC(SHUNT)
CC
CC
REF
●
●
I
CC
V
2.175V < V < 6V (C-Grade, I-Grade)
50
50
220
280
μA
μA
CC
2.175V < V < 6V (H-Grade)
CC
V
RT
ADJ Input Threshold
495.0
492.5
500
500
505.0
507.5
mV
mV
●
ΔV
ADJ Hysteresis (Note 4)
ADJ Input Current
TMR = V
1.5
3.5
10.0
mV
RT
CC
●
●
I
V
ADJ
= 0.55V (C-Grade, I-Grade)
= 0.55V (H-Grade)
0
0
15
40
nA
nA
ADJ
V
ADJ
●
●
●
V
V
CC
–10% UVLO Threshold
LTC2919-2.5
LTC2919-3.3
LTC2919-5
2.175
2.871
4.350
2.213
2.921
4.425
2.250
2.970
4.500
V
V
V
CC(UVLO)
ΔV
UVLO Hysteresis (Note 4)
Buffered Reference Voltage
TMR = V
0.3
0.7
2.0
%
CC(UVLO)
CC
V
REF
V
CC
> 2.175V, I =
REF
1mA
0.990
0.985
1.000
1.000
1.010
1.015
V
V
●
●
●
●
●
●
I
I
t
t
TMR Pull-Up Current
V
TMR
= 1V
–1.5
1.5
15
–2.2
2.2
20
–2.9
2.9
27
μA
μA
ms
ms
V
TMR(UP)
TMR Pull-Down Current
Reset Timeout Period, External
Reset Timeout Period, Internal
Timer Disable Voltage
V
TMR
= 1V
TMR(DOWN)
RST(EXT)
RST(INT)
C
= 2.2nF
= 0V
TMR
V
TMR
140
200
280
V
V
TMR
Rising
V
V
V
CC
– 0.10
TMR(DIS)
CC
CC
– 0.40
– 0.20
●
●
●
●
ΔV
Timer Disable Hysteresis
V
Falling
Falling
Rising
40
100
160
mV
V
TMR(DIS)
TMR
V
Timer Internal Mode Voltage
Timer Internal Mode Hysteresis
V
TMR
0.10
40
0.20
100
0.40
160
TMR(INT)
ΔV
TMR(INT)
V
TMR
mV
μs
t
ADJx Comparator Propagation Delay to ADJx Driven Beyond Threshold (V ) by
50
150
800
PROP
RTX
OUT
5mV
X
●
t
V
CC
Undervoltage Detect to RST
V
CC
CC(UVLO)
Less Than UVLO Threshold
50
150
800
μs
UV
(V
) by 1%
●
●
●
V
Output Voltage Low
V
CC
V
CC
V
CC
= 0.5V, I = 5μA
= 1V, I = 100μA
= 3V, I = 2500μA
0
0
0
0.01
0.01
0.10
0.15
0.15
0.30
V
V
V
OL
●
●
I
Output Voltage High Leakage
Output = V (C-Grade, I-Grade)
0
0
1
5
μA
μA
OH
CC
Output = V (H-Grade)
CC
Three-State Input SEL
●
●
V
IL
V
IH
V
Z
Low Level Input Voltage
0
0.4
V
V
V
High Level Input Voltage
1.4
0.8
V
CC
Pin Voltage when Left in Open State
I
= 0μA
0.9
1.0
SEL
2919f
3
LTC2919
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V (LTC2919-2.5), VCC = 3.3V (LTC2919-3.3), VCC = 5V
(LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = floating, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5
UNITS
μA
●
●
I
I
Allowable Leakage When Open
SEL Input Current
SEL(Z)
SEL
SEL = V or SEL = GND
17
25
μA
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
which exceeds 6V may exceed the rated terminal current. Operation
from higher voltage supplies requires a series dropping resistor. See
Applications Information.
Note 4: Threshold voltages have no hysteresis unless the part is in
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
comparator mode. Hysteresis is one-sided, affecting only invalid-to-valid
transitions. See Applications Information.
Note 3: V maximum pin voltage is limited by input current. Since the
CC
V
pin has an internal 6.5V shunt regulator, a low impedance supply
CC
U W
T = 25°C unless otherwise noted.
A
TYPICAL PERFOR A CE CHARACTERISTICS
ADJ Threshold Voltage
vs Temperature
VCC UVLO Threshold Variation
vs Temperature
REF Output Voltage
vs Temperature
1.5
1.0
0.5
0
508
1.015
1.010
1.005
1.000
I
= 0A
REF
506
504
502
500
498
496
494
–0.5
–1.0
–1.5
0.995
0.990
0.985
492
50
100 125 150
–50 –25
0
25
75
–25
0
50 75 100 125 150
25
TEMPERATURE (°C)
–50
50
100 125 150
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
2919 G02
2919 G01
2919 G03
Quiescent Supply Current
vs Temperature
REF Output Load Regulation
REF Output Line Regulation
0.6
0.4
90
80
70
60
50
40
30
20
0.6
0.4
I
= 0A
V
= 2.5V
REF
ADJ1 = 0.55V
ADJ2 = 0.45V
SEL = OPEN
CC
T
A
= 150°C
T
= 150°C
A
0.2
0.0
0.2
0.0
V
= 5V
V
= 3.3V
CC
CC
T
= 25°C
T
= 25°C
A
A
T
A
= 125°C
T
= 125°C
A
V
= 2.5V
CC
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
T
= –40°C
T
= –40°C
A
A
2
3
4
5
6
–25
0
50 75 100 125 150
25
TEMPERATURE (°C)
–50
–1
–0.5
0
0.5
1
SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
2919 G05
2919 G06
2919 G04
2919f
4
LTC2919
U W
TA = 25°C unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
Reset Timeout Period
vs Capacitance
Reset Timeout Period
vs Temperature
Propagation Delay vs Overdrive
700
600
500
400
300
200
100
0
260
240
220
200
10000
1000
100
INTERNAL
EXTERNAL, C
= 22nF
TMR
180
160
140
10
1
0.1
1
10
100
50
100 125 150
–50 –25
0
25
75
0.1
1
10
100
(nF)
1000
TMR PIN CAPACITANCE, C
GLITCH PERCENTAGE PAST THRESHOLD (%)
TEMPERATURE (°C)
TMR
2919 G07
2919 G08
2919 G09
OUT1, OUT2, RST Output Voltage
vs VCC
Shunt Regulation Voltage
vs Temperature
Shunt Regulation Voltage
vs Supply Current
5
4
3
2
1
0
7.0
6.8
6.6
6.4
6.2
6.0
7.6
7.2
6.8
T
= 25°C
ADJ1 = 0.55V
ADJ2 = 0.45V
SEL = OPEN
A
10k PULL-UP R TO V
CC
I
= 10mA
CC
I
= 1mA
CC
I
= 100μA
LTC2919-2.5
LTC2919-3.3
LTC2919-5
CC
6.4
6.0
0
1
2
3
4
5
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
0.01
0.1
1
10
100
SUPPLY VOLTAGE, V (V)
SUPPLY CURRENT, I (mA)
CC
CC
2919 G11
2919 G12
2919 G10
OUT1, OUT2, RST Output Voltage
vs VCC
OUT1, OUT2, RST Pull-Down
Current vs VCC
OUT1, OUT2, RST Pull-Down
Current vs VCC
6
5
1
0.1
0.4
0.3
0.2
0.1
ADJ1 = 0.45V
ADJ2 = 0.55V
SEL = OPEN
OUTPUT AT 150mV
OUTPUT AT 50mV
4
3
V
CC
OUTPUT AT 150mV
OUTPUT AT 50mV
0.01
WITH 10k PULL-UP
2
1
0
0.001
WITH 100k PULL-UP
0
0.0001
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
SUPPLY VOLTAGE, V (V)
SUPPLY VOLTAGE, V (V)
CC
CC
SUPPLY VOLTAGE, V (V)
CC
2919 G15
2919 G13
2919 G14
2919f
5
LTC2919
U W
TA = 25°C unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
OUT1, OUT2, RST VOL vs Output
Sink Current
I
SEL vs Temperature
ISEL vs Temperature
–10
–12
–14
–16
–18
–20
–22
22
1.0
0.8
0.6
0.4
0.2
0
SEL = V
CC
SEL = GND
V
= 3V
CC
NO PULL-UP R
20
18
16
14
12
10
T
A
= 150°C
T
A
= 25°C
T
= 125°C
A
T
A
= –40°C
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
5
10
15
20
25
30
OUTPUT SINK CURRENT (mA)
2919 G17
2919 G18
2919 G16
U
U
U
(MSOP/DFN Package)
PI FU CTIO S
SEL (Pin 1): Input Polarity Select Three-State Input. Con-
Requires an external pull-up resistor and may be pulled
nect to V , GND or leave unconnected in open state to
above V .
CC
CC
select one of three possible input polarity combinations
(refer to Table 1).
GND (Pin 6): Device Ground.
REF (Pin 7): Buffered Reference Output. 1V nominal
reference used for the offset of negative-monitoring ap-
plications. The buffered reference can source and sink
up to 1mA. The reference can drive a capacitive load of
up to 1000pF. Larger capacitance may degrade transient
performance.Thispindoesnotrequireabypasscapacitor,
nor is one recommended. Leave open if unused.
V
CC
(Pin 2): Power Supply. Bypass this pin to ground with
a 0.1ꢀF (or greater) capacitor. Operates as a direct supply
input for voltages up to 6V. Operates as a shunt regulator
for supply voltages greater than 6V and should have a
resistor between this pin and the supply to limit V input
CC
current to no greater than 10mA. When used without a
current-limiting resistor, pin voltage must not exceed 6V.
TMR (Pin 8): Reset Timeout Control. Attach an external
UVLO options allow V to be used as an accurate third
CC
capacitor (C ) to GND to set a reset timeout period
TMR
fixed -10% UV supply monitor.
of 9ms/nF. A low leakage ceramic capacitor is recom-
mended for timer accuracy. Capacitors larger than 1ꢀF
(9 second timeout) are not recommended. See Applica-
tions Information for further details. Leaving this pin open
generates a minimum timeout of approximately 400ꢀs. A
2.2nF capacitor will generate a 20ms timeout. Tying this
pin to ground will enable the internal 200ms timeout. Ty-
OUT1 (Pin 3): Open-Drain Logic Output 1. Asserts low
when positive polarity ADJ1 voltage is below threshold or
negativepolarityADJ1voltageisabovethreshold.Requires
an external pull-up resistor and may be pulled above V .
CC
OUT2 (Pin 4): Open-Drain Logic Output 2. Asserts low
when positive polarity ADJ2 voltage is below threshold
or negative polarity ADJ2 voltage is above threshold.
Requires an external pull-up resistor and may be pulled
ing this pin to V will disable the reset timer and put the
CC
part in comparator mode. Signals from the comparator
outputs will then go directly to RST.
above V .
CC
RST (Pin 5): Open-Drain Inverted Reset Logic Output.
Asserts low when any positive polarity input voltage is
below threshold or any negative polarity input voltage is
ADJ2 (Pin 9): Adjustable Voltage Input 2. Input to volt-
age monitor comparator 2 (0.5V nominal threshold). The
polarity of the input is selected by the state of the SEL
pin (refer to Table 1). Tie to GND if unused (with SEL =
above threshold or V is below UVLO threshold. Held
CC
low for a timeout period after all voltage inputs are valid.
GND or Open).
2919f
6
LTC2919
U
U
U
PI FU CTIO S (MSOP/DFN Package)
Exposed Pad (Pin 11, DFN Only): The Exposed Pad may
beleftunconnected.Forbetterthermalcontact,tietoaPCB
trace. This trace must be grounded or unconnected.
ADJ1 (Pin 10): Adjustable Voltage Input 1. Input to volt-
age monitor comparator 1 (0.5V nominal threshold). The
polarity of the input is selected by the state of the SEL
pin (refer to Table 1). Tie to REF if unused (with SEL =
V
or Open).
CC
W
BLOCK DIAGRA
SEL
V
CC
V
CC
6.5V
THREE-STATE
DECODE
OUT1
TMR
CONTROL 2
CONTROL 1
ADJ1
+
–
V
CC
THREE-STATE
DECODE
ADJUSTABLE
PULSE
RST
GENERATOR
+
–
EN
GND
200ms
PULSE
GENERATOR
OUT2
ADJ2
+
–
SEL CONTROL 1 CONTROL 2
+
500mV
GND
OPEN
V
CC
H
L
L
H
H
L
–
+
–
REF
+
–
1.000V
CONTROL = H = NEGATIVE POLARITY
CONTROL = L = POSITIVE POLARITY
2919 BD
WU
W
TI I G DIAGRA S
Positive Polarity Input Timing
V
RT
+ ΔV
RT
V
ADJ
V
RT
t
t
RST
PROP
1V
RST
OUT
t
PROP
t
PROP
1V
Negative Polarity Input Timing
V
RT
V
ADJ
V
RT
– ΔV
RT
t
PROP
t
RST
RST
OUT
1V
1V
t
PROP
t
PROP
UVLO Timing
V
V
V
+ ΔV
CC CC(UVLO)
CC(UVLO) CC(UVLO)
t
UV
t
RST
RST
OUT
1V
1V
NOTES:
RT
Comparator Mode
t
t
PROP
PROP
1. ΔV AND ΔV
= 0, except in
CC(UVLO)
2. IN COMPARATOR MODE, t .
= t
2919 TD
RST PROP
2919f
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APPLICATIO S I FOR ATIO
Shunt Regulator
The LTC2919 is a low power, high accuracy triple/dual
supplymonitorwithtwoadjustableinputsandanaccurate
UVLO that can monitor a third supply. Reset timeout may
be selected with an external capacitor, set to an internally
generated 200ms, or disabled entirely.
The LTC2919 contains an internal 6.5V shunt regulator on
the V pin to allow operation from a high voltage supply.
CC
To operate the part from a supply higher than 6V, the V
CC
pin must have a current-limiting series resistor, R , to
CC
the supply. This resistor should be sized according to the
following equation:
The three-state polarity select pin (SEL) chooses one of
three possible polarity combinations for the adjustable
input thresholds, as described in Table 1. An individual
output is released when its corresponding ADJ input is
valid (above threshold if configured for positive polarity,
below threshold if configured for negative polarity).
VS(MAX) – 6.2V
10mA
VS(MIN) – 6.8V
≤ RCC
≤
200µA +IREF
whereV
andV
S(MAX)
aretheoperatingminimumand
S(MIN)
Both input voltages (V
CC
and V
) must be valid and
maximum of the supply, and I is the maximum current
ADJ1
ADJ2
REF
V
above the UVLO threshold for longer than the reset
the user expects to draw from the reference output.
timeout period before RST is released. The LTC2919 as-
serts the reset output during power-up, power-down and
brownout conditions on any of the voltage inputs.
Asanexample,consideroperationfromanautomobilebat-
terywhichmightdipaslowas10Vorspiketo60V.Assume
thattheuserwillbedrawing100ꢀAfromthereference.We
must then pick a resistance between 5.4k and 10.7k.
Power-Up
When the V pin is connected to a low impedance supply,
CC
The LTC2919 uses proprietary low voltage drive circuitry
it is important that the supply voltage never exceed 6V,
or the shunt regulator may begin to draw large currents.
Some supplies may have a nominal value sufficiently
close to the shunt regulation voltage to prevent sizing of
the resistor according to the above equation. For such
supplies, a 470Ω series resistor may be used.
for the RST, OUT1 and OUT2 pins which holds them low
with V as low as 200mV. This helps prevent indeter-
CC
minate voltages from appearing on the outputs during
power-up.
In applications where the low voltage pull-down capabil-
ity is important, the supply to which the external pull-up
resistor connects should be the same supply which pow-
ers the part. Using the same supply for both ensures that
RST, OUT1 and OUT2 never float above 200mV during
power-up, as the pull-down ability of the pin will then
increase as the required pull-down current to maintain a
logic low increases.
Adjust Polarity Selection
TheexternalconnectionoftheSELpinselectsthepolarities
of the LTC2919 adjustable inputs. SEL may be connected
to GND, connected to V or left unconnected during
CC
normal operation. When left unconnected, the maximum
leakage allowable from the pin is 5μA. Table 1 shows
the three possible selections of polarity based on SEL
connection.
OnceV passestheUVLOthreshold,polarityselectionand
CC
timer initialization will occur. If the monitored ADJ input is
valid, the corresponding OUT will be released. When both
ADJ1 and ADJ2 are valid, the appropriate timeout delay
will begin, after which RST will be released.
Table 1. Voltage Threshold Selection
ADJ1 INPUT
ADJ2 INPUT
SEL
Positive Polarity
(+) UV or (–) OV
Positive Polarity
(+) UV or (–) OV
V
CC
Power-Down
Positive Polarity
(+) UV or (–) OV
Negative Polarity
(–) UV or (+) OV
Open
Onpower-down,onceV dropsbelowtheUVLOthreshold
CC
Negative Polarity
(–) UV or (+) OV
Negative Polarity
(–) UV or (+) OV
or either V becomes invalid, RST asserts logic low. V
Ground
ADJ
CC
of at least 0.5V guarantees a logic low of 0.15V at RST.
Note: Open = open circuit or driven by a three-state buffer in high impedance
state with leakage current less than 5ꢀA.
2919f
8
LTC2919
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APPLICATIO S I FOR ATIO
Iftheuser’sapplicationrequires,theSELpinmaybedriven
opposite is true for a “positive polarity” input (–OV or
+UV). These polarity definitions are also shown in Table
1. For purposes of this data sheet, a negative voltage is
considered “undervoltage” if it is closer to ground than it
should be (e.g., –4.3V for a –5V supply).
using a three-state buffer which satisfies the V , V and
IL IH
leakage conditions of this three-state input pin.
If the state of the SEL pin configures a given input as
“negative polarity,” the voltage at that ADJ pin must be
below the trip point (0.5V nominal), or the corresponding
OUT and RST output will be pulled low. Conversely, if a
giveninputisconfiguredas“positivepolarity”,theADJpin
voltage must be above the trip point or the corresponding
OUT and RST will assert low.
Proper configuration of the SEL pin and setting of the
trip-points via external resistors allows for any two fault
conditions to be detected. For example, the LTC2919 may
monitor two supplies (positive, negative or one of each)
for UV or for OV (or one UV and one OV). It may also
monitor a single supply (positive or negative) for both UV
and OV. Tables 2a and 2b show example configurations
for monitoring possible combinations of fault condition
and supply polarity.
Thus, a “negative polarity” input may be used to deter-
mine whether a monitored negative voltage is smaller in
absolute value than it should be (–UV), or a monitored
positive voltage is larger than it should be (+OV). The
Table 2a. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5ꢀ Tolerance and
Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity.
SEL = V
SEL = GND
CC
15V
5V
–15V
–5V
R
R
R
R
N2B
137k
P2A
P2B
N2A
309k
115k
309k
ADJ1 OUT1
ADJ2 OUT2
UV (15V)
UV (5V)
ADJ1 OUT1
ADJ2 OUT2
UV (–15V)
UV (–5V)
R
R
R
R
N1B
13.3k
P1A
P1B
N1A
11.5k
13.7k
10.7k
REF
SEL
REF
SEL
2 Positive UV
2 Negative UV
–15V
–5V
15V
5V
R
R
R
R
P2B
133k
N2A
N2B
P2A
1.02M
137k
619k
ADJ1 OUT1
ADJ2 OUT2
OV (–15V)
OV (–5V)
ADJ1 OUT1
ADJ2 OUT2
OV (15V)
0V (5V)
R
R
R
R
P1B
13.7k
N1A
N1B
P1A
30.9k
11.8k
20k
REF
SEL
REF
SEL
2 Negative OV
2 Positive OV
15V
–15V
15V
–15V
R
R
R
R
N2
309k
P2
N2
P2
309k
1.02M
619k
ADJ1 OUT1
ADJ2 OUT2
UV (15V)
ADJ1 OUT1
ADJ2 OUT2
OV (15V)
OV (–15V)
UV (–15V)
R
R
R
R
N1
10.7k
P1
N1
P1
11.5k
30.9k
20k
REF
SEL
REF
SEL
1 Positive UV, 1 Negative OV
1 Positive OV, 1 Negative UV
2919f
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LTC2919
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APPLICATIO S I FOR ATIO
Table 2b. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5ꢀ Tolerance and
Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity.
SEL OPEN
15V
–15V
R
R
N6
1.02M
P6
2.37M
ADJ1 OUT1
ADJ2 OUT2
UV
OV
ADJ1 OUT1
ADJ2 OUT2
OV
UV
R
R
N5
4.02k
P5
10.7k
R
P4
R
N4
30.9k
76.8k
REF
SEL
REF
SEL
1 Positive UV and OV
1 Negative UV and OV
15V
–15V
–15V
15V
R
R
R
R
P2
619k
P2
N2
N2
309k
309k
1.02M
ADJ1 OUT1
ADJ2 OUT2
UV (15V)
ADJ1 OUT1
ADJ2 OUT2
OV (–15V)
OV (15V)
UV (–15V)
R
R
R
R
P1
20k
P1
N1
N1
11.5k
10.7k
30.9k
REF
SEL
REF
SEL
1 Positive UV, 1 Negative UV
1 Negative OV, 1 Positive OV
15V
5V
–15V
–5V
R
R
P2B
133k
R
R
N2B
137k
P2A
N2A
309k
1.02M
ADJ1 OUT1
ADJ2 OUT2
UV (15V)
OV (5V)
ADJ1 OUT1
ADJ2 OUT2
OV (–15V)
UV (–5V)
R
R
R
R
P1A
P1B
N1A
N1B
11.5k
13.7k
30.9k
13.3k
REF
SEL
REF
SEL
1 Positive UV, 1 Positive OV
1 Negative UV, 1 Negative OV
Adjust Input Trip Point
Topreventnuisanceresets,thesupervisorthresholdmust
be guaranteed to lie outside the power supply tolerance
band. To ensure that the threshold lies outside the power
supplytolerancerange,thenominalthresholdmustlieout-
side that range by the monitor’s accuracy specification.
The trip threshold for the supplies monitored by the
adjustable inputs is set with an external resistor divider,
allowing the user complete control over the trip point.
Selection of this trip voltage is crucial to the monitoring
of the system.
All three of the LTC2919 inputs (ADJ1, ADJ2, V UVLO)
CC
have the same maximum threshold accuracy of 1.5% of
theprogrammednominalinputvoltage(overthefulloperat-
ingtemperaturerange). Therefore, usingtheLTC2919, the
typical 10% UV threshold is at 11.5% below the nominal
inputvoltagelevel.Fora5Vinput,thethresholdisnominally
4.425V. With 1.5% accuracy, the trip threshold range is
Any power supply has some tolerance band within which
it is expected to operate (e.g., 5V 10%). It is generally
undesirablethatasupervisorissuearesetwhenthepower
supply is inside this tolerance band. Such a “nuisance”
reset reduces reliability by preventing the system from
functioning under normal conditions.
2919f
10
LTC2919
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APPLICATIO S I FOR ATIO
4.425V 75mV over temperature (i.e., 10% to 13% below
5V). The monitored system must thus operate reliably
down to 4.35V or 13% below 5V over temperature.
it may be added externally. See 48V Telecom UV/OV with
Hysteresis Applications on page 14 for an example.
Selecting External Resistors
The above discussion is concerned only with the DC value
of the monitored supply. Real supplies also have relatively
high frequency variations from sources such as load
transients, noise and pickup.
In a typical positive supply monitoring application, the
ADJx pin connects to a tap point on an external resistive
divider between a positive voltage being monitored and
ground, as shown in Figure 1.
The LTC2919 uses two techniques to combat spurious
outputs toggling from high frequency variation. First,
the timeout period helps prevent high frequency varia-
Whenmonitoringanegativesupply,theADJxpinconnects
to a tap point on a resistive divider between the negative
voltagebeingmonitoredandthebufferedreference(REF),
as shown in Figure 2.
tion whose frequency is above 1/ t
from appearing at
RST
the RST output. Second, the propagation delay versus
overdrive function filters short glitches before the OUT1,
OUT2 toggling or RST pulling low.
V
MON
When an ADJ becomes invalid, the corresponding OUT
and RST pin assert low. When the supply recovers past
the valid threshold, the reset timer starts (assuming it is
not disabled) and RST does not go high until it finishes.
If the supply becomes invalid any time during the timeout
period, the timer resets and starts fresh when the supply
next becomes valid.
R
P2
ADJx
0.5V
+
–
R
P1
+
–
2919 F01
To reduce sensitivity of short glitches from toggling the
outputpins,thecomparatoroutputsgothroughalowpass
filterbeforetriggeringtheoutputlogic.Anytransientatthe
input of a comparator needs to be of sufficient magnitude
and duration to pass the filter before it can change the
monitor state.
Figure 1. Setting Positive Supply Trip Point
REF
R
R
N1
ADJx
+
–
N2
The combination of the reset timeout and comparator
filtering prevents spurious changes in the output state
without sacrificing threshold accuracy. If further supply
glitch immunity is needed, the user may place an external
capacitor from the ADJ input to ground. The resultant RC
lowpass filter with the resistor divider will further reject
high frequency components of the supply, at the cost of
slowing the monitor’s response to fault conditions.
V
MON
+
0.5V
–
2919 F02
Figure 2. Setting Negative Supply Trip Point
Normally the user will select a desired trip voltage based
on their supply and acceptable tolerances, and a value of
A common solution to the problem of spurious reset is
to introduce hysteresis around the nominal threshold.
However, this hysteresis degrades the effective accuracy
of the monitor and increases the range over which the
system must operate. The LTC2919 therefore does not
have hysteresis, except in comparator mode (by tying
R
or R based on current draw. Current used by the
N1
P1
resistive divider will be approximately:
0.5V
RP1
0.5V
RN1
I =
.OR =
TMR pin to V ). If hysteresis is desired in other modes,
CC
2919f
11
LTC2919
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APPLICATIO S I FOR ATIO
To minimize errors arising from ADJ input bias and to
REF
minimize loading on REF choose resistor R (for positive
P1
ADJ1
LOGIC
&
OPEN
DRAIN
MOSFET
+
–
supplymonitoring)orR (fornegativesupplymonitoring)
N1
OUT1
OUT2
OV
UV
in the range of 5k to 100k.
R
R
N4
For a positive-monitoring application, R is then chosen
P2
N5
ADJ2
0.5V
by:
LOGIC
&
OPEN
DRAIN
MOSFET
+
–
R
N6
R
= R (2V
– 1)
P2
P1
TRIP
–V
MON
+
For a negative-monitoring application:
–
R
= R (1 – 2V
)
N2
N1
TRIP
2919 F04
Figure 4. Setting UV and OV Trip Point for a Negative Supply
Note that the value V
application.
should be negative for a negative
TRIP
Forexample,considermonitoringa–5Vsupplyat 10%.For
The LTC2919 can also be used to monitor a single supply
for both UV and OV. This may be accomplished with three
resistors, instead of the four required for two independent
this supply application: V = –5.575V and V = –4.425V.
OV UV
Suppose we wish to consume about 5ꢀA in the divider, so
R =100k.WethenfindR =21.0k,R =1.18M(nearest
N4
N5
N6
supplies.ConfigurationsareshowninFigures3and4.R
1% standard values have been chosen).
P4
or R may be chosen as is R or R above.
N4
P1
N1
V
Monitoring/UVLO
CC
For a given R , monitoring a positive supply:
P4
TheLTC2919containsanaccuratethird-10%undervoltage
VOV – VUV
RP5 = RP4
monitor on the V pin. This monitor is fixed at a nominal
CC
VUV
11.5% below the V specified in the part number. The
CC
standard part (LTC2919-2.5) is configured to monitor a
2.5V supply (UVLO threshold of 2.213V), but versions
to monitor 3.3V and 5.0V (UVLO of 2.921V and 4.425V,
respectively) are available.
VOV
VUV
RP6 = RP4 2V – 1
(
)
UV
For monitoring a negative supply with a given R :
N4
For applications that do not need V monitoring, the
CC
VUV – VOV
RN5 = RN4
2.5V version should be used, and the UVLO will simply
1– VUV
guarantee that the V is above the minimum required for
CC
proper threshold and timer accuracy before the timeout
begins.
1– VOV
1– VUV
RN6 = RN4 1– 2V
(
)
UV
Setting the Reset Timeout
ADJ1
LOGIC
&
OPEN
DRAIN
MOSFET
+
–
V
MON
OUT1
OUT2
RST goes high after a reset timeout period set by the TMR
UV
OV
R
pin when the V and ADJ inputs are valid. This reset
P6
CC
timeout may be configured in one of three ways: internal
200ms,programmedbyexternalcapacitorandnotimeout
(comparator mode).
R
R
P5
ADJ2
0.5V
LOGIC
&
OPEN
DRAIN
MOSFET
+
–
P4
In externally-controlled mode, the TMR pin is connected
byacapacitortoground.Thevalueofthatcapacitorallows
for selection of a timeout ranging from about 400ꢀs to 9
seconds. See the following section for details.
+
–
2919 F03
Figure 3. Setting UV and OV Trip Point for a Positive Supply
2919f
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LTC2919
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APPLICATIO S I FOR ATIO
If the user wishes to avoid having an external capacitor,
the TMR pin should be tied to ground, switching the part
to an internal 200ms timer.
Maximum length of the reset timeout is limited by the
ability of the part to charge a large capacitor on start-up.
Initially, with a large (discharged) capacitor on the TMR
pin, the part will assume it is in internal timer mode (since
the pin voltage will be at ground). If the 2.2ꢀA flowing
out of the TMR pin does not charge the capacitor to the
ground-sense threshold within the first 200ms after sup-
plies become good, the internal timer cycle will complete
and RST will go high too soon.
If the user requires a shorter timeout than 400ꢀs, or
wishes to perform application-specific processing of the
reset output, the part may be put in comparator mode by
tying the TMR pin to V . In comparator mode, the timer
CC
is bypassed and comparator outputs go straight to the
reset output.
This imposes a practical limit of 1ꢀF (9 second timeout) if
the length of timeout during power-up needs to be longer
than 200ms. If the power-up timeout is not important,
larger capacitors may be used, subject to the limitation
thatthecapacitorleakagecurrentmustnotexceed500nA,
or the function of the timer will be impaired.
The current required to hold TMR at ground or V is
CC
about 2.2ꢀA. To force the pin from the floating state to
ground or V may require as much as 100ꢀA during the
CC
transition.
When the part is in comparator mode, one of the two
means of preventing false reset has been removed, so
a small amount of one-sided hysteresis is added to the
inputs to prevent oscillation as the monitored voltage
passes through the threshold. This hysteresis is such
thatthevalid-to-invalidtransitionthresholdisunchanged,
but the invalid-to-valid threshold is moved by about
0.7%. Thus, when the ADJ input polarity is positive,
the threshold voltage is 500mV nominal when the in-
put is above 500mV. As soon as the input drops below
500mV, the threshold moves up to 503.5mV nominal.
Conversely, when configured as a negative-polarity input,
the threshold is 500mV when the input is below 500mV,
and switches to 496.5mV when the input goes above
500mV.
Output Pins Characteristics
The DC characteristics of the OUT1, OUT2 and RST pull-
down strength are shown in the Typical Performance
Characteristics section. OUT1, OUT2 and RST are open-
drain pins and thus require external pull-up resistors to
the logic supply. They may be pulled above V , providing
CC
the absolute maximum rating of the pin are observed.
As noted in the discussion of power up and power down,
the circuits that drive OUT1, OUT2 and RST are powered
by V . During a fault condition, V of at least 0.5V
CC
CC
guarantees a V of 0.15V.
OL
The open-drain nature of the RST pin allows for wired-OR
connection of several LTC2919s to monitor more than two
supplies(seeTypicalApplications). Otherlogicwithopen-
drain outputs may also connect to the RST line, allowing
other logic-determined conditions to issue a reset.
The comparator mode feature is enabled by directly short-
ing the TMR pin to the V pin. Connecting the pin to any
CC
other voltage may have unpredictable results.
Selecting the Reset Timing Capacitor
Connecting a capacitor, C
, between the TMR pin and
RST
TMR
ground sets the reset timeout, t . The following formula
approximatesthevalueofcapacitorneededforaparticular
timeout:
C
= t
• 110 [pF/ms]
TMR
RST
Leaving the TMR pin open with no external capacitor
generates a reset timeout of approximately 400ꢀs.
2919f
13
LTC2919
U
TYPICAL APPLICATIO S
Six Supply Undervoltage Monitor with 2.5V Reset Output and 20ms Timeout
15V
5V
–5V
SYSTEM
–15V
3.3V
2.5V
C
C
BYP2
100nF
BYP1
100nF
R
PU1
10k
R
PU5
10k
R
PU4
10k
R
PU2
10k
R
PU3
10k
SYSTEM_OK
R
R
N2A
137k
P2A
115k
V
V
CC
CC
ADJ1
SEL
SEL
ADJ1
R
N2B
309k
R
N1A
13.3k
R
P1A
13.7k
R
P2B
309k
LTC2919-2.5
LTC2919-3.3
RST
REF
REF
RST
R
N1B
10.7k
R
P1B
11.5k
–5V_OK
5V_OK
ADJ2
TMR
OUT1
OUT2
OUT1
OUT2
ADJ2
TMR
2919 TA02
–15V_OK
15V_OK
C
TMR1
2.2nF
C
TMR2
2.2nF
GND
GND
48V Telecom UV/OV Monitor with Hysteresis
V
IN
36V TO 72V
SYSTEM
5V
R
C
BYP
CC
27k 100nF
0.25W
R
R
P2B
1.91M
P2A
1.43M
R
P2A2
M2
169k
R
PU3
10k
V
CC
R
PU1
10k
ADJ1
RST
V
: 43.3V
: 38.7V
UV(RISING)
PWRGD
V
UV(FALLING)
LTC2919-2.5
R
PU2
10k
V
: 71.6V
OV(RISING)
: 70.2V
OUT1
ADJ2
V
OV(FALLING)
UV
R
R
R
P1B2
681k
P1A
P1B
18.7k
13.7k
REF
SEL
OUT2
TMR
OV
M1
GND
M1, M2: FDG6301N OR SIMILAR
2919 TA03
12V UV Monitor Powered from
12V, 20ms Timeout (1.8V Logic Out)
C
BYP
R
CC
10k
100nF
1.8V
12V
R
PU3
10k
R
P2
V
CC
1.07M
10k*
R
ADJ1
RST
R
PU1
10k
MANUAL
RESET
R
R
P1
LTC2919-2.5
PU2
49.9k
10k
PUSHBUTTON
REF
OUT1
R
N1
N2
12V_OK
10.7k
249k
–12V
ADJ2
SEL
OUT2
TMR
–12V_OK
C
TMR
2.2nF
GND
2919 TA01b
*OPTIONAL FOR ESD
2919f
14
LTC2919
U
PACKAGE DESCRIPTIO
DDB Package
10-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1722 Rev Ø)
R = 0.115
0.64 0.05
(2 SIDES)
0.40 0.10
10
3.00 0.10
(2 SIDES)
TYP
6
R = 0.05
TYP
0.70 0.05
2.55 0.05
1.15 0.05
2.00 0.10
PIN 1 BAR
TOP MARK
PIN 1
(2 SIDES)
R = 0.20 OR
0.25 × 45°
CHAMFER
(SEE NOTE 6)
PACKAGE
OUTLINE
0.64 0.05
(2 SIDES)
0.25 0.05
5
1
(DDB10) DFN 0905 REV Ø
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
0.50 BSC
2.39 0.05
(2 SIDES)
2.39 0.05
(2 SIDES)
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
0.889 ± 0.127
(.035 ± .005)
10 9
8
7 6
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
5.23
(.206)
MIN
4.90 ± 0.152
(.193 ± .006)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
2919f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2919
U
TYPICAL APPLICATIO
Powered from 12V, +5VOUT is Sequenced to Start-up First,
Followed by –5VOUT, with 5V UV Monitor, 200ms Timeout
+12V
R
4.7k
CC
C
0.1μF
BYP
+5V
V
CC
R
115k
P2
LTC2919-2.5
R
10k
PU2
+5V
DC/DC
ADJ1
SEL
CONVERTER
R
13.7k
P1
PWRGD
R
10k
PU3
REF
OUT2
R
13.3k
N1
R
N2
137k
SYS_RESET
–5V
DC/DC
CONVERTER
RST
ADJ2
OUT1
TMR
SHDN
2919 TA06
GND
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LT 0208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTC2919CDDB-3.3#TRPBF
LTC2919 - Precision Triple/Dual Input UV, OV and Negative Voltage Monitor; Package: DFN; Pins: 10; Temperature Range: 0°C to 70°C
Linear
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