LTC2925IGN#TRPBF [Linear]
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| 型号： | LTC2925IGN#TRPBF |
| 厂家： | 
Linear |
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LTC2925
Multiple Power Supply
Tracking Controller with
Power Good Timeout
U
DESCRIPTIO
FEATURES
■
Flexible Power Supply Tracking Up and Down
The LTC®2925 provides a simple solution to power supply
tracking and sequencing requirements. By selecting a few
resistors, the supplies can be configured to ramp-up and
ramp-down together or with voltage offsets, time delays
or different ramp rates.
■
Power Supply Sequencing
■
Supply Stability Is Not Affected
■
Controls Three Supplies Without Series FETs
Controls an Optional Fourth Supply With a
■
Series FET
Electronic Circuit Breaker
The LTC2925 controls the outputs of three independent
supplies without inserting any pass element losses. For
systems that require a fourth supply, or when a supply
does not allow direct access to its feedback resistors, one
supply can be controlled with a series FET. When the FET
is used, an internal remote sense switch compensates for
thevoltagedropacrosstheFETandcurrentsenseresistor,
and an electronic circuit breaker provides protection from
short-circuit conditions.
■
■
Remote Sense Switch Compensates for Voltage
Drop Across a Series FET
■
Supply Shutdown Outputs
■
FAULT Output
■
Adjustable Power Good Timeout
■
Available in Narrow 24-Lead SSOP and Tiny 24-Lead
QFN Packages
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APPLICATIO S
The LTC2925 also includes a power good timeout feature
that turns off the supplies if an external supply monitor
fails to indicate that the supplies have entered regulation
within an adjustable time-out period.
■
VCORE and VI/O Supply Tracking
■
Microprocessor, DSP and FPGA Supplies
■
Servers
Communication Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
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TYPICAL APPLICATIO S
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1µF
3.3V
2.5V
0.1µF
10Ω
SUPPLY
1V/DIV
MONITOR
1.8V
154k
100k
1.5V
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
3.3V
IN
SD1
RUN/SS
DC/DC
REMOTE
STATUS
FB1
FB = 1.235V OUT
1.8V
V
V
IN
SLAVE1
2925 TA02a
10ms/DIV
10k
10k
16.5k
35.7k
3.3V
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
IN
2.5V
SLAVE2
OUT
FAULT
RAMPBUF
3.3V
2.5V
1.8V
1.5V
1.65k
13k
88.7k
41.2k
TRACK1
TRACK2
3.3V
IN
1V/DIV
88.7k
41.2k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
86.6k
100k
OUT
1.5V
SLAVE3
TRACK3
GND SCTMR
SDTMR
0.082µF
PGTMR
0.82µF
86.6k
100k
0.47µF
2925 TA02b
10ms/DIV
2925 TA01
2925f
1
LTC2925
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
GATE (Note 3) ........................................ –0.3 to 11.5V
Average Current
TRACK1, TRACK2, TRACK3 .................................. 5mA
FB1, FB2, FB3 ....................................................... 5mA
Operating Temperature Range
Supply Voltage (VCC) ................................. –0.3V to 10V
Input Voltages
ON, PGI, SENSEP, SENSEN ..................... –0.3V to 10V
TRACK1, TRACK2, TRACK3 .......... –0.3V to VCC + 0.3V
SCTMR, SDTMR, PGTMR............. –0.3V to VCC + 0.3V
Output Voltages
LTC2925C ............................................... 0°C to 70°C
LTC2925I............................................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FAULT, SD1, SD2, SD3,
FB1, FB2, FB3, STATUS ......................... –0.3V to 10V
RAMPBUF, REMOTE..................... –0.3V to VCC + 0.3V
RAMP .............................................. –0.3V to VCC + 1V
MS Package ..................................................... 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
NUMBER
1
2
SCTMR
PGTMR
PGI
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
SENSEP
SENSEN
ON
LTC2925CUF
24 23 22 21 20 19
LTC2925CGN
LTC2925IGN
3
LTC2925IUF
4
STATUS
FAULT
GATE
ON
SDTMR
SD1
1
2
3
4
5
6
18 STATUS
FAULT
GATE
5
17
16
SDTMR
SD1
6
25
SD2
15 RAMP
7
RAMP
REMOTE
FB1
SD2
SD3
REMOTE
14
8
SD3
RAMPBUF
13 FB1
UF PART
MARKING
9
GN PART
MARKING
RAMPBUF
GND
7
8
9 10 11 12
10
11
12
TRACK1
TRACK2
FB2
FB3
2925
2925
LTC2925CGN
LTC2925IGN
TRACK3
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/W
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
EXPOSED PAD (PIN 25) INTERNALLY CONNECTED
TO GND (PCB CONNECTION OPTIONAL)
TJMAX = 125°C, θJA = 37°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
3
UNITS
V
V
Input Supply Range
Input Supply Current
●
●
●
2.9
CC
I
I
= 0, I
= 0, I = 0
RAMPBUF
1.5
mA
mA
CC
FBx
FBx
TRACKx
I
I
= –1mA, I
= –1mA,
10.5
15
TRACKx
= –3mA
RAMPBUF
V
Input Supply Undervoltage Lockout
V
Rising
CC
●
2.3
2.5
2.7
V
CC(UVL)
2925f
2
LTC2925
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
25
MAX
UNITS
mV
V
∆V
∆V
Input Supply Undervoltage Lockout Hysteresis
CC(UVL, HYST)
GATE
External N-Channel Gate Drive (V
GATE pin current
– V
)
CC
I = –1µA
GATE
●
●
●
●
5
–7
7
5.5
–10
10
6
GATE
I
Gate On, V
Gate Off, V
Gate Off, V
= 0V, No Faults
= 5V, No Faults
= 5V,
–13
13
µA
GATE
GATE
GATE
GATE
µA
5
20
50
mA
Short-Circuit or Power Good Timeout
V
ON Pin Threshold Voltage
ON Pin Hysteresis
V
rising
●
●
●
●
1.214
30
1.232
75
1.250
150
V
mV
V
ON(TH)
ON
∆V
ON(HYST)
V
ON Pin Fault Clear Threshold Voltage
ON Pin Input Current
0.3
0.4
0
0.5
ON(FC)
I
V
= 1.2V, V = 5.5V
±100
nA
ON(IN)
ON
CC
∆V
Sense Resistor Over-Current Voltage Threshold 1V < V
< V
CC
●
●
40
30
50
50
60
70
mV
mV
RS-SENSE(TH)
SENSEP
< 1V
SENSEP
(V
– V
)
0V < V
0V < V
0V < V
SENSEP
SENSEN
I
I
SENSEN Pin Input Current
SENSEP Pin Input Current
< V
< V
●
●
●
●
●
●
●
●
●
–1
–1
5
5
10
10
µA
µA
mV
V
SENSEN
SENSEP
SENSEN
SENSEP
CC
CC
V
V
V
V
Ramp Buffer Offset (V
– V
)
V
= V /2, I = 0A
RAMPBUF
–30
0
30
OS
RAMPBUF
RAMP
RAMPBUF
CC
FAULT Output Low Voltage
SDx Output Low Voltage
STATUS Output Low Voltage
RAMP Pin Input Current
RAMPBUF Low Voltage
I
I
I
= 3mA
FAULT
0.2
0.2
0.2
0
0.4
0.4
0.4
±1
FAULT(OL)
SDx(OL)
STATUS(OL)
RAMP
= 1mA, V = 2.3
V
SDx
CC
= 3mA
V
STATUS
I
0V < RAMP < V
V
= 5.5V
µA
mV
mV
CC, CC
V
V
I
I
= 3mA
90
100
150
200
RAMPBUF(OL)
RAMPBUF(OH)
ERROR(%)
RAMPBUF
= –3mA
RAMPBUF
RAMPBUF High Voltage (V – V
)
RAMPBUF
CC
I
I
I
to I
ERROR(%)
Current Mismatch
I
I
= –10µA
= –1mA
●
●
0
0
±5
±5
%
%
FBx
TRACKx
TRACKx
TRACKx
= (I – I
)/I
FBx
TRACKx TRACKx
V
TRACK pin voltage
I
I
= –10µA
= –1mA
●
●
0.78
0.78
0.8
0.8
0.82
0.82
V
V
TRACKx
TRACKx
TRACKx
I
I
Leakage Current
Clamp Voltage
V
= 1.5V, V = 5.5V
●
●
●
●
●
●
●
●
●
●
●
●
±10
2.5
30
nA
V
FB(LEAK)
FB
FB
CC
V
V
1µA < I < 1mA
1.6
2.1
15
FB(CLAMP)
FB
FB
R
REMOTE Feedback Switch Resistance
Short-Circuit Timer Pullup Current
Short-Circuit Timer Pulldown Current
Short-Circuit Timer Threshold Voltage
Shutdown Timer Pullup Current
2V < V
< V
CC
Ω
µA
µA
V
REMOTE
REMOTE
I
I
V
V
= 1V
= 1V
–35
1
–50
2
–65
3
SCTMR(UP)
SCTMR(DN)
SCTMR
SCTMR
V
1.1
–7
1.23
–10
1.23
–10
1.4
–13
1.4
–15
1.4
–14
1.4
SCTMR(TH)
SDTMR(UP)
I
V
V
V
= 1V
µA
V
SDTMR
V
Shutdown Timer Threshold Voltage
Power Good Input Pullup Current
Power Good Input Threshold Voltage
Power Good Timer Pullup Current
Power Good Timer Threshold Voltage
1.1
–5
SDTMR(TH)
PGI(UP)
I
= 0V
µA
V
PGI
V
0.8
–8
PGI(TH)
I
= 1V
–10
µA
V
PGTMR(UP)
PGTMR
V
1.1
1.23
PGTMR(TH)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: The GATE pin is internally limited to a minimum of 11.5V. Driving
this pin to voltages beyond the clamp may damage the part.
Note 2: All currents into the device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
2925f
3
LTC2925
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C.
ICC vs VCC
VGATE vs VCC
VSDx(OL) vs VCC
12
11
10
9
1.5
1.4
1.3
1.2
1.1
1.0
1.0
0.8
0.6
0.4
I
I
= I = 0mA
RAMPBUF
TRACKx FBx
= 0mA
I
= 5mA
SDx
0.2
0
I
= 10µA
SDx
2
8
2.9
3.5
4
4.5
5
5.5
0
3
4
5
1
2
3
4
5
6
V
(V)
V
CC
(V)
V
(V)
CC
CC
2925 G01
2925 G02
2925 G03
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PI FU CTIO S
GN/UF Packages
VCC (Pin 1/Pin 22): Positive Supply Input. The operating
supply input range is 2.9V to 5.5V. An undervoltage
lockout circuit resets the part when the supply is below
2.5V. VCC should be bypassed to GND with a 0.1µF
capacitor.
ramping the supplies down. Pulling the ON pin below 0.4V
resets the electronic circuit breaker in the LTC2925. If a
resistive divider connected to VCC drives the ON pin, the
supplies will automatically start up when VCC is fully
powered.
SENSEP (Pin 2/Pin 23): Circuit Breaker Positive Sense
Input. SENSEP and SENSEN measure the voltage across
the sense resistor and trigger the circuit breaker function
when the current exceeds the level programmed by the
sense resistor for longer than a short circuit timer cycle
(see SCTMR). If unused, tie SENSEN and SENSEP to VCC.
SDTMR (Pin 5/Pin 2): Shutdown Timer. A capacitor from
SDTMR to GND sets the delay time between the ON pin
transitioning high (which releases the SDx pins) and the
supplies beginning to ramp-up. Float SDTMR when it is
unused.
SD1, SD2, SD3 (Pins 6, 7, 8/Pins 3, 4, 5): Outputs for
Slave Supply Shutdowns. The SDx pins are open-drain
outputsthatholdtheshutdown(RUN/SS)pinsoftheslave
supplies low until the ON pin is pulled above 1.23V. The
SDxpinswillbepulledlowagainwhenRAMP<100mVand
ON <1.23V. If a slave supply is capable of operating with
aninputsupplythatislowerthantheLTC2925’sminimum
operatingvoltageof2.9V,theSDxpinscanbeusedtohold
off the slave supplies. Each SDx pin is capable of sinking
greater than 1mA with supplies as low as 2.3V.
SENSEN (Pin 3/Pin 24): Circuit Breaker Negative Sense
Input. SENSEN connects to the low side of the current
sense resistor. SENSEP and SENSEN monitor the current
through the external FET by measuring the voltage across
the sense resistor. The circuit breaker turns off the FET
when the sense voltage exceeds 50mV for longer than a
short circuit timer cycle (see SCTMR). If the short-circuit
timer times out, the GATE pin will be pulled low immedi-
ately to protect the FET. If unused, tie SENSEN and
SENSEP to VCC.
RAMPBUF (Pin 9/Pin 6): Ramp Buffer Output. Provides a
lowimpedancebufferedversionofthesignalontheRAMP
pin. This buffered output drives the resistive dividers that
connect to the TRACKx pins. Limit the capacitance at the
RAMPBUF pin to less than 100pF.
ON (Pin 4/Pin 1): On Control Input. The ON pin has a
threshold of 1.23V with 75mV of hysteresis. An active high
will cause 10µA to flow from the GATE pin, ramping up the
supplies. An active low pulls 10µA from the GATE pin,
2925f
4
LTC2925
U
U
U
PI FU CTIO S
GN/UF Packages
GND (Pin 10/Pins 7, 25): Circuit Ground.
STATUS pin goes high-impedance and the remote sense
switch connects the RAMP pin to the REMOTE pin.
TRACK1, TRACK2, TRACK3(Pins15, 14, 12/Pins12, 11,
9): Tracking Control Input Pin. A resistive divider between
RAMPBUF, TRACKx and GND determines the tracking
profile of OUTx (see Applications Information). TRACKx
pulls up to 0.8V and the current supplied at TRACKx is
mirrored at FBx. The TRACKx pin is capable of supplying
at least 1mA when VCC = 2.9V. It may be capable of
supplying up to 10mA when the supply is at 5.5V, so care
should be taken not to short this pin for extended periods.
Limit the capacitance at the TRACKx pin to less than 25pF.
Float the TRACKx pins if unused.
GATE (Pin 19/Pin 16): Gate Drive for External N-Channel
FET. When the ON pin is high, an internal 10µA current
sourcechargesthegateoftheexternalN-channelMOSFET.
A capacitor connected from GATE to GND sets the ramp
rate. It is a good practice to add a 10Ω resistor between
thiscapacitorandtheFET’sgatetopreventhighfrequency
FET oscillations. An internal charge pump guarantees that
GATE will pull up to 5V above VCC ensuring that logic level
N-channel FETs are fully enhanced. When the ON pin is
pulled low, the GATE pin is pulled to GND with a 10µA
current source. Under a short-circuit condition, the elec-
tronic circuit breaker in the LTC2925 pulls the GATE low
immediately with 20mA. Tie GATE to GND if unused.
FB1, FB2, FB3 (Pins 16, 13, 11/Pins13, 10, 8):Feedback
Control Output. FBx connects to the feedback node of
slave supplies. Tracking is achieved by mirroring the
current from TRACKx into FBx. If the appropriate resistive
divider connects RAMPBUF and TRACKx, the FBx current
will force OUTx to track RAMP. The LTC2925 is capable of
controllingslavesupplies withfeedbackvoltages between
0V and 1.6V. To prevent damage to the slave supply, the
FBx pin will not force the slave’s feedback node above
2.5V. In addition, it will not actively sink current from this
node even when the LTC2925 is unpowered. Float the FBx
pins if unused.
FAULT (Pin 20/Pin 17): Circuit Breaker and Power Good
Timer Fault Output. FAULT is an open-drain output that
pullslowwhentheelectroniccircuitbreakerisactivatedor
a power good timeout fault is detected. FAULT is reset by
pulling ON below 0.4V. To allow retry, tie FAULT to ON.
STATUS (Pin 21/Pin 18): Power Good Status Indicator.
The STATUS pin is an open-drain output that pulls low
until GATE has been fully charged at which time all
supplies will have reached their final operating voltage.
REMOTE (Pin 17/Pin 14): Remote Sense Switch. A 15Ω
switch connects REMOTE to RAMP when the GATE is fully
enhanced (GATE > RAMP + 4.9V). Otherwise, it presents
a high-impedance. When the slave supplies track the
master supply, REMOTE can be used to compensate for
the voltage drop across the external sense resistor and N-
channel FET. A resistor between the output and the sense
nodes of the master supply provides feedback before the
external FET is fully enhanced. If an external FET is not
used, float REMOTE.
PGI (Pin 22/Pin 19): Power Good Timer Input. PGI con-
nects to the RST pin of the downstream supply monitor. If
PGI has not transitioned high within a power good timer
cycle (see PGTMR), the FAULT pin will be pulled low and
the supplies will be turned off by pulling the GATE pin low
with 20mA. PGI is pulled up with 10µA. An internal
schottky diode allows PGI to be pulled safely above VCC.
Float PGI when it is unused.
PGTMR (Pin 23/Pin 20): Power Good Timer. A capacitor
fromPGTMRtoGNDsetsthePowerGoodTimerduration.
While ON > 1.23V, the PGTMR pin will pull up to VCC with
10µA. Otherwise, it pulls to GND. If the voltage on the
PGTMR pin exceeds 1.23V and PGI is still low, FAULT will
be pulled low and the GATE will be pulled to ground with
20mA until the powergood timerfaultis cleared by pulling
ON below 0.4V. If FAULT is tied back to ON the system will
automatically retry after a FAULT. In this mode, verify that
theslavesupplies’currentlimitsprovidesufficientprotec-
tion under short-circuit conditions. Float PGTMR when it
RAMP (Pin 18/Pin15): Ramp Buffer Input. When the
RAMP pin is connected to the source of the external N-
channel FET, the slave supplies track the FET’s source as
it ramps up and down. Alternatively, when no external FET
is used, the RAMP pin can be tied directly to the GATE pin.
In this configuration, the supplies track the capacitor on
the GATE pin as it is charged and discharged by the 10µA
current source controlled by the ON pin. When the GATE
is fully enhanced (GATE > RAMP + 4.9V) the open-drain
is unused.
2925f
5
LTC2925
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PI FU CTIO S
GN/UF Packages
SCTMR (Pin 24/Pin 21): Circuit Breaker Timer. A capaci-
torfromSCTMRtoGNDprogramsthemaximumtimethat
a short circuit can be sustained before GATE is pulled low.
When (SENSEP – SENSEN) > 50mV, SCTMR will pull up
with 50µA, otherwise it pulls down with 2µA. When the
voltage at SCTMR exceeds 1.23V, the GATE will be pulled
to ground with 20mA and the FAULT pin will be pulled low.
The circuit breaker function is reset by pulling ON below
0.4V. The GATE pin will not rise again until SCTMR has
been pulled below 100mV by the 2µA current source. If
FAULT is tied back to ON the system will automatically
retry after a fault. Tie SCTMR to GND if the circuit breaker
is not used.
U
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FU CTIO AL BLOCK DIAGRA
Pin numbers in parentheses are for the UF package.
(22)
1
V
CC
V
CC
FB3
FB2
FB1
TRACK3
(9) 12
11 (8)
0.8V
+
–
TRACK2
(11) 14
13 (10)
16 (13)
TRACK1
(12) 15
V
CC
SENSEP > SENSEN + 50mV
SENSEP
50µA
2µA
(23)
(24)
2
3
SCTMR
(21) 24
50mV
SENSEN
FAULT
(17)
20
+
–
1.2V
1.2V
GATE
PGI
(16)
19
(19) 22
(20) 23
V
CC
CHARGE
PUMP
–
+
10µA
PGTMR
10µA
–
+
1.2V
ONSIG
10µA
SCTMR
0.1V
–
+
S
R
Q
V
CC
+
–
0.4V
10µA
S
R
Q
ON
SDTMR
SDx
(1)
4
(2)
5
+
–
1.2V
+
–
0.1V
V
–
+
CC
2.6V
RAMP
RAMPBUF
(15)
(6)
1×
18
9
REMOTE
STATUS
+
–
(14) 17
10
V
CC
4.9V
GATE
GATE > RAMP + 4.9V
GND
2925 FBD
10
(7, 25)
2925f
6
LTC2925
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APPLICATIO S I FOR ATIO
Power Supply Tracking and Sequencing
Certain applications require one supply to come up after
another. For example, a system clock may need to start
before a block of logic. In this case, the supplies are se-
quenced as in Figure 4 where the 1.8V supply ramps up
completely followed by the 2.5V supply and then the 1.5V
supply.
The LTC2925 handles a variety of power-up profiles to
satisfy the requirements of digital logic circuits including
FPGAs, PLDs, DSPs and microprocessors. These require-
ments fall into one of the four general categories illus-
trated in Figures 1 to 4.
Some applications require that the potential difference
between two power supplies must never exceed a speci-
fied voltage. This requirement applies during power-up
and power-down as well as during steady-state operation,
often to prevent destructive latch-up in a dual supply IC.
Typically, this is achieved by ramping the supplies up and
down together (Figure 1). In other applications it is desir-
able to have the supplies ramp up and down with fixed
voltage offsets between them (Figure 2) or to have them
ramp up and down ratiometrically (Figure 3).
Operation
TheLTC2925providesasimplesolutiontoallofthepower
supply tracking and sequencing profiles shown in Figures
1 to 4. A single LTC2925 controls up to four supplies with
three “slave” supplies that track a “master” signal. With
just two resistors, a slave supply is configured to ramp up
as a function of the master signal. This master signal can
be a fourth supply that is ramped up through an external
FET,whoseramprateissetwithasinglecapacitor,oritcan
be a signal generated by tying the GATE and RAMP pins to
an external capacitor.
MASTER
SLAVE1
MASTER
SLAVE1
1V/DIV
1V/DIV
SLAVE2
SLAVE3
SLAVE2
SLAVE3
10ms/DIV
2925 F01
10ms/DIV
2925 F02
Figure 1. Coincident Tracking
Figure 2. Offset Tracking
MASTER
SLAVE1
SLAVE2
SLAVE3
SLAVE1
2V/DIV
2V/DIV
SLAVE2
SLAVE3
10ms/DIV
2925 F03
10ms/DIV
2925 F04
Figure 3. Ratiometric Tracking
Figure 4. Supply Sequencing
2925f
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LTC2925
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APPLICATIO S I FOR ATIO
Tracking Cell
Inaproperlydesignedsystem,whenthemastersignalhas
reacheditsmaximumvoltagethecurrentfromtheTRACK1
piniszero. Inthiscase, thereisnocurrentfromtheFB1pin
and the LTC2925 has no effect on the output voltage accu-
racy, transient response or stability of the slave supply.
TheLTC2925’soperationisbasedonthetrackingcellshown
in Figure 5, which uses a proprietary wide-range current
mirror. The tracking cell shown in Figure 5 servos the
TRACK pin at 0.8V. The current supplied by the TRACK pin
ismirroredattheFBpintoestablishavoltageattheoutput
of the slave supply. The slave output voltage varies with
the master signal, enabling the slave supply to be con-
trolled as a function of the master signal with terms set by
When the ON pin falls below VON(TH) – ∆VON(HYST), typi-
cally 1.225V, the GATE pin pulls down with 10µA and the
master signal and the slave supplies will fall at the same
rate as they rose previously.
RTA and RTB. By selecting appropriate values of RTA and
The ON pin can be controlled by a digital I/O pin or it can
be used to monitor an input supply. By connecting a resis-
tivedividerfromaninputsupplytotheONpin,thesupplies
will ramp up only after the monitored supply has reached
a preset voltage.
RTB, it is possible to generate any of the profiles in Figures
1 to 4.
V
CC
V
CC
+
–
+
MASTER
R
0.8V
SENSEP – SENSEN > 50mV
SENSEP
–
50µA
2µA
TB
DC/DC
FB
TRACK
SCTMR
FB OUT
SLAVE
50mV
R
TA
SENSEN
R
FB
R
FA
2925 F05
+
–
Figure 5. Simplified Tracking Cell
1.2V
ON
Controlling the Ramp-Up and Ramp-Down Behavior
R
R
ONB
10µA
The operation of the LTC2925 is most easily understood
by referring to the simplified functional diagram in
Figure 6. When the ON pin is low, the GATE pin is pulled to
ground causing the master signal to remain low. Since the
current through RTB1 is at its maximum when the master
signal is low, the current from FB1 is also at its maximum.
This current drives the slave’s output to its minimum
voltage.
+
–
GATE
Q1
ONA
1.2V
C
GATE
10µA
RAMP
RAMPBUF
1×
MASTER
V
CC
0.8V
+
–
When the ON pin rises above 1.23V, the master signal
rises and the slave supply tracks the master signal. The
ramp rate is set by an external capacitor driven by a 10µA
current source from an internal charge pump. If no exter-
nal FET is used, the ramp rate is set by tying the RAMP and
GATE pins together at one terminal of the external capaci-
tor (see the Ratiometric Tracking Example).
R
R
TB1
FB1
TRACK1
SLAVE1
DC/DC
TA1
R
FB1
R
FA1
2925 F06
Figure 6. Simplified Functional Block Diagram
2925f
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Optional External FET
The short-circuit timer duration is configured by a capaci-
tortiedbetweenSCTMRandGND.SCTMRwillpullupwith
50µAwhenSENSEP–SENSEN>50mV.Otherwise,itpulls
downwith2µA.WhenthevoltageatSCTMRexceeds1.23V,
theGATEwillbepulledtogroundwith20mAandtheFAULT
pin will be pulled low. Thus, the capacitor, CSCTMR, re-
quiredtoconfiguretheshort-circuittimerduration,tSCTMR
is determined from:
Figure7illustrateshowanoptionalexternalN-channelFET
can ramp up a single supply that becomes the master
signal. When used, the FET’s gate is tied to the GATE pin
and its source is tied to the RAMP pin. Under normal op-
eration, the GATE pin sources or sinks 10µA to ramp the
FET’sgateupordownataratesetbytheexternalcapacitor
connected to the GATE pin.
50µA • tSCTMR
The series FET easily controls any supply with an output
voltage between 0V and VCC. See the Typical Applications
section for examples.
CSCTMR
=
1.23V
Because the slave supplies track the RAMP pin which is
drivenbytheexternalFET, theyarepulledlowbythetrack-
ing circuit when a short-circuit fault occurs. Following a
short-circuit fault, the FET is latched off and FAULT is
pulled low until the fault is cleared by pulling the ON pin
below 0.4V. Note that the supplies will not be allowed to
ramp up again until SCTMR has been pulled below about
100mV by the 2µA pull down current source. The elec-
troniccircuitbreakersupportsanysupplyvoltagebetween
0V and VCC. Although it is normally used to monitor cur-
rent through the optional series FET, it is capable of moni-
toring other currents, including the current from a slave
supply. The Typical Applications section shows one such
example.
R
Q1
SENSE
V
IN
MASTER
0.1µF
C
GATE
10Ω
SUPPLY
MONITOR
R
R
ONB
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
3.3V
IN
ONA
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
V
V
IN
SLAVE1
10k
10k
R
FB1
R
FA1
3.3V
IN
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
2.5V
SLAVE2
OUT
FAULT
RAMPBUF
R
R
TB1
R
FB2
R
FA2
TRACK1
TRACK2
3.3V
IN
R
TB2
TA1
Iftheelectroniccircuitbreakerisnotused,tieSENSEPand
SENSEN to VCC and SCTMR to GND.
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
R
R
TB3
TA2
OUT
1.5V
SLAVE3
TRACK3
GND SCTMR
C
SDTMR
C
PGTMR
C
R
TA3
R
FB3
Power Good Timeout
SCTMR
SDTMR
PGTMR
R
FA3
2925 F07
The power good timeout circuit turns off the supplies if an
external supply monitor, connected to the PGI pin, fails to
indicate that all supplies have entered regulation in time
after power up begins. After power up is complete, it turns
off the supplies if any supply exits regulation.
Figure 7. Typical Application With External FET
Electronic Circuit Breaker
The LTC2925 features an electronic circuit breaker func-
tion that protects the optional series FET against short
circuits. An external sense resistor is used to measure the
current flowing in the FET. If the voltage across the sense
resistor exceeds 50mV for more than a short-circuit timer
cycle, the gate of the FET is pulled low with 20mA, turning
it off.
The power good timer duration is configured by a capaci-
tor tied between PGTMR and GND. PGTMR will pull up the
C
PGTMR capacitor with 10µA starting when the ON pin is
driven above 1.23V. Once the voltage at the PGTMR ex-
ceeds 1.23V, a fault will trip if the PGI pin is low. When the
power good timeout circuit detects a fault, the GATE pin is
2925f
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LTC2925
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APPLICATIO S I FOR ATIO
pulled low, the supplies are latched off, and the FAULT pin
is held low until the fault is cleared by taking the ON pin
below 0.4V.
ful in systems with an external FET. Since the track cell
drives 0.8V on the TRACKx pins, if RTBx is connected di-
rectly to the FET’s source, the TRACKx pin could poten-
tially pull up the FET’s source towards 0.8V when the FET
is off. RAMPBUF blocks this path.
The PGI pin, which is normally connected to the RST pin
of an external supply monitor, is pulled up with 10µA
through a schottky diode allowing it to be pulled safely
above VCC. Since, PGTMR pulls up with a 10µA current
source, the capacitor, CPGTMR, required to configure the
powergoodtimeoutduration,tPGTMR,isdeterminedfrom:
Shutdown Outputs
In some applications it might be necessary to control the
shutdown or RUN/SS pins of the slave supplies. The
LTC2925 may not be able to supply the rated 1mA of cur-
rent from the FB1, FB2, and FB3 pins when VCC is below
2.9V. If the slave power supplies are capable of operating
at low input voltages, use the open-drain SDx outputs to
drive the SHDN or RUN/SS pins of the slave supplies
(Figures 7 and 8). The SDx pins are released when the ON
pin rises above 1.23V, VCC is above the 2.6V undervoltage
lockout condition, and there are no faults latched. The
shutdown timer begins at the same time, and the supplies
begin to ramp up after the shutdown timer cycle com-
pletes. The duration of the timer cycle is configured by a
capacitor tied between SDTMR and GND. The capacitor
voltage is ramped up by a 10µA current source and the
SDTMR cycle completes when its voltage reaches 1.23V.
Thus, the capacitor, CSDTMR, required for a given shut-
down timer cycle, tSDTMR, is determined from:
10µA • tPGTMR
CPGTMR
=
1.23V
Ifthepowergoodtimeoutcircuitisunused,tiePGTMRlow
and float PGI.
The Ramp Buffer
TheRAMPBUFpinprovidesabufferedversionoftheRAMP
pinvoltagethatdrivestheresistivedividersontheTRACKx
pins. When there is no external FET, it provides up to 3mA
to drive the resistors even though the GATE pin only sup-
plies 10µA (Figure 8). The RAMPBUF pin also proves use-
V
IN
C
GATE
0.1µF
SUPPLY
MONITOR
V
SENSEP SENSEN GATE
RAMP
R
R
CC
10µA • tSDTMR
ONB
RST
CSDTMR
=
ON
V
PGI
IN
IN
OUT
1.23V
ONA
SD1
RUN/SS
DC/DC
REMOTE
STATUS
The SDx pins pull low again when the ON pin is pulled
below 1.23V and the RAMP pin is below about 100mV.
FB1
FB
SLAVE1
V
V
IN
IN
R
FB1
R
FA1
V
IN
IN
OUT
LTC2925
SD2
FB2
RUN/SS
DC/DC
SLAVE2
SLAVE3
FB
FAULT
RAMPBUF
R
R
TB1
R
FB2
R
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
TA1
SD3
FB3
RUN/SS
DC/DC
R
R
TB3
TA2
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
C
C
PGTMR
SDTMR
R
FA3
2925 F08
Figure 8. Typical Application Without External FET
2925f
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Status Output
Retry on Fault
The STATUS pin provides an indication that the supplies
are finished ramping up. This pin is an open-drain output
that pulls low until the GATE has been fully charged. Since
the GATE pin drives the gate of the external FET, or the
RAMP pin directly when no FET is used, the supplies are
completely ramped up when the GATE pin is fully charged.
The STATUS pin will go low again when the GATE pin is
pulled low, either because of a short-circuit fault, a power
good timeout fault, or because the ON pin has been pulled
low.
The LTC2925 continuously attempts to ramp up the out-
puts after a fault if the FAULT pin is tied to the ON pin
(Figure 9). If a short-circuit fault occurs in this configura-
tion, the SCTMR pin ramps up the CSCTMR capacitor with
50µAuntilitreaches1.23V. Then, GATEispulledlowturn-
ing off the shorted FET. At the same time, the FAULT pin’s
open-drain output pulls ON low. The CSCTMR capacitor is
pulled down with 2µA until it reaches about 100mV. After
theCSCTMR capacitorreaches100mV, theshutdowntimer
begins and upon completing a shutdown timer cycle, the
supplies start ramping up again. If there is no short-circuit
this time, the supplies will come up normally. Otherwise,
the retry cycle will repeat. If a longer off time is required
betweenretryattempts,theCSDTMR capacitorvaluecanbe
increased,providingagreaterdelaybeforetheFET’sGATE
ramps up on each cycle. Note that tying FAULT to ON also
causestheLTC2925toretryonPowerGoodTimeoutfaults.
In this mode, verify that the slave supplies’ current limits
providesufficientprotectionundershort-circuitconditions.
Fault Output
TheFAULTpin isanopen-drain outputthatpulls low when
the electronic circuit breaker is activated due to a short-
circuit or power good timeout fault. FAULT is reset by
pulling ON below 0.4V. The supplies will not be allowed to
rampupagainuntiltheSCTMR, PGTMR, andSDTMRpins
are below about 100mV, and the ON pin is pulled above
1.23V.
R
Q1
SENSE
V
IN
MASTER
0.1µF
C
GATE
10Ω
SUPPLY
MONITOR
R
R
ONB
ONA
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
V
IN
SD1
RUN/SS
IN
DC/DC
REMOTE
STATUS
FB1
FB
OUT
SLAVE1
V
IN
10k
R
FB1
R
FA1
V
IN
LTC2925
SD2
FB2
RUN/SS
IN
DC/DC
SLAVE2
SLAVE3
FB
OUT
FAULT
RAMPBUF
R
R
R
TB1
TA1
FB2
R
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
SD3
FB3
RUN/SS
DC/DC
R
R
TB3
TA3
TA2
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
R
FB3
C
C
C
PGTMR
SCTMR
SDTMR
R
FA3
2925 F09
Figure 9. Retry on Fault
2925f
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3-Step Design Procedure
Choose a ramp rate for the slave supply, SS. If the slave
supplyrampsupcoincidentwiththemastersupplyorwith
afixedvoltageoffset, thentheramprateequalsthemaster
supply’s ramp rate. Be sure to use a fast enough ramp rate
for the slave supply so that it will finish ramping before the
mastersupplyhasreacheditsfinalsupplyvalue. Ifnot, the
slave supply will be held below the intended regulation
value by the master supply. Use the following formulas to
determine the resistor values for the desired ramp rate,
where RFB and RFA are the feedback resistors in the slave
supply and VFB is the feedback reference voltage of the
slave supply:
Thefollowing3-stepdesignprocedureallowsonetochoose
the TRACK resistors, RTAx and RTBx, and the gate capaci-
tor, CGATE, that give any of the tracking or sequencing
profiles shown in Figures 1 to 4. A basic four supply appli-
cation circuit is shown in Figure 10.
1. Set the ramp rate of the master signal.
Solve for the value of CGATE, the capacitor on the GATE
pin, based on the desired ramp rate (V/s) of the master
supply, SM.
IGATE
SM
CGATE
=
whereIGATE ≈ 10µA
(1)
SM
SS
R
TB = RFB •
(2)
(3)
If the external FET has a gate capacitance comparable to
CGATE, then the external capacitor’s value should be re-
duced to compensate for the FET’s gate capacitance.
VTRACK
RTA ′ =
V
FB
V
VTRACK
RTB
FB
+
–
If no external FET is used, tie the GATE and RAMP pins
together, connect SENSEN and SENSEP to VCC, and con-
nect SCTMR to GND.
RFB RFA
where VTRACK ≈ 0.8V.
Note that large ratios of slave ramp rate to master ramp
rate, SS/SM, may result in negative values for RTA´. If a
sufficiently large delay is used in step 3, RTA will be posi-
tive, otherwise SS/SM must be reduced.
2. Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
R
SENSE
Q1
V
IN
MASTER
0.1µF
3. Choose RTA to obtain the desired delay.
C
GATE
10Ω
SUPPLY
MONITOR
Ifnodelayisrequired,suchasincoincidentandratiometric
tracking, then simply set RTA = RTA´. If a delay is desired,
asinoffsettrackingandsupplysequencing,calculateRTA´´
to determine thevalue ofRTA wheretD isthe desireddelay.
R
ONB
154k
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
V
IN
IN
OUT
R
ONA
100k
SD1
RUN/SS
DC/DC
REMOTE
STATUS
FB1
FB
SLAVE1
V
V
IN
VTRACK •RTB
10k
10k
R
FB1
R
FA1
RTA ′′ =
(4)
(5)
V
IN
tD • SM
IN
LTC2925
SD2
FB2
RUN/SS
IN
DC/DC
RTA = RTA ′ ||RTA ′′
SLAVE2
SLAVE3
FB
OUT
FAULT
RAMPBUF
R
R
TB1
R
FB2
the parallel combination of RTA´ and RTA´´
R
FA2
TRACK1
TRACK2
V
IN
IN
OUT
R
TB2
TA1
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in se-
quencing) may result in solutions with negative values for
RTA. In such cases, either the delay must be increased or
the ratio of slave ramp rate to master ramp rate must be
reduced.
SD3
FB3
RUN/SS
DC/DC
R
R
TB3
TA2
FB
TRACK3
GND SCTMR
SDTMR
PGTMR
R
TA3
R
FB3
R
FA3
2925 F10
Figure 10. Four Supply Application
2925f
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LTC2925
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APPLICATIO S I FOR ATIO
MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
10ms/DIV
2925 F11a
10ms/DIV
2925 F11b
Figure 11. Coincident Tracking from Figure 12
is held below 1.23V. When the ON pin rises above 1.23V,
10µA pulls up CGATE and the gate of the FET at 100V/s. As
the gate of the FET rises, the source follows and pulls up
the output to 3.3V at 100V/s. This output serves as the
master signal and is buffered from the RAMP pin to the
RAMPBUF pin. As this output and the RAMPBUF pin rise,
the current from the TRACKx pins is reduced. Conse-
quently, the voltages at the slave supplies’ outputs in-
crease, and the slave supplies track the master supply.
When the ON pin is again pulled below 1.23V, 10µA will
pull down CGATE and the gate of the FET at 100V/s. If the
loads on the outputs are sufficient, all outputs will track
down coincidently at 100V/s.
Coincident Tracking Example
AtypicalfoursupplyapplicationisshowninFigure12.The
master signal is a 3.3V module. The slave 1 supply is a
1.8V switching power supply, the slave 2 supply is a 2.5V
switching power supply, and the slave 3 supply is a 1.5V
supply. All three slave supplies track coincidently with the
3.3V supply that is controlled with an external FET. The
ramp rate of the supplies is 100V/s. The 3-step design
procedure detailed previously can be used to determine
component values. Only the slave 1 supply is considered
here as the procedure is the same for the other supplies.
1. Set the ramp rate of the master signal.
From Equation 1:
Q1
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1µF
C
GATE
0.1µF
10µA
100V s
10Ω
CGATE
=
= 0.1µF
SUPPLY
MONITOR
R
ONB
154k
V
CC
ON
SENSEP SENSEN GATE
RAMP
PGI
RST
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
V
V
From Equation 2:
IN
SLAVE1
10k
10k
R
R
FB1
16.5k
FA1
35.7k
100V s
100V s
3.3V
IN
R
TB = 16.5k •
= 16.5k
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
2.5V
SLAVE2
OUT
FAULT
RAMPBUF
From Equation 3:
R
TB1
R
R
FB2
88.7k
FA2
16.5k
41.2k
TRACK1
TRACK2
3.3V
IN
R
TB2
R
0.8V
1.235V 1.235V 0.8V
TA1
88.7k
13k
RTA ′ =
≈ 13k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
R
TA2
41.2k
86.6k
+
–
OUT
1.5V
SLAVE3
TRACK3
16.5k
35.7k 16.5k
R
TA3
100k
GND SCTMR
SDTMR
PGTMR
R
FB3
86.6k
R
FA3
C
C
C
SCTMR
0.47µF
SDTMR
0.082µF
PGTMR
0.82µF
100k
3. Choose RTA to obtain the desired delay.
Since no delay is desired, RTA = RTA´
2925 F12
Figure 12. Coincident Tracking Example
In this example, all supplies remain low while the ON pin
2925f
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SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
10ms/DIV
2925 F13a
10ms/DIV
2925 F13b
Figure 13. Ratiometric Tracking from Figure 14
Ratiometric Tracking Example
From Equation 3:
This example converts the coincident tracking example to
the ratiometric tracking profile shown in Figure 13, using
three supplies without an external FET. The ramp rate of
the master signal remains unchanged (Step 1) and there
is no delay in ratiometric tracking (Step 3), so only the
result of step 2 in the 3-step design procedure needs to be
considered. In this example, the ramp rate of the 1.8V
slave 1 supply ramps up at 60V/s, the 2.5V slave 2 supply
ramps up at 85V/s, and the 1.5V slave 3 supply ramps up
at50V/s. Alwaysverifythatthechosenrampratewillallow
the supplies to ramp-up completely before RAMPBUF
reaches VCC. If the 1.8V supply were to ramp-up at 50V/s
it would only reach 1.65V because the RAMPBUF signal
would reach its final value of VCC = 3.3V before the slave
supply reached 1.8V.
0.8V
1.235V 1.235V 0.8V
RTA ′ =
≈ 10k
+
–
16.5k
35.7k 27.5k
Step 3 is unnecessary because there is no delay, so
RTA = RTA´.
3.3V V
IN
C
GATE
0.1µF
0.1µF
SUPPLY
MONITOR
R
ONB
154k
V
CC
SENSEP SENSEN GATE
RAMP
RST
ON
3.3V
IN
PGI
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
V
V
IN
SLAVE1
10k
10k
R
FB1
16.5k
R
FA1
35.7k
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
3.3V
IN
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
2.5V
SLAVE2
OUT
FAULT
RAMPBUF
From Equation 2:
R
TB1
R
R
FB2
88.7k
FA2
27.4k
41.2k
TRACK1
TRACK2
3.3V
IN
100V s
60V s
R
TB2
100k
R
TA1
10k
R
TB = 16.5k •
≈ 27.4k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
174k
R
TA2
38.3k
OUT
1.5V
SLAVE3
TRACK3
R
TA3
63.4k
GND SCTMR
SDTMR
C
PGTMR
C
R
FB3
86.6k
R
100k
FA3
C
SCTMR
SDTMR
PGTMR
0.41µF
0.082µF
0.82µF
2925 F14
Figure 14. Ratiometric Tracking Example
2925f
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MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
10ms/DIV
2925 F15a
10ms/DIV
2925 F15b
Figure 15. Offset Tracking from Figure 16
Offset Tracking Example
From Equation 4:
0.8V •16.5k
Converting the circuit in the coincident tracking example
totheoffsettrackingshowninFigure15isrelativelysimple.
Here the 1.8V slave 1 supply ramps up 1V below the mas-
ter. Theramprateremainsthesame(100V/s), sothereare
nochangesnecessarytosteps1and2ofthe3-stepdesign
procedure. Only step 3 must be considered. Be sure to
verify that the chosen voltage offsets will allow the slave
supplies to ramp up completely. In this example, if the
voltage offset were 2V, the slave supply would only ramp
up to 3.3V – 2V = 1.3V.
″
RTA
=
= 13.2k
1ms •100V s
From Equation 5:
RTA = 13.1k ||13.2k ≈ 6.65k
Q1
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1µF
C
GATE
0.1µF
10Ω
SUPPLY
MONITOR
3. Choose RTA to obtain the desired delay.
R
ONB
154k
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
3.3V
First, convertthedesiredvoltage offset, VOS, to adelay, tD,
using the ramp rate:
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
IN
REMOTE
STATUS
FB1
1.8V
SLAVE1
V
V
IN
VOS
SS 100V s
1V
10k
10k
R
FB1
16.5k
R
tD =
=
= 10ms
(6)
FA1
35.7k
3.3V
IN
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
2.5V
OUT
FAULT
SLAVE2
RAMPBUF
R
TB1
R
R
FA2
FB2
88.7k
16.5k
41.2k
TRACK1
TRACK2
3.3V
IN
R
TB2
88.7k
R
TA1
6.65k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
86.6k
R
TA2
31.6k
OUT
1.5V
SLAVE3
TRACK3
R
TA3
31.6k
GND SCTMR
SDTMR
PGTMR
R
FB3
86.6k
R
100k
FA3
C
C
C
SCTMR
0.41µF
SDTMR
0.082µF
PGTMR
0.82µF
2925 F16
Figure 16. Offset Tracking Example
2925f
15
LTC2925
U
W U U
APPLICATIO S I FOR ATIO
MASTER
SLAVE2
SLAVE1
SLAVE3
1V/DIV
1V/DIV
10ms/DIV
2925 F17a
10ms/DIV
2925 F17b
Figure 17. Supply Sequencing from Figure 18
Supply Sequencing Example
3. Choose RTA to obtain the desired delay.
From Equation 4:
In Figure 17, the three slave supplies are sequenced in-
stead of tracking. As in the coincident tracking example,
the 3.3V master supply ramps up at 100V/s through an
external FET, so step 1 remains the same. The 1.8V slave
1 supply ramps up at 1000V/s beginning 10ms after the
master signal starts to ramp up. The 2.5V slave 2 supply
ramps up at 1000V/s beginning 20ms after the master
signal begins to ramp up. The 1.5V slave 3 supply ramps
up at 1000V/s beginning 25ms after the master signal
begins to ramp up. Note that not every combination of
ramp rates and delays is possible. Small delays and large
ratios of slave ramp rate to master ramp rate may result in
solutions that require negative resistors. In such cases,
either the delay must be increased or the ratio of slave
ramp rate to master ramp rate must be reduced. In this
example, solving for the slave 1 supply yields:
0.8V •1.65k
10ms •100V s
″
RTA
=
= 1.32k
From Equation 5:
RTA = –2.13k ||1.32k ≈ 3.48k
Q1
0.015Ω
Si4412ADY
3.3V V
IN
MASTER
0.1µF
C
GATE
0.1µF
10Ω
SUPPLY
MONITOR
R
ONB
154k
V
SENSEP SENSEN GATE
RAMP
PGI
CC
ON
RST
3.3V
IN
R
ONA
100k
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
REMOTE
STATUS
FB1
1.8V
SLAVE1
V
V
IN
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
10k
10k
R
FB1
16.5k
R
FA1
35.7k
3.3V
IN
IN
LTC2925
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
From Equation 2:
2.5V
OUT
FAULT
SLAVE2
RAMPBUF
100V s
1000V s
R
TB1
R
R
FA2
FB2
88.7k
1.65k
R
TB = 16.5k •
≈ 1.65k
41.2k
TRACK1
TRACK2
3.3V
IN
R
TB2
8.87k
R
TA1
3.48k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
R
TB3
8.66k
R
TA2
4.87k
From Equation 3:
OUT
1.5V
SLAVE3
TRACK3
R
TA3
3.74k
GND SCTMR
SDTMR
C
PGTMR
R
FB3
86.6k
R
100k
FA3
0.8V
C
C
SCTMR
SDTMR
PGTMR
0.82µF
0.41µF
0.082µF
RTA ′ =
≈ –2.13k
1.235V 1.235V 0.8V
2925 F18
+
–
16.5k
35.7k 1.65k
Figure 18. Supply Sequencing Example
2925f
16
LTC2925
U
W U U
APPLICATIO S I FOR ATIO
Final Sanity Checks
Therefore, the LTC2925’s tracking cell will not effectively
drive the supply’s output below the input.
The collection of equations below is useful for identifying
unrealizable solutions.
Special caution should be taken when considering the use
of linear regulators. Three-terminal linear regulators have
a reference voltage that is referred to the output supply
rather than to ground. In this case, driving current into the
regulator’sfeedbacknodewillcauseitsoutputtoriserather
than fall. Even linear regulators that have their reference
voltage referred to ground, including low-dropout regula-
tors (LDOs), may be problematic. Linear regulators com-
monly contain circuitry that prevents driving their outputs
below their reference voltage. This may not be obvious
fromthedatasheets,solabtestingisrecommendedwhen-
ever the LTC2925’s tracking cell is used to control linear
regulators.
As stated in step 2, the slave supply must finish ramping
before the master signal has reached its final voltage. This
can be verified by the following equation:
RTB
RTA
VTRACK 1+
< VMASTER
Here, VTRACK = 0.8V. VMASTER is the final voltage of the
mastersignal,eitherthesupplyvoltagerampedupthrough
the optional external FET or VCC when no FET is present.
It is possible to choose resistor values that require the
LTC2925 to supply more current than the Electrical Char-
acteristicstableguarantees.Toavoidthiscondition,check
that ITRACKx does not exceed 1mA and IRAMPBUF does not
exceed ±3mA.
Load Requirements
When the supplies are ramped down quickly, either the
loadorthesupplyitselfmustbecapableofsinkingenough
current to support the ramp rate. For example, if there is
a large output capacitance on the supply and a weak resis-
tive load, supplies that do not sink current will have their
fallingrampratelimitedbytheRCtimeconstantoftheload
andtheoutputcapacitance.Figure19showsthecasewhen
the 2.5V supply does not track the 1.8V and 3.3V supplies
near ground.
To confirm that ITRACKx < 1mA, the TRACKx pin(s) maxi-
mum guaranteed current, verify that:
VTRACK
< 1mA
RTA RTB
Finally, check that the RAMPBUF pin will not be forced to
sink more than 3mA when it is at 0V or be forced to source
more than 3mA when it is at VMASTER
.
Start-Up Delays
Often power supplies do not start-up immediatley when
their input supplies are applied. If the LTC2925 tries to
ramp-upthesepowersuppliesassoonastheinputsupply
is present, the start-up of the outputs may be delayed
VTRACK VTRACK VTRACK
RTA1 RTB1 RTA2 RTB2 RTA3 RTB3
+
+
< 3mA and
VMASTER
TA1+RTB1
VMASTER
TA2 +RTB2
VMASTER
RTA3 +RTB3
+
+
< 3mA
R
R
Caution with Boost Regulators and Linear Regulators
MASTER
SLAVE2
SLAVE1
Note that the LTC2925’s tracking cell is not able to control
the outputs of all types of power supplies. If it is necessary
to control a supply, where the output is not controllable
through its feedback node, the series FET can be used to
control its output. For example, boost regulators com-
monly contain an inductor and diode between the input
supply and the output supply providing a DC current path
when the output voltage falls below the input voltage.
1V/DIV
2925 F19
1ms/DIV
Figure 19. Weak Resistive Load
2925f
17
LTC2925
U
W U U
APPLICATIO S I FOR ATIO
defeating the tracking circuit (Figure 20). Often this delay
isintentionallyconfiguredbyasoft-startcapacacitor. This
canberemediedeitherbyreducingthesoft-startcapacitor
on the slave supply or by increasing the shutdown timer
advantageous to add a resistor near the feedback node of
the slave supply in series with the FBx pin of the LTC2925.
This resistor must not exceed:
cycle configured by CSDTMR
.
1.6V – VFB
IMAX
1.6V
VFB
RSERIES
=
=
– 1 R ||R
FA FB
(
)
Layout Considerations
Be sure to place a 0.1µF bypass capacitor as near as pos-
Thisresistorismosteffectiveifthereisalreadyacapacitor
at the feedback node of the slave supply (often a compen-
sation component). Increasing the capacitance on a slave
supply’s feedback node will further improve the noise
immunity, but could affect the stability and transient re-
sponse of the supply.
sible to the supply pin of the LTC2925.
To minimize the noise on the slave supplies’ outputs, keep
the traces connecting the FBx pins of the LTC2925 and the
feedback nodes of the slave supplies as short as possible.
In addition, do not route those traces next to signals with
fast transition times. In some circumstances it might be
For proper circuit breaker operation, Kelvin-sense PCB
connectionsbetweenthesenseresistorandtheLTC2925’s
SENSEP and SENSEN pins are strongly recommended.
The drawing in Figure 22 illustrates the correct way of
making connections between the LTC2925 and the sense
resistor. PCB layout should be balanced and symmetrical
to minimize wiring errors. In addition, the PCB layout for
the sense resistor should include good thermal manage-
ment techniques for optimal sense resistor power
dissipation.
MASTER
SLAVE1
1V/DIV
SLAVE2
ON
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
2925 F20
1ms/DIV
Figure 20. Power Supply Start-Ups Delayed
IRC-TT SENSE RESISTOR
LR251201R010F
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
OR EQUIVALENT
V
CC
0.01Ω, 1%, 1W
LTC2925
FB1
R
DC/DC
FB OUT
SERIES
TRACK WIDTH W:
0.03' PER AMP
ON 1 OZ COPPER
MINIMIZE
TRACE
LENGTH
W
GND
R
FB
R
FA
2925 F23
0.1µF
2925 F22
TO TO
SENSEP SENSEN
Figure 21. Layout Considerations
Figure 22. Making PCB Connections to the Sense Resistor
2925f
18
LTC2925
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9
10 11 12
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
× 45°
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
0.70 ±0.05
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
1
2
4.50 ± 0.05
2.45 ± 0.05
(4 SIDES)
2.45 ± 0.10
(4-SIDES)
3.10 ± 0.05
PACKAGE OUTLINE
(UF24) QFN 1103
0.25 ± 0.05
0.50 BSC
0.200 REF
0.25 ±0.05
0.50 BSC
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE
MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
2925f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC2925
U
TYPICAL APPLICATIO S
External FET Controls 1V Supply
Electronic Circuit Breaker Monitors Slave Output
Q1
Q1
0.015Ω
Si4412ADY
Si4412ADY
MASTER
1V
V
IN
MASTER
0.1µF
0.1µF
C
GATE
0.1µF
C
GATE
0.1µF
10Ω
10Ω
3.3V
SUPPLY
MONITOR
SUPPLY
MONITOR
R
R
ONB
154k
ONB
154k
V
SENSEP SENSEN GATE
RAMP
PGI
V
GATE
RAMP
PGI
CC
ON
RST
CC
RST
ON
3.3V
IN
3.3V
IN
R
R
ONA
100k
ONA
100k
SD1
SD1
RUN/SS
DC/DC
FB = 1.235V OUT
RUN/SS
DC/DC
FB = 1.235VOUT
REMOTE
STATUS
REMOTE
FB1
1.8V
FB1
1.8V
SLAVE1
V
V
V
V
IN
IN
SLAVE1
10k
10k
10k
10k
R
FB1
16.5k
R
FB1
16.5k
R
R
FA1
35.7k
FA1
35.7k
STATUS
3.3V
IN
3.3V
IN
IN
IN
LTC2925
SD2
FB2
SD2
FB2
RUN/SS
DC/DC
FB = 0.8V
RUN/SS
DC/DC
FB = 0.8V OUT
2.5V
SLAVE2
2.5V
SLAVE2
OUT
FAULT
RAMPBUF
FAULT
RAMPBUF
LTC2925
R
TB1
8.66k
R
TB1
16.5k
R
FA2
R
FA2
R
FB2
88.7k
R
FB2
88.7k
41.2k
41.2k
TRACK1
TRACK2
TRACK1
TRACK2
TRACK3
3.3V
IN
3.3V
IN
R
TB2
32.4k
R
TB2
88.7k
R
TA1
48.7k
R
TA1
13k
SD3
FB3
RUN/SS
DC/DC
FB = 0.8V
SD3
FB3
RUN/SS
DC/DC
R
TB3
53.6k
R
TB3
86.6k
R
TA2
215k
R
TA2
41.2k
0.015Ω
OUT
1.5V
SLAVE3
FB = 0.8V OUT
1.5V
SLAVE3
TRACK3
R
TA3
348k
R
TA3
100k
GND SCTMR
SDTMR
PGTMR
R
FB3
86.6k
R
R
R
FB3
FA3
FA3
100k
C
C
C
SCTMR
0.41µF
SDTMR
0.082µF
PGTMR
0.82µF
86.6k
100k
SENSEP
SENSEN
2925 TA03a
GND SCTMR
SDTMR
PGTMR
2925 TA03b
C
C
C
SCTMR
0.41µF
SDTMR
0.082µF
PGTMR
0.82µF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2900
Quad Voltage Monitor in MSOP and DFN
Quad Voltage Monitor with Watchdog
Quad Voltage Monitor with Adjustable Reset
Power Supply Margining Controller
16 User Selectable Combinations, ±1.5% Threshold Accuracy
16 User Selectable Combinations, Adjustable Timers
LTC2901
LTC2902
5%, 2.5%, 10% and 12.5% Selectable Supply Tolerances
Single or Dual, Symmetric/Asymmetric High and Low Margining
LTC2920
LTC2921/LTC2922
LTC2923
Power Supply Tracker with Input Monitors
Includes Three (LTC2921) or Five (LTC2922) Remote Sense Switches
Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages
Power Supply Sequencing/Tracking Controller
2925f
LT/TP 0404 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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