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LTC2926IGN#TRPBF [Linear]

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LTC2926IGN#TRPBF
型号： LTC2926IGN#TRPBF
厂家： Linear    Linear
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LTC2926  
MOSFET-Controlled  
Power Supply Tracker  
U
DESCRIPTIO  
FEATURES  
■
Flexible Power Supply Tracking and Sequencing  
The LTC2926 provides a simple solution for tracking and  
sequencing up to three power supply rails. An N-channel  
MOSFET and a few resistors per channel configure the  
load voltages to ramp up and down together, with voltage  
offsets, with time delays or with different ramp rates.  
■
Adjustable Ramp Rates, Offsets and Time Delays  
■
Controls Three Supplies with Series MOSFETs  
■
Integrated Remote Sense Switching  
■
FAULT Input/Output  
■
STATUS Output/Power Good Input  
Automaticremotesenseswitchingcompensatesforvoltage  
drops across the MOSFETs. The LTC2926 provides two  
integrated switches as well as a signal to control optional  
additional external N-channel MOSFET sense switches.  
■
Available in 20-Lead Narrow SSOP and 20-Lead QFN  
(4mm × 5mm) Packages  
U
APPLICATIO S  
The LTC2926 includes I/O signals for communication with  
other devices. The status output asserts after tracking and  
sequencing have completed. A low voltage on the power  
good input after an adjustable timeout period causes load  
disconnect. A low voltage on the fault I/O causes immedi-  
ate load disconnect. Until it is reset, a fault latch prevents  
tracking and keeps the loads disconnected.  
■
V
and V Supply Tracking  
CORE  
I/O  
■
■
■
Microprocessor, DSP and FPGA Supplies  
Servers  
Communications Systems  
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
*Protected by U.S. Patents including 6897717.  
U
TYPICAL APPLICATIO  
1.8V MODULE  
IRF7413Z  
OUT  
3.3V SLAVE2  
1.8V  
SLAVE1  
100Ω  
SENSE  
10Ω  
1.8V SLAVE1  
500mV/DIV  
3.3V MODULE  
IRF7413Z  
3.3V  
SLAVE2  
OUT  
0.1µF  
100Ω  
SENSE  
10Ω  
SGATE2 SGATE1  
2926 TA01b  
V
CC  
5ms/DIV  
D1  
D2  
S1  
15.0k  
9.53k  
FB1  
3.3V SLAVE2  
RAMPBUF  
TRACK1  
15.0k  
9.53k  
S2  
15.0k  
15.0k  
LTC2926  
1.8V SLAVE1  
500mV/DIV  
FB2  
V
CC  
4.02k  
TRACK2  
V
CC  
10k  
4.02k  
STATUS  
STATUS/PGI  
MGATE  
10k  
FAULT  
FAULT  
ON  
0.1µF  
2926 TA01c  
ON/OFF  
RAMP  
5ms/DIV  
GND PGTMR  
1µF  
2926 TA01  
2926fa  
1
LTC2926  
W W U W  
ABSOLUTE AXI U RATI GS  
(Notes 1, 2)  
RMS Currents  
Supply Voltage (V ) ................................. –0.3V to 10V  
CC  
TRACK1, TRACK2................................................5mA  
FB1, FB2 ..............................................................5mA  
D1, S1, D2, S2...................................................30mA  
Operating Temperature  
Input Voltages  
ON ......................................................... –0.3V to 10V  
RAMP .............................................–0.3V to V + 1V  
CC  
TRACK1, TRACK2........................–0.3V to V + 0.3V  
CC  
LTC2926C ................................................ 0°C to 70°C  
LTC2926I ............................................. –40°C to 85°C  
Storage Temperature Range  
PGTMR........................................–0.3V to V + 0.3V  
CC  
Input/Output Voltages  
FAULT .................................................... –0.3V to 10V  
STATUS/PGI (Note 3).......................... –0.3V to 11.5V  
Output Voltages  
GN Package ....................................... –65°C to 150°C  
UFD Package...................................... –65°C to 125°C  
Lead Temperature (Soldering, 10 sec)  
RAMPBUF....................................–0.3V to V + 0.3V  
CC  
GN Package ...................................................... 300°C  
FB1, FB2, D1, S1, D2, S2....................... –0.3V to 10V  
MGATE, RSGATE (Note 3)................... –0.3V to 11.5V  
SGATE1, SGATE2 (Note 3).................. –0.3V to 11.5V  
U
W
U
PACKAGE/ORDER I FOR ATIO  
TOP VIEW  
TOP VIEW  
V
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
RAMPBUF  
TRACK2  
FB2  
CC  
20 19 18 17  
TRACK1  
FB1  
FB1  
S1  
1
2
3
4
5
6
16 FB2  
15 S2  
S1  
S2  
SGATE1  
D1  
14 SGATE2  
13 D2  
SGATE1  
D1  
SGATE2  
D2  
21  
ON  
12 STATUS/PGI  
11 RSGATE  
ON  
STATUS/PGI  
RSGATE  
MGATE  
RAMP  
PGTMR  
PGTMR  
FAULT  
7
8
9 10  
GND 10  
GN PACKAGE  
20-LEAD PLASTIC SSOP  
= 125°C, θ = 85°C/W  
UFD PACKAGE  
20-LEAD (4mm × 5mm) PLASTIC QFN  
T
JMAX  
JA  
EXPOSED PAD (PIN 21) IS GND  
PCB CONNECTION OPTIONAL  
T
JMAX  
= 125°C, θ = 43°C/W  
JA  
ORDER PART NUMBER  
ORDER PART NUMBER  
UFD PART MARKING*  
LTC2926CGN  
LTC2926IGN  
LTC2926CUFD  
LTC2926IUFD  
2926  
2926  
Order Options Tape and Reel: Add #TR  
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF  
Lead Free Part Marking: http://www.linear.com/leadfree/  
Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.  
2926fa  
2
LTC2926  
ELECTRICAL CHARACTERISTICS  
The  
●
denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise specified.  
A
CC  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Supply Voltage  
●
●
V
Input Supply Voltage  
Input Supply Current  
Operating Range  
2.9  
1.5  
3.3  
2.5  
5.5  
3.5  
V
CC  
I
I
I
= 0mA, I = 0mA,  
RAMPBUF  
mA  
CC  
TRACKn  
FBn  
= 0mA  
●
I
I
= –1mA, I = –1mA,  
RAMPBUF  
8.5  
9.5  
10.5  
mA  
TRACKn  
FBn  
= –3mA  
●
●
V
Input Supply Undervoltage Lockout  
V
CC  
Rising  
2.2  
15  
2.4  
50  
2.6  
75  
V
CC(UVLO)  
ΔV  
Input Supply Undervoltage Lockout  
Hysteresis  
mV  
CC(UVLO)  
Control and I/O  
●
●
●
●
●
●
●
●
●
●
●
V
ON Pin Threshold Voltage  
V
Rising  
1.20  
40  
1.23  
75  
1.26  
110  
V
mV  
nA  
V
ON(TH)  
ON  
ΔV  
ON Pin Threshold Voltage Hysteresis  
ON Pin Input Current  
ON(TH)  
I
ON  
V
V
V
V
V
V
= 1.2V, V = 5.5V  
0
100  
ON  
CC  
V
ON Pin Fault Clear Threshold Voltage  
Fault Clear Delay  
Falling  
Falling  
Rising  
Rising  
0.465  
1
0.500  
3
0.535  
10  
ON(CLR)  
CLR  
ON  
t
µs  
V
ON  
V
ON Pin Fault Arm Threshold Voltage  
Fault Arm Delay  
0.565  
1
0.600  
4.5  
0.635  
10  
ON(ARM)  
ARM  
ON  
t
µs  
V
ON  
V
FAULT Pin Input Threshold Voltage  
FAULT Pin Pull-up Current  
FAULT Pin Output Low Voltage  
FAULT Pin Output High Voltage  
Falling  
0.465  
–3.0  
0.500  
–8.5  
100  
550  
0.535  
–13  
FAULT(TH)  
FAULT  
I
Fault Latch Clear, V  
= 1.5V  
µA  
mV  
mV  
FAULT(UP)  
FAULT  
V
V
Fault Latch Set, I  
= 5mA, V = 2.7V  
400  
FAULT(OL)  
FAULT  
CC  
Fault Latch Clear, I  
= –1µA  
300  
1.10  
30  
900  
FAULT(OH)  
FAULT  
(V – V  
)
CC  
FAULT  
●
●
V
STATUS/PGI Pin Input Threshold  
Voltage  
V
Rising  
1.23  
75  
1.36  
150  
V
PGI(TH)  
STATUS/PGI  
ΔV  
STATUS/PGI Pin Input Threshold  
Voltage Hysteresis  
mV  
PGI(TH)  
●
●
●
I
STATUS/PGI Pin Pull-Up Current  
STATUS/PGI Pin Output Low Voltage  
STATUS/PGI Pin Output High Voltage  
STATUS/PGI On, V  
= 1.5V  
–7  
–10  
200  
5.5  
–13  
400  
6.0  
µA  
mV  
V
PGI(UP)  
STATUS/PGI  
V
V
V
ON  
Low, I  
= 5mA, V = 2.7V  
STATUS/PGI CC  
STATUS(OL)  
I
= –1µA  
5.0  
STATUS(OH)  
STATUS/PGI  
(V  
– V )  
CC  
STATUS/PGI  
●
●
●
●
V
PGTMR Pin Threshold Voltage  
PGTMR Pin Pull-Up Current  
V
Rising  
1.10  
–8  
1.23  
–10  
4
1.36  
–12  
10  
V
µA  
PGTMR(TH)  
PGTMR(UP)  
PGTMR(DN)  
PGTMR  
I
I
ON High, V  
= 1V  
PGTMR  
PGTMR Pin Pull-Down Current  
PGTMR Pin Clear Threshold Voltage  
ON Low, V  
= 0.1V, V = 2.7V  
0.5  
50  
mA  
mV  
PGTMR  
CC  
V
V
Falling  
100  
150  
PGTMR(CLR)  
PGTMR  
Ramp Buffer  
●
●
●
I
RAMP Pin Input Current  
0V < V  
< 5.5V, V = 5.5V  
0
0
1
10  
60  
µA  
mV  
mV  
RAMP(IN)  
RAMP  
CC  
= 0mA  
CC RAMPBUF  
V
V
Ramp Buffer Offset Voltage  
RAMPBUF Pin Output Low Voltage  
V
RAMP  
= 1/2 V , I  
RAMPBUF(OS)  
I
= 3mA  
32  
RAMPBUF(OL)  
RAMPBUF  
2926fa  
3
LTC2926  
ELECTRICAL CHARACTERISTICS  
The  
●
denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at T = 25°C. V = 3.3V unless otherwise specified.  
A
CC  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
●
V
RAMPBUF Pin Output High Voltage  
I
= –3mA  
60  
80  
mV  
RAMPBUF(OH)  
RAMPBUF  
(V – V  
)
CC  
RAMPBUF  
Tracking Channels  
●
●
I
I
to I  
FBn  
Current Mismatch  
TRACKn TRACKn  
I
I
= –10µA  
= –1mA  
0
0
3
3
%
%
ERROR(%)  
FBn  
TRACKn  
TRACKn  
TRACKn  
(I – I  
)/I  
• 100%  
●
●
V
TRACK Pins Voltage  
I
I
= –10µA  
= –1mA  
0.776  
0.776  
0.800  
0.800  
0.824  
0.824  
V
V
TRACK  
TRACKn  
TRACKn  
●
●
●
V
FB Pins Internal Reference Voltage  
FB Pins Leakage Current  
V
= V , I = 0mA  
0.784  
0.800  
0
0.816  
10  
V
nA  
V
FB(REF)  
TRACKn  
CC FBn  
I
V
FBn  
= 0.8V, V = 5.5V  
CC  
FB(LEAK)  
V
FB Pins Clamp Voltage  
–1mA < I < –1µA  
1.7  
2.0  
2.4  
FB(CLAMP)  
FBn  
Master Ramp and Supply  
●
ΔV  
MGATE Pin External N-Channel Gate  
Drive (V – V  
I
= –1µA  
MGATE  
5.0  
5.5  
6.0  
V
MGATE  
)
CC  
MGATE  
●
●
●
I
I
I
MGATE Pin Pull-Up Current  
Fault Latch Clear, V High, V  
= 3.3V  
= 3.3V  
–7  
7
–10  
10  
–13  
13  
µA  
µA  
MGATE(UP)  
MGATE(DN)  
MGATE(FAULT)  
ON  
MGATE  
MGATE Pin Pull-Down Current  
MGATE Pin Fault Pull-Down Current  
Fault Latch Clear, V Low, V  
ON  
MGATE  
Fault Latch Set, V High, V  
CC  
= 5.5V,  
5
20  
50  
mA  
ON  
MGATE  
V
= 5.5V  
Slave Supplies  
●
●
●
ΔV  
SGATE Pins External N-Channel Gate  
I
= –1µA, V = 0.75V  
5.0  
–6  
6
5.5  
–10  
10  
6.0  
–13  
13  
V
µA  
µA  
SGATE  
SGATEn  
FBn  
Drive (V  
– V )  
CC  
SGATEn  
I
I
SGATE Pins Pull-Up Current  
Fault Latch Clear, V = V  
V
– 10mV,  
+ 10mV,  
SGATE(UP)  
SGATE(DN)  
FBn  
FB(REF)  
FB(REF)  
= 3.3V  
SGATEn  
SGATE Pins Pull-Down Current  
Fault Latch Clear, V = V  
FBn  
V
= 3.3V  
SGATEn  
●
●
●
I
I
I
SGATE Pins Fast Pull-Up Current  
SGATE Pins Fast Pull-Down Current  
SGATE Pins Fault Pull-Down Current  
Fault Latch Clear, V = 0V, V  
= 3.3V  
–21  
21  
5
–30  
30  
–39  
39  
µA  
µA  
SGATE(UPFST)  
SGATE(DNFST)  
SGATE(FAULT)  
FBn  
SGATEn  
Fault Latch Clear, V = 1V, V  
= 3.3V  
FBn  
SGATEn  
Fault Latch Set, V High, V  
CC  
= 5.5V,  
20  
50  
mA  
ON  
SGATEn  
V
= 5.5V  
Remote Sense Switches  
●
ΔV  
RSGATE  
RSGATE Pin External N-Channel Gate  
Drive (V – V  
I
= –1µA  
5.0  
5.5  
6.0  
V
RSGATE  
)
CC  
RSGATE  
●
●
I
I
RSGATE Pin Pull-Up Current  
Fault Latch Clear, Switches On, V  
= 0V  
RSGATE  
–7  
7
–10  
10  
–13  
13  
µA  
µA  
RSGATE(UP)  
RSGATE(DN)  
RSGATE Pin Pull-Down Current  
Fault Latch Clear, Switches Off,  
V
= 3.3V  
RSGATE  
●
●
●
I
RSGATE Pin Fault Pull-Down Current  
RSGATE Pin Threshold Voltage  
Fault Latch Set, Switches Off,  
= 5.5V, V = 5.5V  
5
20  
1.23  
2
50  
1.36  
10  
mA  
V
RSGATE(FAULT)  
V
RSGATE  
CC  
V
Ramping Completed on Pin Low, RSGATE  
Falling  
1.10  
RSGATE(TH)  
Ω
R
Remote Sense Switch On-Resistance Switches On, V = V + 0.3V, I = –10mA  
Dn CC Sn  
SW(ON)  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 3: The MGATE, SGATE1, SGATE2, RSGATE and STATUS/PGI pins are  
internally limited to a minimum of 11.5V. Driving these pins to voltages  
beyond the clamp level may damage the part.  
Note 2: All currents into the device pins are positive; all currents out of  
the device pins are negative. All voltages are referenced to ground unless  
otherwise specified.  
2926fa  
4
LTC2926  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at T = 25°C, V = 3.3V  
A
CC  
unless otherwise specified.  
Supply Current vs Supply Voltage  
Supply Current vs Temperature  
Track Pin Voltage vs Temperature  
12  
10  
8
12  
10  
8
0.812  
0.808  
0.804  
0.800  
0.796  
0.792  
0.788  
I
I
I
= –3mA  
RAMPBUF  
TRACKn  
FBn  
I
I
I
= –3mA  
RAMPBUF  
TRACKn  
FBn  
I
= –10µA  
= –1mA  
TRACK  
= –1mA  
= –1mA  
= –1mA  
6
6
I
= –1mA  
TRACK  
I
I
I
= 0mA  
RAMPBUF  
TRACKn  
FBn  
I
I
I
= 0mA  
RAMPBUF  
TRACKn  
FBn  
= 0mA  
= 0mA  
4
4
= 0mA  
= 0mA  
2
2
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
(V)  
–50  
–25  
0
25  
50  
75  
100  
–50  
–25  
0
25  
50  
75  
100  
V
TEMPERATURE (°C)  
TEMPERATURE (°C)  
CC  
2926 G01  
2926 G02  
2926 G03  
Gate Drive Voltages vs  
Supply Voltage  
Gate Drive Voltages vs  
Load Current  
Gate Fault Pull-Down Currents vs  
Supply Voltage  
6
5
4
3
2
1
0
6.0  
5.8  
5.6  
5.4  
5.2  
5.0  
30  
25  
20  
15  
10  
5
GATE DRIVE = V – V  
PIN  
MGATE, RSGATE, SGATE1, SGATE2 PINS  
MGATE, RSGATE, SGATE1, SGATE2 PINS  
CC  
SGATE1,  
SGATE2 PINS  
FAST PULL-UP  
MODE  
MGATE, RSGATE,  
SGATE1, SGATE2 PINS  
PULL-UP MODE  
GATE DRIVE = V – V  
PIN  
CC  
FAULT LATCH SET  
I
= –1µA  
GATE  
0
0
5
10  
15  
20  
25  
30  
35  
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
(V)  
I
(µA)  
V
(V)  
V
LOAD  
CC  
CC  
2926 G06  
2926 G05  
2926 G07  
MGATE, RSGATE Fault Pull-Down  
Currents vs Temperature  
SGATE Fault Pull-Down Current vs  
Temperature  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
MGATE, RSGATE PINS  
SGATE1, SGATE2 PINS  
V
= 5.5V  
V
= 5.5V  
CC  
CC  
V
= 3.3V  
= 2.9V  
V
= 3.3V  
= 2.9V  
CC  
CC  
FAULT LATCH SET  
V
V
CC  
FAULT LATCH SET  
CC  
0
–50  
0
–50  
–25  
0
25  
50  
75  
100  
–25  
0
25  
50  
75  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
2926 G08  
2926 G09  
2926fa  
5
LTC2926  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Specifications are at T = 25°C, V = 3.3V  
A
CC  
unless otherwise specified.  
RAMPBUF Output Low Voltage vs  
Temperature  
RAMPBUF Output High Voltage vs  
Temperature  
Logic Output Low Voltages vs  
Supply Voltage  
50  
40  
30  
20  
10  
0
100  
80  
60  
40  
20  
0
250  
200  
150  
100  
50  
I
= 3mA  
I
V
= –3mA  
RAMPBUF  
OH  
RAMPBUF  
= V – V  
CC RAMPBUF  
STATUS/PGI PIN  
V
= 2.9V  
CC  
I
= 5mA  
STATUS/PGI  
V
= 2.9V  
CC  
V
= 5.5V  
CC  
V
= 5.5V  
CC  
FAULT PIN  
I
= 5mA  
FAULT  
0
–50  
–25  
0
25  
50  
75  
100  
–50  
–25  
0
25  
50  
75  
100  
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
(V)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
V
CC  
2926 G10  
2926 G11  
2926 G12  
2926fa  
6
LTC2926  
U
U
U
PI FU CTIO S GN/UFD Packages  
to the slave supply, the FB pins will not force the slave’s  
feedback node above 2.4V. In addition, it will not actively  
sink current even when the LTC2926 is not powered. Tie  
unused FB pins to GND.  
D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15):  
Remote Sense Switches #1 and #2. A 10Ω (max) switch  
connectseachpairofpins(D1/S1andD2/S2)afterMGATE,  
SGATE1 and SGATE2 are all fully enhanced (MGATE >  
RAMP + 4.9V or RAMP > V , and SGATE1, SGATE2 >  
CC  
GND (Pin 10/Pin 8): Device Ground.  
V
+ 4.9V). The switch can be used to compensate for  
CC  
MGATE (Pin 12/Pin 10): Master Gate Drive for External  
N-Channel MOSFET/Master Ramp. When the ON pin is  
high, an internal 10µA current charges the gate of an  
external N-channel MOSFET. A capacitor from MGATE  
to GND sets the master ramp rate. Add a 10Ω resistor  
between the capacitor and the MOSFET’s gate to prevent  
high frequency oscillations. An internal charge pump  
guarantees that the MGATE pin voltage will pull up to  
thevoltagedropacrosstheexternalMOSFETthatcontrols  
a slave or the master supply. Connect the switch between  
the load and the supply’s sense node. Before the external  
MOSFET is fully enhanced, a resistor between the supply’s  
output and sense nodes provides local feedback. When  
the ON pin voltage is low, the switch will open before the  
MGATE, SGATE1 and SGATE2 pins will ramp down. Leave  
unused switch terminal pairs unconnected.  
5.5V above V , which ensures that logic-level N-channel  
CC  
Exposed Pad (Pin 21, UFD Package Only): Exposed pad  
may be left open or connected to device GND.  
MOSFETs are fully enhanced. When the ON pin is pulled  
low, the MGATE pin is pulled to GND by a 10µA current  
source. Upon a fault condition, the MGATE pin is pulled  
low immediately with 20mA. To create a master ramp  
signal without an external MOSFET, tie the MGATE pin to  
the RAMP pin. A weak internal clamp on the RAMP pin  
FAULT (Pin 9/Pin 7): Negative-Logic Fault Input/Output.  
Under normal conditions the internal fault latch is not set  
andan8.5µAcurrentpullsupFAULTtoadiodedropbelow  
V . When the voltage at FAULT is pulled below 0.5V, a  
CC  
limits MGATE to V + 1V in this case. Leave the MGATE  
fault condition is latched and an internal N-channel MOS-  
FET pulls FAULT to GND until the latch is reset. The fault  
condition also pulls STATUS/PGI low, opens the remote  
sense switches, and pulls MGATE, SGATE1 and SGATE2  
to GND to disconnect the master and slave supplies from  
their loads. Pulling STATUS/PGI below 1V after the power  
good time-out delay also latches a fault. The fault latch is  
CC  
pin unconnected if it is unused.  
ON (Pin 7/Pin 5): On Control Input. The ON pin has  
a threshold of 1.23V with 75mV of hysteresis. A high  
causes 10µA to flow out of the MGATE pin, ramping up  
the supplies. A low causes 10µA to flow into the MGATE  
pin, ramping down the supplies. Pull the ON pin below  
0.5V to reset the fault latch. Pull the ON pin above 0.6V  
after a fault latch reset to arm the fault latch.  
reset when the ON pin voltage is below 0.5V, or when V  
CC  
is undervoltage. The fault latch is armed when the ON pin  
voltage exceeds 0.6V. To auto-retry after a fault, connect  
FAULT to the ON pin. Leave the FAULT pin unconnected  
if it is unused.  
PGTMR (Pin 8/Pin 6): Power Good Timer. Connect an  
external capacitor between PGTMR and GND to set the  
Power Good Time-Out Delay. When the ON pin is above  
FB1, FB2 (Pins 3, 18/Pins 1, 16): Feedback Control In-  
put/Outputs. Each FB pin connects to the feedback node  
of a slave supply. Connect an FB pin to the tap point of a  
resistive voltage divider between the source (load side)  
of the external MOSFET and GND. For a slave supply with  
an accessible feedback path, no external MOSFET may  
be necessary. In that case, connect an FB pin to the tap  
point of a resistive voltage divider between the supply  
generator’s feedback node and GND. To prevent damage  
1.23V, a 10µA current pulls up PGTMR to V , otherwise  
CC  
an internal N-channel MOSFET pulls PGTMR to GND. If  
the voltage on PGTMR exceeds 1.23V and the voltage  
on STATUS/PGI is not above 1.23V, a fault condition is  
latched,theremotesenseswitchesareopened,andFAULT,  
STATUS/PGI, MGATE, SGATE1, SGATE2 and RSGATE will  
be immediately pulled to GND. To disable the Power Good  
Timer tie PGTMR to GND.  
2926fa  
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RAMP (Pin 11/ Pin 9): Ramp Buffer Input. Connect the  
RAMP pin to the master ramp signal to force the slave  
supplies to track it. When the RAMP pin is connected to  
the source of an external N-channel MOSFET, the slave  
supplies track the MOSFET’s source, the master supply  
voltage, as it ramps up and down. When a master supply  
is not required, the RAMP pin can be tied directly to the  
MGATEpintoformamasterrampvoltage.Inthisconfigura-  
tion, the supplies track the capacitor on the MGATE pin as  
it is charged and discharged by the 10µA current source  
that is controlled by the ON pin. The RAMP pin is weakly  
SGATE1,SGATE2(Pins5,16/Pins3,14):SlaveGateCon-  
trollers for External N-Channel MOSFETs. Each SGATE pin  
ramps a slave supply by controlling the gate of an external  
N-channel MOSFET so that its source terminal follows the  
tracking profile set by external resistors and the master  
ramp. It is a good practice to add a 10Ω resistor between  
this pin and the MOSFET’s gate to prevent high frequency  
oscillations. An internal charge pump guarantees that the  
SGATE pin voltage will pull up to 5.5V above V , which  
CC  
ensures that logic-level N-channel MOSFETs are fully  
enhanced. Leave unused SGATE pins unconnected.  
clamped to V + 1V. Do not drive RAMP above V with  
CC  
CC  
STATUS/PGI (Pin 14/Pin 12): Status Output/Power Good  
Input. A 10µA current pulls up STATUS/PGI when MGATE,  
SGATE1 and SGATE2 are fully enhanced, and the remote  
senseswitchesareclosed,otherwiseaninternalN-channel  
MOSFET pulls down STATUS/PGI. If the STATUS/PGI pin  
is pulled below 1V after the power-good time-out delay  
(see PGTMR pin description), the fault latch is set, and  
MGATE, SGATE1, SGATE2 and RSGATE are all pulled low  
immediately. An internal charge pump guarantees that the  
a low impedance source to avoid sinking large currents  
into the pin. Ground the RAMP pin if it is unused.  
RAMPBUF (Pin 20/Pin 18): Ramp Buffer Output. The  
RAMPBUF pin provides a low impedance buffered ver-  
sion of the signal on the RAMP pin. This buffered output  
drives the resistive voltage dividers that connect to the  
TRACK pins. Limit the capacitance at the RAMPBUF pin  
to less than 100pF.  
STATUS/PGI pin voltage will pull up to 5.5V above V .  
CC  
RSGATE (Pin 13/Pin 11): Gate Drive for Internal and  
External N-Channel MOSFET Remote Sense Switches. A  
remote sense path between a load and the sense input of  
itssupplygeneratorautomaticallycompensatesforvoltage  
drops across the tracking MOSFET. After the series MOS-  
FETs are fully enhanced, a 10µA current pulls up RSGATE.  
An internal charge pump guarantees that RSGATE will  
An external pull-up resistor may be added to limit the  
STATUS/PGIvoltagetologiclevels.LeavetheSTATUS/PGI  
pin unconnected if it is unused.  
TRACK1,TRACK2(Pins2,19/Pins20,17):TrackingCon-  
trol Inputs. A resistive voltage divider between RAMPBUF  
and each TRACK pin determines the tracking profile of  
each supply channel. Each TRACK pin pulls up to 0.8V,  
and the current supplied at TRACK is mirrored at FB. The  
TRACK pins are capable of supplying at least 1mA when  
pull up to 5.5V above V , which ensures that logic-level  
CC  
N-channel MOSFETs are fully enhanced. When the voltage  
atRSGATEexceedsV +4.9V,theSTATUS/PGIpull-down  
CC  
is released. When the ON pin is low, a 10µA current source  
pulls RSGATE to GND. Supplies will not track down until  
the RSGATE pin voltage falls below 1.23V, which ensures  
that the remote sense switches open before the loads are  
disconnected. Connect RSGATE to the gates of additional  
externalN-channelMOSFETstocreatemoreremotesense  
switches. Upon a fault condition, the RSGATE pin is pulled  
low immediately with 20mA. Optionally connect a capaci-  
tor between RSGATE and GND to set the switch-on rate  
or to add delay between switch closure and STATUS/PGI  
assertion. Leave RSGATE unconnected if it is unused.  
V
= 2.9V. They may be capable of supplying up to 10mA  
CC  
when the supply is at 5.5V, so care should be taken not to  
short this pin for extended periods. Limit the capacitance  
at the TRACK pins to less than 25pF. Leave unused TRACK  
pins unconnected.  
V
(Pin 1/Pin 19): Positive Voltage Supply. Operating  
CC  
rangeisfrom2.9Vto5.5V. Anundervoltagelockoutresets  
the part when the supply is below 2.4V. V should be  
bypassed to GND with a 0.1µF capacitor.  
CC  
2926fa  
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LTC2926  
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V
CC  
+
–
2.4V  
UVLO  
FAST PULL-DOWN  
V
CC  
CLEAR/ARM  
SIGNAL LATCH  
V
CC  
ON  
+
–
R
8.5µA  
FAULT LATCH  
R
DELAY  
CLR/ARM  
0.6V  
0.5V  
S
Q
FAULT  
FAULT  
+
–
S
Q
DELAY  
+
–
1.23V  
+
–
0.5V  
V
CC  
10µA  
+
–
0.1V  
PGTMR  
UVLO  
+
–
PGTMR HIGH  
1.23V  
1.23V  
CHARGE  
PUMP  
+
–
10µA  
PGI LOW  
STATUS/PGI  
+
–
UVLO  
RSGATE  
V
+ 4.9V  
CC  
CHARGE  
PUMP  
+
–
10µA  
RSGATE  
1.23V  
GATE UP  
MGATE  
+
–
FAST  
PULL-DOWN  
MGATE  
10µA  
RAMP + 4.9V  
+
–
RAMP  
CHARGE  
PUMP  
V
CC  
10µA  
RSGATE UP  
RSGATE  
+
–
SGATE1  
+ 4.9V  
V
V
CC  
FAST  
PULL-DOWN  
10µA  
+
–
SGATE2  
+ 4.9V  
CC  
D1  
S1  
S2  
D2  
CHARGE  
PUMP  
V
CC  
SGATE2  
SGATE1  
10µA/30µA  
+
–
0.8V  
UP/DOWN  
V
CC  
FAST  
PULL-DOWN  
+
–
0.8V  
10µA/30µA  
TRACK2  
TRACK1  
FB2  
FB1  
RAMPBUF  
RAMP  
1x  
GND  
2926 BD  
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APPLICATIO S I FOR ATIO  
Power Supply Tracking and Sequencing  
Operation  
The LTC2926 handles a variety of power-up profiles to  
satisfy the requirements of digital logic circuits including  
FPGAs, PLDs, DSPs and microprocessors. These require-  
mentsfallintooneofthefourgeneralcategoriesillustrated  
in Figures 1 to 4.  
The LTC2926 provides a simple solution to allow all of  
the power supply tracking and sequencing profiles shown  
in Figures 1 to 4. A single LTC2926 controls up to three  
supplies:two“slave”suppliesthattracka“master”signal.  
WithjustfourresistorsandanexternalN-channelMOSFET,  
each slave supply is configured to ramp up and down as  
a function of the master signal. This master signal can  
be a third supply that is ramped up through an external  
MOSFET, whose ramp rate is set with a single capacitor,  
or it can be a signal generated by tying the MGATE and  
RAMP pins together to an external capacitor.  
Some applications require that the potential difference  
between two power supplies must never exceed a speci-  
fied voltage. This requirement applies during power-up  
and power-down as well as during steady-state operation,  
often to prevent destructive latch-up in a dual supply IC.  
Typically, this is achieved by ramping the supplies up  
and down together (Figure 1). In other applications it is  
desirable to have the supplies ramp up and down ratio-  
metrically (Figure 2) or with fixed voltage offsets between  
them (Figure 3).  
Tracking Cell and Gate Controller Cell  
The LTC2926’s operation is based on the combination of  
a tracking cell and a gate controller cell that is shown in  
Figure 5. The tracking cell servos the TRACK pin at 0.8V,  
andthecurrentsuppliedbytheTRACKpinismirroredatthe  
FB pin. The gate controller cell servos the FB pin at 0.8V by  
Certain applications require one supply to come up after  
another. For example, a system clock may need to start  
before a block of logic. In this case, the supplies are se-  
quenced as in Figure 4, where the 1.8V supply ramps up  
completely followed by the 2.5V supply.  
driving the gate of the external N-channel MOSFET (Q ),  
EXT  
and establishes the slave output voltage at the source of  
theMOSFETbasedontheTRACKpincurrentandresistors  
MASTER  
SLAVE2  
SLAVE2  
SLAVE1  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F01  
2926 F02  
5ms/DIV  
5ms/DIV  
Figure 1. Coincident Tracking  
Figure 2. Ratiometric Tracking  
MASTER  
SLAVE2  
SLAVE2  
SLAVE1  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F03  
2926 F04  
5ms/DIV  
5ms/DIV  
Figure 3. Offset Tracking  
Figure 4. Supply Sequencing  
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APPLICATIO S I FOR ATIO  
Q
EXT  
SUPPLY  
SLAVE  
LTC2926  
TRACKING CELL  
GATE CONTROLLER CELL  
V
CC  
V
+ 5V  
CC  
10µA  
0.8V  
+
–
SGATE  
+
–
0.8V  
10µA  
MASTER  
RAMP  
R
R
FB  
FA  
TB  
TA  
TRACK  
FB  
I
I
FB  
TRACK  
R
R
2926 F05  
Figure 5. Simplified Tracking Cell and Gate Controller Cell Combination  
R and R . The slave output voltage varies as a function  
The rising master signal decreases the tracking current  
mirrored out of the FB1 pin. The gate controller circuitry  
maintains 0.8V at FB1 by driving the SGATE1 voltage and,  
via the external MOSFET source-follower, the slave supply  
output. When the slave supply output reaches the slave  
supply module voltage, the FB1 pin will fall below 0.8V  
and the gate controller will drive the SGATE1 pin above  
FA  
FB  
of the master signal with terms set by R and R . By  
TA  
TB  
selecting appropriate values of R and R , it is possible  
TA  
TB  
to generate any of the profiles in Figures 1 to 4.  
Controlling the Ramp-Up and Ramp-Down Behavior  
TheoperationoftheLTC2926ismosteasilyunderstoodby  
referring to the simplified functional diagram in Figure 6.  
WhentheONpinislow,theremotesenseswitchisopened  
and the MGATE pin is pulled to ground causing the master  
V
to fully enhance the MOSFET.  
CC  
After the MGATE, SGATE1 and SGATE2 pins reach their  
maximum voltages, the RSGATE pin is pulled up by a  
10µA current source from an internal charge pump,  
which closes the integrated remote sense switches. The  
integrated remote sense switch allows the slave supply  
generatortocompensateforvoltagedropacrosstheslave’s  
MOSFET (Q1).  
signal to remain low. Since the current through R is at  
TB1  
its maximum when the master signal is low, the current  
sourced by FB1 is also at its maximum. The current forces  
the FB1 pin voltage above 0.8V, which pulls the SGATE1  
pin low and disconnects the slave’s supply generator. The  
minimum voltage across the slave load is a function of the  
maximum FB1 current, the feedback divider resistors, and  
the load resistance (see Load Requirements).  
When the ON pin falls below V  
– ΔV , typically  
ON(TH)  
ON(TH)  
1.16V, the remote sense switch opens and the MGATE pin  
pulls down with 10µA. The master signal and the slave  
supplies will fall at the same rate as they rose previously,  
following the tracking or sequencing profile in reverse.  
When the ON pin rises above 1.23V, the master signal  
ramps up, and the slave supply tracks the master signal.  
The master ramp rate is set by an external capacitor driven  
by a 10µA current source from an internal charge pump. If  
noexternalMOSFETisusedforthemastersignal,theramp  
rate is set by tying the MGATE and RAMP pins together  
at one terminal of the external capacitor (see Ratiometric  
Tracking Example or Supply Sequencing Example). The  
The ON pin can be controlled by a digital I/O pin or it  
can be used to monitor an input supply. By connecting a  
resistive voltage divider from an input supply to the ON  
pin, the supplies will ramp up only after the monitored  
supply reaches a preset voltage.  
MGATE pin voltage will be limited to V + 1V (max) by  
CC  
the weak internal clamp on the RAMP pin.  
2926fa  
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APPLICATIO S I FOR ATIO  
SUPPLY MODULE  
Q0  
OUT  
MASTER  
SLAVE1  
C
MGATE  
SUPPLY MODULE  
OUT  
Q1  
R
X1  
SENSE  
V
CC  
MGATE  
RAMP  
REMOTE SENSE SWITCH  
D1  
S1  
MGATE  
+
–
RAMP + 4.9V  
SGATE1  
CHARGE  
PUMP  
10µA  
10µA  
+
–
TO  
RSGATE  
PIN  
V
+ 4.9V  
CC  
SGATE2  
+ 4.9V  
+
–
V
CC  
CHARGE  
PUMP  
10µA  
10µA  
ON  
ON/OFF  
+
–
1.23V  
RAMPBUF  
1x  
V
CC  
CHARGE  
PUMP  
10µA  
10µA  
0.8V  
+
SGATE1  
FB1  
0.8V  
+
–
–
R
R
R
R
TB1  
FB1  
TRACK1  
GND  
TA1  
FA1  
2926 F06  
Figure 6. Simplified Functional Block Diagram  
Optional Master Supply MOSFET  
the MGATE pin. The series MOSFET controls any supply  
with an output voltage between 0V and V .  
CC  
Figure 7 illustrates how an optional external N-channel  
MOSFET(deviceQ0)canrampupasupplythatdoublesas  
themastersignal. TheMOSFET’sgateistiedtotheMGATE  
pin and its source is tied to the RAMP pin. The MGATE pin  
sources or sinks 10µA to ramp the MOSFET’s gate up or  
down at a rate set by the external capacitor connected to  
To compensate for voltage drop across the master supply  
MOSFET, add an optional external remote sense switch  
(device Q3 in Figure 7) connected between RAMP and the  
sense input of the master voltage supply module. Tie the  
gate of the external switch MOSFET to the RSGATE pin  
for automatic remote sense switching.  
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APPLICATIO S I FOR ATIO  
3.3V MODULE  
1.8V MODULE  
IN OUT  
IN  
Q0  
Q1  
1.8V  
SLAVE1  
V
IN  
V
IN  
V
IN  
IN OUT  
MASTER  
V
R
X0  
R
X1  
R
X2  
R
R
X1  
Q3  
SENSE  
SENSE  
10Ω  
10Ω  
1.8V MODULE  
IN OUT  
2.5V MODULE  
IN OUT  
Q1  
Q2  
1.8V  
SLAVE1  
2.5V  
V
IN  
SLAVE2  
C
MGATE  
X2  
NC  
SENSE  
SENSE  
10Ω  
10Ω  
RSGATE MGATE RAMP SGATE1 SGATE2  
2.5V MODULE  
IN OUT  
D1  
D2  
Q2  
2.5V  
SLAVE2  
C
MGATE  
V
V
CC  
S1  
S2  
IN  
0.1µF  
SENSE  
10Ω  
RAMPBUF  
R
R
R
R
TB1  
FB1  
RSGATE MGATE RAMP SGATE1 SGATE2  
TRACK1  
FB1  
FB2  
D1  
D2  
LTC2926  
FA1  
TA1  
R
R
TB2  
R
R
FB2  
V
V
CC  
S1  
S2  
IN  
0.1µF  
TRACK2  
V
IN  
RAMPBUF  
TA2  
FA2  
R
R
R
R
V
TB1  
FB1  
IN  
10k  
TRACK1  
FB1  
FB2  
FAULT  
FAULT  
ON  
LTC2926  
10k  
FA1  
TA1  
STATUS/PGI  
STATUS  
ON/OFF  
R
R
GND  
PGTMR  
TB2  
R
R
FB2  
2926 F08  
TRACK2  
FAULT  
C
V
IN  
PGTMR  
TA2  
FA2  
V
IN  
10k  
FAULT  
Figure 8. Typical Application Without Master Supply  
10k  
STATUS/PGI  
STATUS  
ON/OFF  
ON  
GND  
PGTMR  
2926 F07  
currentpullstheFAULTpinvoltagehigh.Whenanupstream  
monitor signal pulls FAULT below 0.5V, the LTC2926’s  
internal fault latch is set, which immediately opens the  
remote sense switches and cuts off the master and slave  
supplies by pulling MGATE, SGATE1 and SGATE2 to GND.  
AfaultalsoactivatestheinternalMOSFETpull-downonthe  
STATUS/PGI pin, which indicates to external downstream  
monitoring circuits that the supplies are no longer valid  
(see Status Output). Until the fault latch is reset, the sup-  
plies stay disconnected and an internal pull-down keeps  
the FAULT pin low as a signal to upstream monitors.  
C
PGTMR  
Figure 7. Typical Application with Master Supply  
Ramp Buffer  
TheRAMPBUFpinprovidesabufferedversionoftheRAMP  
pin voltage that drives the resistive dividers on the TRACK  
pins.WhenthereisnoexternalMOSFET,itsourcesorsinks  
up to 3mA to drive the track resistors even though the  
MGATE pin only supplies 10µA (Figure 8). The RAMPBUF  
pinalsoprovesusefulinsystemswithanexternalMOSFET.  
If R  
were directly connected to the MOSFET’s source  
TBn  
Fault latch reset is initiated by bringing the ON pin voltage  
below0.5V, andcompletedwhenPGTMRis<0.1V. Reduc-  
(the master output), the servo mechanism of the tracking  
cellcouldpotentiallydrivethemasteroutputtowards0.8V  
when the MOSFET is off. The ramp buffer prevents this  
by eliminating that path for current.  
ing the V pin voltage below V  
– ΔV  
,
CC  
CC(UVLO)  
CC(UVLO)  
typically 2.35V, also resets the fault latch. After it is  
cleared, the fault latch is armed by bringing the ON pin  
voltage above 0.6V. No faults can be latched until after  
the latch is armed.  
Fault Input/Output  
TheFAULTpinallowsexternalupstreammonitoringcircuits  
to control and to communicate with the LTC2926. The pin  
is driven internally by an N-channel MOSFET pull-down  
The FAULT pin is pulled up by 8.5µA to V through a  
CC  
Schottky diode, which allows the pin to be pulled safely  
above the LTC2926’s supply if required. Leave the FAULT  
pin unconnected if it is unused.  
to GND, and by an 8.5µA pull-up to V through a series  
CC  
diode.Undernormalconditions,theMOSFETisoffandthe  
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APPLICATIO S I FOR ATIO  
Status Output  
timeallotted.Ifsupplyrampingcompletes,anydownstream  
circuits that pull down the STATUS/PGI pin after the timer  
duration also will trip the timeout circuit. A fault caused  
by a power good timeout has the same effect as a fault  
triggered by the FAULT pin: supplies are disconnected  
and the fault latch is set. The fault latch may be cleared as  
described in the Fault Input/Output section above.  
The output aspect of the STATUS/PGI pin allows the  
LTC2926 to control and communicate with external  
downstream circuits. The pin is driven internally by an  
N-channel MOSFET pull-down to GND and a 10µA pull-  
up to an internal charge pump. The pull-down keeps the  
STATUS/PGI pin low until MGATE, SGATE1 and SGATE2  
are fully enhanced, and the remote sense switches are  
closed. The pull-down then shuts off, and STATUS/PGI  
pin rises, indicating to downstream monitors that the  
supplies are fully ramped up. The STATUS/PGI pin pulls  
low when the MGATE, SGATE1, SGATE2 or RSGATE pin  
is low, either because a fault has been latched, or because  
the ON pin is low.  
Thepowergoodtimerdurationisconfiguredbyacapacitor  
tied between PGTMR and GND. The pin’s 10µA current  
source ramps up the capacitor voltage when the ON pin is  
high, otherwise 4mA pulls PGTMR to GND. The capacitor,  
C
, required to configure the power good timeout  
PGTMR  
duration, t  
, is determined from:  
PGTMR  
10µA • tPGTMR  
CPGTMR  
=
An internal charge pump rail at V + 5.5V sources the  
CC  
1.23V  
STATUS/PGI pull-up current. An external resistor may be  
added to create logic level voltages, or the pin may be  
used to enhance the gates of external N-channel MOSFET  
switches, if desired.  
If the power good timeout feature is not used, tie PGTMR  
to GND.  
Retry on Fault  
Power Good Timeout  
TheLTC2926continuouslyattemptstorampupthesupplies  
after a fault if the FAULT pin is tied to the ON pin. When  
the FAULT and ON pins go low together, the internal fault  
latch is set by the falling FAULT pin, and the fault latch is  
reset by the falling ON pin. A short internal delay of several  
microseconds guarantees triggering of fast pull-down  
circuits on the RSGATE, MGATE, SGATE1 and SGATE2  
pins, which opens the remote sense switches and discon-  
nects the master and slave supplies before the fault latch  
is reset. If no external signal pulls down the FAULT pin,  
the internal 8.5µA pull-up current or an external pull-up  
resistor increases the ON (and FAULT) pin voltage above  
0.6V, which arms the fault latch. A ramp-up begins when  
ON is above 1.23V.  
The input aspect of the STATUS/PGI pin allows external  
downstreammonitoringcircuitstocontroltheLTC2926as  
showninFigure9. Thepowergoodtimeoutcircuitdiscon-  
nects the supply generators if for any reason the voltage  
level of the STATUS/PGI pin is not high after the timeout  
period. During a ramp-up, the timeout circuit will trip if the  
internal pull-down on STATUS/PGI fails to release, which  
indicates that supply ramping was not completed in the  
Q1  
1.8V  
1.8V  
SOURCE  
SLAVE1  
10Ω  
Q2  
2.5V  
2.5V  
SOURCE  
SLAVE2  
LTC2904  
V2  
V1  
S2  
10Ω  
In applications where the LTC2926 is configured for fault  
retry, some details of the retry behavior are determined by  
the source and duration of the fault signal. When a fault  
is triggered by an external pull-down signal on the FAULT  
(and ON) pin, supply ramping will not restart until the low  
input ceases. When a power good fault is triggered by an  
external pull-down signal on the STATUS/PGI pin, supply  
ramping restarts immediately. If the low signal persists  
RST  
RST  
GND  
R
R
SGATE1 SGATE2  
FB1  
FB1  
S1  
ON/OFF  
ON  
TOL  
FA1  
LOAD VOLTAGE  
MONITOR  
(10% TOLERANCE)  
LTC2926  
STATUS/PGI  
R
R
FB2  
FB2  
GND PGTMR  
2926 F09  
FA2  
C
PGTMR  
Figure 9. External Load Monitor Controlling LTC2926 via Power  
Good Input  
2926fa  
14  
LTC2926  
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APPLICATIO S I FOR ATIO  
through the power good timeout period, a fault and retry  
will subsequently occur.  
Automatic Remote Sense Switching  
The LTC2926 provides integrated remote sense switches  
thatsolvetheproblemofvoltagedropsintheexternalseries  
MOSFETs that control supply ramping. A switch creates  
a feedback path from a slave supply output to the slave  
supply generator sense input that allows the generator  
to compensate for the I • R drop across the controlling  
MOSFET (see, for example, Figure 6). After the supply  
ramping is complete, but before the internal pull-down  
releases the STATUS/PGI pin, the two integrated remote  
sense switches are closed.  
To ensure a consistent power good timeout period, the  
LTC2926requiresthePGTMRpinvoltagetofallbelow0.1V  
forthefaultlatchresettocomplete.TheONpinneedstobe  
held low for only 10µs to initiate fault reset; it is allowed to  
go high while the timing capacitor on PGTMR discharges  
to 0.1V (see Functional Block Diagram).  
When a resistive voltage divider drives the ON and FAULT  
pins together, include the contribution of I  
choosing the resistor values (Figure 10a). When a logic  
output drives both pins, up to 30kΩ of series resistance  
may be added to limit the output current while the fault  
pull-down is active (Figure 10b).  
when  
FAULT(UP)  
For applications that require more than two remote sense  
switches,connecttheRSGATEpintothegatesofadditional  
external N-channel MOSFETs. An internal charge pump  
guarantees that RSGATE will reach V + 5.5V, which al-  
lowsfullenhancementoflogic-levelMOSFETswithsource  
CC  
V
IN  
or drain voltages up to V .  
LTC2926  
CC  
V
CC  
R
ONB  
V
ON  
ON  
The switches are open when supply ramping has not  
completed to avoid creating a power path between the  
supply generator and the load. When the remote sense  
switchesareopen,thesupplygenerator’ssenseinputmust  
be connected locally to its output through a resistor that  
is much larger than the remote sense switch resistance  
of 10Ω (max); a 100Ω resistor is adequate for most ap-  
plications as in Figure 7.  
V
CC  
R
ONA  
I
FAULT(UP)  
FAULT  
FAULT LATCH  
R
ONA  
|| R  
Q
S
R
ONA  
V
=
• V  
IN  
ON  
R
+ R  
ONB  
GND  
+ (R  
ONA  
) • I  
ONB  
FAULT(UP)  
Some supply modules have built-in resistors of 10Ω or  
less between their out and sense pins, which may require  
a lower switch resistance. Choose an external N-channel  
(a)  
V
V
IN  
MOSFET with an R  
that is at most 1/10 the module  
DS(on)  
LTC2926  
out-to-sense resistance, but that is still much larger than  
the R of the power path MOSFET.  
CC  
R
SERIES  
ON  
DS(on)  
V
CC  
I
OUT  
If neither external remote sense switches nor a sta-  
tus activation delay is required, leave the RSGATE pin  
unconnected.  
I
FAULT(UP)  
FAULT  
FAULT LATCH  
Q
S
R
LIMIT I  
OUT  
SERIES  
WITH R  
SERIES  
R
≤ 30kΩ  
GND  
2926 F10  
(b)  
Figure 10. Fault Retry Configurations, (a) Resistive Voltage  
Divider and (b) Logic Driven  
2926fa  
15  
LTC2926  
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APPLICATIO S I FOR ATIO  
SUPPLY  
MODULE  
To minimize switch current, choose R >> R . In appli-  
+ V  
–
X
DS  
DS  
Q0  
MASTER  
SUPPLY  
cations that use the LTC2926’s integrated remote sense  
OUT  
switches, I must not exceed the Absolute Maximum  
SW  
LOAD  
R
Ratings for switch pin currents.  
X
MGATE  
I
Q3  
SW  
SENSE  
It is recommended design practice to satisfy both  
resistance value conditions.  
RSGATE  
SGATE Voltage at Ramp Start/End  
(a)  
When the master ramp is 0V (before ramp up or after  
ramp down), the control MOSFET ideally conducts no  
current. If the tracking profile has no delay or offset, the  
gate control loops may force the SGATE pins either to  
ground or to just below the MOSFET threshold voltage,  
depending on reference offsets, resistor mismatches and  
the load resistance. In both cases the slave load will be at  
about 0V, but if a known state of SGATE is desired, include  
an offset in the tracking profile.  
+ V  
R
–
DS  
V
V
SUPPLY  
OUT  
DS  
I
L
R
X
R
I
SW  
SW  
V
SENSE  
(b)  
2926 F11  
Figure 11. Supply and Sense Path Detail, (a) Functional Diagram  
and (b) Equivalent Circuit When Remote Sense Switch Is Closed  
To guarantee grounding of the SGATE pins at RAMP = 0V,  
Considerations when Using Remote Sense Switches  
includeapositiveoffset,V ,basedonthemaximumslave  
OS  
Consider the supply and sense path detail functional  
diagram and equivalent circuit in Figure 11. For proper  
compensation of the I • R drop across the external control  
MOSFET Q0 by the supply module, the voltage at its sense  
pin input must be equal to the supply voltage at the load.  
supply voltage, V  
(max), and the tracking/feedback  
SLAVE  
resistor tolerance. Note that at the start of ramp up, the  
gate capacitance of the MOSFET must be charged to the  
threshold voltage before the source begins ramping. The  
SGATE pins do provide extra current to speed the initial  
charging.  
Solving for V  
in the equivalent circuit yields:  
SENSE  
Calculate the required V from:  
OS  
⎛
⎞
⎛
⎞
RSW  
RX  
R +R  
VSENSE  
=
• VSUPPLY  
+
• VOUT  
V
OS  
≥ k • V  
(max)  
SLAVE  
⎜
⎟
⎜
⎟
R +R  
⎝
⎠
⎝
⎠
X
SW  
X
SW  
For 1% resistors k = 1/8, for 5% resistors k = 1/4, for  
10% resistors k = 2/5.  
For the best compensation, i.e., V  
≈ V  
, choose  
SUPPLY  
SENSE  
R >> R  
.
X
SW  
To guarantee the SGATE pins sit at the MOSFET threshold  
voltages at RAMP = 0V, include a negative offset. Note that  
when the master ramp goes to 0V, the slave supplies will  
remain above ground by the magnitude of the offset.  
The remote sense switch is intended to be a low-current  
voltage feedback path. The control MOSFET (Q0 in Figure  
11a) should carry all but a tiny fraction of the entire load  
current. The remote sense switch current is:  
Calculate the required V from:  
OS  
⎛
⎞
RDS  
V
OS  
≤ –k • V  
(max)  
SLAVE  
ISW =ILOAD  
•
⎜
⎟
R +RSW +RDS  
⎝
⎠
X
2926fa  
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LTC2926  
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APPLICATIO S I FOR ATIO  
Q0  
If the master ramp signal is not a master supply, tie the  
RAMP pin to the MGATE pin.  
V
IN  
MASTER  
SLAVE1  
SUPPLY MODULE  
Q1  
V
IN  
IN OUT  
SENSE  
R
X1  
10Ω  
2. Choose the feedback resistors based on the slave  
supply voltage and slave load.  
10Ω  
SUPPLY MODULE  
It is important that the feedback resistors are significantly  
larger than the load resistance, especially as the slave  
voltage nears ground (see Load Requirements).  
Q2  
SLAVE2  
V
IN OUT  
IN  
0.1µF  
C
MGATE  
R
X2  
SENSE  
10Ω  
V
MGATE RAMP SGATE1 SGATE2  
First determine the effective slave load resistance, R (not  
CC  
L
D1  
D2  
shown), at low slave voltage levels, and select the value  
S1  
S2  
of the top feedback resistor, R , to satisfy:  
FB  
RAMPBUF  
R
TB1  
R
R
FB1  
R
FB  
R
FB  
≥ 100 • R (recommended),  
L
TRACK1  
FB1  
R
TA1  
LTC2926  
FA1  
≥ 23 • R (required)  
(2)  
L
R
R
TB2  
R
R
FB2  
TRACK2  
FAULT  
FB2  
Second, determine a value for the lower feedback resistor,  
V
IN  
TA2  
FA2  
V
R , that will ensure that the LTC2926 fully enhances the  
IN  
FA  
10k  
gate of the slave control MOSFET at the end of ramping.  
FAULT  
10k  
STATUS/PGI  
STATUS  
ON/OFF  
ON  
GND  
PGTMR  
Select R based on R , the resistor tolerance, TOL , and  
FA  
FB  
R
2926 F12  
the maximum slave supply voltage, V  
(max):  
SLAVE  
C
PGTMR  
⎛
⎝
⎞
⎠
V
SLAVE(max)  
0.784V  
1− TOLR  
⎛
⎞
⎠
Figure 12. Three-Supply Application  
RFA <RFB •  
−1  
(3)  
⎜
⎝
⎟
⎜
⎟
1+ TOL  
R
Three-Step Design Procedure  
The following three-step design procedure allows one  
to choose the FBn resistors, R and R , the TRACKn  
Note: Choose the value of V  
(max) to cover all slave  
SLAVE  
supplyvoltagetolerancesbyagoodmargin.Exceedingthe  
FAn  
FBn  
V
(max) voltage used for this calculation can result in  
SLAVE  
resistors, R and R , and the master ramp capacitor,  
TAn  
TBn  
triggering a Power Good Fault unintentionally.  
C
,thatgiveanyofthetrackingorsequencingprofiles  
MGATE  
shown in Figures 1 to 4. A three-supply application circuit  
If the slave generator has an accessible resistive divider  
and a ground-based voltage reference, it may be able to  
be controlled without a series MOSFET. In that case, let  
is shown in Figure 12.  
1. Set the ramp rate of the master signal.  
the generator’s design set R and R , substitute the  
FA  
FB  
FB(REF)  
Solve for the value of C  
, the capacitor on the MGATE  
generator’s reference voltage for V  
in step 3, and  
MGATE  
pin, based on the desired ramp rate (volts per second)  
of the master ramp signal, S , and the MGATE pull-up  
see the subsection Slave Control Without MOSFETs.  
M
3. Solve for the tracking resistors that set the desired  
ramp rate and voltage offset or time delay of the slave  
supply.  
current I  
, which is nominally 10µA.  
MGATE  
IMGATE  
SM  
(1)  
CMGATE  
=
Choose a ramp rate for the slave supply, S . If the slave  
S
supply tracks coincidently with the master supply or with  
only a fixed offset or delay, then the slave ramp rate equals  
the master ramp rate. Be sure that the slave ramp rate and  
itsoffsetordelayallowstheslavevoltagetofinishramping  
If the master ramp signal is a master supply, consider  
the gate capacitance of the required external N-channel  
MOSFET. If the gate capacitance is comparable to C  
,
MGATE  
reduce the external capacitor’s value to compensate for  
the gate capacitance of the MOSFET.  
2926fa  
17  
LTC2926  
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APPLICATIO S I FOR ATIO  
MASTER  
SLAVE2  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F13  
5ms/DIV  
5ms/DIV  
Figure 13. Coincident Tracking Waveforms from Figure 14 Circuit  
before the master ramp reaches its final value; otherwise,  
the slave supply voltage will be held below its intended  
Coincident Tracking Example  
A typical three-supply application is shown in Figure 14.  
The master signal is 3.3V, the slave 1 supply is a 1.8V  
module, and the slave 2 supply is a 2.5V module. Allow for  
10% tolerance of the slave supply voltages. Both slave  
supplies track coincidently with the 3.3V master supply  
that is controlled by an external MOSFET. The ramp rate of  
the supplies is 100V/s. The slave supplies’ minimum load  
resistancesare150Ω.Theexternalconfigurationresistors  
level. Calculate the upper track resistor, R , from:  
TB  
⎛
⎞
SM  
RTB =RFB •  
(4)  
⎜
⎟
S
⎝
⎠
S
Choose a voltage difference between the master and slave  
ramps, ΔV, if offset tracking is desired. If a time delay is  
desired for supply sequencing, calculate an effective volt-  
age difference based on the master ramp rate. If neither  
voltage offset nor time delay is required, set ΔV = 0V.  
Q0  
IRF7413Z  
3.3V  
3.3V V  
IN  
MASTER  
Q1  
1.8V MODULE  
IN OUT  
IRF7413Z  
1.8V  
SLAVE1  
ΔV = a voltage difference (offset tracking), or  
ΔV = S • t (supply sequencing), or  
(5a)  
(5b)  
(5c)  
3.3V  
R
X1  
100Ω  
10Ω  
SENSE  
M
DLY  
10Ω  
ΔV = 0V (coincident/ratiometric tracking)  
Q2  
2.5V MODULE  
IN OUT  
IRF7413Z  
2.5V  
SLAVE2  
Use the following formula to determine the lower track  
resistors, R , using the TRACK pin voltage, V , and  
3.3V  
C
MGATE  
0.1µF  
R
X2  
0.1µF  
100Ω  
TA  
TRACK  
, both from  
SENSE  
10Ω  
the FB pin internal reference voltage, V  
the Electrical Characteristics:  
FB(REF)  
V
CC  
MGATE RAMP SGATE1 SGATE2  
D1  
D2  
S1  
S2  
VTRACK  
RTA  
=
(6)  
RAMPBUF  
VFB(REF) VFB(REF)  
R
R
FB1  
VTRACK  
RTB  
TB1  
∆V  
RTB  
15.0k  
15.0k  
+
−
+
TRACK1  
FB1  
RFB  
RFA  
R
R
FA1  
TA1  
LTC2926  
9.53k  
9.53k  
R
TB2  
R
FB2  
15.0k  
15.0k  
Note that large ratios of slave ramp rate to master ramp  
rate, S /S , may result in negative values for R . In such  
TRACK2  
FAULT  
FB2  
R
V
TA2  
IN  
V
IN  
R
FA2  
5.76k  
5.76k  
S
M
TA  
10k  
casesincreasetheoffsetordelay,orreducetheslaveramp  
10k  
FAULT  
ON/OFF  
STATUS/PGI  
STATUS  
rate to realize positive values of R .  
TA  
ON  
RSGATE  
NC  
GND  
PGTMR  
2926 F14  
C
PGTMR  
1µF  
Figure 14. Coincident Tracking Example  
2926fa  
18  
LTC2926  
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APPLICATIO S I FOR ATIO  
Since no offset or delay is required, Equation 5c applies:  
have 1% tolerance. The 3-step design procedure detailed  
above can be used to determine component values. Only  
the slave 1 supply is considered here, as the procedure  
is the same for the slave 2 supply.  
ΔV = 0V  
From Equation 6:  
1. Set the ramp rate of the master signal.  
0.8V  
RTA  
=
= 9.53kΩ  
0.8V  
0.8V  
0.8V  
0V  
From Equation 1:  
+
−
+
15.0kΩ 9.53kΩ 15.0kΩ 15.0kΩ  
10µA  
100V s  
CMGATE  
=
= 0.1µF  
In this example, all supplies remain low while the ON pin  
is held below 1.23V. When the ON pin rises above 1.23V,  
10µApullsupC  
andthegateofMOSFETQ0at100V/s.  
MGATE  
2.Choosethefeedbackresistorsbasedontheslavesupply  
voltage and slave load.  
The source of Q0 follows the gate and pulls up the output  
to 3.3V at the rate of 100V/s. This output serves as the  
master ramp and is buffered from the RAMP pin to the  
RAMPBUF pin. As the master output and the RAMPBUF  
pin rise, the current from the TRACK pins is reduced. Con-  
sequently, the voltage at the FB pins begins to fall below  
0.8V, which causes the SGATE pins to rise. The sources  
of the slave supply MOSFETs, Q1 and Q2, follow the rising  
SGATE signals, and the slave supplies track the master  
supply. When all the supplies have finished ramping, the  
RSGATE pin voltage rises to close the integrated remote  
sense switches, which allows the slave supply modules  
to compensate for voltage drops in the series MOSFETs. If  
the supplies have ramped within the power good timeout  
period (about 123ms in this example), the STATUS/PGI  
pin will rise, indicating completed ramping. When the  
ON pin is again pulled below 1.23V, the STATUS/PGI pin  
falls and the RSGATE pin falls, which opens the remote  
R = 150Ω  
L
From Equation 2:  
R
≥ 100 • 150Ω = 15kΩ  
FB  
Choose R = 15.0kΩ.  
FB  
From Equation 3:  
0.99  
1.01  
1.98V  
0.784V  
⎛
⎞ ⎛  
⎞
⎠
R <15.0kΩ•  
−1 = 9.64kΩ  
⎜
⎝
⎟ ⎜  
⎠ ⎝  
⎟
FA  
Choose R = 9.53kΩ.  
FA  
3. Solveforthetrackingresistorsthatsetthedesiredramp  
rate and voltage offset or time delay of the slave supply.  
From Equation 4:  
⎛
⎞
100V s  
100V s  
sense switches. Next, 10µA will pull down C  
and the  
MGATE  
RTB =15.0kΩ•  
=15.0kΩ  
⎜
⎟
⎝
⎠
gate of MOSFET Q0 at 100V/s. If the loads on the outputs  
are sufficient, all outputs will track down coincidently at  
100V/s.  
2926fa  
19  
LTC2926  
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APPLICATIO S I FOR ATIO  
SLAVE2  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F15  
5ms/DIV  
5ms/DIV  
Figure 15. Ratiometric Tracking Waveforms from Figure 16 Circuit  
Ratiometric Tracking Example  
the ramp rate of the 1.8V slave supply is 60V/s, and the  
ramp rate of the 2.5V supply is 83.3V/s. Always verify that  
the chosen ramp rate will allow the supplies to ramp-up  
This example converts the coincident tracking example to  
the ratiometric tracking profile shown in Figure 15, using  
two slave supplies and a master ramp signal (not a master  
ramp supply). The ramp rate of the master signal remains  
unchanged (Step 1), the minimum load resistance of the  
slave loads remains unchanged (Step 2), and there is no  
delay in ratiometric tracking. Only Step 3 of the three-step  
designprocedureneedstobeconsidered. Inthisexample,  
completelybeforeRAMPBUFreachesV .Ifthe1.8Vslave  
CC  
supply were to ramp up at 50V/s it would only reach 1.65V  
because the RAMPBUF signal would reach its final value  
of V = 3.3V before the slave supply reached 1.8V.  
CC  
3. Solveforthetrackingresistorsthatsetthedesiredramp  
rate and voltage offset or time delay of the slave supply.  
From Equation 4:  
Q1  
1.8V MODULE  
IN OUT  
IRF7413Z  
1.8V  
SLAVE1  
3.3V  
R
X1  
100Ω  
⎛
⎞
100V s  
60V s  
RTB =15.0kΩ•  
= 25kΩ  
SENSE  
⎜
⎟
10Ω  
⎝
⎠
Q2  
2.5V MODULE  
IN OUT  
Choose R = 24.9kΩ.  
IRF7413Z  
TB  
2.5V  
SLAVE2  
3.3V  
C
MGATE  
0.1µF  
R
X2  
100Ω  
0.1µF  
Since no offset or delay is required, Equation 5c applies:  
3.3V  
IN  
SENSE  
V
10Ω  
ΔV = 0V  
V
MGATE RAMP SGATE1 SGATE2  
CC  
D1  
D2  
From Equation 6:  
S1  
S2  
RAMPBUF  
0.8V  
R
R
FB1  
TB1  
RTA  
=
= 7.61kΩ  
24.9k  
15.0k  
0.8V  
0.8V  
0.8V  
0V  
TRACK1  
FB1  
+
−
+
R
R
FA1  
TA1  
LTC2926  
15.0kΩ 9.53kΩ 24.9kΩ 24.9kΩ  
9.53k  
7.68k  
R
TB2  
R
FB2  
18.2k  
15.0k  
TRACK2  
FAULT  
FB2  
Choose R = 7.68kΩ.  
R
V
TA2  
TA  
IN  
V
IN  
R
FA2  
5.76k  
5.36k  
10k  
10k  
FAULT  
ON/OFF  
STATUS/PGI  
STATUS  
ON  
RSGATE  
2926 F16  
NC  
GND  
PGTMR  
C
PGTMR  
1µF  
Figure 16. Ratiometric Tracking Example  
2926fa  
20  
LTC2926  
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APPLICATIO S I FOR ATIO  
MASTER  
SLAVE2  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F17  
5ms/DIV  
5ms/DIV  
Figure 17. Offset Tracking Waveforms from Figure 18 Circuit  
Offset Tracking Example  
design procedure. Only step 3 must be considered. Be  
sure to verify that the chosen voltage offsets will allow  
the slave supplies to ramp up completely. In this example,  
if the voltage offset on the 1.8V supply were 2V, it could  
ramp up only to 3.3V – 2V = 1.3V.  
Convertingthecircuitinthecoincidenttrackingexampleto  
the offset tracking profile shown in Figure 17 is relatively  
simple. Here the 1.8V slave supply ramps up 1V below the  
master, and the 2.5V slave supply ramps up 0.5V below  
the master. The ramp rate remains the same (100V/s), as  
do the slave supplies’ minimum load resistances, so there  
are no changes necessary to steps 1 or 2 of the three-step  
3. Solveforthetrackingresistorsthatsetthedesiredramp  
rate and voltage offset or time delay of the slave supply.  
From Equation 4:  
Q0  
IRF7413Z  
⎛
⎞
100V s  
100V s  
3.3V  
3.3V V  
IN  
MASTER  
RTB =15.0kΩ•  
=15kΩ  
Q1  
IRF7413Z  
1.8V MODULE  
IN OUT  
⎜
⎟
⎝
⎠
1.8V  
SLAVE1  
3.3V  
3.3V  
R
X1  
100Ω  
10Ω  
SENSE  
Choose R = 15.0kΩ.  
10Ω  
TB  
Since offset is required, Equation 5a applies:  
ΔV = 1.0V  
Q2  
2.5V MODULE  
IN OUT  
IRF7413Z  
2.5V  
SLAVE2  
C
MGATE  
0.1µF  
R
X2  
100Ω  
0.1µF  
SENSE  
From Equation 6:  
10Ω  
V
MGATE RAMP SGATE1 SGATE2  
CC  
0.8V  
D1  
D2  
RTA  
=
= 5.31kΩ  
0.8V  
0.8V  
0.8V  
1.0V  
S1  
S2  
+
−
+
RAMPBUF  
15.0kΩ 9.53kΩ 15.0kΩ 15.0kΩ  
Choose R = 5.36kΩ.  
R
R
FB1  
TB1  
15.0k  
15.0k  
TRACK1  
FB1  
R
R
TA  
FA1  
TA1  
LTC2926  
9.53k  
5.36k  
R
TB2  
R
FB2  
15.0k  
15.0k  
TRACK2  
FAULT  
FB2  
R
V
IN  
TA2  
V
IN  
R
FA2  
5.76k  
4.64k  
10k  
10k  
FAULT  
ON/OFF  
STATUS/PGI  
STATUS  
ON  
RSGATE  
2926 F18  
NC  
GND  
PGTMR  
C
PGTMR  
1µF  
Figure 18. Offset Tracking Example  
2926fa  
21  
LTC2926  
U
W U U  
APPLICATIO S I FOR ATIO  
SLAVE2  
SLAVE1  
500mV/DIV  
500mV/DIV  
2926 F19  
5ms/DIV  
5ms/DIV  
Figure 19. Supply Sequencing Waveforms from Figure 20 Circuit  
Supply Sequencing Example  
starts to ramp up. Note that not every combination of  
ramp rates and delays is possible. Small delays and large  
ratios of slave ramp rate to master ramp rate may result  
in solutions that require negative resistors. In such cases,  
either the delay must be increased or the ratio of slave  
ramp rate to master ramp rate must be reduced.  
In Figure 19, the two slave supplies are sequenced using a  
masterrampsignal.Asintheratiometrictrackingexample,  
the master signal ramps up at 100V/s, and the minimum  
slave loads are the same as the coincident example, so  
steps 1 and 2 remain the same. The 1.8V slave 1 supply  
ramps up at 1000V/s beginning 10ms after the master  
signal starts to ramp up. The 2.5V slave 2 supply ramps  
up at 1000V/s beginning 20ms after the master signal  
3. Solveforthetrackingresistorsthatsetthedesiredramp  
rate and voltage offset or time delay of the slave supply.  
From Equation 4:  
Q1  
IRF7413Z  
1.8V MODULE  
IN OUT  
⎛
⎞
1.8V  
SLAVE1  
100V s  
1000V s  
3.3V  
RTB =15.0kΩ•  
=1.5kΩ  
R
X1  
100Ω  
⎜
⎟
⎝
⎠
SENSE  
10Ω  
Choose R = 1.50kΩ.  
TB  
Q2  
2.5V MODULE  
IN OUT  
IRF7413Z  
2.5V  
SLAVE2  
3.3V  
Since a delay is required, Equation 5b applies:  
ΔV = 100V/s • 10ms = 1V  
C
MGATE  
0.1µF  
R
X2  
100Ω  
0.1µF  
3.3V  
IN  
SENSE  
V
10Ω  
From Equation 6:  
V
MGATE RAMP SGATE1 SGATE2  
CC  
D1  
D2  
0.8V  
S1  
S2  
RTA  
=
= 2.96kΩ  
RAMPBUF  
0.8V  
0.8V  
0.8V  
1V  
R
R
FB1  
TB1  
+
−
+
1.50k  
15.0k  
15.0kΩ 9.53kΩ 1.50kΩ 1.50kΩ  
TRACK1  
FB1  
R
R
FA1  
TA1  
LTC2926  
9.53k  
2.94k  
R
TB2  
R
FB2  
2.49k  
Choose R = 2.94kΩ.  
TA  
24.9k  
TRACK2  
FAULT  
FB2  
R
V
TA2  
IN  
V
IN  
R
FA2  
9.53k  
Note that the values of R and R are larger than those  
1.33k  
FA2  
FB2  
10k  
10k  
oftheCoincidentTrackingExample.Largerfeedbackresis-  
FAULT  
ON/OFF  
STATUS/PGI  
STATUS  
tor values resulted in larger tracking resistor values for  
ON  
RSGATE  
2926 F20  
NC  
GND  
PGTMR  
R
and R , which limits the maximum TRACK2 pin  
TB2  
TA2  
C
PGTMR  
1µF  
current to <1mA; see Final Sanity Checks.  
Figure 20. Supply Sequencing Example  
2926fa  
22  
LTC2926  
U
W U U  
APPLICATIO S I FOR ATIO  
Slave Control Without MOSFETs  
Use the feedback resistor values required by the supply  
generator in step 3. Next, split resistor R as in Figure  
FA  
The LTC2926 can control tracking and sequencing of a  
slave supply without a MOSFET if the supply generator’s  
output voltage is set by an accessible resistive voltage  
divider and if its voltage reference is ground-based. Track-  
ing currents mirrored to the FB pins are injected into the  
feedback nodes of the supply generators to control the  
output voltage. When master ramp signal has reached  
it maximum voltage, the FB pin current is zero, and the  
LTC2926 has no effect on the output voltage accuracy,  
transient response or stability of the generator.  
21b, so that  
0.75V  
VFB(GEN)  
RFAA ≤RFA •  
and  
R
= R – R  
FAB  
FA  
FAA  
and tie the LTC2926’s FB pin to the node in between. The  
new tap point allows the LTC2926’s FB pin to see <0.75V  
at the end of ramp-up. Finally, scale the track resistors to  
match R  
:
FAA  
To control a supply generator (e.g., DC/DC converter) with  
a feedback reference voltage V  
of 0.75V or less,  
FB(GEN)  
RFAA  
R′ =  
•RTA and  
•RTB  
connect the FB pin of the LTC2926 to the tap point of the  
generator’s resistive divider, as shown in Figure 21a. Fol-  
low steps 1 and 3 of the Three-Step Design Procedure to  
set the ramp rates and tracking profile. Use the feedback  
TA  
RFAA +RFAB  
RFAA  
R′ =  
TB  
RFAA +RFAB  
resistor values required by the supply generator for R  
FA  
and R in step 3.  
FB  
Voltage regulators that force their reference voltage be-  
tween their output and feedback nodes do not employ a  
ground-based reference, and thus will not be controllable  
by the LTC2926 without a series MOSFET.  
AgeneratorwithV  
>0.75Vmaybecontrolledwithout  
FB(GEN)  
a MOSFET if the slave voltage is large enough (see Figure  
22). First follow steps 1 and 3 of the Three-Step Design  
Procedure to set the ramp rates and tracking profile.  
SUPPLY GENERATOR  
OUT  
SUPPLY GENERATOR  
IN OUT  
Slave Supply Control Without  
V
SLAVE  
V
SLAVE  
a MOSFET  
IN  
IN  
IN  
6
5
4
3
2
1
0
CONTROL VIA  
FB PIN AND  
SPLIT R  
R
R
R
FB  
FB  
FA  
RESISTOR  
V
V
FB(GEN)  
FB(GEN)  
GND  
FB  
GND  
FB  
R
R
FA  
FAB  
FAA  
CONTROL  
VIA FB PIN  
LTC2926  
RAMPBUF  
LTC2926  
RAMPBUF  
SGATE  
NC  
SGATE  
NC  
′
R
R
R
TB  
TB  
MOSFET  
CONTROL ONLY  
FB  
FB  
TRACK  
TRACK  
GND  
GND  
′
R
2926 F21  
TA  
TA  
0
0.50 0.75 1.00  
(V)  
1.25 1.50  
0.25  
V
FB(GEN)  
(a)  
(b)  
2926 F22  
Figure 21. Slave Supply Control Without a MOSFET  
(a) Generator Reference V ≤ 0.75V and (b) Generator Reference V  
Figure 22. Regions of Possible  
Slave Control Without a MOSFET  
> 0.75V  
FB(GEN)  
FB(GEN)  
2926fa  
23  
LTC2926  
U
W U U  
APPLICATIO S I FOR ATIO  
Final Sanity Checks  
Load Requirements  
The collection of equations below is useful for identifying  
unrealizable solutions.  
A weak resistive load can cause static and dynamic track-  
ing errors. The behavior of the source-follower topology  
of MOSFET-controlled tracking relies on the load’s abil-  
ity to support the ramp rates and tracking currents of a  
particular application. Consider the simplified slave load  
schematic in Figure 23.  
As stated in step 3 of the design procedure, the slave  
supply must finish ramping before the master signal has  
reached its final voltage. This can be verified with the  
following equation:  
SUPPLY  
MODULE  
⎛
⎜
⎝
⎞
RTB  
RTA  
SLAVEn  
Qn  
VMASTER > VTRACK • 1+  
⎟
OUT  
⎠
LOAD  
R
R
R
L
C
FB  
FA  
L
Here, V  
= 0.8V. V  
is the final voltage of the  
MASTER  
SGATEn  
TRACK  
FBn  
mastersignal,eitherthesupplyvoltagerampedupthrough  
LTC2926  
the optional external MOSFET or V when no MOSFET  
is present.  
CC  
2926 F23  
It is possible to choose resistor values that require the  
LTC2926 to supply more current than the Electrical Char-  
acteristicstableguarantees. Toavoidthiscondition, check  
Figure 23. Simplified Slave Supply Load  
Whenthesuppliesarerampeddownquickly,theloadmust  
be capable of sinking enough current to support the ramp  
rate. Forexample, ifthereisalargeoutputcapacitanceand  
a weak resistive load on a particular supply, that supply’s  
falling rate will be limited by the RC time constant of the  
load. In Figure 24, the falling 2.5V slave cannot keep up  
with the falling master ramp.  
that each TRACK pin’s current, I  
, does not exceed  
TRACKn  
1mA, and that the RAMPBUF pin current, I  
not exceed 3mA.  
, does  
RAMPBUF  
To confirm that I  
≤ 1mA, verify that:  
TRACKn  
VTRACK  
RTA ||RTB  
≤1mA  
When the supplies are near ground, the load must be  
capable of sinking the tracking current without creating  
a large offset voltage. For weak resistive loads and slave  
voltage levels near ground, the tracking current (at its  
maximum there) can be in excess of the load’s current  
demand. Having no capability for sinking current, the  
MOSFETshutsoff. Allofthemirroredtrackingcurrentthat  
Check that the RAMPBUF pin will not be forced to sink  
more than 3mA when it is at 0V and will not be forced to  
source more than 3mA when it is at V  
.
MASTER  
VTRACK  
RTA1||RTB1 RTA2 ||RTB2  
VTRACK  
+
≤3mA and  
flows through R also flows through the load resistance,  
FB  
R , which creates a voltage offset between the slave and  
L
VMASTER VMASTER  
RTA1+RTB1 RTA2 +RTB2  
ground. In Figure 24, the 1.8V supply shows an offset  
+
≤3mA  
from ground.  
2926fa  
24  
LTC2926  
U
W U U  
APPLICATIO S I FOR ATIO  
Layout Considerations  
MASTER  
Be sure to place a 0.1µF bypass capacitor as near as pos-  
sible to the supply pin of the LTC2926.  
SLAVE2  
LARGE τ = R C  
L
L
L
SLAVE1  
500mV/DIV  
R
≈ R  
L
FB  
To minimize the noise on the slave supplies’ outputs, keep  
the traces connecting the FB pins of the LTC2926 and the  
feedback nodes of the slave supplies’ resistive voltage  
dividers as short as possible. In addition, do not route  
those traces next to signals with fast transitions times.  
2926 F24  
5ms/DIV  
Figure 24. Tracking Effects of Weak Resistive Load  
To get the best compensation of the series I • R drops  
of the external MOSFETs, make sure the supply output  
nodes and the supply generator sense connections use  
Kelvin-sensing. The feedback resistive voltage divider  
should Kelvin-sense the slave supply output node for  
accuracy, as well.  
Under worst-case conditions, FB pin voltages may reach  
the maximum clamp voltage of 2.4V. To limit the slave  
voltage offset to below 100mV, choose R ≥ 23 • R .  
FB  
L
Add a resistor in parallel with the load to strengthen weak  
resistive loads as required.  
SUPPLY  
Start-Up Delays  
MODULE  
Q1  
OUT  
Often power supplies do not start up immediately when  
theirinputsuppliesareapplied.IftheLTC2926triestoramp  
up these power supplies as soon as the input supply is  
present, the start-up of the outputs may be delayed, which  
defeats the tracking circuit. Make sure the ON pin does not  
initiate ramp-up until all supply sources are available.  
100Ω  
10Ω  
KELVIN-SENSE  
CONNECTIONS  
SENSE  
GND  
SGATE1  
D1  
S1  
KELVIN-SENSE  
CONNECTIONS  
MINIMIZE  
TRACE  
LTC2926  
GND  
R
MINIMIZE  
TRACE LENGTH  
SLAVE  
LOAD  
FB  
LENGTH  
FB1  
V
CC  
RAMP Pin Clamp  
R
FA  
0.1µF  
The RAMP pin is weakly clamped to the V pin. When  
CC  
MGATE and RAMP are tied together their pin voltages will  
2926 F25  
KELVIN-SENSE  
CONNECTIONS  
not exceed V + 1V. If the RAMP pin is driven by a low  
CC  
impedance source that can exceed V , include a series  
CC  
Figure 25. Layout Considerations  
resistortolimitthecurrentto<20µA.Use50kΩpersource  
volt above V .  
CC  
2926fa  
25  
LTC2926  
U
PACKAGE DESCRIPTIO  
GN Package  
20-Lead Plastic SSOP (Narrow .150 Inch)  
(Reference LTC DWG # 05-08-1641)  
.337 – .344*  
(8.560 – 8.738)  
.058  
(1.473)  
REF  
.045 .005  
20 19 18 17 16 15 14 13 12 11  
.254 MIN  
.150 – .165  
.229 – .244  
.150 – .157**  
(5.817 – 6.198)  
(3.810 – 3.988)  
.0165 .0015  
.0250 BSC  
1
2
3
4
5
6
7
8
9 10  
RECOMMENDED SOLDER PAD LAYOUT  
.015 .004  
(0.38 0.10)  
.0532 – .0688  
(1.35 – 1.75)  
× 45°  
.004 – .0098  
(0.102 – 0.249)  
.0075 – .0098  
(0.19 – 0.25)  
0° – 8° TYP  
.016 – .050  
(0.406 – 1.270)  
.008 – .012  
.0250  
(0.635)  
BSC  
(0.203 – 0.305)  
TYP  
NOTE:  
1. CONTROLLING DIMENSION: INCHES  
INCHES  
(MILLIMETERS)  
2. DIMENSIONS ARE IN  
GN20 (SSOP) 0204  
3. DRAWING NOT TO SCALE  
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE  
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD  
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE  
2926fa  
26  
LTC2926  
U
PACKAGE DESCRIPTIO  
UFD Package  
20-Lead Plastic QFN (4mm × 5mm)  
(Reference LTC DWG # 05-08-1711)  
0.70 0.05  
4.50 0.05  
3.10 0.05  
2.65 0.05  
(2 SIDES)  
PACKAGE OUTLINE  
0.25 0.05  
0.50 BSC  
3.65 0.05  
(2 SIDES)  
4.10 0.05  
5.50 0.05  
2.65 0.10  
(2 SIDES)  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
PIN 1 NOTCH  
R = 0.30 TYP  
R = 0.115  
TYP  
19 20  
0.75 0.05  
4.00 0.10  
(2 SIDES)  
0.40 0.05  
PIN 1  
TOP MARK  
(NOTE 6)  
1
2
5.00 0.10  
(2 SIDES)  
3.65 0.10  
(2 SIDES)  
(UFD20) QFN 0304  
0.25 0.05  
0.50 BSC  
0.200 REF  
0.00 – 0.05  
BOTTOM VIEW—EXPOSED PAD  
NOTE:  
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
2926fa  
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,  
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that  
the interconnection of its circuits as described herein will not infringe on existing patent rights.  
27  
LTC2926  
U
TYPICAL APPLICATIO  
Chaining to Track/Sequence More Supplies  
SUPPLY GENERATOR 4  
Q4  
IN  
SLAVE4  
SLAVE3  
V
IN OUT  
R
X4  
SENSE  
10Ω  
SUPPLY GENERATOR 3  
Q3  
V
IN  
IN OUT  
R
X3  
SENSE  
10Ω  
SGATE1 SGATE2  
D1  
D2  
V
CC  
S1  
S2  
0.1µF  
R
R
FB3  
ON  
MGATE  
RAMP  
FB1  
NC  
LTC2926  
FA3  
RAMPBUF  
R
R
FB4  
V
CC  
R
R
TB3  
FB2  
TRACK1  
FA4  
RSGATE  
NC  
10k  
10k  
TA3  
R
R
TB4  
FAULT  
TRACK2  
STATUS/PGI  
GND PGTMR  
TA4  
SUPPLY GENERATOR 2  
Q2  
SLAVE2  
SLAVE1  
V
IN  
IN OUT  
R
X2  
SENSE  
10Ω  
SUPPLY GENERATOR 1  
Q1  
V
IN  
IN OUT  
R
X1  
SENSE  
10Ω  
SGATE1 SGATE2  
D1  
D2  
V
CC  
S1  
S2  
0.1µF  
R
R
ONB  
R
R
FB1  
ON  
FB1  
FB2  
ONA  
FA1  
R
R
MGATE  
RAMP  
RAMPBUF  
FB2  
LTC2926  
C
MGATE  
FA2  
R
R
TB1  
TRACK1  
RSGATE  
NC  
TA1  
R
TB2  
FAULT  
STATUS  
FAULT  
TRACK2  
STATUS/PGI  
GND PGTMR  
2926 TA02  
R
TA2  
C
PGTMR  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
Precision Six Supply Monitor  
COMMENTS  
LTC2908  
Four Fixed (Various Levels) and Two Adjustable Input Thresholds  
Single or Dual, Symmetric/Asymmetric High and Low Margining  
Monitor up to Five Supplies, Includes Remote Sense Switches  
Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages  
LTC2920-1/LTC2920-2 Single/Dual Power Supply Margining Controllers  
LTC2921/LTC2922  
LTC2923  
Power Supply Trackers with Input Monitors  
Power Supply Tracking Controller  
LTC2925  
Multiple Power Supply Tracking Controller with  
Power Good Timeout  
Controls Three Supplies Without FETs, Includes Three Shutdown Control  
Pins  
LTC2927  
Single Power Supply Tracking Controller  
Controls Single Supply Without FETs, Daisy-Chain for Multiple Supplies  
2926fa  
LT 0506 REV A • PRINTED IN USA  
28 LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
●
●
© LINEAR TECHNOLOGY CORPORATION 2005  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  

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