LTC2970CUFD-1#PBF_技术文档

LTC2970/LTC2970-1

2

Dual I C Power

Supply Monitor and

Margining Controller

FeaTures

DescripTion

TheLTC^®2970isadualpowersupplymonitorandmargin-

n

Less Than ±±0.5 Total Unadjusted Error 14-Bit DΣ

2

ingcontrollerwithanSMBuscompatibleI Cbusinterface.

ADC with On-Chip Reference

n

A low-drift, on-chip reference and 14-bit ΔΣ A/D converter

allow precise measurements of supply voltages, load

currents or internal die temperature. Fault management

allows ALERT to be asserted for configurable overvoltage

and undervoltage fault conditions. Two voltage buffered,

8-bit IDACs allow highly accurate programming of DC/DC

converter output voltages. The IDACs can be configured

to automatically servo the power supplies to the desired

voltages using the ADC. The LTC2970-1 adds a tracking

feature that can be used to turn multiple power supplies

on or off in a controlled manner.

Dual, 8-Bit IDACs with 1x Voltage Buffers

n

Linear, Voltage Servo Adjusts Supply Voltages by

Ramping IDAC Outputs Up/Down

2

n

I C Bus Interface (SMBus Compatible)

n

Extensive, User Configurable Fault Monitoring

n

On-Chip Temperature Sensor

n

Available in 24-Pin 4mm × 5mm QFN Package

applicaTions

n

Dual Power Supply Voltage Servo

n

Monitoring Supply Voltage and Current

The bus address is set to 1 of 9 possible combinations by

pin strapping the ASEL0 and ASEL1 pins. The LTC2970/

LTC2970-1 are packaged in a 24-pin, 4mm × 5mm QFN

package.

n

Programmable Power Supplies

Programmable Reference

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

Dual Power Supply Monitor and Controller (One of Two Channels Shown)

ADC Total Unadjusted Error

vs Temperature

8V TO 15V

0.50

0.25

0

16 PARTS MOUNTED ON PCB

0.1µF

12V

IN

V

DD

IN

OUT

IN

1/2 LTC2970

GPIO_CFG

I+

I–

V

IN0_BP

IN0_BM

OUT0

ALERT

SCL

DC/DC

2

I C BUS

SMBUS

COMPATIBLE

CONVERTER

–0.25

SDA

V

I

(

)

IN0_AP

ADC VIN = 5V

RUN/SS FB

GPIO_0

REF

LOAD

OUT0

–0.50

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

V

SGND

GND

IN0_AM

29701 TA01b

GND ASEL0 ASEL1

0.1µF

29701 TA01

29701fe

1

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1 and 2)

TOP VIEW

Supply Voltages:

V

.......................................................... –0.3V to 6V

IN

DD

12V ..................................................... –0.3V to 15V

24 23 22 21 20

Digital Input/Output Voltages:

V

1

2

3

4

5

6

7

19

18

17

16

15

14

13

SDA

IN0_AP

ASEL0, ASEL1............................. –0.3V to V + 0.3V

V

SCL

IN0_AM

DD

V

ALERT

GPIO_0

GPIO_1

SDA, SCL, GPIO_CFG,

IN0_BP

IN0_BM

25

GND

ALERT, GPIO_0, GPIO_1........................... –0.3V to 6V

Analog Voltages:

V

IN1_AP

IN1_AM

I

OUT0

V

, V

,

IN0_AP IN0_AM IN0_BP

V

I

IN1_BP

OUT1

, V

,

8

9

10 11 12

IN0_BM IN1_AP IN1_AM

, V

............... –0.3V to 6V

IN1_BP IN1_BM OUT0 OUT1

I

, I

, REF......................... –0.3V to V + 0.3V

OUT0 OUT1 DD

UFD PACKAGE

24-LEAD (4mm × 5mm) PLASTIC QFN

= 150°C, θ = 34°C/W, θ = 3°C/W

RGND.................................................... –0.3V to 0.3V

Operating Ambient Temperature Range:

LTC2970C................................................ 0°C to 70°C

LTC2970I .............................................–40°C to 85°C

LTC2970H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

T

JMAX

JA

JC

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

http://www0linear0com/product/LTC297±#orderinfo

orDer inForMaTion

LEAD FREE FINISH

LTC2970CUFD#PBF

LTC2970CUFD-1#PBF

LTC2970IUFD#PBF

LTC2970IUFD-1#PBF

LTC2970HUFD#PBF

LTC2970HUFD-1#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

24-Pin (4mm × 5mm) Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

LTC2970CUFD#TRPBF

2970

LTC2970CUFD-1#TRPBF 29701

24-Pin (4mm × 5mm) Plastic QFN

0°C to 70°C

LTC2970IUFD#TRPBF

LTC2970IUFD-1#TRPBF

LTC2970HUFD#TRPBF

2970

29701

2970

–40°C to 85°C

–40°C to 125°C

LTC2970HUFD-1#TRPBF 29701

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

29701fe

2

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2.°C0 V_12VIN= 12V, V_DDand REF pins floating unless otherwise indicated,

C_VDD= 1±±nF and C_REF= 1±±nF0

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

UNITS

Power-Supply Characteristics

l

I

12V Supply Current

V

= 12V, V Floating

4.24

3.7

7.5

5

mA

V12

DD

IN

12VIN

DD

V

DD

V

DD

V

DD

Supply Current

= 5V, V

= V

DD

mA

DD

12VIN

V

Undervoltage Lockout

Undervoltage Lockout Hysteresis

Ramping-Down, V

= V

DD

3.7

4.14

118

4.4

V

LKO

12VIN

mV

l

V

Supply Input Operating Range

Regulator Output Voltage

4.5

5.75

5.25

V

DD

8V ≤ V

≤ 15V, –1mA ≤ I

≤ 0

4.75

4.95

10

12VIN

VDD

Regulator Output Voltage

Temperature Coefficient

ppm/°C

Regulator Output Voltage Load

Regulation

–1mA ≤ I

≤ 0

160

ppm/mA

VDD

Regulator Line Regulation

8V ≤ V

≤ 15V, I

= 0mA

80

ppm/V

mA

12VIN

VDD

l

Regulator Output Short-Circuit Current

V

12VIN

= 12V, V = 0V

–5

8

–34

–63

15

DD

V

12VIN

12V Supply Operating Range

V

IN

Voltage Reference Characteristics

V

REF

Reference Output Voltage

1.229

2

V

Reference Voltage Temperature

Coefficient

ppm/°C

l

Reference Overdrive Voltage Input

Range

1

1.5

V

ADC Characteristics

N_ADC

Resolution

N_ADC = 8.192V/16384

= 3V, V = V – V (Note 3)

INn_xM

500

2

µV/LSB

%

l

TUE_ADC

INL_ADC

DNL_ADC

Total Unadjusted Error

Integral Nonlinearity

Differential Nonlinearity

Input Voltage Range

Offset Error

V

IN

0.5

4.5

0.5

6

IN

INn_xP

(Note 4)

(Note 7)

–4.5

LSB

V

0

IN_ADC

OS_ADC

V

–1000

–316

0.19

1000

µV

Offset Error Drift

µV/°C

%

l

GAIN_ADC

Gain Error

Full-Scale V = 6V

0.4

IN

Gain Error Drift

3

ppm/°C

ms

T

Conversion Time

33.3

3

CONV_ADC

C

Input Sampling Capacitance

Input Sampling Frequency

Input Leakage Current

pF

IN_ADC

F

61.4

kHz

µA

l

I

0V < V < 6V

IN

0.1

LEAK_ADC

IDAC Output Current Characteristics

N_I

Resolution (Guaranteed Monotonic)

Integral Nonlinearity

8

Bits

LSB

OUT

l

INL_I

V

< V – 1.5V

1

OUT

IOUTn

DD

DNL_I

Differential Nonlinearity

Full-Scale Output Current

Output Current Drift

< V – 1.5V

LSB

OUT

DD

I

-I

< V – 1.5V, DAC Code = 'hff

–236

–255

32

–276

µA

FS OUT

DD

-I

DAC Code = 'hff

DAC Code = 'h00

ppm/°C

DRIFT OUT

l

-I

Offset Current

0.1

µA

OS OUT

29701fe

3

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2.°C0 V_12VIN= 12V, V_DDand REF pins floating unless otherwise indicated,

C_VDD= 1±±nF and C_REF= 1±±nF0

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

UNITS

Voltage Buffered IDAC Output Characteristics

l

INL_V

Integral Nonlinearity

Differential Nonlinearity

Offset Voltage

R

= 10kΩ, No Load on V

(Note 5)

1

LSB

OUT

IOUTn

OUTn

DNL_V

OUT

IOUTn

OUTn

V

-V

OS OUT

V

OS

= V

– V , No Load on V

IOUTn

OUTn

1.6

0.17

–57

100

1

10

mV

OUTn

Output Voltage Drift

Load Regulation

No Load on V

µV/°C

ppm/mA

nA

V

0.1V < V

< V – 1.5V, I

Source = 1mA

Sink = 1mA

OUT

OUTn

DD

VOUTn

< V – 1.5V, I

DD

l

Leakage Current

V

OUTn

V

OUTn

V

OUTn

High-Z, 0V ≤ V

≤ V

DD

100

–50

50

OUTn

Short-Circuit Current Low

Short-Circuit Current High

Shorted to GND

Shorted to V

mA

DD

Soft Connect Comparator Characteristics (CMP±, CMP1)

Offset Voltage

Temperature Sensor Characteristics

TMP Gain

12V Voltage Divider Characteristics

V

3

mV

°C/LSB

V/V

OS

0.25

0.333

IN

l

GAIN_12V

Gain

0.329

0.335

IN

Digital Inputs SCL, SDA, GPIO_CFG, GPIO_±, GPIO_1

l

V

High Level Input Voltage

Low Level Input Voltage

SDA, SCL

2.1

1.6

V

IH

GPIO_CFG, GPIO_0, GIPO_1

SDA, SCL

1.5

1.0

V

IL

GPIO_CFG, GPIO_0, GIPO_1

V

Input Hysteresis

0.08

10

V

HYST

LEAK

l

I

Input Leakage Current

Input Capacitance

0V ≤ V ≤ 6V

1

µA

pF

IN

C

IN

Three State Inputs ASEL[1:±]

l

V

Input High Threshold Voltage

Input Low Threshold Voltage

High, Low Input Current

High Z Input Current

V

DD

– 0.5

V

IH_ASEL

IL_ASEL

IN,HL

0.5

2

I

ASEL[1:0] = 0, V

20

µA

DD

IN,Z

Open Drain Outputs SDA, GPIO_CFG, GPIO_±, GPIO_1, ALERT

l

V

Output Low Voltage

I

= 3mA

0.4

1

V

OL

OH

SINK

I

Input Leakage Current

0V ≤ V ≤ 6V

µA

IN

29701fe

4

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2.°C0

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

UNITS

2

I C Interface Timing Characteristics

l

f

t

Serial Clock Frequency

(Note 6)

10

1.3

0.6

1.3

600

400

kHz

µs

ns

SCL

Serial Clock Low Period

LOW

Serial Clock High Period

HIGH

Bus Free Time Between Stop and Start

Start Condition Hold Time

Start Condition Setup Time

Stop Condition Setup Time

BUF

HD,STA

SU,STA

SU,STO

HD,DAT

Data Hold Time (LTC2970 Receiving Data)

Data Hold Time (LTC2970 Transmitting Data)

0

300

ns

900

l

t

Data Setup Time (LTC2970 Receiving Data)

Pulse Width of Spike Suppressed

GPIO_0 and GPIO_1 Setup Time

(Note 6)

100

ns

µs

SU,DAT

98

SP

GPIO_0 and GPIO_1 input setup time

prior to the 26th rising SCL of an IO()

2.5

SETUP_GPIO

2

I C read. These inputs must be valid and

stable by this time to be returned in the

IO() read result. (Note 6)

l

t

GPIO_0 and GPIO_1 Hold Time

GPIO_0 and GPIO_1 Output Time

GPIO_0 and GPIO_1 input hold time

2.5

µs

HOLD_GPIO

OUT_GPIO

2

after the 26th rising SCL of an IO() I C

read. These inputs must be held until this

amount of time has elapsed to be returned

in the IO() read result. (Note 6)

l

t

GPIO_0 and GPIO_1 output delay after

2.5

39

2

the 35th rising SCL of an I C write. These

outputs will become high impedance or

begin driving low by this time. (Note 6)

Internal Timers

2

t

Stuck BUS Timer

The LTC2970 will release the I C bus and

24

32

304

255

32

ms

µs

TIMEOUT_SMB

SETUP_ADC

TIMEOUT_

terminate the current command if the

command is not completed before this

amount of time has elapsed.

ADC Channel Setup Time

Tracking SYNC Failure Timer

Tracking IDAC Disconnect Delay

After selecting a new ADC channel, the

LTC2970 will wait this amount of time

to allow the analog input to settle before

beginning an ADC conversion.

LTC2970-1 Only: The LTC2970-1 will

abort a pending SYNC() command if a

tracking command is not received before

this amount of time has elapsed.

ms

SYNC

t

LTC2970-1 Only: After the tracking

algorithm asserts CPIO_CFG low, the

LTC2970-1 will delay disconnecting the

IDACs from the power supply feedback

nodes by this amount of time. Used while

tracking power supplies on.

HOLD_TRACK

29701fe

5

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 2.°C0

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

UNITS

t

Tracking IDAC Disconnect Delay

LTC2970-1 Only: After the tracking

algorithm asserts CPIO_CFG high, the

LTC2970-1 will wait this amount of time

before starting to decrement Chn_a_

delay_track[9:0]. Used while tracking

power supplies off.

32

ms

SETUP_TRACK

t

Tracking IDAC Decrement Rate

LTC2970-1 Only: The LTC2970-1 changes

Chn_a_delay_track[9:0] at this rate.

88

µs/LSB

DEC_TRACK

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Integral nonlinearity (INL) is defined as the deviation of a code

from a straight line passing through the actual endpoints (0V and 6V)

of the transfer curve. The deviation is measured from the center of the

quantization band.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground unless otherwise

specified.

Note .: Nonlinearity is defined from the first code that is greater than or

equal to the maximum offset specification to code 255 (full-scale).

Note 6: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and

Note 3: TUE (%) is defined as:

clock rise time (t ) and fall time (t ) are: (20 + 0.1 • C )(ns) < t < 300ns

r f B r

and (20 + 0.1 • C )(ns) < t < 300ns. C = capacitance of one bus line in

(INL•500µV/LSB+ V_OS

)

B

f

B

%GainError+

•100

pF. SCL and SDA external pull-up voltage, V , is 3V < V < 5.5V.

IO

V

IN

Note 7: This specification is guaranteed by design.

TiMing DiagraM

The I²C Bus Specification

SDA

t

SU;DAT

t

r

t

BUF

f

LOW

r

f

HD;STA

SP

t

SCL

t

SU;STA

HD;STA

SU;STO

t

HIGH

HD;DAT

START

CONDITION

REPEATED START

CONDITION

STOP

START

CONDITION CONDITION

29701 TD

29701fe

6

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

Typical perForMance characTerisTics

ADC Total Unadjusted Error

vs Temperature

ADC INL

ADC DNL

0.200

0.150

2.5

2.0

1.5

1.0

0.5

0

1.00

BASED ON AVERAGE OF 16 PARTS

ASSEMBLED ON PCB

0.75

0.50

0.25

0.100

0.050

0.000

0

ADC V

–0.050

–0.100

–0.150

–0.200

–0.25

IN

1.0V

1.8V

2.5V

3.3V

5.0V

–0.50

–0.75

–1.00

–0.5

–1.0

–50 –25

0

25 50 75 100 125 150

0

3

4

5

6

1

2

1

2

4

0

5

6

3

TEMPERATURE (°C)

INPUT VOLTAGE (V)

29701 G01

29701 G02

29701 G03

ADC Zero Code Center Offset

Voltage vs Temperature

ADC Rejection vs Frequency

at V_IN

ADC Rejection vs Frequency

at V_IN

–75

–100

–125

–150

–175

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–50 –25

0

25 50 75 100 125 150

100

FREQUENCY AT V (Hz)

10000

1

10

1000

0

5000

15000 20000 25000 30000

10000

TEMPERATURE (°C)

FREQUENCY AT V (Hz)

IN

29701 G04

29701 G05

29701 G06

ADC Noise Histogram

Voltage Buffered IDAC INL

Voltage Buffered IDAC DNL

0.50

0.25

0

0.50

0.25

0

10,000,000

1,000,000

CHANNELS 0 AND 1 SHOWN

V

= 0V

IN

R

IOUT0

= R

= 10kΩ

R

IOUT0

= R

= 10kΩ

IOUT1

100,000

10,000

1000

100

–0.25

–0.50

–0.25

–0.50

10

1

0

50

100

150

200

250

0

50

100

150

200

250

–1

0

2

–2

1

DAC CODE

OUTPUT CODE (LSBs)

29701 G09

29701 G08

29701 G07

29701fe

7

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

Typical perForMance characTerisTics

IDAC Output Current

vs Temperature

V

_OUTnOffset Voltage

Voltage Buffered IDAC Load

Regulation Sourcing

vs Temperature

2.0

1.5

257.50

256.75

256.00

255.25

254.50

3.500

3.499

3.498

3.497

IDAC CODE = 'hff

IDAC CODE = 'h00

125°C

90°C

25°C

–45°C

R

= 13kΩ

IOUT

10 TYPICAL PARTS

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

V

IOUT = 3.5V

n

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

–2

–4

–6

–8

–10

TEMPERATURE (°C)

CURRENT (mA)

29701 G11

29701 G10

29701 G12

Voltage Buffered IDAC Load

Regulation Sinking

Voltage Buffered IDAC Transient

Voltage Buffered IDAC Soft-

Response to 1LSB DAC Code Change

Connect Transient Response

0.4

0.3

0.2

0.1

0

100kΩ SERIES RESISTANCE ON V

IOUT

100kΩ SERIES RESISTANCE ON V

IOUT

CODE 'h80

V

= 0.1V

OUTn

IOUT

R

= 10kΩ

R

= 10kΩ

CODE 'h80

HIGH-Z

CODE 'h7f

CONNECTED

125°C

90°C

25°C

–45°C

0

2

4

6

8

10

1µs PER DIVISION

CURRENT (mA)

5µs PER DIVISION

29701 G13

29701 G14

29701 G15

Voltage Buffered IDAC Transient

Response During Transition from

On State to High-Z State

Temperature Sensor Error

vs Temperature

V_DDRegulator Output Voltage

vs Temperature

5.0

2.5

4.95

4.94

4.93

4.92

4.91

4.90

100kΩ SERIES RESISTANCE ON V

IOUT

OUTn

V

VDD

=12V

12VIN

8 TYPICAL PARTS

R

= 10kΩ

I

= 0A

HIGH-Z

0

CONNECTED

–2.5

–5.0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

10µs PER DIVISION

TEMPERATURE (°C)

29701 G17

29701 G18

29701 G16

29701fe

8

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

Typical perForMance characTerisTics

V_DDRegulator Short-Circuit

Current vs Temperature

–30

V_DDRegulator Load Regulation

V_DDRegulator Line Regulation

750

500

250

0

–100

–200

–300

–400

–500

–600

–700

NO LOAD ON V

DD

V

=12V

12IN

DD

125°C

V

= 0V

90°C

25°C

–45°C

–35

–40

–45

–50

–250

–500

–750

125°C

90°C

25°C

–45°C

V

= 12V

12VIN

8

9

10

11

12

13

14

15

–50 –25

0

25 50 75 100 125 150

0

–1

–2

–3

–4

–5

V

(V)

TEMPERATURE (°C)

CURRENT (mA)

12VIN

29701 G20

29701 G21

29701 G19

pin FuncTions

V

(Pin 1): Positive CH0_A ADC Multiplexer Input.

V

(Pin7):PositiveCH1_B ADCMultiplexerInput.The

IN0 _AP

IN1_BP

The output of the differential, 7:1 multiplexer connects to

the input of the ADC. CH0_A can be configured to servo

IDAC0.

output of the differential, 7:1 multiplexer connects to the

input of the ADC. CH1_B is a voltage monitor input only.

V

(Pin 8): Negative CH1_B ADC Multiplexer Input.

IN1_BM

V

(Pin 2): Negative CH0_A ADC Multiplexer Input.

The output of the differential, 7:1 multiplexer connects to

IN0 _AM

The output of the differential, 7:1 multiplexer connects to

the input of the ADC. CH0_A can be configured to servo

IDAC0.

theinputoftheADC.CH1_Bisavoltagemonitorinputonly.

V

(Pin 9): V Power Supply, Voltage Monitor Input,

DD

and Internal 5V Regulator Output. The supply input range

V

(Pin3):PositiveCH0_B ADCMultiplexerInput.The

is 4.5V to 5.75V. The V pin voltage can be connected

IN0 _BP

DD

output of the differential, 7:1 multiplexer connects to the

to the ADC through an internal mux. Bypass the V pin

DD

input of the ADC. CH0_B is a voltage monitor input only.

to device ground with a 100nF capacitor (C ). If no 5V

VDD

input voltage supply is available, float the V pin and

DD

V

(Pin 4): Negative CH0_B ADC Multiplexer Input.

IN0 _BM

power the LTC2970 from the 12V pin.

IN

The output of the differential, 7:1 multiplexer connects to

theinputoftheADC.CH0_Bisavoltagemonitorinputonly.

12V (Pin 10 ): 12V Power Supply and Voltage Monitor

IN

Input. An internal regulator generates 5V from 12V . The

IN

V

(Pin 5): Positive CH1_A ADC Multiplexer Input.

IN1_AP

input range for 12V is 8V to 15V. Bypass this pin with a

IN

The output of the differential, 7:1 multiplexer connects to

the input of the ADC. CH1_A can be configured to servo

IDAC1.

100nF capacitor. The regulator’s output is connected to

the V pin. The 12V pin voltage can also be monitored

DD

IN

by the ADC through a 3:1 attenuator and the internal mux.

If no 12V supply input is available, tie the 12V to the V

V

(Pin 6): Negative CH1_A ADC Multiplexer Input.

IN1_AM

IN

DD

The output of the differential, 7:1 multiplexer connects to

the input of the ADC. CH1_A can be configured to servo

IDAC1.

pin and operate from 4.5V to 5.75V.

V

(Pin 11): CH0 Voltage Output. Buffered version of

OUT0

IDAC0 output voltage.

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LTC2970/LTC2970-1

pin FuncTions

V

(Pin 12): CH1 Voltage Output. Buffered version of

SDA (Pin 19): Serial Bus Data Input and Output.

OUT1

IDAC1 output voltage.

GPIO_CFG (Pin 20 ): GPIO Configuration Digital Input and

Open Drain Output. Pulling GPIO_CFG high will cause the

GPIO_0 and GPIO_1 open-drain outputs to automatically

assert low after a power-on reset. If GPIO_CFG is pulled

low, then GPIO_0 and GPIO_1 do not assert low after

power-up.

I

(Pin 13): IDAC1 Current Output. Connect a resistor

OUT1

between this pin and the point-of-load ground for channel

1. The IDAC sources between 0 and 255µA.

I

(Pin 14): IDAC0 Current Output. Connect a resistor

OUT0

between this pin and the point-of-load ground for channel

0. The IDAC sources between 0 and 255µA.

ASEL1 (Pin 21): Slave Address Select Bit 1. Tie this pin to

the V pin, ground, or float in order to select the address

DD

GPIO_1 (Pin 15): General Purpose Input or Open Drain

Digital Output. GPIO_1 can be configured as the IDAC

Fault or Faults output, a digital input, or an open-drain

digital output.

location (see Table 2).

ASEL0 (Pin 22): Slave Address Select Bit 0. Tie this pin to

the V pin, ground, or float in order to select the address

DD

location (see Table 2).

GPIO_0 (Pin 16): General Purpose Input or Open Drain

Digital Output. GPIO_0 can be configured as the voltage

monitor power-good or power-good bar output, a digital

input, or a programmable open-drain output. Power good

is the NOR of all instantaneous OV and UV faults; it does

not include IDAC faults.

REF(Pin23):InternalReferenceOutputorADCReference

Overdrive Input. The voltage at this pin determines the

full-scale input voltage of the delta-sigma ADC (V

FULL-

= 6.65 • V , typically). An internal 3.5k resistor

SCALE

REF

decouples the reference output from this pin. Bypass this

pin to RGND with a 100nF capacitor (C ).

REF

ALERT (Pin 17): Open Drain Digital Output. Connect the

SMBALERT signal to this pin. ALERT is asserted low when

either IDAC0 or IDAC1 rails out (optional), or when one

of the monitored voltages ventures outside its UV and OV

thresholds (also optional).

RGND (Pin 24): Reference Ground. Connect to device

ground.

GND(Pin25):DeviceGround.Mustbesolderedtoground.

SCL (Pin 18): Serial Bus Clock Input.

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LTC2970/LTC2970-1

block DiagraM

5V REGULATOR

0µA TO 255µA

IDAC0

8 BITS

12V

IN

10

V

OUT

IN

2R

14

I

OUT0

R

V

DD

V

9

DD

+

–

12V

P

CMP0

12V

M

DDP

DDM

V

+

GND 25

VBUF0

11 V

OUT0

V

DD

–

TEMP

SENSOR

TSNSP

TSNSM

POR

UVLO

V

1

CH0_AP

CH0_AM

CH0_BP

CH0_BM

CH1_AP

CH1_AM

CH1_BP

CH1_BM

IN0_AP

0µA TO 255µA

V

2

3

4

5

6

7

8

IN0_AM

IDAC1

8 BITS

13

I

OUT1

+

–

V

IN0_BP

14-BIT

DELTA-SIGMA

A/D

V

IN0_BM

V

+

IN1_AP

IN1_AM

CMP1

ADC

CLOCKS

–

V

+

IN1_BP

IN1_BM

6.65X

(TYP)

V

DD

12

V

OUT1

VBUF1

–

7:1 MUX

3.5k

REFERENCE

1.229V (TYP)

REF 23

RGND 24

RAM

20Ω

ADC_Results

MONITOR LIMITS

SERVO TARGETS

SCL 18

SDA 19

18

2

CLOCK

GENERATION

I C BUS INTERFACE

OSCILLATOR

POR

(400kHz, SMBUS COMPATIBLE)

ASEL0 22

ASEL1 21

REGISTERS

I/O CONFIGURATION

IDAC0

IDAC1

ADC MONITOR

FAULT ENABLE

INSTANTANEOUS FAULTS

LATCHED FAULTS

SERVO CONTROLLER

GPIO_0 16

GPIO_1 15

ALERT 17

DAC SOFT CONNECT FUNCTION

SERVO FUNCTION

7

2

MONITOR FUNCTION

MANAGE FAULT REPORTING

WATCH DOG

GPIO_CFG 20

TRACKING CONTROL (LT2970-1)

POR

29701 BD

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LTC2970/LTC2970-1

Table oF conTenTs ^{(For Operations Sections)}

1. LTC2970 Operation Overview.............................................................................................................................13

2

2. I C Serial Digital Interface .................................................................................................................................14

3. Register Command Set.......................................................................................................................................15

2

4. Detailed I C Command Register Descriptions...................................................................................................16

5. Soft Connecting the LTC2970 to the Power Supply Feedback Node..................................................................20

6. Hard Connecting the LTC2970 to the Power Supply Trim Pin............................................................................20

7. Programming a Previously Connected IDAC......................................................................................................21

8. Disconnecting the LTC2970 from the Power Supply Trim Pin ...........................................................................21

9. Tracking Power Supplies Overview (LTC2970 -1 Only).......................................................................................21

10 . Tracking Power Supplies On (LTC2970 -1 Only) .................................................................................................21

11. Tracking Power Supplies Off (LTC2970 -1 Only) .................................................................................................22

12. Continuous Power Supply Voltage Servo...........................................................................................................23

13. One Time Power Supply Voltage Servo .............................................................................................................24

14. One Time Power Supply Voltage Servo with Repeat On Fault ..........................................................................24

15. Configuring ADC to Monitor Input Channels and Internal Temperature Sensor................................................24

16. Generating and Monitoring Instantaneous Faults..............................................................................................25

17. Generating and Monitoring Latched Faults........................................................................................................26

18. General Purpose Input/Output Pins....................................................................................................................27

19. Advanced Development Features.......................................................................................................................27

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LTC2970/LTC2970-1

operaTion

1. LTC2970 Operation Overview

All communication with the LTC2970 is performed over

2

an industry standard I C bus. The LTC2970 I C interface

alsomeetsallSMBussetuptimes,holdtimes,andtimeout

requirements. The ALERT pin may be used to signal that

one or more of the fourteen configurable fault limits have

been reached. Each fault may be individually masked. The

The LTC2970 is designed to control and monitor two

power supplies. The LTC2970’s superior accuracy allows

it to precisely servo each supply’s output voltage over a

wide range of operating conditions; increasing accuracy,

reducing power requirements and component costs. Mar-

gining may be performed with equal ease and precision.

The monitoring functions allow for increased reliability by

alerting a system host about incipient failures before they

occur.ThesevenchannelADCmayalsobeusedtomonitor

current, temperature, and the 5V or optional 12V supply.

2

I C interface supports word reads, word writes and the

SMBus Alert Response Address protocol. Two general

purpose IO pins may be used to provide additional fault

information or user defined system control. Powering

2

down the LTC2970 will not interfere with I C operation.

The LTC2970-1 enables power supply tracking and se-

quencing with the addition of a few external components.

A special global address and synchronization command

allowmultipleLTC2970-1’stotrackandsequencemultiple

pairs of power supplies.

The LTC2970’s unique architecture and control algorithm

have been especially tailored for power supply manage-

ment.ThesoftconnectfeatureallowstheLTC2970tobegin

controlling a power supply without perturbing its initial

value. The delta-sigma ADC architecture was specifically

chosen to average out power-supply noise and allow the

LTC2970 to ignore fast transients. Unlike discrete time

DACs, the LTC2970’s continuous time, voltage buffered

IDAC is ideal for noise sensitive applications. The servo

algorithmlimitstheIDACstepsizetooneLSBperiteration

in order to minimize power supply transients. The point

of load ground reference for the IDAC outputs minimize

errors that would otherwise occur in a power system that

experiences ground bounce. By selecting two resistor

values, the user can choose the appropriate resolution

while providing an important hardware range limit beyond

which the supply may not be driven. The servo on fault

optionallowstheLTC2970tofurtherreduceoutputvoltage

disturbances by only stepping the IDAC when the output

voltage drifts outside of a user programmable window.

The LTC2970 powers up in a high impedance state and

will not interfere with default power supply operation.

Similarly, powering down the LTC2970 will restore its

high impedance state.

The LTC2970 can perform the following operations:

• Accept all programming commands and report status

2

over the I C or SMBus bus.

• CommandeachvoltagebufferedIDACtoconnecttothe

corresponding power supply’s feedback node through

an external resistor using the IDAC code that most

closely approximates the feedback node’s regulation

voltage (Soft Connect).

• CommandeachvoltagebufferedIDACoutputtoconnect

to the corresponding power supply’s feedback node

through an external resistor with a user-selected IDAC

code (Hard Connect).

• Change the code of a previously connected IDAC.

• Disconnect each voltage buffered IDAC output from the

power supply’s feedback node.

• LTC2970-1 Only: Track two power supplies up or down.

Multiple LTC2970-1’s can be configured to track simul-

taneously or in a sequence.

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LTC2970/LTC2970-1

operaTion

• Continuously servo one or both supplies to a pro-

The two bus lines, SDA and SCL, must be high when the

bus is not in use. External pull-up resistors or current

sources are required on these lines.

grammed voltage.

• Perform a one-time servo of one or both supplies to a

programmed voltage and hold the servo codes in the

controlling IDAC.

2

TheLTC2970I CinterfaceisSMBuscompatible;itmeetsall

SMBussetuptimes,holdtimesandtimeoutrequirements.

• Perform a one time servo of one or both supplies to

a programmed voltage and hold the code(s) in the

controlling IDAC(s) until over/under voltage monitor-

ing detects a fault, at which point a control bit may be

used to allow the LTC2970 to servo back to the initial

voltage target.

TheLTC2970isareceive-only(slave)device.TheLTC2970

can signal the host through the SMBALERT protocol that

it wants to talk by asserting ALERT low. The LTC2970

2

supports the three I C protocols summarized in Table 1.

Slave Address

The LTC2970 can respond to one of nine 7-bit addresses.

The two slave address select pins (ASEL1 and ASEL0) are

programmedbytheuseranddeterminetheslaveaddress,

as shown in Table 2.

• SelectanycombinationofsevenpossibleADCchannels

to be monitored by the ADC.

• Generate instantaneous faults based on user

programmable overvoltage and undervoltage limits

and fixed IDAC limits. The status of OR’d voltage limit

faults and IDAC faults may be output over GPIO_0 and

GPIO_1, respectively.

The LTC2970 also supports the ARA address and a global

addressthatallowsmultipleLTC2970stobeprogrammed

with the same data simultaneously, as shown in Table 3.

Table 1. Supported I²C Command Types

READ DATA WORD:

• Enable instantaneous faults to set associated latched

faults using the FAULT_EN register. The status of OR’d

latched faults may be signalled using ALERT.

S:ADR:W:A:CMD:A:Sr:ADR:R:A:DATA:A:DATA:NACK:P

WRITE DATA WORD:

• Configure the GPIO_0 and GPIO_1 pins to act as inputs

S:ADR:W:A:CMD:A:DATA:A:DATA:A:P

ALERT RESPONSE

or outputs.

2

2. I C Serial Digital Interface

S:ARA:R:A:ADR:NACK:P:

The LTC2970 communicates with a host (master) using

2

the 2-wire, I C serial bus interface. The Timing Diagram

shows the timing relationship of the signals on the bus.

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LTC2970/LTC2970-1

operaTion

Table 2. LTC2970 Address Table

Table 3. Special LTC2970 Addresses

ADDRESS[7:0 ]

(R/W = 0 )

ADDRESS[7:1]

ASEL1

ASEL0

ADDRESS[7:0 ] ADDRESS[7:1] FUNCTION

(R/W = 0 )

8’hB8

8’hBA

8’hBC

8’hBE

8’hD6

8’hD8

8’hDA

8’hDC

8’hDE

7’h5C

7’h5D

7’h5E

7’h5F

7’h6B

7’h6C

7’h6D

7’h6E

7’h6F

L

F

L

F

ARA

8’h18

7’h0C

7’h5B

This is the standard Alert

Response Address for all

SMBus devices. This address is

independent of the value of the

ASEL1 and ASEL0 pins.

H

L

F

Global

8’hB6

This a global address to which

all LTC2970s will respond. This

address is independent of the

value of the ASEL1 and ASEL0

pins.

F

H

L

F

H

L: V

< V

F: ASELn Floating H: V

> V

ASELn

IL_ASEL

ASELn IH_ASEL

3. Register Command Set

COMMAND FUNCTION

DESCRIPTION

R/W

DATA

LENGTH

COMMAND

BYTE VALUE

FAULT()

Instantaneous Fault Status For All Channels

Enable For All Latched Faults and Servo On Fault

Index to All Latched Faults

Read Only

Read/Write

Read Only

Read/Write

Read Only

Read/Write

Read Only

Read/Write

Read Only

Read/Write

Read Only

Read/Write

Read Only

Read/Write

16 Bits

‘h00

‘h08

‘h10

‘h11

‘h17

‘h18

‘h1F

‘h28

‘h29

‘h2A

‘h38

‘h39

‘h3A

‘h40

‘h41

‘h42

‘h43

‘h44

‘h45

‘h46

‘h48

‘h49

‘h4A

‘h50

‘h51

‘h52

FAULT_EN()

FAULT_LA_INDEX()

FAULT_LA()

IO()

Latched Fault Status For All Channels

IO Control and Status Register

ADC_MON()

*SYNC()

Control Register For Selecting ADC Channels to Monitor

Control Register For Synchronizing Tracking Across Multiple Devices

VDD_ADC()

VDD_OV()

V

DDIN

V

DDIN

V

DDIN

ADC Conversion Result Register

Overvoltage Monitor Control Register

Undervoltage Monitor Control Register

VDD_UV()

V12_ADC()

12V ADC Conversion Result Register

IN

V12_OV()

12V Overvoltage Monitor Control Register

IN

V12_UV()

12V Undervoltage Monitor Control Register

IN

CH0_A_ADC()

CH0_A_OV()

CH0_A_UV()

CH0_A_SERVO()

CH0_A_IDAC()

*CH0_A_IDAC_TRACK()

CH0_A ADC Conversion Result Register

CH0_A Overvoltage Monitor Control Register

CH0_A Undervoltage Monitor Control Register

CH0_A Voltage Servo Control Register

CH0_A IDAC Control Register

CH0_A IDAC Track Final Value Register

*CH0_A_DELAY_TRACK() CH0_A IDAC Track Delay Register

CH0_B_ADC()

CH0_B_OV()

CH0_B_UV()

CH1_A_ADC()

CH1_A_OV()

CH1_A_UV()

CH0_B ADC Conversion Result Register

CH0_B Overvoltage Monitor Control Register

CH0_B Undervoltage Monitor Control Register

CH1_A ADC Conversion Result Register

CH1_A Overvoltage Monitor Control Register

CH1_A Undervoltage Monitor Control Register

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LTC2970/LTC2970-1

operaTion

3. Register Command Set (Cont.)

COMMAND FUNCTION

DESCRIPTION

R/W

DATA

LENGTH

COMMAND

BYTE VALUE

CH1_A_SERVO()

CH1_A Voltage Servo Control Register

CH1_A IDAC Control Register

Read/Write

Read Only

Read/Write

16 Bits

‘h53

‘h54

‘h55

‘h56

‘h58

‘h59

‘h5A

‘h68

‘hXX

CH1_A_IDAC()

*CH1_A_IDAC_TRACK()

CH1_A IDAC Track Control Register

*CH1_A_DELAY_TRACK() CH1_A IDAC Track Delay Register

CH1_B_ADC()

CH1_B_OV()

CH1_B_UV()

TEMP_ADC()

RESERVED()

CH1_B ADC Conversion Result Register

CH1_B Overvoltage Monitor Control Register

CH1_B Undervoltage Monitor Control Register

Temperature ADC Conversion Result Register

All other commands are reserved for future expansion and should not be

written or read.

*LTC2970-1 Only. LTC2970 will not acknowledge these commands.

2

4. Detailed I C Command Register Descriptions

FAULT_EN: Fault Enabling Register – Read/Write

BIT(s)

SYMBOL

OPERATION

FAULT: Instantaneous Fault Register – Read

b[0]

Fault_en_ch0_a_ov

Fault_en_ch0_a_uv

Fault_en_ch0_a_idac

Fault_en_ch0_b_ov

Fault_en_ch0_b_uv

Fault_en_ch1_a_ov

Fault_en_ch1_a_uv

Fault_en_ch1_a_idac

Fault_en_ch1_b_ov

Fault_en_ch1_b_uv

Fault_en_vdd_ov

0 = The associated bit in the

FAULT_LA register will always be 0.

(default)

BIT(s)

SYMBOL

OPERATION

b[1]

b[0]

b[1]

b[2]

b[3]

b[4]

b[5]

b[6]

b[7]

b[8]

b[9]

b[10]

b[11]

b[12]

b[13]

Fault_ch0_a_ov

Fault_ch0_a_uv

Fault_ch0_a_idac

Fault_ch0_b_ov

Fault_ch0_b_uv

Fault_ch1_a_ov

Fault_ch1_a_uv

Fault_ch1_a_idac

Fault_ch1_b_ov

Fault_ch1_b_uv

Fault_vdd_ov

0 = The associated channel is clear of

instantaneous faults.

b[2]

1 = Instantaneous faults reported in

the FAULT register will set associated

bit in the FAULT_LA register.

b[3]

1 = The associated channel has an

instantaneous fault.

b[4]

The reported faults are instantaneous

and not latched. When used in

conjunction with latched faults they

may indicate faults that are transient in

nature.

b[5]

b[6]

b[7]

b[8]

b[9]

b[10]

b[11]

b[12]

b[13]

b[14]

Fault_en_vdd_uv

Fault_en_v12_ov

Fault_vdd_uv

Fault_en_v12_uv

Fault_v12_ov

Fault_en_ch0_a_servo 0 = Do not re-servo CH0_A in

response to instantaneous OV or UV

fault.

Fault_v12_uv

b[15:14] Reserved

Always Returns 0

1 = Repeat a one time servo of CH0_A

in response to instantaneous OV or

UV fault. CH0_A must have servo

operation enabled with Ch0_a_idac_

servo_repeat set low, and Adc_mon_

ch0_a set high.

b[15]

Fault_en_ch1_a_servo 0 = Do not re-servo CH1_A in

response to instantaneous OV or UV

fault.

1 = Repeat a one time servo of CH1_A

in response to instantaneous OV or

UV fault. CH1_A must have servo

operation enabled with Idac_ch1_a_

servo_repeat set low, and Adc_mon_

ch1_a set high.

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LTC2970/LTC2970-1

operaTion

2

IO: Input/Output Data and General Purpose Control Register –

Read/Write unless specified otherwise.

4. Detailed I C Command Register Descriptions

(Cont.)

BIT(s)

SYMBOL

OPERATION

FAULT_INDEX: Latched Fault Index Register – Read

b[1:0]

Io_cfg_0[1:0] Io_cfg_0[1:0] is used to configure the function of

the GPIO_0 pin and IO(Io_gpio_0).

BIT(s)

SYMBOL

OPERATION

00: Io_gpio_0 = GPIO_0 = Power_good. Power_

good asserts high if there are no instantaneous

overvoltage or undervoltage faults.

b[0]

Fault_la_index

0 = All faults indicated by FAULT_LA

are clear.

1 = One or more faults indicated by

FAULT_LA are set.

01: Io_gpio_0 = GPIO_0 = Power_good_bar.

Power_good_bar is the complement of

Power_good.

This register allows a summary of all

latched faults to be viewed in a single

read without resetting latched faults.

10: GPIO_0 is a general-purpose open-drain

output and mirrors the value written to Io_gpio_0

(default).

b[15:1] Reserved

Always Returns 0

11: GPIO_0 is a general-purpose digital input

with Io_gpio_0 = GPIO_0

FAULT_LA: Latched Fault Register – Read

BIT(s)

SYMBOL

OPERATION

b[3:2]

Io_cfg_1[1:0] Io_cfg_1[1:0] is used to configure the function

of the GPIO_1 pin and IO(Io_gpio_1).

b[0]

b[1]

b[2]

b[3]

b[4]

b[5]

b[6]

b[7]

b[8]

b[9]

b[10]

b[11]

b[12]

b[13]

Fault_la_ch0_a_ov

Fault_la_ch0_a_uv

Fault_la_ch0_a_idac

Fault_la_ch0_b_ov

Fault_la_ch0_b_uv

Fault_la_ch1_a_ov

Fault_la_ch1_a_uv

Fault_la_ch1_a_idac

Fault_la_ch1_b_ov

Fault_la_ch1_b_uv

Fault_la_vdd_ov

0 = The associated channel is clear of

faults.

00: Io_gpio_1 = GPIO_1 = Idac_fault.

Idac_fault asserts if either IDAC value is faulted

(Chn_idac[7:0] = 8’h00 or 8’hff)

1 = The associated channel has faulted

and is enabled.

01: Io_gpio_1 = GPIO_1 = Idac_fault_bar.

Idac_fault_bar is the complement of Idac_fault.

The latched faults are set and held

when the associated channel's

instantaneous fault has occured with

faults enabled. Clearing the enable

bit for the associated channel in

FAULT_EN will immediately clear its

corresponding latched fault bit.

10 = GPIO_1 is a general-purpose open-

drain output and mirrors the value written to

Io_gpio_1 (default).

11 = GPIO_1 is a general-purpose digital input

with Io_gpio_1 = GPIO_1

All latched channel faults are cleared

when this register is read. They may

be set again if the instantaneous

fault condition and fault_en have not

changed.

b[4]

b[5]

Io_gpio_0

Io_gpio_1

Io_alertb

See Io_cfg_0.

If the GPIO_CFG pin is pulled-high during a

power on reset, Io_gpio_0 is cleared and the

GPIO_0 open-drain output will assert low.

Fault_la_vdd_uv

Fault_la_v12_ov

See Io_cfg_1.

Fault_la_v12_uv

If the GPIO_CFG pin is pulled-high during a

power on reset, Io_gpio_1 is cleared and the

GPIO_1 open-drain output will assert low.

b[15:14] Reserved

Always Returns 0

b[6]

b[7]

Mirrors the value of the ALERT pin.

Read only.

Io_alertb_enb 1 = ALERT pin never asserts (default).

0 = ALERT pin asserts low when one or more

FAULT_LA bits are set.

b[8]

Io_i2c_adc_

wen

1 = Special test mode that inhibits ADC from

writing to ADC result register and allows user

2

to update registers over the I C serial interface.

0 = Normal operation (default).

b[9]

Io_gpio_cfg

Read only. GPIO_CFG digital input and open-

drain output. Reading this bit returns the

current state of the GPIO_CFG pin voltage.

b[10]

Io_track_start Writing a 1 to this bit will start tracking all

enabled channels. Returns a 1 when tracking

is pending (LTC2970-1). Reserved on

LTC2970 and always returns 0.

b[15:11] Reserved

Always Returns 0

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4. Detailed I C Command Register Descriptions

VDD_ADC, V12_ADC, CH0 _A_ADC, CH0 _B_ADC, CH1_A_ADC,

CH1_B_ADC, and TEMP_ADC: ADC Conversion Result Registers

– Read Only Unless Specified Otherwise

(Cont.)

ADC_MON: ADC Monitoring Mux Control Register – Read/Write

BIT(s)

SYMBOL

OPERATION

BIT(s)

SYMBOL

OPERATION

b[14:0] Vdd_adc[14:0]

V12_adc[14:0]

Measured data from ADC conversion.

b[0]

b[1]

b[2]

b[3]

b[4]

b[5]

b[6]

Adc_mon_vdd

0 = ADC will not convert associated channel.

(Default)

'h4000 corresponds to negative full-scale

input voltage.

Adc_mon_v12

Ch0_a_adc[14:0]

Ch0_b_adc[14:0]

Ch1_a_adc[14:0]

Ch1_b_adc[14:0]

Temp_adc[14:0]

'h0000 corresponds to 0V.

1 = ADC will continuously convert associated

channel.

Adc_mon_ch0_a

Adc_mon_ch0_b

Adc_mon_ch1_a

Adc_mon_ch1_b

Adc_mon_temp

'h3fff corresponds to full-scale input voltage.

12V is divided by 3 before being measured

IN

by the ADC.

2’s complement format, b[14] = sign.

Read/Write when Io_i2c_adc_wen = 1.

Default value is undefined.

b[15:7] Reserved

Always Returns 0

b[15]

Vdd_adc_new

1 = The ADC has updated the associated

result register since the last time the data

was read.

SYNC: Tracking Synchronization Control Register – Read/Write

LTC2970 -1 Only

V12_adc_new

Ch0_a_adc_new

Ch0_b_adc_new

Ch1_a_adc_new

Ch1_b_adc_new

Temp_adc_new

0 = Previously read data. (Default)

BIT(s)

SYMBOL

OPERATION

b[0]

Sync_track

Write

0 = Do not synchronize.

1 = Synchronize all tracking enabled

registers to the same starting point.

Read

VDD_OV, V12_OV, CH0 _A_OV, CH0 _B_OV, CH1_A_OV, CH1_B_

OV: Over Voltage Limit Registers – Read/Write

0 = The LTC2970-1 is not synchronized for

tracking (default).

1 = The LTC2970-1 is synchronized for

tracking.

BIT(s)

SYMBOL

OPERATION

b[14:0] Vdd_ov[14:0]

V12_ov[14:0]

ADC overvoltage threshold limit.

Use of the global address will allow

The associated instantaneous over voltage

fault is asserted if the channel’s ADC result

is greater than this limit. Code 'h3fff disables

OV threshold detect feature for that channel.

the synchronization status of multiple

LTC2970-1s to be verified in a single read;

since a one can only be returned if all

LTC2970-1s are synchronized. The IO_track_

start command may then be issued with the

same global address to begin synchronized

tracking across multiple ICs.

Ch0_a_ov[14:0]

Ch0_b_ov[14:0]

Ch1_a_ov[14:0]

Ch1_b_ov[14:0]

12V is divided by 3 before being measured

IN

by the ADC.

2’s complement format, b[14] = sign.

Default value is undefined.

Always Returns 0

b[15:1] Reserved

Always Returns 0

b[15]

Reserved

VDD_UV, V12_UV, CH0 _A_UV, CH0 _B_UV, CH1_A_UV, CH1_B_

UV: Under Voltage Limit Registers – Read/Write

BIT(s)

SYMBOL

OPERATION

b[14:0] Vdd_uv[14:0]

V12_uv[14:0]

ADC undervoltage threshold limit.

The associated instantaneous under voltage

fault is asserted if the channel’s ADC result is

greater than this limit. Code 'h4000 disables

UV threshold detect feature for that channel.

Ch0_a_uv[14:0]

Ch0_b_uv[14:0]

Ch1_a_uv[14:0]

Ch1_b_uv[14:0]

12V is divided by 3 before being measured

IN

by the ADC.

2’s complement format, b[14] = sign.

Default value is undefined.

Always Returns 0

b[15]

Reserved

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4. Detailed I C Command Register Descriptions

b[10]

Ch0_a_idac_pol

Ch1_a_idac_pol

0 = Use this setting when increasing

causes (VINn_AP-VINn_AM)

to decrease. Inverting configuration

common to DC/DC converters with

external feedback networks.

V

OUTn

(Cont.)

CH0 _A_SERVO, CH1_A_SERVO: Voltage Servo Control

Registers – Read/Write

1 = Use this setting when increasing

BIT(s)

SYMBOL

OPERATION

V

causes

OUTn

b[14:0] Ch0_a_servo[14:0]

Ch1_a_servo[14:0]

During servo operation

(VINn_AP-VINn_AM) to increase.

Non-inverting configuration

common to DC/DC converters with

trim pins.

Chn_a_idac[7:0] output current is

stepped to force Chn_a_adc[14:0]

code to equal target code stored in

Chn_a_servo[14:0].

b[11]

Ch0_a_idac_servo_repeat 0 = During servo operation, servo

Chn_a until the measured result is

stable and matches the target code.

2’s complement format, b[14] = sign

Default value is undefined.

Ch1_a_idac_servo_repeat

1 = During servo operation,

continuously servo Chn_a to the

target code.

b[15]

Ch0_a_servo_en

Ch1_a_servo_en

0 = Chn_a servo disabled (default).

1 = Chn_a servo enabled.

b[15:12] Reserved

Always Returns 0

CH0 _A_IDAC, CH1_A_IDAC: IDAC Control/Data Registers –

Read/Write

CH0 _A_IDAC_TRACK and CH1_A_IDAC_TRACK: IDAC Tracking

data and control registers – Read/Write

LTC2970 -1 Only

BIT(s)

SYMBOL

OPERATION

b[7:0]

Ch0_a_idac[7:0]

Ch1_a_idac[7:0]

Ch0_a_idac_en

Ch1_a_idac_en

Chn_a IDAC data value.

BIT(s)

SYMBOL

OPERATION

b[7:0]

Ch0_a_idac_

track[7:0]

Final target value for of Chn_a_

idac[7:0]. During tracking, Chn_a_

idac[7:0] is incremented/decremented

by 1 until it is equal to this value.

b[8]

0 = V

1 = V

output tri-stated.

output enabled.

OUTn

Ch1_a_idac_

track[7:0]

There are two ways to enable V

1) When Chn_a_idac_en is set

high with Chn_a_idac_con low,

the LTC2970 will perform a soft

connect. During a soft connect,

.

OUTn

b[8]

Ch0_a_idac_track_en 0 = inhibit tracking of Chn_a_idac[7:0].

Ch1_a_idac_track_en 1 = enable tracking of Chn_a_idac[7:0]

b[15:9] Reserved

Always Returns 0

the V

voltage buffer output

OUTn

will not be connected to the V

OUTn

pin until the internal algorithm has

CH0 _A_DELAY_TRACK and CH1_A_DELAY_TRACK: IDAC

Tracking delay register – Read/Write

LTC2970 -1 Only

servo’d the voltage at the IDACn

pin to match the V

pin voltage.

OUTn

Resolution is one Chn_a_idac LSB.

BIT(s)

SYMBOL

OPERATION

2) When Chn_a_idac_en is enabled

with Chn_a_idac_con high, the

LTC2970 will perform a hard

b[9:0]

Ch0_a_delay_track[9:0] Delay used to synchronize or offset

tracking events.

Ch1_a_delay_track[9:0]

connect. The V

voltage buffer

OUTn

b[1510] Reserved

Always Returns 0

will be immediately connected to the

V

pin.

OUTn

b[9]

Ch0_a_idac_con

Ch1_a_idac_con

0 = V

is not enabled or

OUTn

has been enabled but is not yet

connected to the output of the CHn

voltage buffer. (Default)

1 = V

is enabled and has been

OUTn

connected to the output of the CHn

voltage buffer.

See Chn_a_idac_en for additional

information.

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5. Soft Connecting the LTC2970 to the Power Supply

onthatchannelorthepreviouslyissuedsoftconnectfailed

with an IDAC fault (Fault_chn_a_idac = 1). Recall that the

Chn_a_idac_en bit must initially have been set to 0.

Feedback Node

The soft connect feature allows the LTC2970 to connect to

thepowersupply’sfeedbacknodewithminimaldisturbance

to the supply’s output voltage. This is accomplished by

LTC2970-1 Only: Soft connect requests will be ignored

and the user will not be able to change Chn_a_idac_pol or

Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0

or GPIO_1 are high.

comparing the buffered voltage of I

to the voltage at

OUTn

V

OUTn

andincrementingordecrementingChn_a_idac[7:0]

until the comparator output (COMPn) changes. The value

ofChn_a_idac[7:0]whenthecomparatortransitionsisthe

appropriate value for a soft connect. The voltage buffer

LTC2970-1Only:Softconnectrequestswillbeignoredand

the user will not be able to change the Chn_a_idac_pol bit

if there is a pending tracking operation.

output is only connected to V

if the IDAC reaches this

OUTn

soft connect value without generating an instantaneous

6. Hard Connecting the LTC2970 to the Power Supply

Trim Pin

IDAC fault (Fault_chn_a_idac).

Soft-Connect Procedure:

ThehardconnectfeatureallowstheLTC2970tobypassthe

soft connect algorithm and connect directly to the power

supply’s feedback node using the value programmed into

Chn_a_idac[7:0]. This feature is useful for systems that

havecalculatedormeasuredanacceptablevoltageatwhich

Determine the appropriate polarity for Chn_a_idac_pol.

Select Chn_a_idac_pol = 1 if incrementing V

differential voltage (VINn_AP – VINn_AM) to increase.

Whenproperlyprogrammed,loweringthevalueinChn_a_

idac[7:0] will always cause the output of the controlled

power supply to decrease.

causes

OUTn

to connect the IDAC’s buffered voltage V

to V

.

BUFn

OUTn

Hard Connect Procedure:

Ensure that the channel’s IDAC is not currently enabled

for connection, i.e., the Chn_a_idac_en bit must be 0.

Determine the appropriate polarity for Chn_a_idac_pol.

Select Chn_a_idac_pol = 1 if incrementing V causes

OUTn

(VINn_AP – VINn_AP) to increase. When properly pro-

grammed,loweringthevalueintheIDACwillalwayscause

the output of the controlled power supply to decrease.

UpdateCHn_A_IDAC()withChn_a_idac_pol,Chn_a_idac_

con = 0, Chn_a_idac_en = 1, and Chn_a_idac[7:0] = 0x80.

The value programmed into Chn_a_idac[7:0] is ignored

and Chn_a_idac[7:0] is initially set to 8’h80.

Determine the value for Chn_a_idac[7:0]. The values ‘h00

or ‘hff are allowed, but they will trip the IDAC’s fault bit

(Fault_chn_a_idac = 1).

The LTC2970 will now ramp Chn_a_idac[7:0] while

monitoring the output of the soft connect comparator. If

thesoftconnectcomparatortrips,theLTC2970willconnect

When the IDAC is already connected, the value Chn_a_

idac[7:0] and Chn_a_idac_pol will be programmed into

the IDAC provided all other conditions are met. See “Pro-

grammingaPreviouslyConnectedCurrentDAC”fordetails

theoutputofV

toV

andsetChn_a_idac_conhigh.

BUFn

OUTn

If the soft connect comparator does not trip before the

IDAC value reaches ‘h00 or ‘hFF, then the soft connection

willfail,anIDACfaultwillbeindicated(Fault_chn_a_idac),

and Chn_a_idac_con will remain low.

Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_

idac_con = 1, Chn_a_idac_en = 1, and Chn_a_idac[7:0].

Soft-Connect Rules:

Hard Connect Rules:

When both channels are requesting a soft connect, chan-

nel 0 has priority.

Hardconnectrequestswillbeignoredandtheuserwillnot

be able to change Chn_a_idac_pol, Chn_a_idac_con or

Chn_a_idac[7:0] if the LTC2970 is servicing a previously

issuedsoftconnectonthatchannelorthepreviouslyissued

Soft connect requests will be ignored and the user will not

be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if

the LTC2970 is servicing a previously issued soft connect

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soft connect failed with an IDAC fault (Fault_chn_a_idac =

1).Recallthatanewhardconnectionrequirestheprevious

value of Chn_a_idac_en = 0.

8. Disconnecting the LTC2970 from the Power Supply

Trim Pin

V

OUTn

can be placed in a high impedance state simply by

LTC2970-1 Only: Hard connect requests will be ignored

and the user will not be able to change Chn_a_idac_pol,

Chn_a_idac_con or Chn_a_idac[7:0] if GPIO_CFG is high

and either GPIO_0 or GPIO_1 are high.

clearing the Chn_a_idac_en bit. In order to minimize the

resulting disturbance to the power supply voltage, the

IDAC code should not be changed from its current value

when clearing the Chn_a_idac_en bit. This is not an issue

if the channel’s associated servo_en bit is high.

LTC2970-1Only:Hardconnectrequestswillbeignoredand

theuserwillnotbeabletochangeChn_a_idac_pol,Chn_a_

idac_con or Chn_a_idac[7:0] if there is a pending tracking

operation.

Disconnect Procedure:

Update CHn_IDAC() with Chn_a_idac_en set low.

The LTC2970 will immediately disconnect the buffered

7. Programming a Previously Connected IDAC

I

from V

.

OUTn

The LTC2970 IDAC’s may be programmed after they have

been connected with a soft connect or a hard connect

provided a servo operation is not enabled on the associ-

ated channel.

Disconnect Rules:

Clearing Chn_a_idac_con with Chn_a_idac_en high will

not disconnect the IDAC. Only setting Chn_a_idac_en low

will clear Chn_a_idac_con.

Procedure:

LTC2970-1 Only: Chn_a_idac_en may not be changed if

the feedback node connection is configured for tracking.

Tracking is enabled when GPIO_CFG is high and either

GPIO_0 or GPIO_1 are high.

Determine the value for Chn_a_idac[7:0]. The values

‘h00 or ‘hff are allowed, but will trip the IDAC’s fault bit

(Fault_chn_a_idac = 1).

Verify that the IDAC is already connected, and that

Chn_a_idac_con is high.

9. Tracking Power Supplies Overview (LTC2970 -1

Only)

Ensure that servo mode is not enabled for the channel

being programmed. Chn_a_servo_en must be low. This

requirement prevents the user from interfering with a

previously requested servo operation.

2

The LTC2970-1 tracking feature allows the I C interface

to initiate a controlled power up or power down of two

or more supplies (Figure 2 shows a typical LTC2970-1

application circuit). Multiple LTC2970-1’s with different

addresses may be simultaneously programmed using

the LTC2970 group address and the SYNC() command.

Tracking is enabled when GPIO_CFG is pulled high and

either GPIO_0 or GPIO_1 are high.

Update the CHn_A_IDAC() register with Chn_a_idac_pol,

Chn_a_idac_con = 1, Chn_a_idac_en = 1, and Chn_a_

idac[7:0].

Note: Care should be taken to preserve the current value

of the Chn_a_idac_pol bit, since the LTC2970 does not

prevent the user from changing this value when writing

to the IDAC control registers.

10 . Tracking Power Supplies On (LTC2970 -1 Only)

2

The LTC2970-1 tracking feature allows the I C to initiate

a controlled power up of two or more supplies.

Rules:

Procedure: This procedure describes all the steps neces-

sary to track up two or more power supplies. Steps that

require I C interaction are prefixed with the required I C

command function.

Setting Chn_a_idac_con to zero will not disconnect the

DAC unless Chn_a_idac_en is also set low.

2

All Hard Connect rules apply.

Power-up the LTC2970-1 with GPIO_CFG pulled high.

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This causes open-drain outputs GPIO_1 and GPIO_0 to

automatically pull the power supplies’ run/soft-start pins

to ground.

Power-Up Tracking Rules:

TrackingcannotbeginifChn_a_idac_conisnotconnected.

This condition is met when the previous procedure is

followed.

CHn_A_IDAC(): Hard connect Chn_a_idac[7:0] with a

value that forces the power supplies off when GPIO_CFG

=1. VerifythatChn_a_idac_polisattheappropriatevalue.

Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_

idac[7:0] updates will be ignored after IO(Io_track_start)

isasserteduntiltrackingiscompleteorwhenevertracking

is pending, i.e., GPIO_CFG pulled high with either GPIO_0

or GPIO_1 asserted pulled high.

CHn_A_IDAC_TRACK(): Set Chn_a_idac_track_en = 1,

and set the Chn_a_idac_track[7:0] target value to the

code that causes V

to most closely approximate the

OUTn

corresponding power supply’s feedback node voltage

when it is in regulation.

11. Tracking Power Supplies Off (LTC2970 -1 Only)

2

The LTC2970-1 tracking feature allows the I C to initiate

CHn_A_DELAY_TRACK(): Set the value by which the

incrementing of IDACn should be delayed with respect

to the start of tracking event. This controls whether the

power supplies track up coincidentally or sequentially.

a controlled power down of two or more supplies.

Procedure: This procedure describes all steps necessary

to track down two or more power supplies. Steps that

2

require I C interaction are prefixed with the required I C

command function.

IO(): Release the run/soft-start pins by programming

io_gpio_n = 1. This will enable the power supplies without

allowing their outputs to move since these are held low

by Chn_a_idac[7:0]. Wait until power supplies have had

sufficient time to start running before starting tracking.

CHn_IDAC(): Disable the IDAC’s for each tracking enabled

channel (Chn_a_idac_en = 0). Ensure Chn_a_idac_pol is

at the appropriate value.

SYNC():OptionalcommandthatallowsmultipleLTC2970-

1’s to be synchronized for tracking. Writing Sync_track

= 1 will allow the LTC2970-1 to finish its current ADC

conversion before having it wait to receive io_track_start

= 1. The LTC2970-1 will timeout this wait command after

CHn_IDAC_TRACK(): Select the channels to be tracked

by setting Chn_a_idac_track_en = 1, and set the target

value for each Chn_a_idac_track[7:0] to that which forces

the supply off.

CHn_A_DELAY_TRACK(): Set the value by which the

decrementing of that channel’s DAC should be delayed

with respect to the start of the tracking event. This con-

trols whether the supplies track down coincidentally or

sequentially.

t

. Reading back Sync_track = 1 using the

TIMEOUT_SYNC

globaladdresswillensureallLTC2970-1’saresynchronized

before proceeding with the tracking operation.

IO(): Set Io_track_start = 1 and keep the run/soft-start

2

pinsenabled.UsetheglobalI Caddresstosimultaneously

SYNC():OptionalcommandthatallowsmultipleLTC2970-

1’s to be synchronized for tracking. Writing Sync_track

= 1 will allow the LTC2970-1 to finish its current ADC

conversion before having it wait to receive io_track_start

= 1. The LTC2970-1 will timeout this wait command after

track up power supplies across multiple LTC2970-1’s.

LTC2970-1 response: For each tracking enabled channel,

the LTC2970-1 will decrement the CHn_A_delay_track

counter at a rate of t

. As soon as a channel’s

DEC_TRACK

tracking counter reaches zero, the LTC2970-1 will begin

stepping the value of Chn_a_idac[7:0] by one count until

thefinalvalueofChn_a_idac_track[7:0]isreached,atwhich

point Chn_a_idac_track_en is de-asserted. When the final

value is reached for all channels, GPIO_CFG is asserted

t

. Reading back Sync_track = 1 using the

TIMEOUT_SYNC

global address will ensure all LTC2970’s are synchronized

before proceeding with the tracking operation.

2

IO(): Set Io_track_start = 1. Use the global I C address to

simultaneouslytrackdownpowersuppliesacrossmultiple

LTC2970’s.

low. After a time delay of t , Chn_a_idac_en is

HOLD_TRACK

de-asserted.

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LTC2970-1response:Eachtrackingenabledchannelissoft

connected. The GPIO_CFG pin is released allowing it to be

Determine the target servo voltage, Chn_a_servo[14:0].

Update CHn_A_SERVO() with Chn_a_servo_en = 1, and

Chn_a_servo[14:0].

pulled high. The LTC2970-1 waits t

to allow

SETUP_TRACK

GPIO_CFG to settle. For each tracking enabled channel,

Update CHn_A_IDAC() with Chn_a_idac_servo_repeat =

1. This step may be skipped if Chn_a_idac_servo_repeat

was set high during the soft or hard connect procedure.

the Chn_a_delay_track counter is decremented at a rate

of t . As soon as a channel’s tracking counter

DEC_TRACK

reaches zero, the LTC2970-1 will begin stepping the value

of Chn_a_idac[7:0] by one count until the final value of

Chn_a_idac_track[7:0]isreached.Thetrackingenablebitis

thenclearedforbothchannels(Chn_a_idac_track_en=0).

LTC2970 response: The LTC2970 will continuously

increment, decrement or hold Chn_a_idac[7:0] in order

to match the measured value of (VINn_AP-VINn_AM) to

Chn_a_servo[14:0].

2

IO(): The I C interface may then be used to set GPIO_1

and GPIO_0 low, disabling the power supplies.

Whenever the CHn_A_SERVO() register is updated an

internalflagisclearedindicatingthatasuccessfulservohas

notbeencompleted.Thisinternalflag,Chn_a_servo_done,

initially causes the ADC to operate in an accelerated 12-bit

mode. Once the channel reaches the servo target, the ADC

switches back to 14-bit mode for two conversions before

asserting Chn_a_servo_done high.

Power Down Tracking Rules:

Power down tracking requests will be ignored until the

user has disabled the IDAC’s by setting Chn_a_idac_en

= 0 for each tracking enabled channel.

Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_

idac[7:0]updateswillbeignoredafterIO(IO_track_start)is

asserted until tracking is complete and whenever tracking

range is configured; (GPIO_CFG high with either GPIO_0

or GPIO_1 asserted high).

IncontinuousvoltageservomodetheChn_a_servo_done

flags allow the initial servo target to be reached quickly.

During this time, ADC conversions for all non-servo chan-

nels are temporarily inhibited.

12. Continuous Power Supply Voltage Servo

Rules:

The continuous voltage servo feature allows the LTC2970

to servo an external power supply to a programmed

value. The voltage of the external supply is monitored

over Chn_A_ADC and compared to a target value stored

in Chn_a_servo. After each conversion, Chn_A_IDAC is

incremented by 1, decremented by 1, or held; whichever

brings or keeps the measured voltage closer to the tar-

geted servo value.

The IDAC associated with the servo channel must be

enabled. If Chn_a_idac_en is low the servo enable bit

Chn_a_servo_en is always forced low.

The IDAC associated with the servo channel must be

connected (Chn_a_idac_con = 1).

AnIDACfaultmaybegeneratedduringacontinuousservo

operation. The LTC2970 will report the fault and continue

trying to servo that channel.

Procedure:

LTC2970-1 Only: There must be no pending tracking

commands. A pending tracking command will clear

Chn_a_servo_en.

Follow procedure for hard connecting or soft connecting

the LTC2970 to power supply trim pin; when updating

CHn_A_IDAC(), Chn_a_idac_servo_repeat should be

asserted high. The servo channel’s IDAC must be enabled

before Chn_A_servo_en can be set high.

LTC2970-1 Only: The tracking range must not be enabled;

(GPIO_CFG high with either GPIO_0 or GPIO_1 asserted

high).AnenabledtrackingrangewillclearChn_a_servo_en

low.

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13. One Time Power Supply Voltage Servo

Procedure:

The one time voltage servo feature allows the LTC2970 to

servo an external power supply to a programmed value

and then stop updating the IDAC once the target value

has been reached.

Follow procedure outlined for “One Time Power Supply

Voltage Servo”.

Update FAULT_EN() with Fault_en_chn_a_servo = 1.

Enable detection of the appropriate instantaneous faults

for all servo channels; see “Generating and Monitoring

Instantaneous Faults”.

Procedure:

Follow procedure for hard connecting or soft connecting

the LTC2970 to power supply trim pin; when updating

CHn_A_IDAC(), Chn_a_idac_servo_repeat should be de-

asserted low. The servo channel’s IDAC must be enabled

before Chn_a_servo_en may be set high.

LTC2970 response: Any time an instantaneous

undervoltage or overvoltage fault is detected on the servo

channel(Fault_ov_a_chnorFault_uv_a_chn), theinternal

Chn_a_servo_done flag for that channel is cleared, and

the LTC2970 will perform a complete one time servo. This

allows the LTC2970 to precisely restore the power supply

to the target servo value, after it has drifted beyond a user

defined operating window.

Update CHn_A_IDAC() with Chn_a_idac_servo_repeat =

0. This step may be skipped if Chn_a_idac_servo_repeat

wasclearedlowduringthesoftorhardconnectprocedure.

Update FAULT_EN() with Fault_en_chn_a_servo = 0. This

prevents the LTC2970 from reinitiating a servo after an

overvoltage or undervoltage fault.

Rules:

All “Continuous Power Supply Voltage Servo” rules

apply.

Determine the target servo voltage, Chn_a_servo[14:0].

Update CHn_A_SERVO() register with Chn_a_servo_en

= 1, and Chn_a_servo[14:0].

During a permanent undervoltage or overvoltage fault

the LTC2970 will continuously try to correct the faulted

channel, after each failed attempt all other channels that

need monitoring by the ADC will be serviced.

LTC2970response:TheLTC2970willincrement,decrement

or hold Chn_a_idac[7:0] in order to match the measured

value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. The

servo procedure will end when the internal Chn_a_servo_

done flag is set (see “Continuous Power Supply Voltage

Servo”). At this point the IDAC is either programmed to

the appropriate servo value or faulted.

15. Configuring ADC to Monitor Input Channels and

Internal Temperature Sensor

The LTC2970 is able to perform ADC conversions on any

combination of seven different input channels. A channel

is converted if its associated ADC_MON() bit is set high.

Refer to Table 7 for details.

Rules:

All “Continuous Power Supply Voltage Servo” rules

apply.

Procedure:

Update ADC_MON() with the control bit of each channel

that is to be monitored set high.

14. One Time Power Supply Voltage Servo with

Repeat On Fault

LTC2970response:Allenabledchannelswillbesequentially

converted.Theresultofthemostrecentconversionmaybe

read from the ADC result register. Each time a conversion

is completed the new data bit associated with the result

register is asserted high. The new data bit is reset each

The LTC2970 one time voltage servo feature may be

modified to allow the LTC2970 to perform an additional

power supply servo operation after an undervoltage or

overvoltage fault is detected on the servo channel.

29701fe

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LTC2970/LTC2970-1

operaTion

Table 7. LTC2970 ADC Conversion and Fault Limit Registers

INPUT CHANNEL

ADC_MON()

CONTROL BIT

ADC RESULT REGISTER

(2s COMPLEMENT)

OV FAULT REGISTER

(2s COMPLEMENT)

UV FAULT REGISTER

(2s COMPLEMENT)

TEMPERATURE

VIN1_BP-VIN1_BM

VIN1_AP-VIN1_AM

VIN0_BP-VIN0_BM

VIN0_AP-VIN0_AM

12VIN

Adc_mon_temp

Adc_mon_b_ch1

Adc_mon_a_ch1

Adc_mon_b_ch0

Adc_mon_a_ch0

Adc_mon_v12

Temp_adc[14:0]

Ch1_b_adc[14:0]

Ch1_a_adc[14:0]

Ch0_b_adc[14:0]

Ch0_a_adc[14:0]

V12_adc[14:0]

-

Ch1_b_ov[14:0]

Ch1_a_ov[14:0]

Ch0_b_ov[14:0]

Ch0_a_ov[14:0]

V12_ov[14:0]

Vdd_ov[14:0]

Ch1_b_uv[14:0]

Ch1_a_uv[14:0]

Ch0_b_uv[14:0]

Ch0_a_uv[14:0]

V12_uv[14:0]

Vdd_uv[14:0]

VDD

Adc_mon_vdd

Vdd_adc[14:0]

time the result register is read. This provides a simple

mechanismforsupervisorysoftwaretodetermineifanew

conversion has been completed since data was last read.

16. Generating and Monitoring Instantaneous Faults

The LTC2970 supports fourteen different types of

instantaneous faults. These faults together with the

conditions that trigger them are defined in Table 8. There

are six undervoltage faults, six overvoltage faults and two

IDAC limit faults. The FAULT() command may be used to

read the status of all instantaneous fault bits. The IO()

command may be used to configure GPIO_0 and GPIO_1

toviewvoltagelimitandIDACfaultsrespectively.Thestate

of GPIO_0 and GPIO_1 may be read using IO().

Rules:

The LTC2970 assigns priority to ADC conversions of

CH1_A_ADC and CH0_A_ADC when these channels are

in their initial fast servo mode.

The IO() register control bit Io_i2c_adc_wen must be low

in order for ADC conversions to be performed.

LTC2970-1 Only: ADC conversions are suspended during

any pending tracking requests.

Table 8. LTC2970 Fault Reporting Bits and Conditions

CONDITION THAT GENERATES AN

INSTANTANEOUS FAULT

FAULT()

FAULT_EN()

FAULT_LA()

INSTANTANEOUS FAULT REPORTING ENABLE FOR LATCHED FAULT REPORTING LATCHED FAULT REPORTING

V12_adc[14:0] < V12_uv[14:0]

V12_adc[14:0] > V12_ov[14:0]

Vdd_adc[14:0] < Vdd_uv[14:0]

Vdd_adc[14:0] > Vdd_ov[14:0]

Ch1_b_adc[14:0] < Ch1_b_uv[14:0]

Ch1_b_adc[14:0] > Ch1_b_ov[14:0]

Idac_a_ch1[7:0] = 8’ff or 8’h00

Ch1_a_adc[14:0] < Ch1_a_uv[14:0]

Ch1_a_adc[14:0] > Ch1_a_ov[14:0]

Ch0_b_adc[14:0] < Ch0_b_uv[14:0]

Ch0_b_adc[14:0] > Ch0_b_ov[14:0]

Idac_a_ch0[7:0] = 8’ff or 8’h00

Ch0_a_adc[14:0] < Ch0_a_uv[14:0]

Ch0_a_adc[14:0] > Ch0_a_ov[14:0]

Fault_v12_uv

Fault_v12_ov

Fault_en_v12_uv

Fault_en_v12_ov

Fault_la_v12_uv

Fault_la_v12_ov

Fault_vdd_uv

Fault_en_vdd_uv

Fault_la_vdd_uv

Fault_vdd_ov

Fault_en_vdd_ov

Fault_la_vdd_ov

Fault_ch1_b_uv

Fault_ch1_b_ov

Fault_ch1_a_idac

Fault_ch1_a_uv

Fault_ch1_a_ov

Fault_ch0_b_uv

Fault_ch0_b_ov

Fault_ch0_a_idac

Fault_ch0_a_uv

Fault_ch0_a_ov

Fault_en_ch1_b_uv

Fault_en_ch1_b_ov

Fault_en_ch1_a_idac

Fault_en_ch1_a_uv

Fault_en_ch1_a_ov

Fault_en_ch0_b_uv

Fault_en_ch0_b_ov

Fault_en_ch0_a_idac

Fault_en_ch0_a_uv

Fault_en_ch0_a_ov

Fault_la_ch1_b_uv

Fault_la_ch1_b_ov

Fault_la_ch1_a_idac

Fault_la_ch1_a_uv

Fault_la_ch1_a_ov

Fault_la_ch0_b_uv

Fault_la_ch0_b_ov

Fault_la_ch0_a_idac

Fault_la_ch0_a_uv

Fault_la_ch0_a_ov

29701fe

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For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

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Procedure:

Instantaneous Ch0_a and Ch1_a faults may be used to

trigger a servo on fault event.

Update the overvoltage limit register with the value above

which the ADC result should generate an overvoltage

fault. Instantaneous overvoltage faults are updated after

each ADC conversion. They are asserted high when the

ADC result is greater than the overvoltage limit. They

are cleared if the ADC result is less than or equal to the

overvoltage limit. Setting the overvoltage limit to 14’h3fff

inhibits instantaneous faults for the associated channel.

Overvoltage and undervoltage faults require that the

associated ADC_MON control bit be asserted high for

instantaneous fault detection to be updated.

17. Generating and Monitoring Latched Faults

TheLTC2970isabletoselectivelylatchinstantaneousfaults

inthelatchedfaultregisterFAULT_LA.Eachinstantaneous

fault has an associated latched fault bit in FAULT_LA and

a fault enable bit in FAULT_EN; (see Table 8) for details.

When an instantaneous fault enable bit is high, any event

that sets the instantaneous fault will simultaneously set

the latched fault. The latched fault will remain set even if

conditions permit the instantaneous fault to be cleared.

The latched faults are immediately cleared whenever the

associated fault enable bit is cleared. All latched faults are

also cleared when the latched fault register is read over

FAULT_LA().

Updatetheundervoltagelimitregisterwiththevaluebelow

which the ADC result should generate an undervoltage

fault. Instantaneous undervoltage faults are updated after

each ADC conversion. They are asserted high when the

ADC result is less than the undervoltage limit. They are

cleared if the ADC result is greater than or equal to the un-

dervoltage limit. Setting the overvoltage limit to 14’h4000

inhibits instantaneous faults for the associated channel.

UpdateADC_MON()controlbitstoallowADCconversions

on all channels that are to be monitored for over and under

voltage limits. Instantaneous IDAC faults are polled after

all ADC conversions are completed and set when the as-

sociated IDAC registers are at ‘h00 of ‘hff.

The FAULT_INDEX() command may be read to determine

ifanylatchedfaultsareasserted.ReadingFAULT_INDEX()

doesnotclearlatchedfaults.TheALERToutputmayalsobe

configuredtoviewwhetheranylatchedfaultsareasserted.

Read FAULT() to view the value of all instantaneous faults.

Procedure:

The IO(Io_cfg_0) command may be used to configure

the GPIO_0 pin to output the internal Power_good flag.

Power_goodisassertedhighiftherearenoinstantaneous

overvoltage or undervoltage faults. IO() may be used to

read the value of Power_good through io_gpio_0.

Follow procedure for generating instantaneous faults.

Write FAULT_EN() to enable any combination of latched

faults.

Read FAULT_INDEX() to determine if any latched faults

are asserted without clearing latched faults.

The IO(Io_cfg_1) command may be used to configure the

GPIO_1pintooutputtheinternalIdac_faultflag.Idac_fault

is asserted high if either IDAC value is faulted. IO() may

be used to read the value of Idac_fault through io_gpio_1.

Read FAULT_LA() to monitor all latched faults. Reading

FAULT_LA() will clear all latched faults. These will remain

clear until the next time the LTC2970 polls and sets an

associated instantaneous fault.

Rules:

The overvoltage and undervoltage limits must be initial-

ized; they do not have a default value.

Setting IO(Io_alert_enb) low will cause ALERT to be as-

serted low whenever any one of the fourteen latched faults

is asserted high. The value of the ALERT pin may also be

read through IO(Alertb).

Allovervoltagelimits,undervoltagelimitsandADCresults

use 2’s complement notation with bit position [14] of

register [14:0] being used for the sign.

29701fe

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For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

operaTion

Rules:

ThepoweronresetconfigurationsforGPIO_0andGPIO_1

are output pins with a value equal to the complement of

the GPIO_CFG level.

See “Generating and Monitoring Instantaneous Faults”.

18. General Purpose Input/Output Pins

The GPIO_0 and GPIO_1 may be used to: (1) monitor

instantaneous faults (see “Generating and Monitoring

Instantaneous faults”); (2) control switcher run/start pins

duringtracking(see“TrackingPowerSuppliesOverview”);

or (3) provide general purpose input/output pins.

19. Advanced Development Features

The internal ADC may be disabled with the ADC result reg-

2

isters accepting written I C data. This feature allows faults

to be generated for diagnostic purposes, without having

to generate an actual overvoltage or undervoltage event.

Procedure:

To program GPIO_n as an open drain output set Io_cfg_n

= 2’b10. The value written to lo_gpio_n will be output

over GPIO_n.

SetIO(Io_i2c_adc_wen)hightoenableADCresultregister

writes and disable internal ADC updates.

Rules:

To program GPIO_n as an input set Io_cfg_n = 2’b11. The

value of GPIO_n may now be read through lo_gpio_n.

Io_i2c_adc_wen must be clear for normal operation.

applicaTions inForMaTion

Margining DC/DC Converters with External Feedback

Resistors

8V TO 15V

0.1µF

V

IN

R50

V

DD

IN

OUT

IN

Figure 1 shows a typical application circuit for margining

a power supply with an external feedback network. The

1/2 LTC2970

0.1µF

GPIO_CFG

+

I

V

IN0_BP

IN0_BM

OUT0

V

and V

differential inputs sense the load

IN0_AP

IN0_AM

–

I

ALERT

SCL

DC/DC

2

voltagedirectly,anddifferentialinputsV

andV

IN0_BM

I C BUS

IN0_BP

CONVERTER

R30

SDA

are connected across load current sense resistor R50. A

correctionvoltageisdevelopedattheI pinbysourcing

V

I

IN0_AP

R20

R10

+

V

–

OUT0

RUN/SS FB

GPIO_0

REF

LOAD

OUT0

DC0

IDAC0’scurrentintoresistorR40.R40isKelvinconnected

R40

V

SGND

GND

IN0_AM

to the point-of-load GND in order to isolate V from

IOUT0

GND ASEL0 ASEL1

0.1µF

ground bounce due to load current changes. V

is

IOUT0

replicatedatV

byanon-chip,unity-gainvoltagebuffer.

OUT0

29701 F01

V

isthenconnectedtothefeedbacknodeofthepower

OUT0

supply through resistor R30. The feedback node can be

Figure 1. Typical LTC2970 Application Circuit for

DC/DC Converters with External Feedback Resistors

isolated from the DAC’s correction voltage by placing the

V

pin in high-impedance mode. Since the GPIO_CFG

OUT0

pin is pulled-up to V , the LTC2970’s GPIO_0 pin will

DD

automatically hold the power supply’s RUN/SS pin low

2

after power-up until the I C interface releases it.

29701fe

27

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

4-Step Resistor Selection Procedure for DC/DC

R20

R10

⎛

⎝

⎞

V_DC0,NOM= V • 1+

+I •R20

(4)

(5)

⎜

⎟

⎠

FB

Converters with External Feedback Resistors

The following 4-step procedure should be used to quickly

calculatetheresistorvaluesshownfortheTypicalApplica-

tion Circuit shown in Figure 1.

R20

R30

V

_DC0,MIN≤ V_DC0,NOM

−

•

R40•236μA− V −10mV

(

)

FB0

1. Assume values for feedback resistor R20 and the

nominal DC/DC converter output voltage V

solve for R10.

, and

DC0,NOM

R20

R30

V_DC0,MAX≥ V_DC0,NOM

+

• V −10mV

(6)

(7)

(

)

FB0

V

is the desired output voltage of the DC/DC

DC0,NOM

converter when the LTC2970’s V

pin is in a high

The margining resolution is bounded by:

OUT0

impedance state. V

is the voltage at the converter’s

FB0

R20

feedback node when the loop is in regulation, and I is

•R40•276µA

R30

FB0

V_RES

≤

volts/DAC LSB

the feedback node’s input current.

256

R20•V

V_DC,NOM−I_FB0•R20− V

FB0

R10=

(1)

Margining DC/DC Converters with a TRIM Pin

FB0

Figure2illustratesatypicalapplicationcircuitformargining

the output voltage of a DC/DC converter with a TRIM Pin.

2.SolveforthemaximumvalueofR30thatyieldsthemaxi-

mum required DC/DC converter output voltage V

.

DC0,MAX

TheLTC2970’sV

pinconnectsdirectlytotheTRIMpin

OUT0

When V

is at 0V, the output of the DC/DC converter

through resistor R30 and the I

pin is terminated at the

OUT0

is at its maximum voltage. Note that the 10mV term cor-

responds to the maximum offset voltage of the IDAC 1X

voltage buffer.

converter's point-of-load ground through R40. Resistors

R30 and R40 give this application circuit two degrees of

freedom so that the margin-up and margin-down percent-

ages can be specified independently.

R20• V −10mV

(

)

FB

R30≤

(2)

Following power-up, the LTC2970's V

pin defaults

V_DC,MAX− V_DC,NOM

OUT0

to a high-impedance state. If the soft-connect feature

3. Solve for the minimum value of R40 that’s needed

to yield the minimum required DC/DC converter output

8V TO 15V

voltage V

.

DC0,MIN

0.1µF

12V

IN

The DC/DC converter output voltage will be a minimum

whenIDAC0isatitsfull-scalecurrent.Inordertoguarantee

that R40 is large enough, assume that IDAC0’s full-scale

current is at the data sheet minimum of 236µA.

V

IN

VO+

V

DD

1/2 LTC2970

0.1µF

GPIO_CFG

R30

TRIM

DC/DC

CONVERTER

V

ALERT

SCL

OUT0

2

I C BUS

IN0_AP

SDA

R30

R20

236µA

V

SENSE+

V

_DC,NOM− V_DC,MIN

•

+ V +10mV

FB

(

)

+

V

–

ON/OFF

V

I

GPIO_0

REF

LOAD

OUT0

DC0

R40≥

(3)

R40

V

SENSE–

VO–

IN0_AM

GND ASEL0 ASEL1

0.1µF

4. Re-calculatetheminimum, nominal, andmaximumDC/

DC converter output voltages and the resulting margining

resolution.

29701 F02

Figure 2. LTC2970 Application Circuit for

DC/DC Converters with a TRIM Pin

29701fe

28

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

is used, the LTC2970 will automatically find the IDAC

code that most closely approximates the TRIM pin's

Tracking with the LTC2970 -1

AtypicalLTC2970-1trackingapplicationcircuitisshownin

Figure3(thesequenceofeventsfortrackingaredescribed

insections9and10oftheOperationsection). TheGPIO_0

andGPIO_1pinsaretieddirectlytotheirrespectiveDC/DC

converter RUN/SS pins. Since GPIO_CFG is pulled-up to

open-circuit voltage before enabling V

. Note: The

OUT0

relationship between V

and the converter's output is

TRIM

typically non-inverting, so be sure to set the LTC2970's

CH0_a_idac_polbitto1inordertoallowthevoltageservo

feature to function properly.

V , the LTC2970-1 will automatically hold off the DC/DC

DD

convertersafterpower-upbyassertingopendrainoutputs

GPIO_0 and GPIO_1 low. N-channel FETs Q10/11 and

diodes D10/11 form unidirectional range switches around

resistors R30A/31A while GPIO_CFG is high. These range

DC/DC converters with a TRIM pin are usually margined

high or low by connecting an external resistor between

+

–

the TRIM pin and either the V

or V

pin. The

SENSE

relationships between these resistors and the D% change

in the output voltage of the DC/DC converter are typically

expressed as:

switches allow the LTC2970-1’s V

and V

pins to

OUT0

OUT1

drive the converter outputs all the way to/from ground

through resistors R30B/31B. When GPIO_CFG pulls low,

N-channel FETs Q10 and Q11 will turn off. R30A/31A

and R30B/31B then combine in series for normal margin

operation. The 100k/0.1µF low-pass filter in series with

the gates of Q10/11 minimizes charge injection into the

feedback nodes of the DC/DC converters when GPIO_CFG

pulls low.

R_TRIM•50

(8)

(9)

R_{TRIM_DOWN}

R_TRIM

=

−R_TRIM

D_DOWN

%

_

=

UP

⎡

⎤

R

_TRIM•V • 100+ D

%

UP

(

)

R_TRIM•50

D_UP%

DC

−

−R_TRIM

⎢

⎥

2•V_REF•D_UP

%

⎣

⎦

8V TO 15V

where R

is the resistance looking into the TRIM pin,

TRIM

V

is the TRIM pin's opern-circuit output voltage and

is the DC/DC converter's nominal output voltage.

0.1µF

REF

DC

Δ % and Δ

UP

12V

IN

V

DD

Q10, Q11: 2N7002

D10, D11: MMBD4448V

*SOME DETAILS OMITTED FOR CLARITY

10k

% denote the percentage change in the

0.1µF

DOWN

GPIO_CFG

GPIO_0

converter's output voltage when margining up or down

respectively.

100k

V

IN

RUN/SS IN

D10

DC/DC

LTC2970-1

CONVERTER

2-Step Resistor Selection Procedure for DC/DC

Converters with a TRIM Pin

Q10

R30A

V

FB

OUT

OUT0

DC0

R30B

ALERT

SCL

R20

R10

The following two-step procedure should be used to cal-

culatevaluesforresistorsR30andR40showninFigure 2.

2

I C BUS

I

0.1µF

SDA

R40

1. Solve for R30:

V

GPIO_1

RUN/SS IN

IN

D11

DC/DC

CONVERTER

⎛

⎞

50− D_DOWN

%

R30≤R_TRIM

•

(10)

(11)

Q11

R31A

⎜

⎟

D_DOWN

%

⎝

⎠

V

FB

OUT

OUT1

DC1

R31B

R21

R11

2. Solve for R40:

I

OUT1

GND

R41

⎛

⎞

D_UP

D_DOWN

%

V_REF

29701 F03

R40≥ 1+

•

⎜

⎟

236µA

⎝

⎠

Figure 3. LTC2970 -1 Tracking Application Circuit

29701fe

29

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LTC2970/LTC2970-1

applicaTions inForMaTion

7-Step Procedure for Calculating Tracking Application

Circuit Resistor Values, Counter Delay Values, and

Terminal IDAC Codes

Due to the forward drop of diodes D10 and D11 (0.8V

max), the minimum value for R40 = R41 from expression

(14) may result in small or even negative values of R30

and R31 in Step 4. If this is the case, assume a minimum

allowablevalueforR3nB,andusethefollowingexpression

to calculate the minimum value R40 = R41:

Thefollowing7-stepprocedureshouldbeusedtocalculate

the resistor values, tracking counter delays, and terminal

IDAC codes for the Tracking Application Circuit shown in

Figure 3.

(15)

R40=R41≥

R3nB R3nB

1. Assume a value for R20 and solve for R21.

⎛

⎞

V

• 1+

+

+0.8V+10mV

⎜

⎟

⎠

FBn

⎝

R1n

R2n

236µA

V

is the output voltage of the DC/DC converter

DCn,NOM

whentheLTC2970’sV

pinisinahighimpedancestate.

OUTn

V_DC1,NOM

Note: Use the channel whose parameters yield the maxi-

mum value for R40 = R41.

R21=R20•

(12)

V_DC0,NOM

4. Solve for R30B and R31B.

2. Solve for R10 and R11.

Solve for the upper limits of R30B and R31B and then

determine which resistor value constrains the maximum

value of the other resistor using Equation 17.

R2n

R1n =

(13)

V

⎛

⎞

DCn,NOM

–1

⎜

⎟

V

⎝

⎠

FBn

R4n•236µA− V −0.8V−10mV

(

)

FBn

R3nB≤

(16)

1

⎛

⎞

3. Solve for R40 and R41.

For simplicity, this procedure assumes that R40 = R41.

and V are the maximum and minimum

V

•

+

⎜

⎝

⎟

⎠

FBn

R1n R2n

R30B R31B

=

V

DCn,MAX

DCn,MIN

(17)

converter output margin voltages, respectively.

The value of R40 = R41 is constrained by:

R40=R41≥

R20 R21

5. Solve for R30A and R31A.

(14)

R30A and R31A are constrained by:

⎛

⎜

⎝

⎞

V

_DCn,NOM− V_DCn,MIN

(18)

R3nA ≤

R2n

(

)

⎟

V

•

+1 +10mV

FBn

⎟

⎠

V_DCn,MAX− V_DCn,NOM

(

)

−R3nB

⎛

⎞

V_DCn,MAX− V_DCn,NOM

R2n

R1n

⎛

⎞

236µA

1+

•

⎜

⎝

⎟

⎠

⎜

⎟

V_DCn,NOM

⎝

⎠

29701fe

30

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

6. Solve for Channel 1’s tracking counter delay relative to

Channel 0, CH1_A_DELAY_TRACK().

2. Solve for the value of R30 that yields the maximum

required DC/DC converter output voltage V

DC0,MAX

From Equation 2:

CH1_ A_DELAY_TRACK()=

(19)

R31B

R21

R20• V −10mV

(

)

′

FB

V_DC1,NOM− V_DC0,NOM

•

(

)

R30≤

=

V_DC,MAX− V_DC,NOM

(counts)

1µA /count•R41

10.0kΩ• 0.8V−10mV

(

)

= 7,861Ω

Note: V

′ is based on the final values of R2n and

DCn,NOM

3.63V−2.625V

R1n. If the result for CH1_A_DELAY_TRACK() is less than

0,applytheunsignedresulttotheCH0_A_DELAY_TRACK()

register.

Let R30 = 7.68kΩ.

3.SolveforthevalueofR40that’sneededtoyieldthemini-

mum required DC/DC converter output voltage V

.

7. Solve for the IDAC0 and IDAC1 terminal tracking codes,

DC0,MIN

Chn_a_idac_track[7:0].

From Equation 3:

R30

(20)

Chn_a_idac_ track[7:0]=

V

_DC,NOM− V_DC,MIN

•

+ V

FB

(

)

V

R20

FBn

R40≥

=

255−

(LSB’s)

236µA

1µA /LSB•R4n

7.96kΩ

10kΩ

2.625V−1.62V •

+0.8V

(

)

Note: This formula assumes that the Chn_a_idac_pol bit

is set to 0.

= 6,780Ω

236µA

Margining Application Circuit Design Example

Let R40 = 6.81kΩ.

ConsidertheLTC2970applicationcircuitshowninFigure1.

Channel 0 is a DC/DC converter whose output needs to be

4. Re-calculate the minimum, nominal, and maximum

DC/DC converter output voltages and the resulting mar-

gining resolution.

varied between 3.63V and 1.62V. V = 0.8V and assume

FB0

that I = 0A.

FB0

From Equations 4, 5, and 6:

1. Assume values for feedback resistor R20 and the

R20

R10

nominal DC/DC converter output voltage V , and

DC0,NOM

solve for R10.

⎛

⎝

⎞

V_DC0,NOM= V • 1+

+I •R20=

FB

⎜

⎟

⎠

FB

Let V

= 2.625V (the average of 3.63V and 1.62V)

10kΩ

4.37kΩ

⎛

⎝

⎞

DC0,NOM

0.8V• 1+

= 2.631V

⎜

⎟

⎠

and assume that R20 = 10kΩ. From Equation 1:

R20•V

V_DC,NOM−I_FB0•R20− V

FB0

R20

R30

R10=

=

V

_DC0,MIN< V_DC0,NOM

−

• 236µA•R40− V

FB0

(

)

FB0

10kΩ•0.8V

= 4,384Ω

10kΩ

7.68kΩ

2.625V−0.8V

→ V_DC0,MIN<2.631V−

•

Let R10 = 4.37kΩ (the nearest E192 series resistor value).

236µA•6.81kΩ−0.8V−10mV =1.59V

(

)

29701fe

31

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

Tracking Application Circuit Design Example

R20

V

_DC0,MAX> V_DC0,NOM

+

• V −10mV

(

)

FB0

R30

10kΩ

Consider the LTC2970-1 application circuit shown in

Figure 3. Channel 0 is a 1.8V DC/DC converter while chan-

nel 1 is a 2.5V switching power supply. Both converters

have a feedback node voltage of 0.8V and need to track

on and off coincidentally. In addition, a margin range of

+5% and –10% is required for each supply.

→ V_DC0,MAX>2.631V+

•

7.68kΩ

0.8V−10mV = 3.660V

(

)

FromEquation7,themarginingresolutionwillbelessthan:

1. Assume a value for R20 and solve for R21.

Let R20 = 5,970Ω. From Equation 12:

R20

•R40•276µA

R30

V_RES

<

=

V_DC1,NOM

2.5V

1.8V

256

•6.65kΩ•276µA

256

R21=R20•

= 5,970Ω•

= 8,292Ω

10kΩ

V_DC0,NOM

7.68kΩ

= 9.33mV/LSB

LetR21=8,250Ω(thenearestE192Seriesresistorvalue).

2. Solve for R10 and R11.

Margining DC/DC Converter with TRIM Pin Design

Example

From Equation 13:

R20

5,970Ω

TheoutputvoltageoftheDC/DCconverterinFigure2needs

to be margined 10% about its nominal value. Assume

R10=

R11=

=

= 4,776Ω

= 3,882Ω

1.8V

0.8V

V

⎛

⎞

⎛

⎞

⎠

^DC0,NOM−1

−1

⎜

⎝

⎟

⎜

⎟

V

that R

= 10.22kΩ and V = 1.225V.

⎝

⎠

TRIM

REF

FB0

1. Solve for R30 using Equation 10:

R21

8,250Ω

=

2.5V

0.8V

⎛

⎞

V

⎛

⎞

⎛

⎞

⎠

50− D_DOWN

%

^DC1,NOM−1

−1

R30≤R_TRIM

=10.22kΩ •

•

⎜

⎟

⎜ ⎟

⎜

⎟

⎝

D_DOWN

%

V

FB1

⎝

⎠

⎝

⎠

50−10

⎛

⎞

Let R10 = 4,750Ω and R11 = 3,880Ω.

3. Solve for R40 and R41.

Assume that R40 = R41.

R40=R41≥

= 40,880Ω

⎜

⎟

⎠

⎝

10

Let R30 = 39.2kΩ.

2. Solve for R40 using Equations 11:

⎛

⎞

D_UP%

V_REF

236µA

⎛

⎜

⎝

⎞

⎟

⎠

V

_DCn,NOM− V_DCn,MIN

(

)

R40≥ 1+

•

⎜

⎟

V

•

+1 +10mV

D_DOWN

%

⎝

⎠

FBn

V_DCn,MAX− V_DCn,NOM

(

)

=

10 1.225V

10 236µA

⎛

⎞

236µA

= 1+

•

⎟

=10,381Ω

⎜

⎝

⎠

⎛ (1−0.9)

⎞

0.8V•

+1 +10mV

⎜

⎟

⎠

Let R40 = 10.5kΩ.

⎝ (1.05−1)

=10,212Ω

236µA

Let R40 = R41 = 10.5kΩ

29701fe

32

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

4. Solve for R30B and R31B.

R21

R31A ≤

−R31B=

⎛

⎞

V

_DC1,MAX− V_DC1,NOM

R21

⎞

R40•236µA− V −0.8V−10mV

(

)

⎛

FB0

1+

•

⎟

R30B≤

=

⎜

⎝

⎜

⎟

⎠

R11

V_DC1,NOM

1

⎛

⎞

⎝

⎠

V

•

+

⎜

⎝

⎟

⎠

FB0

R10 R20

8,250Ω

−2,890Ω = 49,888Ω

(10.5kΩ•236µA−0.8V−0.8V−10mV)

8,250Ω

3,880Ω

1.05−1

⎞

⎛

⎞

⎛

= 2,870Ω

1+

•

⎜

⎝

⎟

⎜

⎝

⎟

⎠

1

⎛

⎞

⎠

1

0.8V•

+

⎜

⎝

⎟

⎠

4,750Ω 5,970Ω

Let R30A = 49.9kΩ and R31A = 48.7kΩ.

R41•236µA− V −0.8V−10mV

(

)

=

FB1

6. Solve for Channel 1’s tracking counter delay relative to

Channel 0, CH1_A_DELAY_TRACK().

R31B≤

1

⎞

⎛

V •

+

⎜

⎝

⎟

FB1

⎠

R11 R21

First, recalculate the values of V

values of R1n and R2n:

based on the final

DCn,NOM

(10.5kΩ•236µA−0.8V−0.8V−10mV)

= 2,863Ω

1

⎛

⎞

0.8V•

+

R20

R10

⎛

⎝

⎞

⎠

⎜

⎝

⎟

⎠

′

V_DC0,NOM= V • 1+

+I •R20=

FB

3,880Ω 8,250Ω

⎜

⎟

FB

For coincident tracking to occur Equation 17 also must

be satisfied:

5,970Ω

4,750Ω

⎛

⎝

⎞

0.8V• 1+

+0=1.805V

⎜

⎟

⎠

R30B R31B

=

8,250Ω

3,880Ω

⎛

⎝

⎞

R20 R21

′

V_DC1,NOM= 0.8V• 1+

+0= 2.501V

⎜

⎟

⎠

R31B

R21

2,863Ω

8,250Ω

→R30B=

→R31B=

•R20=

•R21=

•5,970Ω = 2,078Ω

•8,250Ω = 3,957Ω

Next, apply Equation 19:

CH1_ A_DELAY_TRACK()=

R30B

R20

2,870Ω

5,970Ω

R31B

R21

′

V_DC1,NOM− V_DC0,NOM

•

(

)

=

Let R30B = 2,100Ω and R31B = 2,890Ω.

5. Solve for R30A and R31A.

Referring to Equation 18:

1µA /count•R41

2,890Ω

8,250Ω

1µA /count•10.5kΩ

2.501V−1.805V •

)

= 23counts

R20

R30A ≤

−R30B=

7. Solve for the IDAC0 and IDAC1 terminal tracking codes,

⎛

⎞

V

_DC0,MAX− V_DC0,NOM

R20

R10

⎛

⎞

1+

•

⎜

⎝

⎟

⎠

Chn_a_idac_track[7:0].

⎜

⎟

V_DC0,NOM

⎝

⎠

Ch0_a_idac[7:0]=Ch1_a_idac[7:0]=

5,970Ω

−2,100Ω = 50,806Ω

0.8V

5,970Ω

4,750Ω

1.05−1

⎞

⎛

⎞

⎛

255−

=179

1+

•

⎜

⎝

⎟

⎜

⎝

⎟

⎠

1µA /LSB•10.5kΩ

⎠

1

29701fe

33

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

applicaTions inForMaTion

2.7

drop across resistor R

. Since the V pin voltage is

DD

SENSE

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

V

DC1

monitoredbytheLTC2970, itstolerancecanbeaccounted

for when calculating the point of load voltage. Transistor

V

DC0

Q1allowstheI

pintoforcecurrentintotheconverter’s

OUT0

feedbacknodewithoutforwardbiasingtheLTC2970’sI

OUT0

body diode. Note that I

128mA after the LTC2970 comes out of power-on reset.

’s output current defaults to

OUT0

0

29701 F04

5ms/DIV

15-Bit Programmable Power Supply Application

Circuit

Figure 4. Tracking Design Example DC/DC

Converter Output Waveforms

Figure6illustrateshowbothservochannelsoftheLTC2970

can be configured to adjust a single DC/DC converter over

a 15-bit dynamic range. R30 and R31 are sized to force

1 bit of overlap between the coarse (channel 0) and fine

(channel1)servoloops.Onecoarseservoiterationshould

be performed first on channel 0 with IDAC1 programmed

to mid-scale, and then channel 1 can be programmed to

servo to the desired voltage.

Figure 4 shows the DC/DC converter output voltages for

this design example tracking-up and tracking-down.

Temperature Sensor Conversion

The LTC2970's internal temperature sensor output is

proportional to absolute temperature (PTAT). In order to

convert the ADC reading to degrees Celsius, apply the

following formula:

Programmable Reference Application Circuit

ADC_temp_sensor_reading

Figure 7 shows a LTC2970 configured as a program-

mable reference that can span a 0V to 3.5V range with

a resolution of 100µV and an absolute accuracy of less

than 0.5%. The two IDAC’s are paralleled by terminating

result(°C)=

–273.15 (21)

4

Negative Power Supply Application Circuit

IDAC1’s output resistor in the V

output and taking the

OUT0

Figure 5 shows the LTC2970 controlling a negative power

supply. The R30/R40 resistor divider translates the point

output of the composite DAC from V

. IDAC0 should

OUT1

servo once with IDAC1 set to mid-scale, and then IDAC1

can servo once, continuously, or trigger on drift to the

desired target voltage.

of load voltage to the LTC2970’s V

inputs while the

IN0_A

V

IN0_B

inputs monitor the converter’s input current I • R

8V TO 15V

0.1µF

12V

IN

12V

IN

V

DD

V

IN

OUT

0.1µF

IN

V

R40

R30

DD

V

IN0_AP

IN0_AM

+

0.1µF

LTC2970

C

LOAD

GPIO_CFG

ALERT

SCL

1/2 LTC2970

V

OUT1

OUT0

V

ALERT

IN0_BP

IN0_BM

R31

DC/DC

2

I C BUS

SCL

SDA

I C BUS

R

SENSE

CONVERTER

IN0_AP

IN1_AP

OUT1

R30

SDA

V

I

Q1

R20

R10

I

TP0610K

RUN/SS FB

GPIO_0

REF

OUT0

LOAD

R41

GND

OUT0

REF

R40

OUT

GND ASEL0 ASEL1

0.1µF

V

SGND

GND

IN0_AM

IN1_AM

DC/DC

CONVERTER

R20

R10

29701 F05

R31 ≥ R30 • 128

R41 = R40

FB

LOAD

GND ASEL0 ASEL1

0.1µF

R30

R40

• V

– V

V

OUT

= V – 1+

DD

(

)

IN0_AP

IN0_AM

)

(

V

IN

V

EE

29701 F06

Figure 6. Programmable Power Supply Application Circuit

Figure 5. Negative Power Supply Application Circuit

29701fe

34

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

Typical applicaTions

8V TO 15V

0.1µF

12V

IN

V

DD

LTC2970

IN1_AP

0.1µF

V

IN1_AM

IN0_AP

IN0_AM

OUT1

ALERT

SCL

2

I C BUS

SDA

I

OUT1

22µF

100Ω

12.7k

+

OUT

–

V

OUT0

10Ω

I

REF

OUT0

GND ASEL0 ASEL1

0.1µF

29701 F07

Figure 7. Programmable Reference Application Circuit

29701fe

35

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

package DescripTion

Please refer to http://www.linear.com/product/LTC2970 #packaging for the most recent package drawings.

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-ꢀ696 Rev A)

0.70 0.05

4.50 0.05

3.ꢀ0 0.05

2.65 0.05

2.00 REF

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.00 REF

4.ꢀ0 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.05 TYP

PIN ꢀ NOTCH

2.00 REF

R = 0.20 OR C = 0.35

R = 0.ꢀꢀ5

TYP

0.75 0.05

4.00 0.ꢀ0

(2 SIDES)

23

24

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

(NOTE 6)

ꢀ

2

5.00 0.ꢀ0

(2 SIDES)

3.00 REF

3.65 0.ꢀ0

2.65 0.ꢀ0

(UFD24) QFN 0506 REV A

0.25 0.05

0.200 REF

0.50 BSC

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

29701fe

36

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

revision hisTory ^{(Revision history begins at Rev D)}

REV

DATE

DESCRIPTION

PAGE NUMBER

D

06/14 Order Information: Corrected DFN to QFN

Figure 5: Corrected top R10 to R30, top R20 to R40

10/16 Added H-grade information

2

34

E

2

Fixed V and V specification column placement

4

IH

IL

Updated temperature dependent curves to include H-grade temperature range

Clarified that the 12V ADC measurement has a divide by 3

7, 8, 9

18

IN

29701fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

For more information www.linear.com/LTC2970

LTC2970/LTC2970-1

Typical applicaTion

8V TO 15V

10

0.1µF

12V

IN

R50

9

V

DD

IN

OUT

IN

10k

GPIO_CFG

3

4

20

I+

I–

V

IN0_BP

IN0_BM

OUT0

11

DC/DC

CONVERTER 0

1

R30

V

IN0_AP

R20

R10

14

RUN/SS FB

I

LOAD

OUT0

R40

V

SGND

PGND

IN0_AM

17

18

19

2

ALERT

SCL

2

I C BUS

SMBUS

16

GPIO_0

SDA

(

)

COMPATIBLE

LTC2970

R51

V

IN

OUT

IN

7

8

I+

I–

V

IN1_BP

IN1_BM

OUT1

12

DC/DC

CONVERTER 1

5

R31

V

IN1_AP

R21

R11

13

R41

6

I

RUN/SS FB

LOAD

OUT1

23

24

V

SGND

PGND

REF

IN1_AM

0.1µF

15

GPIO_1

RGND

GND ASEL0 ASEL1

25 22 21

29701 TA01

Figure 8. Typical LTC2970 Application Circuit for

DC/DC Converters with External Feedback Resistors

relaTeD parTs

PART NUMBER

DESCRIPTION

4-Channel PMBus Power System Manager

COMMENTS

LTC2975

0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and

Supervision, Input Current and Power, Input Energy Accumulator

LTC2920-1/LTC2920-2 Single/Dual Power Supply Margining Controllers

Symmetric/Asymmetric High and Low Voltage Margining

3 (LTC2921) or 5 (LTC2922) Remote Sense Switches

Up to 3 Supplies

LTC2921/LTC2922

LTC2923

Power Supply Trackers with Input Monitors

Power Supply Tracking Controller

Quad Power Supply Sequencer

LTC2924

Voltage Monitoring and Sequence Error Detection and Reporting

Power Good Timer, Remote Sense Switch

Point of Load Applications

LTC2925

Multiple Power Supply Tracking Controller

Single Power Supply Tracker

LTC2927

29701fe

LT 1016 REV E • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

For more information www.linear.com/LTC2970

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2970

●

 LINEAR TECHNOLOGY CORPORATION 2006


型号：	LTC2970CUFD-1#PBF
厂家：	Linear
描述：	LTC2970 - Dual I<sup>2</sup>C Power Supply Monitor and Margining Controller; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C
文件：	总38页 (文件大小：763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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