LTC3256EMSE#PBF_技术文档

LTC3256

Wide V Range

IN

Dual Output 350mA Step-Down

Charge Pump with Watchdog Timer

DescripTion

FeaTures

The LTC^®3256 is a wide input range switched capacitor

n

Input Voltage Range: 5.5V to 38V

n

Independently Enabled 5V and 3.3V Fixed Outputs

5V Output: 100mA Max

step-down DC/DC converter that produces two regulated

outputs: a 5V output via direct connection to the charge

pump output, and a 3.3V output via a low dropout (LDO)

linear post-regulator. The device provides up to 350mA

n

3.3V LDO Output: 250mA Max

Multimode Step-Down Charge Pump (2:1, 1:1) with

Automatic Mode Switching

of total output current. At 12V V and maximum load on

IN

n

Low Quiescent Current

both outputs, power dissipation is reduced by over 2W

compared to a dual LDO regulator solution.

n

20μA with Both Outputs Regulating (No Load)

n

0.5μA in Shutdown

The LTC3256 maximizes efficiency by running the charge

pumpin2:1modeoveraswideanoperatingrangeaspos-

sible, and automatically switches to 1:1 mode as needed

Engineered for Diagnostic Coverage in

ISO26262 Systems

1.1V Reference Output for System Diagnostics

Power-On Reset and Watchdog Controller with

Adjustable Timing

Overcurrent Fault Protection on Each Output

Overtemperature Protection

150°C Max Operating Junction Temperature

Thermally Enhanced 16-Lead MSOP Package

n

duetoV andloadconditions.Controlledinputcurrentand

IN

switchingslewratesminimizeconductedandradiatedEMI.

An integrated watchdog timer, independent power good

outputs and reset input ensure reliable system operation

and fault monitoring. A buffered 1.1V reference output

enablessystemself-testingforsafetycriticalapplications.

n

The LTC3256 has numerous safety features including

overcurrent fault protection, overtemperature protection

and tolerance of 38V input transients. The LTC3256 is

available in a thermally enhanced 16-lead MSOP plastic

package with exposed pad (MSE16).

applicaTions

n

Automotive ECU/CAN Transceiver Supplies

n

Industrial/Telecom Housekeeping Supplies

n

Low Power 12V to 5V and 3.3V Conversion

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

Typical applicaTion

High Efficiency Dual Output Power Supply

Power Dissipation vs Input Voltage

5.0

3.3V LOAD = 250mA

5V LOAD = 100mA

4.5

10µF

1µF

4.0

+

–

OUTCP

RT

C

3.5

OUT5

5V OUTPUT

100mA MAX

3.0

WT

10µF

IDEAL DUAL LDO

2.5

5.5V TO 38V

OUT3

3.3V LDO OUTPUT

250mA MAX

V

2.0

1.5

1.0

IN

INPUT SUPPLY

LTC3256

10µF

1M

EN5

EN3

PG5

PG3

RSTI

LTC3256

10µF

0.5

RST

WDI

0.0

MICROCONTROLLER

6

7

8

9

10 11 12 13 14 15 16

INTERFACE

REFOUT

GND

INPUT VOLTAGE (V)

3256 TA01

0.1µF

3256 TA01a

3256fb

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For more information www.linear.com/LTC3256

LTC3256

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

–

+

V , EN3, EN5, WDI.................................... –0.3V to 38V

OUTCP, OUT3, OUT5................................. –0.3V to 5.5V

OUT3, OUT5 Short Circuit Duration ................. Indefinite

IN

1

2

3

4

5

6

7

8

C

16 EN5

15 EN3

OUTCP

OUT5

REFOUT

OUT3

PG3

14 V

IN

17

GND

13 WDI

12 RSTI

11 RT

PG3, PG5, REFOUT............................... –0.3V to V

OUTCP

RST ........................................................... –0.3V to 5.5V

10 WT

PG5

9

RST

WT, RT.................................................. –0.3V to V

OUTCP

MS PACKAGE

16-LEAD PLASTIC MSOP

RSTI ......................................................... –0.3V to 5.5V

Operating Junction Temperature Range (Notes 3, 4)

LTC3256E .......................................... –40°C to 125°C

LTC3256I ........................................... –40°C to 125°C

LTC3256H.......................................... –40°C to 150°C

LTC3256MP....................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

T

= 150°C, θ = 10°C/W

JC

JA

JMAX

θ

= 40°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion ^{http://www.linear.com/product/LTC3256#orderinfo}

LEAD FREE FINISH

LTC3256EMSE#PBF

LTC3256IMSE#PBF

LTC3256HMSE#PBF

LTC3256MPMSE#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LTC3256EMSE#TRPBF

LTC3256IMSE#TRPBF

LTC3256HMSE#TRPBF

3256

LTC3256MPMSE#TRPBF 3256

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

3256fb

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For more information www.linear.com/LTC3256

LTC3256

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 3). V_IN= 12V, C_FLY= 1µF unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

38

UNITS

l

V

IN

Operating Input Voltage Range (Note 5)

5.5

V

Undervoltage Lockout Threshold

1.8

2.7

IN

Quiescent Current

EN5 = EN3 = 0V

IN

Shutdown

Output In Regulation, No Load

0.5

15

20

2

30

35

µA

Only One Output Enabled

Both OUT3 and OUT5 Enabled

EN3, EN5 Input High Voltage

EN3, EN5 Input Low Voltage

EN3, EN5 Input Low Current

EN3, EN5 Input High Current

1.2

0.9

0

2

V

0.4

–1

V

= 0V

1

3

µA

= 38V

1

Charge Pump Operation

V

OUTCP Regulation Voltage

OUTCP Short Circuit Current

Charge Pump Output Impedance

EN3 and/or EN5 High

= GND

5.05

600

V

OUTCP

V

mA

OUTCP

2:1 Step-Down Mode

1:1 Step-Down Mode, V = 5.5V

2

Ω

IN

5V Output Operation

l

V

Fixed 5V Output Regulation (Note 5)

EN5 High, V = 5.5V, I

≤ 100mA

= 0mA

4.85

5.05

5.19

V

OUT5

IN

OUT

EN5 High, V = 12V, I

IN

EN5 High, V = 38V, I

IN

OUTCP to OUT5 Power Switch

On-Resistance

EN5 High

0.6

Ω

l

OUT5 Overvoltage Threshold

V

OUT5

V

OUT5

Rising Makes PG5 Go Low

Falling Makes PG5 Go Hi-Z

5.25

5.1

5.4

V

OUT5 Undervoltage Threshold

V

Rising Makes PG5 go Hi-Z

Falling Makes PG5 go Low

4.9

V

OUT5

l

4.6

–1

4.75

PG5 Output Low Voltage

PG5 Output Hi-Z Leakage

I

= 100µA

= 5V

0.1

0

0.4

1

V

PG5

V

µA

PG5

3.3V LDO Operation

l

V

OUT3

Fixed 3.3V LDO Output Regulation (Note 5)

EN3 High, V = 5.5V, I

≤ 250mA

= 0mA

3.170

3.200

3.234

3.30

3.366

V

IN

OUT

EN3 High, V = 12V, I

IN

EN3 High, V = 38V, I

IN

l

OUT3 Overvoltage Threshold

OUT3 Undervoltage Threshold

V

Rising Makes PG3 Go Low

Falling Makes PG3 Go Hi-Z

3.465

3.35

3.58

V

OUT3

V

OUT3

V

OUT3

Rising Makes PG3 Go Hi-Z

Falling Makes PG3 Go Low

3.24

3.135

V

l

3.04

–1

PG3 Output Low Voltage

PG3 Output Hi-Z Leakage

I

= 100µA

= 5V

0.1

0

0.4

1

V

PG3

V

µA

PG3

Buffered 1.1V Reference Output (REFOUT)

REFOUT Pin Output Voltage

l

EN3 and/or EN5 High, I

= 0mA

1.068

1.1

2

1.132

4

V

REFOUT

REFOUT Pin Output Resistance

Reset Timer Control (RT)

kΩ

l

External Timer RT Pull-Up Current

External Timer RT Pull-Down Current

Internal Timer RT Pull Down Current

RT Internal Timer Select Threshold

V

RT

V

RT

V

RT

= 0.3V

= 1.3V

–1.1

1.1

–1.9

1.9

–2.6

2.6

1

µA

V

= V

0.25

2.3

OUTCP

1.8

2.7

3256fb

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For more information www.linear.com/LTC3256

LTC3256

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 3). V_IN= 12V, C_FLY= 1µF unless otherwise noted.

SYMBOL

Reset Timer Input (RSTI)

RSTI Input High Voltage

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

1.2

1.16

0

1.26

V

RSTI Input Low Voltage

RSTI Input Low Current

RSTI Input High Current

1.1

–1

V

= 0V

= 5V

1

µA

RST_IN

0

RST_IN

Reset Output (RST)

l

t

Internal Reset Timeout Period

External Reset Timeout Period

RSTI Low to RST Asserted

RST Output Voltage Low

V

C

= V

150

26

200

32

80

0.1

0

260

44

ms

µs

V

RST(INT)

RST(EXT)

UV

RT

OUTCP

= 2.2nF

RT

From RSTI falling to 1V or less

= 5V, I = 100µA

10

150

0.4

1

V

OUTCP

RST

RST Output Voltage High Leakage

RST = 5V

–1

µA

Watchdog Timer Control (WT)

External Timer WT Pull-Up Current

l

V

WT

V

WT

V

WT

= 0.3V

= 1.3V

–1.1

1.1

–1.9

1.9

–2.6

2.6

1

μA

V

External Timer WT Pull-Down Current

Internal Timer WT Detect Pull Down Current

WT Internal Timer Select Threshold

= V

0.25

2.3

OUTCP

1.8

2.7

Watchdog Input (WDI)

l

t

Internal Watchdog Upper Boundary

Internal Watchdog Lower Boundary

External Watchdog Reset Time

External Watchdog Upper Boundary

External Watchdog Lower Boundary

WDI Input High Voltage

V

WT

V

WT

C

WT

= V

1.3

37.5

200

1.6

50

2

s

ms

V

WDU(INT)

WDL(INT)

WDR(EXT)

WDU(EXT)

WDL(EXT)

OUTCP

62.5

340

OUTCP

= 2.2nF

260

t

• (128/129)

WDR(EXT)

t

• (5/129)

WDR(EXT)

1.2

2

WDI Input Low Voltage

0.4

–1

0.9

0

V

WDI Input Low Current

V

= 0V

= 5V

1

µA

ns

WD_IN

WDI Input High Current

–1

0

WD_IN

l

Input Pulsewidth

100

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and lifetime.

The junction temperature (T , in °C) is calculated from the ambient

J

temperature (T , in °C) and power dissipation (P , in Watts) according to

A

D

the formula:

T = T + (P • θ )

JA

Note 2: All voltages are referenced to GND unless otherwise specified.

J

A

D

Note 3: The LTC3256E is guaranteed to meet performance specifications

from 0°C to 85°C operating junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3256I is guaranteed over the –40°C to 125°C operating junction

temperature range. The LTC3256H is guaranteed over the –40°C to 150°C

operating junction temperature range. The LTC3256MP is guaranteed and

tested over the –55°C to 150°C operating junction temperature range.

High junction temperatures degrade operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board layout,

the rated package thermal resistance and other environmental factors.

where θ (in °C/W) is the package thermal impedance.

JA

Note 4: This IC has overtemperature protection that is intended to protect

the device during momentary overload conditions. Junction temperatures

will exceed 150°C when overtemperature protection is active. Continuous

operation above the specified maximum operating junction temperature

may impair device reliability.

Note 5: The maximum operating junction temperature of 150°C must be

followed. Certain combinations of input voltage and output current will

cause the junction temperature to exceed 150°C and must be avoided. See

Thermal Management section for information on calculating maximum

operating conditions. Due to thermal limitations of production equipment,

only no load regulation is checked at 38V.

3256fb

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For more information www.linear.com/LTC3256

LTC3256

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Input Shutdown Current

vs Input Voltage

No Load Input Current

vs Input Voltage

Input Operating Current

vs Input Voltage

10

9

8

7

6

5

4

3

2

1

0

50

40

30

20

10

0

50

40

30

20

10

0

150°C

25°C

–55°C

BOTH HIGH

EN5 HIGH

EN3 HIGH

125°C

85°C

25°C

–55°C

EN3=EN5=HIGH

0

4

8

12 16 20 24 28 32 36 40

(V)

0

5

10 15 20 25 30 35 40

(V)

5

6

7

8

9

10 11 12 13 14 15

V (V)

IN

V

IN

3256 G01

3256 G02

3256 G03

3.3V Output Voltage

vs Input Voltage at 25mA

3.3V Output Voltage

vs Input Voltage at 250mA

Output Voltages vs Input Voltage

3.45

3.40

3.35

3.30

3.25

3.20

3.15

3.45

3.40

3.35

3.30

3.25

3.20

3.15

5.5

5.0

4.5

4.0

3.5

3.0

2.5

I

=25mA

I

=250mA

125°C

25°C

–55°C

OUT3

V

OUTCP

OUT5

OUT3

150°C

25°C

–55°C

No Load

0

5

10 15 20 25 30 35 40

(V)

5

6

7

8

9

10 11 12 13 14 15

5

6

7

8

9

10 11 12 13 14 15

V

(V)

V (V)

IN

3256 G04

3256 G05

3256 G06

5V Output Voltage

vs Input Voltage at 10mA

5V Output Voltage

vs Input Voltage at 100mA

Efficiency and Power Loss

vs Input Voltage

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

90

80

70

60

50

40

30

20

10

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

I

=100mA

125°C

25°C

–55°C

I

=10mA

OUT5

I

=250mA

OUT3

OUT5

I

=100mA

EFFICIENCY

150°C

25°C

–55°C

LOSS

5

6

7

8

9

10 11 12 13 14 15

(V)

5

6

7

8

9

10 11 12 13 14 15

(V)

0

5

10 15 20 25 30 35 40

(V)

V

IN

3256 G08

3256 G09

3256 G07

3256fb

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For more information www.linear.com/LTC3256

LTC3256

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Internal Reset Timeout Period

Internal Watchdog Timeout

Period vs Temperature

REFOUT Voltage vs Input Voltage

vs Temperature

1.14

1.13

1.12

1.11

1.10

1.09

1.08

1.07

1.06

0.30

0.25

0.20

0.15

0.10

1.8

1.7

1.6

1.5

1.4

1.3

1.2

150°C

25°C

–55°C

0

5

10 15 20 25 30 35 40

(V)

−60 −30

0

30

60

90 120 150

−60

−30

0

30

60

90

120

V

TEMPERATURE (°C)

IN

3256 G10

3256 G11

3256 G12

Reset Timeout Period

vs RT Capacitance

Watchdog Timeout Period

vs WT Capacitance

RSTI Threshold vs Temperature

50k

1.230

1.210

1.190

1.170

1.150

1.130

500k

10k

100k

1k

100

10

10k

1k

100

10

1

RISING

FALLING

0.1

0.001 0.01

0.1

1

10

100

1k

0.001 0.01

0.1

1

10

100

1k

–60 –30

0

30

60

90 120 150

RT PIN CAPACITANCE, C (nF)

WT PIN CAPACITANCE, C (nF)

TEMPERATURE (°C)

RT

WT

3256 G13

3256 G15

3256 G14

3256fb

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For more information www.linear.com/LTC3256

LTC3256

T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Output Ripple

OUTCP

AC 0.1V/DIV

OUTCP

AC 0.1V/DIV

OUTCP

AC 0.1V/DIV

OUT5

AC 0.1V/DIV

OUT5

AC 0.1V/DIV

OUT5

AC 0.1V/DIV

OUT3

AC 5mV/DIV

OUT3

AC 5mV/DIV

OUT3

AC 5mV/DIV

REFOUT

AC 5mV/DIV

REFOUT

AC 5mV/DIV

REFOUT

AC 5mV/DIV

3256 G16

3256 G19

3256 G22

3256 G17

3256 G20

3256 G23

3256 G17

3256 G21

3256 G24

25µs/DIV

5µs/DIV

V

= 12V

= 100mA

= 250mA

V

= 12V

V = 5.5V

IN

I

= 20mA

OUT5 = 20mA

I = 100mA

OUT3

OUT5

OUT3

OUT5

OUT3

= 100mA

OUT3 Power-Up

OUT3 Transient Response

1

EN3

0

1

EN3

0

OUTCP

AC 0.1V/DIV

OUTCP

DC 5V/DIV

OUTCP

DC 5V/DIV

OUT3

AC 20mV/DIV

OUT3

DC 1V/DIV

OUT3

DC 1V/DIV

250mA

I

PG3

OUT3

20mA

100µs/DIV

V

R

= 12V

= 33Ω

V = 5.5V

IN

V

= 12V

IN

OUT3

IN

R

OUT3

= 33Ω

OUT5 Power-Up

OUT5 Transient Response

1

EN5

0

1

EN5

0

OUT5

AC 50mV/DIV

V

=12V

OUTCP

DC 5V/DIV

OUTCP

DC 5V/DIV

IN

OUT5

DC 2V/DIV

OUT5

DC 2V/DIV

AC 50mV/DIV

V

=5.5V

IN

100mA

10mA

I

OUT5

PG5

500µs/DIV

100µs/DIV

V

= 12V

OUT5

V = 5.5V

IN

OUT5

IN

R

= 100Ω

R

= 100Ω

3256fb

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For more information www.linear.com/LTC3256

LTC3256

pin FuncTions

C (Pin 1): Charge Pump Flying Capacitor Negative Con-

nection.

–

RT (Pin 11):Reset Timeout Control Pin. Attach an external

capacitor (C ) to GND to set the reset timeout period,

RT

RT can be left open to minimize the reset timeout. Tie RT

to OUTCP to generate a reset timeout of about 200ms.

+

C (Pin 2): Charge Pump Flying Capacitor Positive Con-

nection.

RSTI(Pin12):ResetLogicComparatorInputPin.TheRSTI

input is compared to a 1.2V (typical) threshold voltage. If

RSTIisbelowthethresholdvoltagetheLTC3256willenter

the reset state and drive the RST pin low. Once RSTI rises

above the threshold voltage, the reset timer is started and

the RST pin is held low until the reset period times out.

OUTCP (Pin 3): Charge Pump Output. The charge pump

output should be bypassed with a 10µF or greater X7R

ceramic capacitor. The charge pump output is enabled if

either ENx pin is logic high. OUTCP is the input supply

for the 3.3V LDO.

OUT5 (Pin 4): 5V Output Pin. Connects to the charge

WDI (Pin 13): Watchdog Logic Input Pin. Application

circuitry must toggle the logic state of this pin such that

falling edges occur at a rate faster than the watchdog up-

per boundary time but slower than the watchdog lower

boundary time. If these conditions are not met, RST will

be asserted low. Tie WT and WDI to GND to disable the

watchdog timer. Do not float this pin.

pump output, OUTCP, through an internal power switch

controlled by the EN5 input when V > 10V (typical),

IN

and regulates to 5V with V as a power source when

IN

V < 10V (typical).

IN

REFOUT (Pin 5): 1.1V Reference Output. Provides a buff-

ered version of the LTC3256’s internal bandgap reference

voltage with 2k output impedance (typical). To maximize

supplyrejection,REFOUTshouldbebypassedwitha0.1µF

ceramic capacitor.

V

(Pin 14): Power Input Pin. Input voltage for both

IN

charge pump and IC control circuitry.

EN3 (Pin 15): Logic input pin which enables the 3.3V LDO

when high and disables it when low. Bringing EN3 high

causes the charge pump to enable if it isn’t already on. The

LDO powers up once the charge pump output, OUTCP,

rises above 97.5% of its regulation value (typical). The

EN3 pin has a 1μA (typical) pull down current to ground

and can tolerate 38V inputs.

OUT3 (Pin 6): 3.3V Low-Dropout Linear Regulator (LDO)

Output Pin. The charge pump output, OUTCP, serves as

the 3.3V LDO’s input supply.

PG3 (Pin 7): Power Good Open Drain Logic Output. Goes

high impedance when OUT3 is near its final operating volt-

age. PG3 is intended to be pulled up to alow voltagesupply

(such as OUT3, OUT5 or OUTCP) with an external resistor.

EN5 (Pin 16): Logic Input Pin. Enables or disables the 5V

output, OUT5. Bringing EN5 high causes the charge pump

to enable if it isn’talready on. When the charge pump output

rises above 97.5% of its regulation value (typical), a fault

protected internal power switch connects OUTCP to OUT5,

delivering power to any OUT5 load. A soft-start circuit limits

anyinrushcurrentthroughtheswitchtohelpavoidglitching

the charge pump output. If the input voltage falls below 10V

(typical) and the charge pump regulates to a voltage lower

PG5 (Pin 8): Power Good Open Drain Logic Output. Goes

high impedance when OUT5 is near its final operating volt-

age. PG5 is intended to be pulled up to alow voltage supply

(such as OUT3, OUT5 or OUTCP) with an external resistor.

RST (Pin 9): Reset Open Drain Logic Output. The RST

pin is low impedance to GND during the reset period, and

goes high impedance during the watchdog period. RST is

intended to be pulled up to low voltage supply (such as

OUT3, OUT5, or OUTCP) with an external resistor.

than5V,OUT5receivesitspowerdirectlyfromaV -powered

IN

1:1 mode regulator. The EN5 pin has a 1μA (typical) pull

WT (Pin 10): Watchdog Timer Control Pin. Attach an

down current to ground and can tolerate 38V inputs.

external capacitor (C ) to GND to set the watchdog

WT

GND(ExposedPad):Ground. Theexposedpackagepadis

groundandmustbesolderedtothePCboardgroundplane

forproperfunctionalityandforratedthermalperformance.

upper boundary timeout. Tie WT to OUTCP to generate a

timeout of about 1.6s. Tie WT and WDI to GND to disable

the watchdog timer.

3256fb

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For more information www.linear.com/LTC3256

LTC3256

TiMing DiagraM

Reset Timing

RSTI

t

RST

UV

RST

3256 TD01

Watchdog Timing

WDI

RST

t

< t < t

t

WDR

WDL

WDU

t < t

t

RST

WDL

RST

3256 TD02

3256fb

9

For more information www.linear.com/LTC3256

LTC3256

siMpliFieD block DiagraM

V

IN

2:1/1:1 MODE STEP-DOWN CHARGE PUMP

EN5

EN3

V

-POWERED

1:1 MODE

IN

OUT5 ON

OUTCP ON

OUT3 ON

V

+

OUTCP

C

ENABLE LOGIC

5V REGULATOR

5.05V

3.6V

EXTERNAL

FLYING

CAPACITOR

CONNECTION

+

5V

–

V

IN

–

C

5.5V 7.2V

10.1V

38V

1.1V

BANDGAP

REFERENCE

1:1 2:1

MODE MODE

+

–

OUTCP

REFOUT

3.4V

3.3V 250mA LDO

2k

OUTCP

GOOD

3.3V

–

+

FAULT-PROTECTED

PMOS SWITCH

RST

OUT3

PG3

RSTI

+

–

+

–

1.2V

5V

WATCHDOG

TIMER

–

+

OUT5 INPUT

SELECTOR

RT

CLOCK

POWER GOOD

WINDOW

OSCILLATOR

–

+

COMPARATORS

PG5

WT

FALLING

EDGE

DETECTOR

WDI

–

+

OUT5

GND

3256 BD

3256fb

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For more information www.linear.com/LTC3256

LTC3256

applicaTions inForMaTion

TheLTC3256isaninductorlesswideinputrangestep-down

DC/DC converter that produces 5V and 3.3V regulated

outputs with a total output current of 350mA. It uses a

step-down charge pump with automatic 2:1/1:1 mode

switching as a pre-regulator for the 5V and 3.3V outputs.

This optimizes system efficiency and minimizes thermal

problems due to excess power dissipation. In typical

12V automotive systems, the LTC3256 reduces power

dissipation by a full 2W at maximum load relative to a

dual LDO solution.

IDEAL 2:1 CHARGE PUMP

INPUT OUTPUT

I

LOAD

2

I

=

IN

I

LOAD

I

+

LOAD

2

V

OUT

–

LOAD

+

V

IN

–

GND

3256 F01

I

LOAD

I

LOAD

2

I

IN

=

Figure 1. Steady-State Time-Averaged Current

Flows in an Ideal 2:1 Charge Pump

Each regulated output may be independently enabled to

providemaximumflexibility.Enablingeitheroftheregulator

outputswillfirstturnonthestep-downchargepump.Once

the charge pump nears its regulation point, the enabled

outputs will turn on in a controlled, soft-started manner.

The 3.3V output is provided by an LDO that is always

powered from the charge pump output. The 5V output

is typically powered from the regulated charge pump via

an overcurrent protected switch directly connected to the

charge pump output.

Figure 2 shows the power switch topology of the 2:1

step-down charge pump in the LTC3256. When operat-

ing in 2:1 mode, the part employs a two phase clock to

turn on only switches A and C in one phase followed by

switches B and D only in the other phase. Current source

I controls the maximum output current that the part can

A

deliver. When the charge pump clock is active, V

OUTCP

will increase towards V /2. Once V

reaches the

IN

OUTCP

appropriate regulation point, the charge pump shuts off

all four switches and enters a SLEEP state to minimize

quiescent current until the output voltage falls below its

regulation point.

The charge pump typically produces a regulated 5.05V

output but allows this output to drop as needed in order to

stayin2:1modeandmaximizeoverallefficiencywhenever

V falls below ~10.1V. If V falls near the low end of its

IN

operating range, the charge pump automatically enters

1:1 mode as required to keep the 3.3V LDO in regulation.

Whenever the charge pump output drops below 5V, the

regulated 5V output will automatically be supplied using

V

IN

SWITCH A

SWITCH B

I

A

+

V

IN

–

+

–

C

a simple gated switch regulator powered from V .

IN

OUTCP

+

C

FLY

2:1 Step-Down Charge Pump Operation (V > ~10.1V)

IN

The increased efficiency and reduced power dissipation

advantages of the LTC3256 arise from the use of a 2:1

step-downchargepumptoperformthebulkofthevoltage

V

GND

OUTCP

SWITCH D

SWITCH C

step-down from V to 5V and 3.3V. An ideal 2:1 charge-

IN

C

OUTCP

pump has the property that its input current is exactly

half its output current (See Figure 1). In real-world charge

pumps like the LTC3256, input current slightly exceeds

half the output current due to additional current needed

for biasing and for driving power switches.

–

3256 F02

Figure 2. LTC3256 2:1 Step-Down Charge

Pump Power Switch Topology

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LTC3256

applicaTions inForMaTion

V

OUTCP

Under typical conditions (V > 10.1V), the LTC3256

IN

operates in 2:1 mode and both the 5V output and 3.3V

LDO are powered directly from the charge pump output

(see Figure 3).

5.05V

PMOS

SWITCH

OUT5

OUT3

5V OUT

100mA MAX

CHARGE PUMP

IN 2:1 MODE

V

IN

3.6V

12V IN

350mA

MAX OUTPUT

3.3V OUT

250mA MAX

3.3V LDO

V

IN

5.5V

7.2V

10.1V

38V

OUTCP

3256 F03

1:1

MODE

2:1

MODE

5.05V PREREGULATED OUTPUT FOR

EXTERNAL BYPASS CAPACITOR CONNECTION

Figure 3. Power Connections for Typical 12V V_INOperation

Figure 4. Typical Charge Pump Output Voltage and Mode vs V_IN

The overall efficiency and power dissipation under typical

2:1 step-down conditions can be approximated with the

equations below.

If OUT5 is enabled and the charge pump output falls below

5V, OUT5 is disconnected from the charge pump output

and a separate internal V -powered 1:1 step-down mode

IN

Total LTC3256 efficiency when V > ~10.1V:

IN

regulator is used to regulate 5V at the OUT5 pin. Refer

to the Simplified Block Diagram. The 3.3V LDO remains

powered by the 2:1 charge pump output.

5V •I_OUT5+3.3V •I_OUT3

η≅

I

I_OUT3

⎛

⎞

OUT5

V •

+

⎜

⎝

⎟

⎠

IN

2

Overall efficiency and power dissipation in this operating

region can be approximated by the equations below.

Total LTC3256 power dissipation when V > ~10.1V:

IN

Total LTC3256 efficiency when ~7.2V < V < ~10.1V:

IN

V

2

V

2

⎛

⎝

⎞

⎠

⎛

⎞

⎠

P ≅ ^IN–5V •I

+

^IN–3.3V •I

⎟

OUT3

⎜

⎟

⎜

⎝

D

OUT5

5V •I_OUT5+3.3V •I_OUT3

η≅

I_OUT3

⎛

⎞

V • I

+

⎜

⎟

⎠

IN

OUT5

2:1 Step-Down Charge Pump Operation

(~7.2V < V < ~10.1V)

⎝

2

IN

TotalLTC3256powerdissipationwhen~7.2V<V <~10.1V:

IN

Inthisoperatingregion,thechargepumpregulatesslightly

below V /2 in order to remain in 2:1 mode and maximize

V

⎛

⎞

IN

P ≅ V –5V •I

+

^IN–3.3V •I

(

)

⎜

⎝

⎟

D

IN

OUT5

OUT3

overall V to 3.3V conversion efficiency. Figure 4 shows

⎠

IN

2

typical charge pump step-down mode and output voltage

as a function of V .

IN

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LTC3256

applicaTions inForMaTion

1:1 Step-Down Charge Pump Operation (V < ~7.2V)

Flying Capacitor Selection

IN

At the low end of the V operating range, the minimum

The flying capacitor should always be a ceramic type.

Polarized capacitors such as tantalum or aluminum

electrolytics are not recommended. The flying capacitor

controls the strength of the charge pump. In order to

achieve the rated output current, it is necessary for the

flying capacitor to have at least 0.4μF of capacitance over

operating temperature at 5.05V (see Ceramic Capacitor

Selection Guidelines). The voltage rating of the ceramic

capacitor should be 6V or greater.

IN

charge pump regulation point is typically V

= 3.6V,

OUTCP

withthechargepumpautomaticallyswitchingto1:1mode

as needed to maintain regulation. Under 1:1 mode condi-

tions, both the 5V and 3.3V outputs are powered directly

from V with no improvement in efficiency over a dual

IN

LDO solution. The overall efficiency and power dissipa-

tion in 1:1 step-down mode can be approximated by the

equations below.

Total LTC3256 efficiency when V < ~7.2V:

IN

Ceramic Capacitor Selection Guidelines

5V •I_OUT5+3.3V •I_OUT3

Capacitors of different materials lose their capacitance

with higher temperature and voltage at different rates.

For example, a ceramic capacitor made of X5R or X7R

material will retain most of its capacitance from –40°C

to 85°C, whereas a Z5U or Y5V style capacitor will lose

considerable capacitance over that range (60% to 80%

loss typical). Z5U and Y5V capacitors may also have a

very strong voltage coefficient, causing them to lose an

additional60%ormoreoftheircapacitancewhentherated

voltage is applied. Therefore, when comparing different

capacitors, it is often more appropriate to compare the

amount of achievable capacitance for a given case size

ratherthandiscussingthespecifiedcapacitancevalue.For

example, over rated voltage and temperature conditions,

a 4.7μF, 10V, Y5V ceramic capacitor in an 0805 case may

not provide any more capacitance than a 1μF, 10V, X5R

or X7R available in the same 0805 case. In fact, over bias

and temperature range, the 1μF, 10V, X5R or X7R will

provide more capacitance than the 4.7μF, 10V, Y5V. The

capacitor manufacturer’s data sheet should be consulted

to determine what value of capacitor is needed to ensure

minimum capacitance values are met over operating

temperature and bias voltage. Table 1 is a list of ceramic

capacitor manufacturers in alphabetical order:

η≅

V • I_OUT5+I_OUT3

(

)

IN

Total LTC3256 power dissipation when V < ~7.2V:

IN

P ≅ V –5V •I

+ V –3.3V •I

(

IN

OUT3

(

)

D

IN

OUT5

ReferringtoFigure2,in1:1mode,chargepumpswitchesC

and D remain off, and switches A and B are pulsed on and

off together to transfer charge directly from V to OUTCP.

IN

V Bypass Capacitor Selection

IN

The total amount and type of capacitance necessary for

inputbypassingisverydependentontheimpedanceofthe

inputpowersourceaswellasexistingbypassingalreadyon

the V node. For optimal input noise and ripple reduction,

IN

it is recommended that a low ESR ceramic capacitor be

used for V bypassing. Low ESR will reduce the voltage

IN

stepscausedbychanginginputcurrent,whiletheabsolute

capacitorvaluewilldeterminethelevelofripple.Anelectro-

lytic or tantalum capacitor may be used in parallel with the

ceramic capacitor on V to increase the total capacitance,

IN

but due to the higher ESR, it is not recommended that an

electrolytic or tantalum capacitor be used alone for input

bypassing. The LTC3256 will operate with capacitors less

than 10μF, but depending on the source impedance, input

noise can feed through to the output causing degraded

performance. For best performance, 10μF or greater total

capacitance is suggested for V bypassing.

IN

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LTC3256

applicaTions inForMaTion

Table 1

As shown in the Block Diagram, two on-board regulators

can drive the 5V output: the 2:1 charge pump and the

IN

CERAMIC CAPACITOR MANUFACTURER WEBSITE

V -powered gated-switch regulator. Regulator selection

AVX

www.avxcorp.com

www.kemet.com

www.murata.com

www.t-yuden.com

www.tdk.com

is automatic. The LTC3256 prefers the 2:1 charge pump

Kemet

whenever possible due to its increased efficiency, but

Murata

transitionsautomaticallytotheV -poweredgated-switch

IN

Taiyo Yuden

TDK

regulator as needed to maintain regulation depending on

line and load conditions.

Wurth Elektronik

www.we-online.com

To reduce 5V output noise and ripple, it is suggested that

a low ESR (equivalent series resistance < 0.1Ω) ceramic

capacitor (10μF or greater) be used for OUT5 bypass.

Tantalum or aluminum electrolytic capacitors can be

used in parallel with a ceramic capacitor to increase the

total capacitance but should not be used alone because

of their high ESR.

3.3V LDO Operation (OUT3)

The 3.3V LDO post-regulates the charge pump output to

producealowernoiseoutputthanistypicallyavailablefrom

switching regulators, and supports a load of up to 250mA.

To ensure stability, the LDO output should be bypassed

to ground with at least a 10µF X7R ceramic capacitor.

Drive the EN3 pin high or low to turn the LDO on or off,

respectively. When turning on the LDO, the LTC3256

checks whether the charge pump output (OUTCP) is on,

enabling the charge pump automatically if needed.

5V Output from 2:1 Charge Pump via Fault-Protected

PMOS Switch

If at least 5V (typical) is present at OUTCP when EN5 is

brought high, the LTC3256 connects OUT5 to OUTCP

via an internal PMOS power switch. Soft-start circuitry

controls the PMOS turn-on rate to limit in-rush current

draw from OUTCP. See Figure 5.

3.3V LDO Fault Protection

The 3.3V LDO output is current limited to 350mA (typical)

toprotectagainstoverloadsandshortcircuits.Inaddition,

to reduce power dissipation during an output fault condi-

tion, foldback circuitry reduces the LDO current limit to

Upon a hard short circuit to ground, OUT5’s foldback cir-

OUT5 Startup Into No Load

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

116mA (typical) for V

< 0.9V (typical).

OUT3

To avoid startup issues due to the foldback feature, it is

recommendedthatheavyloadsonOUT3beheldoffduring

LDO startup until the PG3 pin goes Hi-Z to indicate that

the LDO has completed power up.

5V Output Operation (OUT5)

Bringing EN5 high enables the 5V output at the OUT5

pin. When the 5V output is enabled, the LTC3256 checks

whether the charge pump output (OUTCP) is on, enabling

the charge pump automatically if needed.

0

0.5

1

1.5

2

2.5

3

3.5

4

TIME (ms)

3256 G05

Figure 5. OUT5 Startup

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LTC3256

applicaTions inForMaTion

cuitry limits current to 85mA (typical). This limit remains

would give a 32ms reset timeout period.

in effect for V

< 0.8V (typical). To avoid startup issues

OUT5

Figure 6 shows the desired reset timeout period as a func-

tion of the value of the timer capacitor. Leaving RT open

with no external capacitor generates a reset timeout of

approximately 0.75ms. Shorting RT to OUTCP generates

a reset timeout of approximately 0.2s.

due to this foldback feature, heavy loads on OUT5 should

be held off during OUT5 startup until PG5 goes Hi-Z.

The LTC3256 has current limit circuitry to protect against

overcurrent faults beyond hard shorts to ground.

Reset Generation (RSTI input, RST output)

50k

The LTC3256 pulls the RST open-drain output low when-

ever RSTI is below threshold (typically 1.2V) or OUTCP

is not in regulation. RST remains asserted low for a reset

10k

1k

100

10

timeout period (t ) once RSTI goes above the threshold

RST

and OUTCP is in regulation. Requiring that OUTCP is in

regulation ensures that at least one of the outputs (OUT5

or OUT3) is enabled before the reset timeout period starts.

RST deasserts by going high impedance at the end of the

reset timeout period.

1

0.1

0.001 0.01

0.1

1

10

100

1k

The reset timeout can be configured to use an internal

timerwithoutexternalcomponents, oranadjustabletimer

programmed by connecting an external capacitor from

the RT pin to GND. Glitch filtering ensures reliable reset

operation without false triggering.

RT PIN CAPACITANCE, C (nF)

RT

3256 F06

Figure 6. Reset Timeout Period vs RT Pin Capacitance

RST Output Characteristics

During initial power up, the RST output asserts low while

RST is an open-drain pin and thus requires an external

pull-up resistor to the logic supply. RST is typically pulled

up to OUT5, OUT3, or OUTCP, but can be pulled up to any

other supply voltage providing the voltage limits of the

pin are observed.

V is below the V undervoltage lockout threshold. The

IN

state of OUTCP and RSTI have no effect on RST while

V

is below the undervoltage lockout threshold. The

IN

reset timeout period cannot start until V exceeds the

IN

undervoltage lockout threshold.

Watchdog Timer (WDI input, RST output)

Selecting the Reset Timing Capacitor

The LTC3256 includes a windowed watchdog function

that can continuously monitor the application’s logic or

microprocessorandissueautomaticresetstoaidrecovery

from unintended lockups or crashes. With the RSTI input

held above threshold, the application must periodically

toggle the logic state of the watchdog input (WDI pin) in

ordertoclearthewatchdogtimer. Specifically, successive

The reset timeout period can be set to a fixed internal

timer or programmed with a capacitor in order to accom-

modate a variety of applications. Connecting a capacitor,

C , between the RT pin and GND sets the reset timeout

RT

period,t .Thefollowingformulaapproximatesthevalue

RST

of capacitor needed for a particular timeout:

67pF

C_RT= t

−0.75ms •

)

(

RST

ms

For example, using a standard capacitor value of 2.2nF

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LTC3256

applicaTions inForMaTion

falling edges on the WDI pin must be spaced by more than

the watchdog lower boundary but less than the watchdog

upper boundary. As long as this condition holds, RST

remains high impedance.

The internal watchdog lower boundary can be calculated

from the internal watchdog reset time by the following:

t_WDR(INT)

t_WDL(INT)

=

32

If a falling edge arrives before the watchdog lower bound-

ary, or if the watchdog timer reaches the upper boundary

without seeing a falling edge on WDI, the watchdog timer

enters its reset state and asserts RST low for the reset

timeout period. Once the reset timeout completes, RST is

released to go high and the watchdog timer starts again.

The watchdog reset time is adjustable and can be opti-

mized for software execution. The watchdog reset time

is adjusted by connecting a capacitor, C , between the

WT

WT and GND pins. Given a desired watchdog reset time

t

, the capacitor value is approximately:

WDR

8.8nF

Duringpower-up,thewatchdogtimerremainsclearedwhile

RST is asserted low. As soon as the reset timer times out,

RST goes high and the watchdog timer is started.

C_WT= t

−3.8ms •

)

WDR

(

s

For example, using a standard capacitor value of 0.047μF

would give a 5.3s watchdog reset time. Shorting WT to

BIAS generates a timeout of approximately 1.6s. Connect-

ing WT to GND disables the watchdog function.

Setting the Watchdog Reset Time

The watchdog upper boundary (t

) and lower bound-

WDU

ary (t

) are not observable outside the part, only the

WDL

Power Good Output Operation (PG3, PG5 Outputs)

watchdog reset time (t

) of the part is observable via

WDR

A built-in dual supply monitor indicates which of the

OUT3 and OUT5 voltages are in regulation. The monitor

detects both overvoltage and undervoltage faults, report-

ing Power Good status via the PG3 and PG5 open-drain

outputs. These will be referred to as the PGx pins in the

description below.

the RSTpin. Thewatchdogupperboundary (t )occurs

WDU

one watchdog clock cycle before the watchdog reset time

(t ). The internal watchdog reset time consists of 8193

WDR

clock cycles, so the internal watchdog upper boundary

time is essentially the same as the internal watchdog reset

time.Converselytheexternalwatchdogresettimeconsists

of only 129 clock cycles, so the external watchdog upper

boundary should be more accurately calculated as:

If the LTC3256 is shut down (EN3 and EN5 both low) or

in undervoltage lockout, both PGx pins are pulled low.

Otherwise, behavior is as follows:

⎛

⎜

⎝

⎞

⎟

⎠

128

129

t

_WDU(EXT)= t_WDR(EXT)•

If the OUTx pin voltage is greater than the overvoltage

threshold or less than the undervoltage threshold, the

corresponding PGx pin will pull low. PGx becomes high

impedance when the OUTx pin voltage is between the

overvoltage and undervoltage thresholds. Hysteresis is

built into the overvoltage and undervoltage comparators

to ensure PGx holds it's state when in regulation.

Theexternalwatchdoglowerboundary(t

)occurs

WDR(EXT)

WDL(EXT)

five clock cycles into the watchdog reset time (t

).

Thus the external watchdog lower boundary can be calcu-

lated from the external watchdog reset time as:

⎛

⎜

⎝

⎞

⎟

⎠

5

129

t

_WDU(EXT)= t_WDR(EXT)•

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LTC3256

applicaTions inForMaTion

A pull-up resistor can be inserted between PGx and a valid

logicsupply(i.e. OUTCP, OUT5orOUT3)tosignalapower

good condition. The use of a large value pull-up resistor

on PGx and a capacitor placed between PGx and GND can

be used to delay the Power Good signal if desired.

ambient impedance well in excess of 40°C/W. See Linear

Technology's Application Notes for thermally Enhanced

Leaded packages.

Because of the wide input operating range it is possible to

exceed the specified operating junction temperature and

even reach thermal shutdown (175°C typ).

1.1V Reference Output (REFOUT Output)

The LTC3256 can operate up to 95°C at full load (I

=

OUT3

An internal bandgap voltage reference determines the

regulation voltages at OUT3 and OUT5. A buffered ver-

sion of this voltage reference appears at the REFOUT pin

when the LTC3256 is enabled. The output has a typical

impedance of 2k and can source but not sink current. To

maximize supply rejection, REFOUT should be bypassed

with a 0.1µF ceramic capacitor.

250mA, I

= 100mA) with V < 15V. Above 95°C, or

OUT5

IN

with input voltages greater than 15V, it is the responsibil-

ity of the user to calculate worst-case power dissipation

to make sure the LTC3256’s specified operating junction

temperature is not exceeded for extended periods of time.

Refer to the power dissipation equations provided earlier

for calculating power dissipation (P ) in the different

D

Thermal Management/Thermal Shutdown

modes of operation.

TheonchippowerdissipationintheLTC3256willcausethe

junction to ambient temperature to rise at rate of 40°C/W

or more. To reduce the maximum junction temperature, a

goodthermalconnectiontothePCboardisrecommended.

For example, if it is determined that the maximum power

dissipation (P ) is 1.2W under normal operation, then the

D

junction to ambient temperature rise will be:

Junction to Ambient = 1.2W • 40°C/W = 48°C

Connecting the die paddle (Pin 17) with multiple vias to a

largegroundplaneunderthedevicecanreducethethermal

resistanceofthepackageandPCboardconsiderably.Poor

board layout and failure to connect the die paddle (Pin 17)

to a large ground plane can result in thermal junction to

Thus,theambienttemperatureunderthisconditioncannot

exceed102°Cifthejunctiontemperatureistoremainbelow

150°Candiftheambienttemperatureexceedsabout127°C

the device will cycle in and out of the thermal shutdown.

3256fb

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For more information www.linear.com/LTC3256

LTC3256

package DescripTion

Please refer to http://www.linear.com/product/LTC3256#packaging for the most recent package drawings.

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev F)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ±0.102

(.112 ±.004)

2.845 ±0.102

(.112 ±.004)

0.889 ±0.127

(.035 ±.005)

1

8

0.35

REF

5.10

(.201)

MIN

1.651 ±0.102

(.065 ±.004)

1.651 ±0.102

(.065 ±.004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 ±0.038

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0.254

(.010)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0° – 6° TYP

4.90 ±0.152

(.193 ±.006)

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MSE16) 0213 REV F

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL

NOT EXCEED 0.254mm (.010") PER SIDE.

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18

For more information www.linear.com/LTC3256

LTC3256

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

08/16 Updated feature list

1

B

12/16 Changed Reset Timer Control (RT) conditions

Changed Watchdog Timer Control (WDT) conditions

Changed title of graph G12

3

4

6

Modified 5V Output from 2:1 Charge Pump section

14

3256fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

For more information www.linear.com/LTC3256

LTC3256

Typical applicaTion

Dual Power Supply with Sequenced Startup (3.3V, Then 5V)

10µF

1µF

+

–

C

OUTCP

OUT5

5V OUTPUT

100mA MAX

5.5V TO 38V

INPUT SUPPLY

V

IN

10µF

LTC3256

OUT3

3.3V LDO OUTPUT

250mA MAX

1M

10µF

PG3

EN5

10µF

EN3

RST

RSTI

RT

WT

MICROCONTROLLER

WDI

INTERFACE

REFOUT

PG5

0.01µF

6.8nF

GND

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC1144

Switched-Capacitor Wide Input Range Voltage Converter with

Shutdown

Wide Input Voltage Range: 2V to 18V, I < 8µA,

SD

SO8 Package

LTC1514/LTC1515

LTC1911

Step-Up/Step-Down Switched Capacitor DC/DC Converters

250mA, 1.5MHz Inductorless Step-Down DC/DC Converter

V : 2V to 10V, V : 3.3V to 5V, I = 60µA, SO8 Package

IN OUT Q

V : 2.7V to 5.5V, V

= 1.5V/1.8V, I = 180µA,

Q

IN

OUT

MS8 Package

LTC3250/LTC3250-1.2 Inductorless Step-Down DC/DC Converter

LTC3250-1.5

V : 3.1V to 5.5V, V

= 1.2V, 1.5V, I = 35µA,

Q

IN

OUT

ThinSOT™ Package

LTC3251

500mA Spread Spectrum Inductorless Step-Down DC/DC Converter V : 2.7V to 5.5V, V : 0.9V to 1.6V, 1.2V, 1.5V,

IN OUT

I = 9µA, MS10E Package

Q

LTC3252

Dual 250mA, Spread Spectrum Inductorless Step-Down DC/DC

Converter

V : 2.7V to 5.5V, V : 0.9V to 1.6V, I = 50µA,

IN

OUT

Q

DFN12 Package

LT^®1054/LT1054L

LTC3200/LTC3200-5

LTC3245

Switched Capacitor Voltage Converter with Regulator

V : 3.5V to 15V/7V, I

= 100mA/125mA, N8, S08,

IN

OUT

SO16 Packages

Low Noise Doubler Charge Pump

I

= 100mA, 2MHz Fixed Frequency, MS8 and ThinSOT

OUT

(LTC3200-5) Packages

Wide V Range, Low Noise, 250mA Buck-Boost Charge Pump

2.7V to 38V V Range, I = 18µA Operating, 4µA in

IN

Q

Shutdown, Multimode Operation (2:1, 1:1, 1:2) with

Automatic Mode Switching, 12V to 5V Efficiency = 81%,

Low Noise, Constant Frequency Operation

LTC3255

Wide V Range, Fault Protected 50mA Charge Pump

Input Voltage Range: 4V to 48V, Adjustable Regulated

Output: 2.4V to 12.5V, Output Current: 50mA Maximum,

16µA Quiescent Current in Regulation at No Load, Input

Fault Protection from –52V to 60V

IN

LTC3260

LTC3261

LTC3265

Low Noise Dual Supply Inverting Charge Pump

V : 4.5V to 32V, I

= 50mA, DE14, MSE16 Packages

= 100mA, MSE12 Package

IN

LDO

OUT

High Voltage, Low Quiescent Current Inverting Charge Pump

Low Noise Dual Supply with Boost and Inverting Charge Pumps

V : 4.5V to 32V, I

IN

Boost Charge Pump Generates 2-VIN_P (VIN_P Range:

4.5V to 16V) Inverting Charge Pump Generates –VIN_N

(VIN_N Range: 4.5V to 32V)

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LT 1216 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

For more information www.linear.com/LTC3256

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3256

●

 LINEAR TECHNOLOGY CORPORATION 2016


型号：	LTC3256EMSE#PBF
厂家：	Linear
描述：	LTC3256 - Wide VIN Range Dual Output 350mA Step-Down Charge Pump with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管输出元件
文件：	总20页 (文件大小：678K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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