LTC3407AEMSE-2#PBF [Linear]
LTC3407A-2 - Dual Synchronous 800mA, 2.25MHz Step-Down DC/DC Regulator; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3407AEMSE-2#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3407A-2 - Dual Synchronous 800mA, 2.25MHz Step-Down DC/DC Regulator; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管 |
| 文件： | 总16页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3407A-2
Dual Synchronous 800mA,
2.25MHz Step-Down
DC/DC Regulator
U
DESCRIPTIO
FEATURES
The LTC®3407A-2 is a dual, constant frequency, synchro-
nousstep-downDC/DCconverter. Intendedforlowpower
applications, it operates from a 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
enabling the use of tiny, low cost capacitors and inductors
1mm or less in height. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power
switches provide high efficiency without the need for
external Schottky diodes.
■
High Efficiency: Up to 95%
■
Low Ripple (<35mVPK-PK) Burst Mode Operation;
IQ = 40μA
■
2.25MHz Constant Frequency Operation
■
No Schottky Diodes Required
■
Low RDS(ON) Internal Switches: 0.35Ω
■
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
■
■
Low Dropout Operation: 100% Duty Cycle
A user selectable mode input is provided to allow the user
to trade-off ripple noise for low power efficiency. Burst
Mode® operation provides the highest efficiency at light
loads, while Pulse Skip Mode provides the lowest ripple
noise at light loads.
■
Ultralow Shutdown Current: IQ <1μA
■
Output Voltages from 5V down to 0.6V
■
Power-On Reset Output
■
Externally Synchronizable Oscillator
■
Optional External Soft-Start
■
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages
U
APPLICATIO S
■
PDAs/Palmtop PCs
■
Digital Cameras
■
Cellular Phones
Wireless and DSL Modems
■
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TYPICAL APPLICATIO
1mm High 2.5V/1.8V at 800mA Step-Down Regulators
Efficiency/Power Loss Curve
100
90
1
2.5V
V = 2.5V
IN
TO 5.5V
1.8V
80
100k
10μF
0.1
RUN/SS2
V
RUN/SS1
POR
IN
70
MODE/SYNC
RESET
60
LTC3407A-2
50
40
0.01
0.001
0.0001
2.2μH
2.2μH
V
OUT2
= 2.5V
V
= 1.8V
OUT1
SW2
SW1
AT 800mA
AT 800mA
22pF
887k
22pF
887k
30
20
V
= 3.3V
IN
Burst Mode OPERATION
V
FB1
V
FB2
10
0
NO LOAD ON OTHER CHANNEL
GND
280k
442k
10μF
10μF
1
10
100
1000
LOAD CURRENT (mA)
3407A2 TA02
3407A2 TA01
3407a2f
1
LTC3407A-2
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Operating Temperature Range (Note 2)
VIN Voltage ..................................................–0.3V to 6V
VFB1, VFB2 Voltages...................................–0.3V to 1.5V
RUN/SS1, RUN/SS2 Voltages ..................... –0.3V to VIN
MODE/SYNC Voltage ..................................–0.3V to VIN
SW1, SW2 Voltages ....................... –0.3V to VIN + 0.3V
POR Voltage ................................................–0.3V to 6V
LTC3407AE-2 ..................................... –40°C to 85°C
LTC3407AI-2 .................................... –40°C to 125°C
Junction Temperature (Note 5)............................. 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
LTC3407AEMSE-2 ............................................ 300°C
LTC3407AIMSE-2............................................. 300°C
U
U
U
PI CO FIGURATIO
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10
V
FB2
FB1
V
1
10 V
FB2
FB1
RUN/SS1
9
8
7
6
RUN/SS2
RUN/SS1 2
9
8
7
6
RUN/SS2
POR
11
V
POR
IN
11
V
3
IN
SW1 4
GND 5
SW2
SW1
GND
SW2
MODE/SYNC
MODE/SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
U
W
U
ORDER I FOR ATIO
LEAD FREE FINISH
LTC3407AEDD-2#PBF
LTC3407AEMSE-2#PBF
LTC3407AIDD-2#PBF
LTC3407AIMSE-2#PBF
LEAD BASED FINISH
LTC3407AEDD-2
TAPE AND REEL
PART MARKING*
LDDH
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 85°C
LTC3407AEDD-2#TRPBF
LTC3407AEMSE-2#TRPBF
LTC3407AIDD-2#TRPBF
LTC3407AIMSE-2#TRPBF
TAPE AND REEL
LTDDJ
10-Lead Plastic MSOP
–40°C to 85°C
LDDH
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 85°C
LTDDJ
PART MARKING*
LDDH
PACKAGE DESCRIPTION
LTC3407AEDD-2#TR
LTC3407AEMSE-2#TR
LTC3407AIDD-2#TR
LTC3407AIMSE-2#TR
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTC3407AEMSE-2
LTC3407AIDD-2
LTDDJ
–40°C to 85°C
LDDH
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
LTC3407AIMSE-2
LTDDJ
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3407a2f
2
LTC3407A-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage (Note 3)
●
●
2.5
IN
I
30
nA
FB
V
0°C ≤ T ≤ 85°C
0.588
0.585
0.6
0.6
0.612
0.612
V
V
FB
A
–40°C ≤ T ≤ 125°C (Note 2)
●
A
ΔV
ΔV
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.5V to 5.5V (Note 3)
IN
0.3
0.5
0.5
%/V
%
LINE REG
MODE/SYNC = 0V (Note 3)
LOAD REG
I
Input DC Supply Current
Active Mode
(Note 4)
S
V
V
= V = 0.5V
= V = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, V = 5.5V, MODE/SYNC = 0V
700
40
0.1
950
60
1
μA
μA
μA
FB1
FB1
FB2
Sleep Mode
Shutdown
FB2
IN
f
f
I
Oscillator Frequency
V
= 0.6V
FBX
●
1.8
1
2.25
2.25
1.2
2.7
MHz
MHz
A
OSC
SYNC
LIM
Synchronization Frequency
Peak Switch Current Limit
V
= 3V, V = 0.5V, Duty Cycle <35%
1.6
IN
FBX
R
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
DS(ON)
I
Switch Leakage Current
V
= 5V, V
= 0V, V = 0V
0.01
1
μA
SW(LKG)
IN
RUN
FBX
POR
Power-On Reset Threshold
V
V
Ramping Up, MODE/SYNC = 0V
Ramping Down, MODE/SYNC = 0V
8.5
–8.5
%
%
FBX
FBX
Power-On Reset On-Resistance
Power-On Reset Delay
100
65,536
1
200
Ω
Cycles
V
RUN/SS Threshold Low
RUN/SS Threshold High
●
●
0.3
0
1.5
2
V
V
RUN
I
RUN/SS Leakage Current
MODE Threshold Low
MODE Threshold High
●
0.01
1
μA
V
RUN
V
0.5
MODE
V
– 0.5
V
IN
V
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3407A-2 is tested in a proprietary test mode that connects
to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
V
FB
Note 2: The LTC3407AE-2 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407AI-2 is guaranteed over the
full –40°C to 125°C operating temperature range.
Note 5: T is calculated from the ambient T and power dissipation P
J
A
D
according to the following formula: T = T + (P • θ ).
J
A
D
JA
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
3407a2f
3
LTC3407A-2
U W
TA = 25°C unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
SW
5V/DIV
SW
5V/DIV
V
OUT
50mV/DIV
V
OUT
10mV/DIV
I
L
I
200mA/DIV
L
100mA/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
3407A2 G01
3407A2 G02
= 1.8V
2μs/DIV
= 1.8V
1μs/DIV
= 50mA
= 50mA
LOAD
LOAD
CIRCUIT OF FIGURE 3
CIRCUIT OF FIGURE 3
Load Step
Soft Start
V
OUT1
200mV/DIV
V
IN
2V/DIV
V
OUT2
100mV/DIV
V
OUT1
I
L
1V/DIV
500mA/DIV
I
L
I
LOAD
500mA/DIV
500mA/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
3407A2 G16
3407A2 G03
1ms/DIV
20μs/DIV
= 50mA TO 600mA
= 500mA
LOAD
LOAD
CIRCUIT OF FIGURE 3
CIRCUIT OF FIGURE 4
Oscillator Frequency vs
Temperature
Oscillator Frequency vs Supply
Voltage
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
10
8
2.5
2.4
2.3
2.2
2.1
2.0
100mA
V
= 3.6V
IN
800mA
10mA
1mA
6
4
2
0
–2
–4
–6
–8
V
= 1.8V
OUT
CIRCUIT OF FIGURE 3
–10
2
3
4
5
6
4
5
6
2
3
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
3407A2 G04
3407A2 G06
3407A2 G05
3407a2f
4
LTC3407A-2
U W
TA = 25°C unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage vs
Temperature
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
0.615
0.610
0.605
0.600
0.595
0.590
0.585
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
150
100
V
= 2.7V
V
= 3.6V
IN
IN
V
= 3.6V
IN
V
= 4.2V
IN
MAIN
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
3
5
7
50
TEMPERATURE (°C)
100 125 150
1
2
4
6
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
V
IN
(V)
3407A2 G08
3407A2 G09
3407A2 G07
Load Regulation
Efficiency vs Load Current
Efficiency vs Load Current
4
3
100
90
80
70
60
100
90
80
70
60
2.7V
Burst Mode OPERATION
4.2V
3.3V
2
Burst Mode OPERATION
PULSE SKIP MODE
1
PULSE SKIP MODE
0
50
40
50
40
–1
–2
–3
–4
30
20
30
20
V
= 3.6V, V
= 1.8V
OUT
V
= 3.6V, V
= 1.8V
OUT
IN
IN
10
0
V
= 2.5V Burst Mode OPERATION
10
0
OUT
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
1
10
100
1000
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3407A2 G12
3407A2 G10
3407A2 G11
Line Regulation
Efficiency vs Load Current
Efficiency vs Load Current
0.5
0.4
100
90
80
70
60
100
90
80
70
60
V
= 1.8V
= 200mA
3.3V
OUT
OUT
3.3V
2.7V
I
2.7V
4.2V
0.3
4.2V
0.2
0.1
50
40
0
50
40
–0.1
–0.2
–0.3
–0.4
–0.5
30
20
30
20
10
0
10
0
V
OUT
= 1.5V Burst Mode OPERATION
V
= 1.2V Burst Mode OPERATION
OUT
1
10
100
1000
2
6
3
4
5
1
10
100
1000
LOAD CURRENT (mA)
V
(V)
LOAD CURRENT (mA)
3407A2 G15
IN
3407A2 G14
3407A2 G13
3407a2f
5
LTC3407A-2
U
U
U
PI FU CTIO S
VFB1 (Pin 1): Output Feedback. Receives the feedback besynchronizedtoanexternaloscillatorappliedtothispin
voltage from the external resistive divider across the and pulse skipping mode is automatically selected.
output. Nominal voltage for this pin is 0.6V.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
RUN/SS1(Pin2):Regulator1EnableandSoft-StartInput. Inductor. This pin swings from VIN to GND.
Forcing this pin to VIN enables regulator 1, while forcing it
POR (Pin 8): Power-On Reset. This common-drain logic
to GND causes regulator 1 to shut down. Connect external
output is pulled to GND when the output voltage is not
RC-network with desired time-constant to enable soft-
within ±8.5% of regulation and goes high after 216 clock
start feature. This pin must be driven; do not float.
cycles when both channels are within regulation.
VIN (Pin3):MainPowerSupply.Mustbecloselydecoupled
RUN/SS2(Pin9):Regulator2EnableandSoft-StartInput.
to GND.
Forcing this pin to VIN enables regulator 2, while forcing it
SW1 (Pin 4): Regulator 1 Switch Node Connection to the to GND causes regulator 2 to shut down. Connect external
Inductor. This pin swings from VIN to GND.
RC-Network with desired time-constant to enable soft-
start feature. This pin must be driven; do not float.
GND (Pin 5): Main Ground. Connect to the (–) terminal of
C
OUT, and (–) terminal of CIN.
VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
MODE/SYNC (Pin 6): Combination Mode Selection and
OscillatorSynchronization.Thispincontrolstheoperation
of the device. When tied to VIN or GND, Burst Mode Exposed Pad (GND) (Pin 11): Power Ground. Connect to
operation or pulse skipping mode is selected, respec- the (–) terminal of COUT, and (–) terminal of CIN. Must be
tively. Do not float this pin. The oscillation frequency can soldered to electrical ground on PCB.
W
BLOCK DIAGRA
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
V
IN
SLOPE
COMP
EN
–
+
+
–
0.6V
SLEEP
–
+
I
TH
5Ω
EA
I
COMP
0.65V
V
FB1
1
BURST
Q
S
R
RS
LATCH
0.55V
–
+
UV
OV
UVDET
OVDET
Q
SWITCHING
LOGIC
ANTI
SHOOT-
THRU
AND
BLANKING
CIRCUIT
4
SW1
+
–
+
–
0.65V
I
RCMP
11 GND
SHUTDOWN
3
8
V
IN
V
IN
PGOOD1
POR
2
RUN/SS1
RUN/SS2
POR
COUNTER
0.6V REF
OSC
9
OSC
5
7
GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
10
SW2
V
FB2
3407A2 BD
3407a2f
6
LTC3407A-2
U
OPERATIO
TheLTC3407A-2usesaconstantfrequency,currentmode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable MODE/SYNC pin
allows the user to trade-off noise for efficiency.
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are domi-
natedbythegatechargelossesofthepowerMOSFETsare
minimized. The main control loop is interrupted when the
output voltage reaches the desired regulated value. A
voltage comparator trips when ITH is below 0.65V, shut-
ting off the switch and reducing the power. The output
capacitor and the inductor supply the power to the load
untilITH exceeds0.65V,turningontheswitchandthemain
control loop which starts another cycle.
The output voltage is set by an external divider returned to
the VFB pins. An error amplifier compares the divided
outputvoltagewithareferencevoltageof0.6Vandadjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
willgohighafter65,536clockcycles(about29msinpulse
skipping mode) of achieving regulation.
For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3407A-2 contin-
ues to switch at a constant frequency down to very low
currents, where it will begin skipping pulses.
Main Control Loop
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the reference voltage. The
current into the inductor and the load increases until the
current limit is reached. The switch turns off and energy
storedintheinductorflowsthroughthebottomswitch(N-
channel MOSFET) into the load until the next clock cycle.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error
amplifier.This amplifier compares the VFB pin to the 0.6V
reference. When the load current increases, the VFB volt-
age decreases slightly below the reference. This
decrease causes the error amplifier to increase the ITH
voltageuntiltheaverageinductorcurrentmatchesthenew
load current.
An important design consideration is that the RDS(ON) of
the P-channel switch increases with decreasing input
supplyvoltage(SeeTypicalPerformanceCharacteristics).
Therefore, the user should calculate the power dissipation
whentheLTC3407A-2isusedat100%dutycyclewithlow
input voltage (See Thermal Considerations in the Applica-
tions Information Section).
The main control loop is shut down by pulling the RUN/SS
pin to ground.
Low Supply Operation
The LTC3407A-2 incorporates an undervoltage lockout
circuit which shuts down the part when the input voltage
drops below about 1.65V to prevent unstable operation.
Low Current Operation
Two modes are available to control the operation of the
LTC3407A-2 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
A general LTC3407A-2 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT can
be selected.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407A-2
3407a2f
7
LTC3407A-2
U
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APPLICATIO S I FOR ATIO
Inductor Selection
Input Capacitor (CIN) Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ΔIL decreases with
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT
/
VIN. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
higher inductance and increases with higher VIN or VOUT
:
⎛
⎞
VOUT
fO •L
VOUT
ΔIL =
• 1–
⎜
⎝
⎟
V
⎠
IN
VOUT(V – VOUT
)
IN
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
ΔIL = 0.3 • ILIM, where ILIM is the peak switch current limit.
The largest ripple current ΔIL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
IRMS ≈IMAX
V
IN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple cur-
rent, IMAX = ILIM – ΔIL/2.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case is commonly used
to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
thanrequired. Severalcapacitorsmayalsobeparalleledto
meet the size or height requirements of the design. An
additional 0.1μF to 1μF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
⎛
⎞
VOUT
fO • ΔIL
VOUT
L =
• 1–
⎜
⎟
V
⎝
⎠
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation be-
gins when the peak inductor current falls below a level set
by the burst clamp. Lower inductor values result in higher
ripple current which causes this transition to occur at
lower load currents. This causes a dip in efficiency in the
upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
Table 1. Representative Surface Mount Inductors
MANU-
MAX DC
FACTURER PART NUMBER VALUE CURRENT
DCR
HEIGHT
Taiyo Yuden CB2016T2R2M
CB2012T2R2M
2.2μH
2.2μH
3.3μH
510mA
530mA
410mA
0.13Ω 1.6mm
0.33Ω 1.25mm
0.27Ω 1.6mm
Inductor Core Selection
CB2016T3R3M
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI require-
ments than on what the LTC3407A-2 requires to operate.
Table 1 shows some typical surface mount inductors that
work well in LTC3407A-2 applications.
Panasonic ELT5KT4R7M
4.7μH
4.7μH
950mA
0.2Ω
1.2mm
2mm
Sumida
Murata
CDRH2D18/LD
630mA 0.086Ω
LQH32CN4R7M23 4.7μH
450mA
0.2Ω
2mm
Taiyo Yuden NR30102R2M
NR30104R7M
2.2μH 1100mA
4.7μH
0.1Ω
0.19Ω
1mm
1mm
750mA
FDK
FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7μH 1100mA 0.11Ω
3.3μH 1200mA 0.1Ω
2.2μH 1300mA 0.08Ω
1mm
1mm
1mm
TDK
VLF3010AT4R7- 4.7μH
MR70
700mA
0.28Ω
1mm
1mm
1mm
VLF3010AT3R3- 3.3μH
MR87
VLF3010AT2R2- 2.2μH 1000mA 0.12Ω
M1R0
870mA
0.17Ω
3407a2f
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APPLICATIO S I FOR ATIO
Output Capacitor (COUT) Selection
trace inductance can lead to significant ringing. Other
capacitor types include the Panasonic Special Polymer
(SP) capacitors.
The selection of COUT is driven by the required ESR to
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (ΔVOUT) is deter-
mined by:
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407A-2 in parallel with the
main capacitors for high frequency decoupling.
V
= 2.5V TO 5.5V
IN
⎛
⎞
1
C
R7
ΔVOUT ≈ ΔIL ESR+
IN
V
⎜
⎝
⎟
IN
BURST*
R6
R5
8fO COUT
⎠
POWER-ON
RESET
MODE/SYNC
POR
RUN/SS1
SW1
PULSESKIP*
LTC3407A-2
RUN/SS2
wherefO =operatingfrequency,COUT =outputcapacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔIL increases
with input voltage. With ΔIL = 0.3 • ILIM the output ripple
willbelessthan100mVatmaximumVIN andfO =2.25MHz
with:
L1
L2
C2
V
V
OUT2
C4
OUT1
SW2
C1
R2
C3
V
V
FB1
FB2
R4
R3
GND
R1
C
C
OUT1
OUT2
3407A2 F01
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V : Burst Mode
ESRCOUT < 150mΩ
IN
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
Figure 1. LTC3407A-2 General Schematic
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, TDK,
and Murata.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
numelectrolytic,specialpolymer,ceramicanddrytantulum
capacitorsareallavailableinsurfacemountpackages.The
OS-CONsemiconductordielectriccapacitoravailablefrom
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
capacitors, such as Sanyo POSCAP, offer very low ESR,
but have a lower capacitance density than other types.
Tantalumcapacitorshavethehighestcapacitancedensity.
However, they also have a larger ESR and it is critical that
they are surge tested for use in switching power supplies.
AnexcellentchoiceistheAVXTPSseriesofsurfacemount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a signifi-
cantly larger ESR, and are often used in extremely cost-
sensitiveapplicationsprovidedthatconsiderationisgiven
to ripple current ratings and long term reliability. Ceramic
capacitorshavethelowestESRandcost, butalsohavethe
lowest capacitance density, a high voltage and tempera-
ture coefficient, and exhibit audible piezoelectric effects.
In addition, the high Q of ceramic capacitors along with
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires,suchasfromawalladapter,aloadstepattheoutput
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
3407a2f
9
LTC3407A-2
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APPLICATIO S I FOR ATIO
At worst, the ringing at the input can be large enough to
damage the part.
Power-On Reset
ThePORpinisanopen-drainoutputwhichpullslowwhen
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 216 clock cycles (about 29ms in
pulse skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can be
bypassed by tying the POR output to the MODE/SYNC
input, to force pulse skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. Thiscanbeavoidedbyusingpulseskippingmode
instead. When either channel is shut down, the POR
output is pulled low, since one or both of the channels are
not in regulation.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
untilthefeedbackloopraisestheswitchcurrentenoughto
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP, is usually
about3timesthelineardropofthefirstcycle.Thus,agood
place to start is with the output capacitor size of approxi-
mately:
ΔIOUT
COUT ≈3
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
Mode Selection & Frequency Synchronization
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10μF ceramic
capacitor is usually enough for these conditions.
TheMODE/SYNCpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higheroutputvoltageripple. Whenthispinisconnectedto
ground, pulse skipping operation is selected which pro-
vides the lowest output ripple, at the cost of low current
efficiency.
Setting the Output Voltage
The LTC3407A-2 develops a 0.6V reference voltage be-
tween the feedback pin, VFB, and ground as shown in
Figure 1. The output voltage is set by a resistive divider
according to the following formula:
The LTC3407A-2 can also be synchronized to another
LTC3407A-2 by the MODE/SYNC pin. During synchroni-
zation, themodeissettopulseskippingandthetopswitch
turn-on is synchronized to the rising edge of the external
clock.
R2
R1
⎛
⎝
⎞
VOUT = 0.6V 1+
⎜
⎟
⎠
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD • ESR, where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
theregulatortoreturnVOUTtoitssteady-statevalue.During
3407a2f
To improve the frequency response, a feed-forward ca-
pacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
10
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APPLICATIO S I FOR ATIO
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
Forapproximatelya1msramptime, useRSS =4.7MΩand
CSS = 680pF at VIN = 3.3V.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phasemargin. Inaddition, afeed-forwardcapacitorcanbe
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creating high frequency zeros with R2 and R4 respec-
tively, which improve the phase margin.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
%Efficiency = 100% - (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
lossesinLTC3407A-2circuits:1)VIN quiescentcurrent, 2)
switching losses, 3) I2R losses, 4) other losses.
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input
capacitors.Thedischargedinputcapacitorsareeffectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot SwapTM controller is
designedspecificallyforthispurposeandusuallyincorpo-
rates current limiting, short-circuit protection, and soft-
starting.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
andcontrolcurrents.VIN currentresultsinasmall(<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continu-
ousmode, IGATECHG =fO(QT +QB), whereQT andQB arethe
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuousmode,theaverageoutputcurrentflowsthrough
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
Soft-Start
The RUN/SS pins provide a means to separately run or
shutdownthetworegulators.Inaddition,theycanoption-
ally be used to externally control the rate at which each
regulator starts up and shuts down. Pulling the RUN/SS1
pin below 1V shuts down regulator 1 on the LTC3407A-2.
Forcing this pin to VIN enables regulator 1. In order to
control the rate at which each regulator turns on and off,
connect a resistor and capacitor to the RUN/SS pins as
shown in Figure 1. The soft-start duration can be calcu-
lated by using the following formula:
⎛
⎞
V −1
IN
tSS = RSSCSSIn
(s)
⎜
⎟
V −1.6
⎝
⎠
IN
Hot Swap is a registered trademark of Linear Technology Corporation.
3407a2f
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the SW pin is a function of both top and bottom MOSFET
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
RDS(ON) and the duty cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
As an example, consider the case when the LTC3407A-2
is in dropout on both channels at an input voltage of 2.7V
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the RDS(ON) resistance of the
main switch is 0.425Ω. Therefore, power dissipated by
each channel is:
I2R losses = IOUT2(RSW + RL)
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
PD = I2 • RDS(ON) = 272mW
The MS package junction-to-ambient thermal resistance,
θJA, is 45°C/W. Therefore, the junction temperature of the
regulator operating in a 70°C ambient temperature is
approximately:
Thermal Considerations
TJ = 2 • 0.272 • 45 + 70 = 94.5°C
which is below the absolute maximum junction tempera-
In a majority of applications, the LTC3407A-2 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3407A-2 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
ture of 125°C.
Design Example
As a design example, consider using the LTC3407A-2 in a
portable application with a Li-Ion battery. The battery
provides a VIN = 2.8V to 4.2V. The load requires a maxi-
mum of 800mA in active mode and 2mA in standby mode.
The output voltage is VOUT = 2.5V. Since the load still
needs power in standby, Burst Mode operation is selected
for good low load efficiency.
TopreventtheLTC3407A-2fromexceedingthemaximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
2.5V
2.25MHz •360mA
2.5V
4.2V
⎛
⎝
⎞
L =
• 1–
= 1.25μH
⎜
⎟
⎠
TRISE = PD • θJA
3407a2f
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LTC3407A-2
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APPLICATIO S I FOR ATIO
Choosing the next highest standardized inductor value of
LTC3407A-2. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
2.2μH, results in a maximum ripple current of:
2.5V
2.25MHz •2.2μH
2.5V
4.2V
⎛
⎝
⎞
ΔIL =
• 1−
= 204mA
1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (exposed pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
⎜
⎟
⎠
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
2. Are COUT and L1 closely connected? The (–) plate of
C
OUT returns current to GND and the (–) plate of CIN.
800mA
2.25MHz •(5%•2.5V)
COUT ≈2.5
= 7.1μF
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of COUT and a ground
sense line terminated near GND (exposed pad). The feed-
back signals VFB1 and VFB2 should be routed away from
noisy components and traces, such as the SW lines (Pins
4 and 7), and their traces should be minimized.
The closest standard value is 10μF. Since the output
impedance of a Li-Ion battery is very low, CIN is typically
10μF.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.
4.KeepsensitivecomponentsawayfromtheSWpins.The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point.
Addtionally the two grounds should not share the high
ThePORpinisacommondrainoutputandrequiresapull-
up resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example. The specific passive components chosen allow
for a 1mm height power supply that maintains a high
efficiency across load.
current paths of CIN or COUT
.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to VIN or GND.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
V
IN
C
IN
RUN/SS2
V
RUN/SS1
POR
IN
MODE/SYNC
LTC3407A-2
L1
C4
L2
V
SW2
SW1
V
OUT1
OUT2
C5
R4
V
V
FB1
FB2
R2
GND
R1
C
C
R3
OUT1
OUT2
3407A2 F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 2. LTC3407A-2 Layout Diagram (See Board Layout Checklist)
3407a2f
13
LTC3407A-2
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TYPICAL APPLICATIO S
V
= 2.5V
IN
TO 5.5V
R5
C1
Efficiency vs Load Current
100k
10μF
RUN/SS2
V
RUN/SS1
POR
IN
100
90
80
70
60
POWER-ON
RESET
MODE/SYNC
2.5V
1.8V
LTC3407A-2
L2
L1
2.2μH
2.2μH
V = 2.5V
OUT2
AT 800mA
V
= 1.8V
OUT1
SW2
SW1
AT 800mA
C5, 22pF
C4, 22pF
50
40
V
V
FB2
FB1
R4
887k
R2
604k
GND
C3
10μF
C2
10μF
R3
280k
R1
301k
30
20
V
= 3.3V
IN
Burst Mode OPERATION
10
0
NO LOAD ON OTHER CHANNEL
3407A2 TA03
C1, C2, C3: TAIYO YUDEN JMK316BJ106MD
L1, L2: TDK VLF3010AT-2R2M1R0
1
10
100
1000
LOAD CURRENT (mA)
3407A2 TA03b
Figure 3. 1mm Height Core Supply
Efficiency vs Load Current
V
= 2.5V TO 5.5V
IN
100
90
80
70
60
R7
C
IN
10μF
R6
4.7MΩ
R5
4.7MΩ
100k
2.5V
V
IN
POWER-ON
RESET
1.2V
POR
LTC3407A-2
RUN/SS2
SW2
RUN/SS1
L2
4.7μH
L1
4.7μH
50
40
V
= 2.5V
V
= 1.2V
OUT1
AT 800mA
OUT2
AT 800mA
SW1
C2, 22pF
C1, 22pF
30
20
C4
680pF
C3
680pF
V
= 3.3V
V
IN
V
FB1
FB2
Burst Mode OPERATION
R4
887k
R2
604k
10
0
MODE/SYNC GND
C
OUT2
10μF
C
NO LOAD ON OTHER CHANNEL
R3
280k
R1
604k
OUT1
10μF
1
10
100
1000
LOAD CURRENT (mA)
3407A2 TA04b
3407A2 TA04
C
, C
, C
TAIYO YUDEN JMK316BJ106ML
L1, L2: TDK VLF3012AT-4R7M74
IN OUT1 OUT2:
Figure 4. Low Ripple Buck Regulators with Soft-Start
3407a2f
14
LTC3407A-2
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PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
0.38 ± 0.10
TYP
6
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
REF
(.081 ± .004)
1
10 9
8
7 6
1.83 ± 0.102
(.072 ± .004)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
DETAIL “A”
0° – 6° TYP
5.23
(.206)
MIN
4.90 ± 0.152
(.193 ± .006)
2.083 ± 0.102
3.20 – 3.45
0.254
(.010)
(.082 ± .004) (.126 – .136)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1
2
3
4
5
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
SEATING
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
0.50
(.0197)
BSC
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3407a2f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3407A-2
U
TYPICAL APPLICATIO
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
V = 2.8V
IN
TO 4.2V
R5
100k
C1
10μF
RUN/SS2
V
RUN/SS1
POR
IN
POWER-ON
RESET
MODE/SYNC
LTC3407A-2
L2
10μH
L1
2.2μH
D1
V = 3.3V
OUT2
AT 200mA
V
= 1.8V
OUT1
SW2
SW1
AT 800mA
C4, 22pF
M1
+
C6
47μF
V
FB1
V
FB2
R4
887k
R2
887k
GND
C3
10μF
C2
10μF
R3
196k
R1
442k
3407A TA05
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302
Efficiency vs Load Current
Efficiency vs Load Current
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
3.6V
4.2V
2.8V
2.8V
4.2V
3.6V
50
40
30
20
V
= 3.3V
V
= 1.8V
OUT
OUT
Burst Mode OPERATION
Burst Mode OPERATION
10
0
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3407A2 TA05a
3407A2 TA05b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
96% Efficiency, V : 2.5V to 5.5V, V
LTC3405/LTC3405A
300mA (I ), 1.5MHz,
Synchronous Step-Down DC/DC Converter
= 0.8V, I = 20μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
I
<1μA, ThinSOT Package
SD
LTC3406/LTC3406B
LTC3407/LTC3407-2
600mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
<1μA, ThinSOT Package
SD
600mA/800mA (I ), 1.5MHz/2.25MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA,
Q
OUT
IN
LTC3407-3/LTC3407-4/ Dual Synchronous Step-Down DC/DC Converter
LTC3407A
I
<1μA, MS10E Package, DFN Package
SD
LTC3410/LTC3410B
300mA (I ), 2.25MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 26μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
Synchronous Step-Down DC/DC Converter in SC70
I
<1μA, SC70 Package
SD
LTC3411
1.25A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
<1μA, MSOP-10 Package
SD
LTC3412/LTC3412A
LTC3414
2.5A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
<1μA, TSSOP-16E Package
SD
4A (I ), 4MHz,
95% Efficiency, V : 2.25V to 5.5V, V
= 0.8V, I = 64μA,
OUT(MIN) Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
<1μA, TSSOP-28E Package
SD
LTC3440/LTC3441
LTC3548/
600mA/1.2A (I ), 2MHz/1MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 2.5V, I = 25μA,
Q
OUT
IN
OUT(MIN)
Synchronous Buck-Boost DC/DC Converter
I
<1μA, MSOP-10 Package/DFN Package
400mA/800mA (I ), 2.25MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.6V, I = 40μA,
Q
OUT
IN
OUT(MIN)
LTC3548-1/LTC3548-2 Dual Synchronous Step-Down DC/DC Converter
I
<1μA, MS10E Package/DFN Package
3407a2f
LT 0907 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
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