LTC3407A [Linear]
Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator; 双同步600毫安，为1.5MHz降压型DC / DC稳压器
| 型号： | LTC3407A |
| 厂家： | 
Linear |
| 描述： | Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator |
| 文件： | 总16页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3407A
Dual Synchronous 600mA,
1.5MHz Step-Down
DC/DC Regulator
DESCRIPTION
FEATURES
n
High Efficiency: Up to 96%
TheLTC®3407Aisadual,constantfrequency,synchronous
step-down DC/DC converter. Intended for low power ap-
plications, it operates from a 2.5V to 5.5V input voltage
range and has a constant 1.5MHz switching frequency,
enabling the use of tiny, low cost capacitors and inductors
1mm or less in height. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power
switches provide high efficiency without the need for
external Schottky diodes.
n
Low Ripple (35mV ) Burst Mode Operation;
Q
1.5MHz Constant Frequency Operation
No Schottky Diodes Required
P-P
I = 40μA
n
n
n
n
Low R
Internal Switches: 0.35Ω
DS(ON)
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: I < 1μA
n
n
n
n
n
n
n
n
A user selectable mode input is provided to allow the user
to trade-off ripple noise for low power efficiency. Burst
Mode® operation provides the highest efficiency at light
loads, while Pulse Skip Mode provides the lowest ripple
noise at light loads.
Q
Output Voltages from 5V down to 0.6V
Power-On Reset Output
Externally Synchronizable Oscillator
Optional External Soft-Start
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
APPLICATIONS
n
PDAs/Palmtop PCs
n
Digital Cameras
n
Cellular Phones
Wireless and DSL Modems
n
TYPICAL APPLICATION
1mm High 2.5V/1.8V at 600mA Step-Down Regulators
LTC3407A Efficiency/Power Loss Curve
100
1
V = 2.5V
IN
TO 5.5V
2.5V
90
1.8V
80
100k
10μF
0.1
RUN/SS2
V
IN
RUN/SS1
70
MODE/SYNC
POR
RESET
60
LTC3407A
50
40
0.01
0.001
0.0001
2.2μH
2.2μH
V
= 2.5V
V
= 1.8V
OUT1
OUT2
SW2
SW1
AT 600mA
AT 600mA
22pF
887k
22pF
30
20
V
= 3.3V
IN
Burst Mode OPERATION
V
FB1
V
10
0
FB2
NO LOAD ON OTHER CHANNEL
887k
GND
280k
442k
10μF
10μF
1
10
100
1000
LOAD CURRENT (mA)
3407A TA02
3407A TA01
3407afa
1
LTC3407A
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V Voltage...................................................–0.3V to 6V
FB1 FB2
Operating Temperature Range (Note 2)
IN
V
, V Voltages................................... –0.3V to 1.5V
LTC3407AE .......................................... –40°C to 85°C
LTC3407AI ......................................... –40°C to 125°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range...................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
RUN/SS1, RUN/SS2 Voltages ......................–0.3V to V
MODE/SYNC Voltage....................................–0.3V to V
IN
IN
SW1, SW2 Voltages......................... –0.3V to V + 0.3V
IN
POR Voltage................................................. –0.3V to 6V
LTC3407AMSE Only.......................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10
9
V
FB2
FB1
V
1
2
3
4
5
10
9
V
FB2
FB1
RUN/SS1
RUN/SS2
POR
RUN/SS1
RUN/SS2
POR
V
IN
11
8
11
V
SW1
GND
8
IN
7
6
SW2
MODE/
SYNC
SW1
GND
7
SW2
6
MODE/
SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD IS PGND (PIN 11)
MUST BE CONNECTED TO GND
EXPOSED PAD IS PGND (PIN 11)
MUST BE CONNECTED TO GND
T
= 125°C, θ = 45°C/W, θ = 10°C/W
JMAX
JA JC
T
= 125°C, θ = 45°C/W, θ = 10°C/W
JA JC
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC3407AEDD#PBF
LTC3407AIDD#PBF
LTC3407AEMSE#PBF
LTC3407AIMSE#PBF
TAPE AND REEL
PART MARKING*
LCQN
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3407AEDD#TRPBF
LTC3407AIDD#TRPBF
LTC3407AEMSE#TRPBF
LTC3407AIMSE#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LCQN
–40°C to 125°C
–40°C to 85°C
LTCRZ
LTCRZ
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage (Note 3)
●
●
2.5
IN
I
FB
30
nA
V
0°C ≤ T ≤ 85°C
0.588
0.585
0.6
0.6
0.612
0.612
V
V
FB
A
–40°C ≤ T ≤ 125°C (LTC3407AI)
●
A
ΔV
Reference Voltage Line Regulation
V
IN
= 2.5V to 5.5V (Note 3)
0.3
0.5
%/V
LINE REG
3407afa
2
LTC3407A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
ΔV
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Load Regulation
MODE/SYNC = 0V (Note 3)
0.5
%
LOAD REG
I
S
Input DC Supply Current
Active Mode
(Note 4)
V
V
= V = 0.5V
600
40
0.1
800
60
1
μA
μA
μA
FB1
FB1
FB2
Sleep Mode
= V = 0.63V, MODE/SYNC = 3.6V
FB2
Shutdown
RUN = 0V, V = 5.5V, MODE/SYNC = 0V
IN
f
f
I
Oscillator Frequency
V
= 0.6V
FBX
●
1.2
1.5
1.5
1
1.8
MHz
MHz
A
OSC
SYNC
LIM
Synchronization Frequency
Peak Switch Current Limit
V
IN
= 3V, V = 0.5V, Duty Cycle <35%
0.75
1.25
FBX
R
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
DS(ON)
I
Switch Leakage Current
V
IN
= 5V, V
= 0V, V = 0V
0.01
1
μA
SW(LKG)
RUN
FBX
POR
Power-On Reset Threshold
V
V
Ramping Up, MODE/SYNC = 0V
Ramping Down, MODE/SYNC = 0V
8.5
–8.5
%
%
FBX
FBX
Power-On Reset On-Resistance
Power-On Reset Delay
100
65,536
1
200
Ω
Cycles
V
RUN/SS Threshold Low
RUN/SS Threshold High
●
●
0.3
0
1.5
2
V
V
RUN
I
RUN/SS Leakage Current
MODE Threshold Low
MODE Threshold High
●
0.01
1
μA
V
RUN
V
0.5
MODE
V
– 0.5
V
IN
V
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3407A is tested in a proprietary test mode that connects
to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
V
FB
Note 2: The LTC3407AE is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407AI is guaranteed over the full
–40°C to 125°C temperature range.
Note 5: T is calculated from the ambient T and power dissipation P
J
A
D
according to the following formula: T = T + (P • θ ).
J
A
D
JA
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
SW
5V/DIV
SW
5V/DIV
V
V
OUT
10mV/DIV
OUT
50mV/DIV
I
I
L
L
200mA/DIV
100mA/DIV
3407 G02
3407 G01
1μs/DIV
2μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 50mA
= 50mA
LOAD
LOAD
CIRCUIT OF FIGURE 3
CIRCUIT OF FIGURE 3
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3
LTC3407A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.
Load Step
Soft Start
V
OUT1
200mV/DIV
V
OUT2
100mV/DIV
V
IN
2V/DIV
I
L
V
OUT1
500mA/DIV
1V/DIV
I
LOAD
I
L
500mA/DIV
500mA/DIV
3407 G03
3407 G04
20μs/DIV
= 50mA TO 600mA
1ms/DIV
V
V
LOAD
= 3.6V
OUT
IN
V
V
LOAD
= 3.6V
IN
= 1.8V
= 1.8V
OUT
I
I
= 500mA
CIRCUIT OF FIGURE 3
CIRCUIT OF FIGURE 4
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Supply Voltage
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.8
1.7
1.6
1.5
1.4
1.3
1.2
100mA
600mA
10mA
1mA
V
= 1.8V
OUT
CIRCUIT OF FIGURE 3
2
3
4
5
6
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
4
5
6
2
3
INPUT VOLTAGE (V)
3407A G06
SUPPLY VOLTAGE (V)
3407A G07
3407A G05
Reference Voltage
vs Temperature
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
0.615
0.610
0.605
0.600
0.595
0.590
0.585
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
150
100
V
= 3.6V
V
= 2.7V
IN
IN
V
= 3.6V
IN
V
= 4.2V
IN
MAIN
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
3
5
7
1
2
4
6
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125 150
–50 –25
0
25
75
–50 –25
0
25
75
V
(V)
3407A G09
3407A G08
3407A G10
IN
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4
LTC3407A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise specified.
Efficiency vs Load Current
Efficiency vs Load Current
Load Regulation
100
90
80
70
60
100
90
80
70
60
4
3
2.7V
Burst Mode OPERATION
4.2V
3.3V
2
Burst Mode OPERATION
PULSE SKIP MODE
1
PULSE SKIP MODE
50
40
50
40
0
–1
–2
–3
–4
30
20
30
20
V
= 3.6V, V
= 1.8V
OUT
V
= 3.6V, V
= 1.8V
OUT
IN
10
0
V
= 2.5V Burst Mode OPERATION
IN
10
0
OUT
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
1
10
100
1000
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3407A G11
3407A G12
3407A G13
Efficiency vs Load Current
Efficiency vs Load Current
Line Regulation
100
90
80
70
60
100
90
80
70
60
0.5
0.4
V
= 1.8V
= 200mA
3.3V
OUT
OUT
3.3V
2.7V
I
2.7V
4.2V
0.3
4.2V
0.2
0.1
50
40
50
40
0
–0.1
–0.2
–0.3
–0.4
–0.5
30
20
30
20
10
0
10
0
V
= 1.5V Burst Mode OPERATION
V
= 1.2V Burst Mode OPERATION
OUT
OUT
1
10
100
1000
1
10
100
1000
2
6
3
4
5
LOAD CURRENT (mA)
LOAD CURRENT (mA)
V
(V)
3407A G16
IN
3407A G15
3407A G14
PIN FUNCTIONS
FB1
age from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
V
(Pin1):OutputFeedback.Receivesthefeedbackvolt-
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from V to GND.
IN
GND (Pin 5): Main Ground. Connect to the (–) terminal
of C , and (–) terminal of C .
OUT IN
RUN/SS1(Pin2):Regulator1EnableandSoft-StartInput.
Forcing this pin to V enables regulator 1, while forcing it
IN
MODE/SYNC (Pin 6): Combination Mode Selection and
to GND causes regulator 1 to shut down. Connect external
RC-networkwithdesiredtime-constanttoenablesoft-start
feature. This pin must be driven; do not float.
Oscillator Synchronization. This pin controls the opera-
tion of the device. When tied to V or GND, Burst Mode
IN
operationorpulseskippingmodeisselected,respectively.
Do not float this pin. The oscillation frequency can be
synchronized to an external oscillator applied to this pin
V (Pin3):MainPowerSupply.Mustbecloselydecoupled
IN
to GND.
and pulse skipping mode is automatically selected.
3407afa
5
LTC3407A
PIN FUNCTIONS
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from V to GND.
RC-Networkwithdesiredtime-constanttoenablesoft-start
feature. This pin must be driven; do not float.
IN
POR (Pin 8): Power-On Reset. This common-drain logic
V
(Pin 10): Output Feedback. Receives the feedback
FB2
output is pulled to GND when the output voltage is not
voltagefromtheexternalresistivedivideracrosstheoutput.
Nominal voltage for this pin is 0.6V.
16
within 8.5% of regulation and goes high after 2 clock
cycles when both channels are within regulation.
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
RUN/SS2(Pin9):Regulator2EnableandSoft-StartInput.
the (–) terminal of C , and (–) terminal of C . Must be
OUT IN
Forcing this pin to V enables regulator 2, while forcing it
soldered to electrical ground on PCB.
IN
to GND causes regulator 2 to shut down. Connect external
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC
6
1
BURST
CLAMP
V
IN
SLOPE
COMP
0.6V
+
–
I
TH
EN
EA
–
+
SLEEP
–
+
V
5Ω
FB1
I
COMP
0.65V
BURST
Q
S
R
RS
LATCH
Q
0.55V
–
+
SWITCHING
LOGIC
UV
OV
UVDET
OVDET
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
4
SW1
+
–
0.65V
+
–
I
RCMP
SHUTDOWN
11 GND
V
IN
3
8
V
IN
PGOOD1
POR
2
RUN/SS1
RUN/SS2
POR
COUNTER
0.6V REF
OSC
OSC
9
5
7
GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
SW2
10
V
FB2
3407afa
6
LTC3407A
OPERATION
The LTC3407A uses a constant frequency, current mode
architecture. The operating frequency is set at 1.5MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable MODE/SYNC pin
allows the user to trade-off noise for efficiency.
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are domi-
nated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltagecomparatortripswhenI isbelow0.65V,shutting
TH
The output voltage is set by an external divider returned
off the switch and reducing the power. The output capaci-
to the V pins. An error amplifier compares the divided
FB
tor and the inductor supply the power to the load until I
TH
outputvoltagewithareferencevoltageof0.6Vandadjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within 8.5%. The POR output
willgohighafter65,536clockcycles(about44msinpulse
skipping mode) of achieving regulation.
exceeds 0.65V, turning on the switch and the main control
loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3407A continues
to switch at a constant frequency down to very low cur-
rents, where it will begin skipping pulses.
Main Control Loop
Dropout Operation
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET)isturnedonatthebeginningofaclockcyclewhen
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turnedoncontinuouslywiththeoutputvoltagebeingequal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
the V voltage is below the reference voltage. The current
FB
into the inductor and the load increases until the current
limit is reached. The switch turns off and energy stored in
the inductor flows through the bottom switch (N-channel
MOSFET) into the load until the next clock cycle.
The peak inductor current is controlled by the internally
An important design consideration is that the R
DS(ON)
compensated I voltage, which is the output of the er-
TH
of the P-channel switch increases with decreasing input
supplyvoltage(SeeTypicalPerformanceCharacteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407A is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica-
tions Information Section).
ror amplifier.This amplifier compares the V pin to the
FB
0.6V reference. When the load current increases, the
V
voltage decreases slightly below the reference. This
FB
decrease causes the error amplifier to increase the I
TH
voltage until the average inductor current matches the
new load current.
Low Supply Operation
The main control loop is shut down by pulling the RUN/SS
pin to ground.
TheLTC3407Aincorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 1.65V to prevent unstable operation.
Low Current Operation
Two modes are available to control the operation of the
LTC3407A at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
A general LTC3407A application circuit is shown in
Figure 1. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, C and C
IN
OUT
can be selected.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407A
automaticallyswitchesintoBurstModeoperationinwhich
3407afa
7
LTC3407A
APPLICATIONS INFORMATION
V
IN
= 2.5V TO 5.5V
Inductor Core Selection
C
R7
IN
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar elec-
trical characterisitics. The choice of which style inductor
to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
what the LTC3407A requires to operate. Table 1 shows
some typical surface mount inductors that work well in
LTC3407A applications.
V
IN
BURST*
R6
R5
POWER-ON
MODE/SYNC
POR
RUN/SS1
SW1
RESET
PULSESKIP*
LTC3407A
RUN/SS2
L1
L2
C2
V
V
OUT2
C4
OUT1
SW2
C1
R2
C3
V
V
FB1
FB2
R4
R3
GND
R1
C
C
OUT1
OUT2
3407A F01
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V : Burst Mode
IN
Figure 1. LTC3407A General Schematic
Table 1. Representative Surface Mount Inductors
MANUF-
MAX DC
Inductor Selection
ACTURER
PART NUMBER VALUE CURRENT
DCR
HEIGHT
Taiyo
Yuden
CB2016T2R2M
CB2012T2R2M
CB2016T3R3M
2.2μH
2.2μH
3.3μH
510mA
530mA
410mA
0.13Ω 1.6mm
0.33Ω 1.25mm
0.27Ω 1.6mm
Although the inductor does not influence the operat-
ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔI decreases
L
Panasonic ELT5KT4R7M
4.7μH
4.7μH
950mA
0.2Ω
1.2mm
2mm
with higher inductance and increases with higher V or
IN
Sumida
Murata
CDRH2D18/LD
630mA 0.086Ω
V
:
OUT
LQH32CN4R7M23 4.7μH
450mA
2.2μH 1100mA
4.7μH 750mA
0.2Ω
2mm
ꢁ
ꢃ
ꢂ
OUT ꢄ
V
VOUT
fO •L
Taiyo
Yuden
NR30102R2M
NR30104R7M
0.1Ω
0.19Ω
1mm
1mm
ꢀIL =
• 1–
ꢆ
V
ꢅ
IN
FDK
FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7μH 1100mA 0.11Ω
3.3μH 1200mA 0.1Ω
2.2μH 1300mA 0.08Ω
1mm
1mm
1mm
Accepting larger values of ΔI allows the use of low
L
inductances, but results in higher output voltage ripple,
TDK
VLF3010AT4R7-
MR70
4.7μH
700mA
0.28Ω
1mm
1mm
1mm
greater core losses, and lower output current capability. A
reasonable starting point for setting ripple current is ΔI =
VLF3010AT3R3-
MR87
3.3μH
870mA
0.17Ω
L
0.3 • I , where I is the peak switch current limit. The
LIM
LIM
VLF3010AT2R2-
M1R0
2.2μH 1000mA 0.12Ω
largest ripple current ΔI occurs at the maximum input
L
voltage. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
Input Capacitor (C ) Selection
IN
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V /V .
Topreventlargevoltagetransients, alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
ꢁ
ꢄ
OUT IN
VOUT
fO • ꢀIL
VOUT
L =
• 1–
ꢃ
ꢆ
V
ꢂ
ꢅ
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this transition to occur
at lower load currents. This causes a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
VOUT(V – VOUT
)
IN
IRMS ≈IMAX
V
IN
where the maximum average output current I
equals
MAX
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
MAX
LIM
L
3407afa
8
LTC3407A
APPLICATIONS INFORMATION
This formula has a maximum at V = 2V , where I
capacitance density. However, they also have a larger
ESR and it is critical that they are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heightsrangingfrom2mmto4mm.Aluminumelectrolytic
capacitors have a significantly larger ESR, and are often
usedinextremelycost-sensitiveapplicationsprovidedthat
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coefficient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing. Other capacitor types include the
Panasonic Special Polymer (SP) capacitors.
IN
OUT
RMS
= I /2. This simple worst-case is commonly used to
OUT
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1μF to 1μF ceramic capacitor is also recommended on
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients. Typically,
once the ESR requirement is satisfied, the capacitance
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407A in parallel with the
main capacitors for high frequency decoupling.
is adequate for filtering. The output ripple (ΔV ) is
OUT
determined by:
Ceramic Input and Output Capacitors
ꢂ
ꢅ
1
ꢀVOUT ꢁ ꢀIL ESR+
ꢄ
ꢇ
8fO C
Higher value, lower cost ceramic capacitors are now be-
comingavailableinsmallercasesizes. Thesearetempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR gener-
ates a loop “zero” at 5kHz to 50kHz that is instrumental in
giving acceptable loop phase margin. Ceramic capacitors
remain capacitive to beyond 300kHz and usually resonate
withtheirESLbeforeESRbecomeseffective.Also,ceramic
caps are prone to temperature effects which requires the
designer to check loop stability over the operating tem-
perature range. To minimize their large temperature and
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK, and Murata.
ꢃ
OUT ꢆ
wheref =operatingfrequency,C
=outputcapacitance
O
OUT
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
with input voltage. With ΔI = 0.3 • I the output ripple
L
LIM
will be less than 100mV at maximum V and f = 1.5MHz
IN
O
with:
ESR
< 150mΩ
COUT
Once the ESR requirements for C
have been met, the
OUT
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantulum capacitors are all available in surface mount
packages.TheOS-CONsemiconductordielectriccapacitor
available from Sanyo has the lowest ESR(size) product
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP, of-
fer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
can induce ringing at the V pin. At best, this ringing can
IN
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
3407afa
9
LTC3407A
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
theoutputcapacitorsize. Typically, 3-4cyclesarerequired
to respond to a load step, but only in the first cycle does
Power-On Reset
ThePORpinisanopen-drainoutputwhichpullslowwhen
either regulator is out of regulation. When both output
voltages are within 8.5% of regulation, a timer is started
16
which releases POR after 2 clock cycles (about 44ms
in pulse skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can
be bypassed by tying the POR output to the MODE/SYNC
input, to force pulse skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. Thiscanbeavoidedbyusingpulseskippingmode
instead.Wheneitherchannelisshutdown,thePORoutput
is pulled low, since one or both of the channels are not
in regulation.
the output drop linearly. The output droop, V
, is
DROOP
usually about 3 times the linear drop of the first cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
ΔIOUT
fO • VDROOP
COUT ≈3
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Mode Selection & Frequency Synchronization
TheMODE/SYNCpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to V enables Burst Mode operation, which
Setting the Output Voltage
IN
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse skipping operation is selected which
provides the lowest output ripple, at the cost of low cur-
rent efficiency.
The LTC3407A develops a 0.6V reference voltage between
the feedback pin, V , and ground as shown in Figure 1.
FB
The output voltage is set by a resistive divider according
to the following formula:
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
The LTC3407A can also be synchronized to another
LTC3407A by the MODE/SYNC pin. During synchroniza-
tion, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
VOUT = 0.6V 1+
ꢂ
ꢅ
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Checking Transient Response
Toimprovethefrequencyresponse,afeed-forwardcapaci-
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
tor C may also be used. Great care should be taken to
F
route the V line away from noise sources, such as the
FB
inductor or the SW line.
When a load step occurs, V
immediately shifts by an
OUT
amount equal to ΔI
• ESR, where ESR is the effective
LOAD
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
OUT
3407afa
10
LTC3407A
APPLICATIONS INFORMATION
Duringthisrecoverytime,V
canbemonitoredforover-
Efficiency Considerations
OUT
shoot or ringing that would indicate a stability problem.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phasemargin.Inaddition,afeed-forwardcapacitorcanbe
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creatinghighfrequencyzeroswithR2andR4respectively,
which improve the phase margin.
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407A circuits: 1) V quiescent current, 2)
IN
2
switching losses, 3) I R losses, 4) other losses.
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1μF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
1) The V current is the DC supply current given in the
IN
Electrical Characteristics which excludes MOSFET
driver and control currents. V current results in a
IN
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
small (<0.1%) loss that increases with V , even at no
IN
can deliver enough current to prevent this problem, if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
Soft-Start
from V to ground. The resulting dQ/dt is a current
IN
out of V that is typically much larger than the DC bias
IN
TheRUN/SSpinsprovideameanstoseparatelyrunorshut
downthetworegulators.Inaddition,theycanoptionallybe
used to externally control the rate at which each regulator
starts up and shuts down. Pulling the RUN/SS1 pin below
1V shuts down regulator 1 on the LTC3407A. Forcing this
current. In continuous mode, I
= f (Q + Q ),
GATECHG
O T B
where Q and Q are the gate charges of the internal
T
B
top and bottom MOSFET switches. The gate charge
losses are proportional to V and thus their effects
IN
will be more pronounced at higher supply voltages.
pin to V enables regulator 1. In order to control the rate
IN
atwhicheachregulatorturnsonandoff,connectaresistor
and capacitor to the RUN/SS pins as shown in Figure 1.
The soft-start duration can be calculated by using the
following formula:
2
3) I R losses are calculated from the DC resistances of
the internal switches, R , and external inductor, R .
SW
L
In continuous mode, the average output current flows
throughinductorL,butis“chopped”betweentheinternal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
ꢁ
ꢄ
V ꢀ1
IN
t
SS =RSSCSSIn
(s)
ꢃ
ꢆ
V ꢀ1.6
ꢂ
ꢅ
IN
bottom MOSFET R
follows:
and the duty cycle (D) as
DS(ON)
For approximately a 1ms ramp time, use R = 4.7Mꢀ
SS
and C = 680pF at V = 3.3V.
R
= (R
)(D) + (R
)(1 – D)
SS
IN
SW
DS(ON)TOP
DS(ON)BOT
Hot Swap is a registered trademark of Linear Technology Corporation.
3407afa
11
LTC3407A
APPLICATIONS INFORMATION
The R
for both the top and bottom MOSFETs can
As an example, consider the case when the LTC3407A is
in dropout on both channels at an input voltage of 2.7V
with a load current of 600mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
DS(ON)
be obtained from the Typical Performance Characteristics
2
curves. Thus, to obtain I R losses:
2
2
I R losses = I
(R + R )
SW L
OUT
graph of Switch Resistance, the R
resistance of
DS(ON)
4) Other ‘hidden’ losses such as copper trace and internal
batteryresistancescanaccountforadditionalefficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
the main switch is 0.425Ω. Therefore, power dissipated
by each channel is:
2
P = I • R
= 153mW
D
DS(ON)
The MS package junction-to-ambient thermal resistance,
can be minimized by making sure that C has adequate
θ , is 45°C/W. Therefore, the junction temperature of
IN
JA
the regulator operating in a 70°C ambient temperature is
approximately:
charge storage and very low ESR at the switching fre-
quency.Otherlossesincludingdiodeconductionlosses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
T = 2 • 0.153 • 45 + 70 = 84°C
J
which is below the absolute maximum junction tempera-
ture of 125°C.
Thermal Considerations
In a majority of applications, the LTC3407A does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3407A is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
Design Example
As a design example, consider using the LTC3407A in a
portable application with a Li-Ion battery. The battery pro-
vides a V = 2.8V to 4.2V. The load requires a maximum
IN
of 600mA in active mode and 2mA in standby mode. The
output voltage is V
= 2.5V. Since the load still needs
OUT
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the inductor value for about 30% ripple
current at maximum V :
To prevent the LTC3407A from exceeding the maximum
junctiontemperature,theuserwillneedtodosomethermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
IN
2.5V
1.5MHz •300mA
2.5V
4.2V
ꢀ
ꢁ
ꢃ
ꢄ
L =
• 1–
= 2.25μH
ꢂ
ꢅ
Choosing the closest inductor from a vendor of 2.2μH
inductor, results in a maximum ripple current of:
2.5V
1.5MHz •2.2μH
2.5V
4.2V
ꢂ
ꢃ
ꢅ
ꢆ
T
= P • θ
D JA
RISE
ꢀIL =
• 1ꢁ
= 307mA
ꢄ
ꢇ
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
The junction temperature, T , is given by:
J
600mA
T = T
J
+ T
AMBIENT
COUT ≈3
= 9.6μF
RISE
1.5MHz •(5%•2.5V)
Thecloseststandardvalueis10μF.Sincetheoutputimped-
ance of a Li-Ion battery is very low, C is typically 10μF.
IN
3407afa
12
LTC3407A
APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μAwiththe0.6VfeedbackvoltagemakesR1~300k.Aclose
standard 1% resistor is 280k, and R2 is then 887k.
2. Are C
and L1 closely connected? The (–) plate of
OUT
C
returns current to GND and the (–) plate of C .
OUT
IN
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of C and a ground
OUT
sense line terminated near GND (exposed pad). The
feedback signals V and V should be routed away
fromnoisycomponentsandtraces,suchastheSWlines
(Pins 4 and 7), and their traces should be minimized.
ThePORpinisacommondrainoutputandrequiresapull-
up resistor. A 100k resistor is used for adequate speed.
FB1
FB2
Figure 3 shows the complete schematic for this design
example. The specific passive components chosen allow
for a 1mm height power supply that maintains a high ef-
ficiency across load.
4. KeepsensitivecomponentsawayfromtheSWpins.The
inputcapacitorC andtheresistorsR1toR4shouldbe
IN
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. Addtionally the two grounds should not share
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3407A. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
the high current paths of C or C
.
IN
OUT
6. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
1. Does the capacitor C connect to the power V (Pin 3)
IN
IN
and GND (exposed pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
to V or GND.
IN
V
IN
C
IN
RUN/SS2
V
RUN/SS1
IN
MODE/SYNC
POR
LTC3407A
L1
C4
L2
V
SW2
SW1
V
OUT1
OUT2
C5
R4
V
FB1
V
FB2
R2
GND
R1
C
C
R3
OUT1
OUT2
3407A F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 2. LTC3407A Layout Diagram (See Board Layout Checklist)
3407afa
13
LTC3407A
TYPICAL APPLICATIONS
V = 2.5V
IN
TO 5.5V
Efficiency vs Load Current
R5
C1
100
90
100k
10μF
RUN/SS2
V
RUN/SS1
IN
2.5V
POWER-ON
RESET
MODE/SYNC
POR
1.8V
80
LTC3407A
L2
2.2μH
L1
2.2μH
70
V
= 2.5V
OUT2
AT 600mA
V
= 1.8V
OUT1
SW2
SW1
60
AT 600mA
C5, 22pF
C4, 22pF
50
40
V
FB1
V
FB2
30
20
R4
887k
R2
604k
GND
C3
10μF
C2
10μF
R3
280k
R1
301k
V
= 3.3V
IN
Burst Mode OPERATION
10
0
NO LOAD ON OTHER CHANNEL
1
10
100
1000
3407A TA03
C1, C2, C3: TAIYO YUDEN JMK316BJ106MD
L1, L2: TDK VLF3010AT-2R2M1R0
LOAD CURRENT (mA)
3407A TA04
Figure 3. 1mm Height Core Supply
V
= 2.5V TO 5.5V
IN
Efficiency vs Load Current
R7
C
IN
10μF
100
90
R6
4.7Mꢀ
R5
4.7Mꢀ
100k
V
IN
1.8V
POWER-ON
RESET
POR
LTC3407A
80
2.5V
RUN/SS2
SW2
RUN/SS1
70
L2
4.7μH
L1
4.7μH
60
V
= 1.8V
V
= 1.2V
OUT1
AT 600mA
OUT2
AT 600mA
SW1
50
40
C2, 22pF
C1, 22pF
C4
680pF
C3
680pF
30
20
V
FB1
V
FB2
R4
887k
R2
604k
V
= 3.3V
IN
MODE/SYNC GND
C
OUT2
10μF
C
R3
442k
R1
604k
OUT1
10μF
Burst Mode OPERATION
10
0
NO LOAD ON OTHER CHANNEL
1
10
100
1000
LOAD CURRENT (mA)
3407A TA05
C
, C
, C
TAIYO YUDEN JMK316BJ106ML
L1, L2: TDK VLF3010AT-4R7MR70
IN OUT1 OUT2:
3407A TA06
Figure 4. Low Ripple Buck Regulators Using Ceramic Capacitors
3407afa
14
LTC3407A
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
0.38 0.10
10
TYP
6
0.675 0.05
3.50 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.10
(2 SIDES)
2.38 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 p 0.102
2.794 p 0.102
(.110 p .004)
0.889 p 0.127
(.035 p .005)
(.081 p .004)
1
1.83 p 0.102
(.072 p .004)
5.23
(.206)
MIN
2.083 p 0.102 3.20 – 3.45
(.082 p .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 p 0.038
(.0120 p .0015)
TYP
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.497 p 0.076
(.0196 p .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0.254
(.010)
0o – 6o TYP
1
2
3
4 5
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
0.50
(.0197)
BSC
MSOP (MSE) 0307 REV B
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3407afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3407A
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
V
= 2.8V
IN
TO 4.2V
R5
100k
C1
10μF
RUN/SS2
V
RUN/SS1
IN
POWER-ON
RESET
MODE/SYNC
POR
LTC3407A
L2
10μH
L1
2.2μH
D1
V
= 3.3V
OUT2
AT 200mA
V
= 1.8V
OUT1
SW2
SW1
AT 600mA
C4, 22pF
M1
+
C6
47μF
V
FB1
V
FB2
R4
887k
R2
887k
GND
C3
10μF
C2
10μF
R3
196k
R1
442k
3407A TA07
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302
Efficiency vs Load Current
Efficiency vs Load Current
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
2.8V
3.6V
4.2V
2.8V
4.2V
3.6V
50
40
30
20
V
= 1.8V
V
= 3.3V
OUT
OUT
Burst Mode OPERATION
Burst Mode OPERATION
10
0
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3407A TA08
3407A TA09
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3405/LTC3405A
300mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 20μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Synchronous Step-Down DC/DC Converter
I
<1μA, ThinSOT Package
LTC3406/LTC3406B
LTC3407/LTC3407-2
600mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
SD
<1μA, ThinSOT Package
600mA/800mA (I ), 1.5MHz/2.25MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA,
Q
OUT
IN
LTC3407-3/LTC3407-4 Dual Synchronous Step-Down DC/DC Converter
I
SD
<1μA, MS10E Package, DFN Package
LTC3410/LTC3410B
300mA (I ), 2.25MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 26μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter in SC70
I
SD
<1μA, SC70 Package
LTC3411
1.25A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
SD
<1μA, MSOP-10 Package
LTC3412/LTC3412A
LTC3414
2.5A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
SD
<1μA, TSSOP-16E Package
4A (I ), 4MHz,
95% Efficiency, V : 2.25V to 5.5V, V
= 0.8V, I = 64μA,
OUT(MIN) Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
SD
<1μA, TSSOP-28E Package
LTC3440/LTC3441
LTC3548/
600mA/1.2A (I ), 2MHz/1MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 2.5V, I = 25μA,
Q
OUT
IN
OUT(MIN)
Synchronous Buck-Boost DC/DC Converter
I
<1μA, MSOP-10 Package/DFN Package
400mA/800mA (I ), 2.25MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.6V, I = 40μA,
Q
OUT
IN
OUT(MIN)
LTC3548-1/LTC3548-2 Dual Synchronous Step-Down DC/DC Converter
I
<1μA, MS10E Package/DFN Package
3407afa
LT 1008 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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