LTC3412AIFE#TRPBF [Linear]
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| 型号： | LTC3412AIFE#TRPBF |
| 厂家： | 
Linear |
| 描述： | 暂无描述 稳压器 |
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LTC3412
2.5A, 4MHz, Monolithic
Synchronous Step-Down Regulator
U
FEATURES
DESCRIPTIO
The LTC®3412 is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.625V to 5.5V and provides an
adjustable regulated output voltage from 0.8V to 5V while
delivering up to 2.5A of output current. The internal
synchronous power switch with 85mΩ on-resistance
increases efficiency and eliminates the need for an exter-
nal Schottky diode. Switching frequency is set by an
external resistor or can be sychronized to an external
clock. 100% duty cycle provides low dropout operation
extending battery life in portable systems. OPTI-LOOP®
compensation allows the transient response to be opti-
mized over a wide range of loads and output capacitors.
The LTC3412 can be configured for either Burst Mode®
operation or forced continuous operation. Forced con-
tinuousoperationreducesnoiseandRFinterferencewhile
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application. To further maximize
battery life, the P-channel MOSFET is turned on continu-
ously in dropout (100% duty cycle).
■
High Efficiency: Up to 95%
2.5A Output Current
Low Quiescent Current: 62μA
Low RDS(ON) Internal Switches: 85mΩ
Programmable Frequency: 300kHz to 4MHz
No Schottky Diode Required
±2% Output Voltage Accuracy
0.8V Reference Allows Low Output Voltage
Selectable Forced Continuous/Burst Mode Operation
with Adjustable Burst Clamp
Synchronizable Switching Frequency
Low Dropout Operation: 100% Duty Cycle
Power Good Output Voltage Monitor
Overtemperature Protection
■
■
■
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■
■
■
■
■
■
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Available in 16-Lead Thermally Enhanced TSSOP
and QFN Packages
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APPLICATIO S
■
Portable Instruments
Battery-Powered Equipment
Notebook Computers
Distributed Power Systems
Cellular Telephones
Digital Cameras
■
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, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Efficiency vs Load Current
V
IN
2.7V TO 5.5V
22μF
100
SV
IN
PV
IN
R
PGOOD
SW
LTC3412
T
1μH
V
2.5V
2.5A
OUT
80
60
40
20
0
309k
4.7M
Burst Mode OPERATION
FORCED CONTINUOUS
100μF
PGND
SGND
RUN/SS
470pF
15k
I
TH
SYNC/MODE
V
FB
1000pF
100pF
392k
110k
75k
3412 F01
V
V
= 3.3V
IN
OUT
= 2.5V
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3412 G01
Figure 1. 2.5V, 2.5A Step-Down Regulator
3412fb
1
LTC3412
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Input Supply Voltage ...................................–0.3V to 6V
ITH, RUN, VFB Voltages ...............................–0.3V to VIN
SYNC/MODE Voltages ................................–0.3V to VIN
SW Voltage ................................... –0.3V to (VIN + 0.3V)
Peak SW Sink and Source Current ......................... 6.5A
Operating Temperature
Range (Note 2) ....................................... –40°C to 85°C
Junction Temperature (Note 5)............................. 125°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
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W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
PV
IN
16
15
14
13
12
11
10
9
SV
IN
SW
PGOOD
16 15 14 13
SW
I
TH
RUN/SS
SGND
1
2
3
4
12 PGOOD
PGND
PGND
SW
V
FB
17
11 SV
IN
IN
R
17
T
PV
IN
PV
10
9
SYNC/MODE
RUN/SS
SW
SW
SW
5
6
7
8
PV
IN
SGND
FE PACKAGE
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 37.6°C/W, θJC = 10°C/W
TJMAX = 125°C, θJA = 34°C/W, θJC = 1°C/W
ORDER PART NUMBER
LTC3412EFE
LTC3412IFE
Order Options Tape and Reel: Add #TR
FE PART MARKING
3412EFE
3412IFE
ORDER PART NUMBER
LTC3412EUF
UF PART MARKING
3412
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
SV
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
Signal Input Voltage Range
Regulated Feedback Voltage
Voltage Feedback Leakage Current
Reference Voltage Line Regulation
Output Voltage Load Regulation
2.625
0.784
IN
V
(Note 3)
●
●
0.800
0.1
0.816
0.4
V
FB
I
μA
FB
ΔV
FB
V
= 2.7V to 5.5V (Note 3)
IN
0.04
0.2
%/V
V
Measured in Servo Loop, V = 0.36V
Measured in Servo Loop, V = 0.84V
●
●
0.02
–0.02
0.2
–0.2
%
%
LOADREG
ITH
ITH
ΔV
PGOOD
Power Good Range
±7.5
±9
%
R
PGOOD
Power Good Pull-Down Resistance
120
200
Ω
I
Input DC Bias Current
Active Current
Sleep
(Note 4)
Q
V
V
V
= 0.78V, V = 1V
250
62
0.02
330
80
1
μA
μA
μA
FB
FB
RUN
ITH
= 1V, V = 0V
ITH
Shutdown
= 0V, V
= 0V
MODE
3412fb
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LTC3412
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
= 309kΩ
MIN
TYP
MAX
UNITS
f
Switching Frequency
Switching Frequency Range
R
0.88
0.3
0.95
1.1
4
MHz
MHz
OSC
OSC
(Note 6)
f
SYNC Capture Range
(Note 6)
0.3
4
MHz
mΩ
mΩ
A
SYNC
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 1A (Note 7)
85
65
110
90
PFET
NFET
DS(ON)
DS(ON)
SW
SW
= –1A (Note 7)
I
Peak Current Limit
4
5.4
LIMIT
V
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
2.375
2.500
0.1
2.625
1
V
UVLO
LSW
I
V
= 0V, V = 5.5V
μA
V
RUN
IN
V
0.5
0.65
0.8
1
RUN
RUN
I
RUN/SS Leakage Current
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3412 is tested in a feedback loop that adjusts V to
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 2: The LTC3412E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3412I is guaranteed to meet
specified performance over the –40°C to 85°C temperature range.
Note 5: T is calculated from the ambient temperature T and power
J
A
dissipation as follows: LTC3412: T = T + P (37.6°C/W).
J
A
D
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test correlation
in the UF package and by production test in the FE package.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Efficiency vs Load Current
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 3.3V
V
= 5V
IN
IN
V
= 3.3V
V
= 5V
IN
IN
Burst Mode OPERATION
FORCED CONTINUOUS
V
= 2.5V
V
= 2.5V
OUT
1MHz
Burst Mode OPERATION
OUT
1MHz
V
V
= 3.3V
IN
OUT
= 2.5V
FORCED CONTINUOUS
0.1 10
LOAD CURRENT (A)
0.001
0.01
0.1
1
10
0.001 0.01 0.1
LOAD CURRENT (A)
1
10
0.001
0.01
1
LOAD CURRENT (A)
3412 G01
3412 G02
3412 G03
3412fb
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LTC3412
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TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
Efficiency vs Input Voltage
Efficiency vs Frequency
0.02
0.00
98
96
94
92
90
88
86
97
96
95
94
93
92
91
V
V
= 3.3V
IN
OUT
= 2.5V
LOAD = 100mA
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
LOAD = 1A
1μH
0.47μH
2.2μH
LOAD = 2.5A
V
V
= 3.3V
= 2.5V
LOAD = 1A
IN
OUT
V
= 2.5V
OUT
1MHz
Burst Mode OPERATION
Burst Mode OPERATION
0
0.5
1
1.5
2
2.5
2.55 3.05 3.55 4.05 4.55 5.05
INPUT VOLTAGE (V)
300 800 1300 1800 2300 2800 3300 3800
FREQUENCY (kHz)
LOAD CURRENT (A)
3412 G06
3412 G04
3412 G05
Load Step Transient Forced
Continuous
Load Step Transient Burst Mode
Operation
Burst Mode Operation
3412 G08
20μs/DIV
3412 G07
20μs/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD STEP = 50mA TO 2.5A
3412 G09
4μs/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD = 50mA
VIN = 3.3V, VOUT = 2.5V
LOAD STEP = NO LOAD TO 2.5A
Reference Voltage
vs Temperature
Switch On-Resistance
vs Input Voltage
Start-Up, Burst Mode Operation
120
100
80
60
40
20
0
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
0.7925
0.7920
V
IN
= 3.3V
PFET ON-RESISTANCE
NFET ON-RESISTANCE
3412 G10
2.5
3
3.5
4
4.5
5
1ms/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD = 1Ω
–45 –25 –5 15 35 55 75 95 115 120
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3412 G12
3412 G11
3412fb
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LTC3412
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TYPICAL PERFOR A CE CHARACTERISTICS
Switch On-Resistance
vs Temperature
Switch Leakage vs Input Voltage
Frequency vs ROSC
120
110
100
90
2.5
2.0
1.5
1.0
0.5
0
4500
4000
3500
3000
2500
2000
1500
1000
500
V
IN
= 3.3V
V
= 3.3V
IN
PFET ON-RESISTANCE
NFET ON-RESISTANCE
80
70
60
50
SYNCHRONOUS SWITCH
MAIN SWITCH
40
30
20
–40 –20
0
0
20 40 60 80 100 120
TEMPERATURE (°C)
2.5
3
3.5
4
4.5
5
5.5
50 150 250 350 450 550 650 750 850 950
(kΩ)
INPUT VOLTAGE (V)
R
OSC
3412 G13
3412 G14
3412 G15
Switching Frequency
vs Temperature
DC Supply Current
vs Input Voltage
Frequency vs Input Voltage
1050
1040
1030
1020
1010
1000
990
1010
1008
1006
1004
1002
1000
998
350
300
250
200
150
100
50
R = 309k
V
= 3.3V
IN
ACTIVE
996
994
992
SLEEP
990
2.5
3
3.5
4
4.5
5
5.5
–40 –20
0
20 40 60 80 100 120
2.5
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3412 G16
3412 G17
3412 G18
Minimum Peak Inductor Current
vs Burst Clamp Voltage
DC Supply Current vs Temperature
Current Limit vs Input Voltage
4000
3500
3000
2500
2000
1500
1000
500
350
300
250
200
150
100
50
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
V
= 3.3V
V
= 3.3V
IN
IN
ACTIVE
SLEEP
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
BURST CLAMP VOLTAGE (V)
1
4.75
INPUT VOLTAGE (V)
2.75
3.25
3.75
4.25
5.25
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
3412 G20
3412 G21
3412 G19
3412fb
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LTC3412
U
U
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PI FU CTIO S (FE/UH Package)
SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor. Normally SVIN is equal to
PVIN. SVIN can be greater than PVIN but keep the voltage
difference between SVIN and PVIN less than 0.5V.
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412. In
shutdown all functions are disabled drawing < 1μA of
supplycurrent.Acapacitortogroundfromthispinsetsthe
ramp time to full output current.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output
voltage is not within ±7.5% of regulation point.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal
components,compensationcomponentsandtheexposed
pad on the bottom side of the IC should connect to this
ground, which in turn connects to PGND at one point.
ITH (Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.2V corresponding to the zero-sense
voltage (zero current).
PVIN(Pins9,16/Pins3,10):PowerInputSupply.Decouple
this pin to PGND with a capacitor.
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
ConnectiontotheInductor.Thispinconnectstothedrains
of the internal main and synchronous power MOSFET
switches.
V
FB (Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the
output.
RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the switching fre-
quency.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of CIN and COUT
.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and thermal
performance.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
ClockSynchronizationInput. Toselectforcedcontinuous,
tietoSVIN.Connectingthispintoavoltagebetween0Vand
1V selects Burst Mode operation with the burst clamp set
to the pin voltage.
3412fb
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LTC3412
U
U
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FU CTIO AL BLOCK DIAGRA
PV
IN
SV
SGND
8
I
TH
3
IN
1
9
16
SLOPE
COMPENSATION
RECOVERY
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
0.8V
BCLAMP
+
–
+
–
–
+
P-CH
4
V
FB
ERROR
AMPLIFIER
BURST
COMPARATOR
+
–
SYNC/MODE
+
–
0.74V
10
SLOPE
11
COMPENSATION
OSCILLATOR
SW
14
15
+
–
RUN/SS
PGOOD
7
2
RUN
0.86V
N-CH
LOGIC
+
–
NMOS
CURRENT
COMPARATOR
–
+
REVERSE
CURRENT
12
PGND
COMPARATOR
13
5
6
3412 FBD
R
SYNC/MODE
T
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OPERATIO
Main Control Loop
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2A for forced continuous mode and 0A for
Burst Mode operation.
TheLTC3412isamonolithic, constant-frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.8V reference. When the load
The operating frequency is set by an external resistor
connected between the RT pin and ground. The practical
switching frequency can range from 300kHz to 4MHz.
3412fb
7
LTC3412
U
OPERATIO
peak inductor current will be determined by the voltage on
theITH pinuntiltheITH voltagedropsbelow200mV. Atthis
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOS-
FET is switched on until either the overvoltage condition
clears or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Frequency Synchronization
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
TheinternaloscillatoroftheLTC3412canbesynchronized
toanexternalclockconnectedtotheSYNC/MODEpin.The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V and
each switching cycle begins at the falling edge of the
external clock signal.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage between 0V
to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the ITH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the ITH pin drops. As the ITH voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top MOSFET is held
off and the ITH pin is disconnected from the output of the
error amplifier. The majority of the internal circuitry is also
turned off to reduce the quiescent current to 62μA while
the load current is solely supplied by the output capacitor.
When the output voltage drops, the ITH pin is reconnected
to the output of the error amplifier and the top power
MOSFET along with all the internal circuitry is switched
back on. This process repeats at a rate that is dependent
on the load demand.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412 is designed to operate down to an input
supply voltage of 2.625V. One important consideration at
low input supply voltages is that the RDS(ON) of the P-
channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Pulse skipping operation can be implemented by connect-
ing the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
3412fb
8
LTC3412
U
OPERATIO
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
Whentheoutputisshortedtoground,theinductorcurrent
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.8A, the top
powerMOSFETwillbeheldoffandswitchingcycleswillbe
skipped until the inductor current falls to a safe level.
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APPLICATIO S I FOR ATIO
The basic LTC3412 application circuit is shown in Fig-
ure 1. External component selection is determined by the
maximumloadcurrentandbeginswiththeselectionofthe
inductor value and operating frequency followed by CIN
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
and COUT
.
Operating Frequency
V
⎡
VOUT
V
IN
⎤
⎡
⎤
OUT
fL
ΔIL =
1−
⎢
⎥
⎢
⎥
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage.
⎣
⎦
⎣
⎦
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. High-
est efficiency operation is achieved at low frequency with
small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
The operating frequency of the LTC3412 is determined by
an external resistor that is connected between the RT pin
andground.Thevalueoftheresistorsetstherampcurrent
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
⎛
⎞
⎛
⎞
VOUT
fΔI
VOUT
L =
1−
3.23 •1011
⎜
⎟
⎜
⎟
V
⎝
⎠
L(MAX)
IN(MAX)
⎝
⎠
ROSC
=
(Ω)− 10kΩ
f(Hz)
The inductor value will also have an effect on Burst Mode
operation.Thetransitionfromlowcurrentoperationbegins
whenthepeakinductorcurrentfallsbelowalevelsetbythe
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc-
tance values will cause the burst frequency to increase.
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
3412fb
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offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, orchooseacapacitorratedatahighertempera-
ture than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, mollypermalloy,
or Kool Mμ® cores. Actual core loss is independent of core
size for a fixed inductor value but it is very dependent on
theinductanceselected.Astheinductanceincreases,core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔVOUT, is determined by:
Ferritedesignshaveverylowcorelossesandarepreferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
⎛
1
⎞
ΔVOUT ≤ ΔI ESR +
⎜
⎟
L
⎝
8fCOUT
⎠
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placedinparallelmaybeneededtomeettheESRandRMS
currenthandlingrequirements.Drytantalum,specialpoly-
mer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoi-
dal current at the source of the top MOSFET. To prevent
largeripplevoltage, alowESRinputcapacitorsizedforthe
maximum RMS current should be used. RMS current is
given by:
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
VOUT
V
IN
V
IN
VOUT
IRMS = IOUT(MAX)
− 1
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
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LTC3412
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thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the ITH pin will decrease. When the ITH voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
IBURST is determined by the desired amount of output
voltage ripple. As the value of IBURST increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, VBURST, can be set by a
resistordividerfromtheVFB pintotheSGNDpinasshown
in Figure 1.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
R2
R1
⎛
⎝
⎞
⎟
⎠
VOUT = 0.8V 1+
⎜
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 2.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
connectingtheSYNC/MODEpintoground.ThissetsIBURST
to0A. Inthiscondition, thepeakinductorcurrentislimited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still op-
erating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skippedwhilemaintainingtheoutputvoltageinregulation.
V
OUT
R2
V
FB
R1
LTC3412
SGND
3412 F02
Figure 2. Setting the Output Voltage
Frequency Synchronization
Burst Clamp Programming
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external fre-
quency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
IfthevoltageontheSYNC/MODEpinislessthanVIN by1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, IBURST, for each switching cycle accord-
ing to the following equation:
3.75A
0.8V
⎛
⎜
⎝
⎞
⎟
⎠
IBURST = V
− 0.2V
(
)
BURST
VBURST is the voltage on the SYNC/MODE pin. IBURST can
be programmed in the range of 0A to 3.75A. For values of
Soft-Start
V
BURST greater than 1V, IBURST is set at 3.75A. For values
of VBURST less than 0.2V, IBURST is set at 0A. As the output
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (IQ < 1μA).
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The LTC3412 contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
⎛
V
IN
⎞
tSS = RSSCSS ln
Seconds
⎟
(
)
⎜
⎝ V − 1.8V⎠
IN
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
Efficiency Considerations
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Thermal Considerations
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
In most applications, the LTC3412 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3412 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
To avoid the LTC3412 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
1. The VIN quiescent current is due to two components:
theDCbiascurrentasgivenintheelectricalcharacteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG=f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
3412fb
12
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The junction temperature, TJ, is given by:
First, calculate the timing resistor:
3.23 •1011
TJ = TA + TR
ROSC
=
− 10k = 313k
where TA is the ambient temperature.
1•106
As an example, consider the LTC3412 in dropout at an
input voltage of 3.3V, a load current of 2.5A and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the RDS(ON) of the P-
channel switch at 70°C is approximately 97mΩ. There-
fore, power dissipated by the part is:
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
⎛
⎞
⎟
2.5V
2.5V
4.2V
⎛
⎜
⎝
⎞
⎟
⎠
L =
1−
= 1.01μH
⎜
⎝ (1MHz)(1A)⎠
Using a 1μH inductor, results in a maximum ripple current
of:
PD = (ILOAD2)(RDS(ON)) = (2.5A)2(97mΩ) = 0.61W
For the TSSOP package, the θJA is 37.6°C/W. Thus the
junction temperature of the regulator is:
⎛
⎞
2.5V
2.5V
4.2V
⎛
⎜
⎝
⎞
⎟
⎠
ΔIL =
1−
= 1.01A
⎜
⎟
(1MHz)(1μH)
⎝
⎠
TJ = 70°C + (0.61W)(37.6°C/W) = 93°C
which is below the maximum junction temperature of
125°C.
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. In this application,
two tantalum capacitors will be used to provide the bulk
capacitanceandaceramiccapacitorinparalleltolowerthe
total effective ESR. For this design, two 100μF tantalum
capacitors in parallel with a 10μF ceramic capacitor will be
used. CIN shouldbesizedforamaximumcurrentratingof:
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
2.5V 4.2V
⎛
⎜
⎝
⎞
IRMS= 2.5A
− 1 = 1.23ARMS
(
)
⎟
⎠
4.2V 2.5V
Decoupling the PVIN and SVIN pins with a 22μF ceramic
capacitor and a 220μF tantalum capacitor is adequate for
most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2 and R3. The
voltageontheMODEpinwillbesetto0.32Vbytheresistor
divider consisting of R2 and R3. A burst clamp voltage of
0.32V will set the minimum inductor current, IBURST, as
follows:
Design Example
As a design example, consider using the LTC3412 in an
application with the following specifications: VIN = 2.7V to
4.2V, VOUT = 2.5V, IOUT(MAX) = 2.5A, IOUT(MIN) = 10mA, f
= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
3.75V
0.8V
⎛
⎜
⎝
⎞
⎟
⎠
IBURST= 0.32V − 0.2V
= 563mA
(
)
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1. Agroundplaneisrecommended.Ifagroundplanelayer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412. The exposed pad should
be connected to SGND.
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
R2 + R3 = 185k
R2 0.8V
R3 0.32V
1+
=
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
The last two equations shown result in the following
values for R2 and R3: R2 = 110k , R3 = 75k. The value of
R1 can now be determined by solving the equation shown
below:
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
R1
2.5V
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail
in your system).
1+
=
185k 0.8V
R1= 393k
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT and
SGND.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412. Check the following in your layout.
Top Side
Bottom Side
Figure 3. LTC3412 Layout Diagram
3412fb
14
LTC3412
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APPLICATIO S I FOR ATIO
V
IN
2.7V TO 4.2V
C
22pF X5R
R1 392k
FB
††
C
IN1
220μF
1
16
SV
PV
IN
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
680pF X7R
ITH
7.15k
ITH
I
TH
C
C
LTC3412
100pF
L1*
1μH
PGND
PGND
SW
V
4
5
OUT
V
FB
2.5V
2.5A
R2
110k
R3
75k
R
†
T
C
OUT2
10μF
R
OSC
SYNC/MODE
309k
6
7
R
SS
4.7M
+
C
**
OUT1
100μF
×2
RUN
SW
C
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF
GND
X5R 6.3V
3412 F04
*TOKO D62CB A920CY-1ROM
**SANYO POSCAP 4TPB100M
†
TAIYO YUDEN LMK325BJ106MN
SANYO POSCAP 2R5TPC220M
††
Figure 4. Single Lithium-Ion to 2.5V, 2.5A Regulator at 1MHz, Burst Mode Operation Using POSCAPs
3412fb
15
LTC3412
U
TYPICAL APPLICATIO S
2.5V, 2.5A Regulator Using All Ceramic Capacitors
V
IN
2.7V TO 5.5V
C
**
IN3
C1 22pF X5R
R1 392k
100μF
C
IN1
22μF
1
16
SV
PV
IN
X5R 6.3V
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
15k
C
1000pF X7R
ITH
I
TH
C
C
LTC3412
100pF
L1*
PGND
PGND
SW
1μH
V
4
5
OUT
V
FB
2.5V
2.5A
R2
110k
R3
75k
R
T
R
OSC
309k
6
7
C
**
OUT
R
SS
4.7M
SYNC/MODE
RUN
100μF
SW
C
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 F05
*TOKO D62CB A920CY-1ROM
**TDK C4532X5R0J107M
1.8V, 2.5A Step-Down Regulator at 1MHz, Burst Mode Operation
V
IN
3.3V
C1 22pF X5R
R1 232k
C
**
IN1
1
16
22μF
SV
IN
PV
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
ITH
560pF X7R
ITH
10k
I
TH
C2
LTC3412
47pF
L1
1μH*
PGND
PGND
SW
V
4
5
OUT
1.8V
2A
V
FB
R2
R3
75k
110k
R
T
R
309k
OSC
C
**
OUT
6
7
R
22μF
SS
SYNC/MODE
RUN
4.7M
×2
SW
C
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF**
GND
3412 TA05
*SUMIDA CR431R0
**AVX 12066D226MAT
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16
LTC3412
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TYPICAL APPLICATIO S
2.5V, 2.5A Low Output Noise Regulator at 2MHz
V
IN
3.3V
C
C
FF
22pF X7R
IN3
R
IN
0.1μF
5Ω
X5R
R1 392k
C
**
IN1
1
16
100μF
SV
IN
PV
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
ITH
1000pF X7R ITH
22.1k
I
TH
C1
LTC3412
56pF
L1
0.47μH*
PGND
PGND
SW
V
4
5
OUT
2.5V
2.5A
V
FB
R2
182k
R
T
R
137k
OSC
C
**
OUT
6
7
100μF
SYNC/MODE
RUN
×2
SW
C
SS
R
SS
470pF X7R
4.7M
8
SGND
PV
IN
C
IN2
100μF**
GND
3412 TA06
*VISHAY DALE IHLP-2525CZ-01 0.47
**TDK C4532X5R0J107M
Efficiency vs Load Current
2MHz, Low Noise
100
90
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
LOAD CURRENT (A)
3412 TA07
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17
LTC3412
U
TYPICAL APPLICATIO S
3.3V, 2.5A Step-Down Regulator at 1MHz, Forced Continuous Mode Operation
V
IN
5V
C
**
IN3
100μF
C1 22pF X5R
R1 634k
C
IN1
22μF
1
16
SV
PV
IN
X5R 6.3V
IN
R
PG
100k
2
3
4
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
ITH
1000pF X7R ITH
15k
I
TH
C
C
LTC3412
100pF
L1*
PGND
PGND
SW
1μH
V
OUT
V
FB
3.3V
2.5A
R2
200k
5
R
T
R
OSC
309k
6
7
C
**
OUT
SYNC/MODE
RUN
100μF
SW
C
R
SS
4.7M
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 TA01
*PULSE P1166.162T
**TDK C4532X5R0J107M
Lithium-Ion to 3.3V, Single Inductor Buck-Boost Converter
V
IN
2.7V TO 4.2V
C
**
IN3
C1
22pF
100μF
×2
GND
R1 576k
C
IN1
22μF
1
16
SV
PV
IN
X5R 6.3V
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
15k
C
1000pF X7R
ITH
I
TH
D1
C2
100pF
LTC3412
DIODES, INC.
B320A
L1*
2μH
PGND
PGND
SW
4
5
V
V
OUT
FB
3.3V
R2
110k
R3
75k
M1
R
T
SILICONIX
Si2302DS
R
OSC
309k
6
7
C
**
OUT
R
SS
SYNC/MODE
RUN
100μF
4.7M
SW
C
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 F04
V
2.7V
3V
3.5V
4.2V
MAXIMUM I
800mA
900mA
1.05A
IN
OUT
*TOKO D63CB
**TDK C4532X5R0J107M
1.2A
3412fb
18
LTC3412
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
SEE NOTE 4
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BA) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
0.75 ± 0.05
R = 0.115
TYP
4.00 ± 0.10
(4 SIDES)
15
16
0.72 ±0.05
0.55 ± 0.20
PIN 1
TOP MARK
(NOTE 6)
1
2
2.15 ± 0.05
2.15 ± 0.10
(4-SIDES)
(4 SIDES)
4.35 ± 0.05
2.90 ± 0.05
PACKAGE
OUTLINE
(UF16) QFN 1004
0.200 REF
0.30 ± 0.05
0.65 BSC
0.30 ±0.05
0.65 BSC
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
3412fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC3412
U
TYPICAL APPLICATIO
2.5V, 2.5A Step-Down Regulator Synchronized to 1.25MHz
V
IN
2.7V TO 5.5V
C
**
IN3
100μF
C1 22pF X5R
R1 392k
C
IN1
22μF
1
16
SV
IN
PV
IN
X5R 6.3V
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
15k
C
ITH
1000pF X7R
I
TH
LTC3412
C
C
100pF
L1*
PGND
PGND
SW
1μH
V
OUT
4
5
V
FB
2.5V
2.5A
R2 182k
309k
R
T
R
OSC
6
7
C
**
1.25MHz
EXT CLOCK
OUT1
R
SS
4.7M
SYNC/MODE
RUN
100μF
SW
C
SS
470pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 TA02
*TOKO D62CB A920CY-1ROM
**TDK C4532X5R0J107M
RELATED PARTS
PART NUMBER
LTC1701/LTC1701B
LTC1772/LTC1772B
LTC1773
DESCRIPTION
COMMENTS
700mA (I ), 1MHz Step-Down Converter
V
IN
V
IN
V
IN
= 2.5V to 5V, B Version: Burst Mode Defeat, ThinSOTTM
OUT
Constant 550kHz Current Mode Step-Down DC/DC Controller
Constant Frequency 550kHz Step-Down DC/DC Controller
= 2.5V to 9.8V, 94% Efficiency, 100% Duty Cycle, ThinSOT
= 2.65V to 8.5V, 95% Efficiency, V
from 0.8V to V ,
IN
OUT
MSOP-10
LTC1875
1.5A (I ), 500kHz Synchronous Step-Down Converter
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.65V to 6V, 95% Efficiency, PLL, SSOP-16
= 2.65V to 10V, 95% Efficiency, MSOP-8
= 2.65V to 6V, 95% Efficiency, MSOP-8
= 2.65V to 10V, 95% Efficiency, SSOP-16
= 2.65V to 6V, 95% Efficiency, MSOP-8
= 2.65V to 6V, 96% Efficiency, ThinSOT Package
= 2.5V to 5.5V, 95% Efficiency, ThinSOT,
OUT
LTC1877
600mA (I ), 500kHz Synchronous Step-Down Converter
OUT
LTC1878
600mA (I ), 550kHz Synchronous Step-Down Converter
OUT
LTC1879
1.2A (I ), 550kHz Synchronous Step-Down Converter
OUT
LTC3404
600mA (I ), 1.4MHz Synchronous Step-Down Converter
OUT
LTC3405A
LTC3406/LTC3406B
300mA (I ), 1.5MHz Synchronous Step-Down Converter
OUT
600mA (I ), 1.5MHz Synchronous Step-Down Converter
OUT
B Version: Burst Mode Defeat
LTC3411
1.25A (I ), 4MHz Synchronous Step-Down Converter
V
IN
= 2.5V to 5.5V, 95% Efficiency, MSOP-10
OUT
ThinSOT is a trademark of Linear Technology Corporation.
3412fb
LT 0707 REV B • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
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