LTC3418_技术文档

LTC3418

8A, 4MHz, Monolithic

Synchronous Step-Down

Regulator

U

FEATURES

DESCRIPTIO

The LTC^®3418 is a high efficiency, monolithic synchro-

nous step-down DC/DC converter utilizing a constant

frequency, current mode architecture. It operates from an

input voltage range of 2.25V to 5.5V and provides a

regulated output voltage from 0.8V to 5V while delivering

up to 8A of output current. The internal synchronous

power switch increases efficiency and eliminates the need

for an external Schottky diode. Switching frequency is set

by an external resistor or can be synchronized to an

external clock. OPTI-LOOP^®compensation allows the

transient response to be optimized over a wide range of

loads and output capacitors.

■

High Efficiency: Up to 95%

■

8A Output Current

■

2.25V to 5.5V Input Voltage Range

Low R_DS(ON)Internal Switch: 35mΩ

■

Tracking Input to Provide Easy Supply Sequencing

■

Programmable Frequency: 300kHz to 4MHz

■

0.8V ±1% Reference Allows Low Output Voltage

■

Quiescent Current: 380µA

Selectable Forced Continuous/Burst Mode^®Operation

■

with Adjustable Burst Clamp

■

Synchronizable Switching Frequency

■

Low Dropout Operation: 100% Duty Cycle

■

Power Good Output Voltage Monitor

Overtemperature Protected

The LTC3418 can be configured for either Burst Mode

operationorforcedcontinuousoperation.Forcedcontinu-

ous operation reduces noise and RF interference while

Burst Mode operation provides high efficiency by reduc-

ing gate charge losses at light loads. In Burst Mode

operation, external control of the burst clamp level allows

the output voltage ripple to be adjusted according to the

requirements of the application. A tracking input in the

LTC3418 allows for proper sequencing with respect to

another power supply.

■

38-Lead Low Profile (0.75mm) Thermally Enhanced

QFN (5mm × 7mm) Package

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APPLICATIO S

■

Microprocessor, DSP and Memory Supplies

■

Distributed 2.5V, 3.3V and 5V Power Systems

■

Automotive Applications

■

Point of Load Regulation

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131,

6724174.

■

Notebook Computers

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TYPICAL APPLICATIO

Efficiency and Power Loss vs Load Current

2.5V/8A Step-Down Regulator

100

90

80

70

60

50

40

30

20

100000

10000

1000

100

V

IN

2.8V TO 5.5V

C

IN

100µF

EFFICIENCY

SV TRACK PV

IN

0.2µH

V

2.5V

8A

OUT

R

SW

T

C

OUT

2.2M

LTC3418

30.1k

100µF

×2

PGOOD

PGND

SGND

POWER LOSS

RUN/SS

I

1000pF

TH

4.99k SYNC/MODE

V

FB

10

V

= 3.3V

IN

OUT

820pF

332Ω

1.69k

4.32k

= 2.5V

3418 TA01a

1

0.01

0.1

1

10

LOAD CURRENT (A)

3418 TA01b

3418f

1

LTC3418

W W U W

U

W U

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

Input Supply Voltage .................................. –0.3V to 6V

I_TH, RUN/SS, V_FBVoltages......................... –0.3V to V_IN

SYNC/MODE Voltages ............................... –0.3V to V_IN

TRACK Voltage .......................................... –0.3V to V_IN

SW Voltage .................................. –0.3V to (V_IN+ 0.3V)

Operating Ambient Temperature Range

(Note 2) .............................................. – 40°C to 85°C

Junction Temperature (Note 5)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

TOP VIEW

38 37 36 35 34 33 32

SW

1

2

3

4

5

6

7

8

9

31 SW

30 SW

PV

29

28

IN

PV

PGOOD

27 SYNC/MODE

R

T

I

TH

26

25

39

RUN/SS

SGND

V

FB

24 SV

23 PV

22 PV

IN

PV

IN

PV 10

IN

SW 11

SW 12

21 SW

20

SW

13 14 15 16 17 18 19

UHF PACKAGE

38-LEAD (7mm × 5mm) PLASTIC QFN

T_JMAX= 125°C, θ_JA= 34°C/W, θ_JC= 1°C/W

EXPOSED PAD (PIN 39) IS PGND AND MUST BE SOLDERED TO PCB

ORDER PART NUMBER

UH PART MARKING

LTC3418EUHF

3418

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3.3V. (Note 2)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Voltage Range

2.25

5.5

V

IN

Regulated Feedback Voltage

0°C ≤ T ≤ 85°C

(Note 3)

0.792

0.784

0.800

0.808

0.816

V

FB

A

●

I

Feedback Input Current

100

200

0.2

nA

FB

∆V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 2.5V to 5.5V (Note 3)

0.04

%/V

FB

IN

V

Measured in Servo Loop, V = 0.36V

Measured in Servo Loop, V = 0.84V

●

0.02

–0.02

0.2

–0.2

%

LOADREG

ITH

V

Tracking Voltage Offset

Tracking Voltage Range

TRACK Input Current

Power Good Range

V

= 0.4V

15

0.8

200

±9

mV

V

TRACK

0

I

100

±7.5

100

nA

%

Ω

TRACK

∆V

PGOOD

R

Power Good Resistance

150

PGOOD

I

Input DC Bias Current

Active Current

Shutdown

(Note 4)

Q

V

FB

= 0.7V, V = 1V

= 0V

380

0.03

450

1.5

µA

ITH

V

RUN

3418f

2

LTC3418

ELECTRICAL CHARACTERISTICS ^The● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3.3V. (Note 2)

SYMBOL PARAMETER CONDITIONS

= 69.8kΩ

MIN

TYP

MAX

UNITS

f

Switching Frequency

R

OSC

0.88

0.3

1

1.12

4

MHz

OSC

Switching Frequency Range

(Note 6)

f

SYNC Capture Range

(Note 6)

0.3

4

MHz

mΩ

A

SYNC

R

of P-Channel FET

of N-Channel FET

I

= 600mA

35

25

50

35

PFET

NFET

DS(ON)

SW

= –600mA

I

Peak Current Limit

12

17

LIMIT

V

Undervoltage Lockout Threshold

Reference Output

1.75

1.219

2

2.25

1.281

1

V

UVLO

REF

1.250

0.1

0.65

V

I

SW Leakage Current

RUN Threshold

V

= 0V, V = 5.5V

µA

V

LSW

RUN

IN

V

0.5

0.8

RUN

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 2: The LTC3418 is guaranteed to meet performance specifications

Note 5: T is calculated from the ambient temperature T and power

dissipation P as follows:

D

J

A

o

from 0 C to 70 C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

LTC3418: T = T + (P )(34°C/W)

J

A

D

Note 6: This parameter is guaranteed by design and characterization.

Note 3: The LTC3418 is tested in a feedback loop that adjusts V to

FB

achieve a specified error amplifier output voltage (I ).

TH

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless otherwise noted.}

Internal Reference Voltage

vs Temperature

Switch On-Resistance

vs Input Voltage

On-Resistance vs Temperature

50

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

0.8000

0.7995

0.7990

0.7985

0.7980

0.7975

0.7970

0.7965

0.7960

V

= 3.3V

V

= 3.3V

IN

PFET

NFET

0

–40 –20

0

20 40 60 80 100 120

TEMPERATURE (°C)

40 60

TEMPERATURE (°C)

–40 –20

0

20

80 100 120

2.25 2.75 3.25 3.75

5.25

4.25 4.75

INPUT VOLTAGE (V)

3418 G02

3418 G07

3418 G01

3418f

3

LTC3418

U W

TYPICAL PERFOR A CE CHARACTERISTICS

T_A= 25°C unless otherwise noted.

Quiescent Current

vs Input Voltage

Switch Leakage vs Input Voltage

Frequency vs R_OSC

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4500

500

450

400

350

300

250

200

150

100

50

V

= 3.3V

IN

4000

3500

3000

2500

2000

1500

1000

500

NFET

PFET

0

2.25 2.75 3.25 3.75

INPUT VOLTAGE (V)

5.25

4.25 4.75

10

50

90

130

(kΩ)

250

170

210

2.5

3

4

4.5

5

5.5

3.5

R

INPUT VOLTAGE (V)

OSC

3418 G03

3418 G08

3418 G04

Efficiency and Power Loss

vs Load Current

Frequency vs Temperature

Frequency vs Input Voltage

100

90

80

70

60

50

40

30

20

100000

10000

1000

100

1100

1080

1060

1040

1020

1000

980

1100

1080

1060

1040

1020

1000

980

V

= 3.3V

IN

EFFICIENCY

POWER LOSS

960

10

940

V

IN

V

OUT

= 3.3V

920

= 2.5V

1

900

0.01

0.1

1

10

2.25 2.75 3.25 3.75

INPUT VOLTAGE (V)

5.25

–40 –20

0

20 40 60 80 100 120

4.25 4.75

LOAD CURRENT (A)

TEMPERATURE (°C)

3418 TA01b

3418 G05

3418 G06

Efficiency vs Load Current

100

90

100

90

100

90

Burst Mode OPERATION

3.3V

5V

80

5V

70

FORCED CONTINUOUS

60

50

60

50

60

50

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

V

= 3.3V

Burst Mode OPERATION

OUT

FORCED CONTINUOUS

OUT

IN

OUT

= 2.5V

V

= 2.5V

V

= 2.5V

0.01

0.1

1

10

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

3418 G10

3418 G11

3418 G12

3418f

4

LTC3418

U W

TYPICAL PERFOR A CE CHARACTERISTICS

T_A= 25°C unless otherwise noted.

Peak Inductor Current

vs Burst Clamp Voltage

Load Step Transient

Load Regulation

12

10

8

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

V

= 3.3V

IN

OUT

= 1.8V

OUTPUT

VOLTAGE

f = 1MHz

100mV/DIV

6

INDUCTOR

CURRENT

5A/DIV

4

5V

3418 G15

2

V

= 3.3V

20µs/DIV

IN

OUT

3.3V

= 2.5V

LOAD STEP: 800mA TO 8A

0

0.5 0.6

(V)

0

0.1 0.2 0.3 0.4

0.7 0.8

5

6

0

1

2

3

4

7

8

V

LOAD CURRENT (A)

BCLAMP

3418 G13

3418 G14

Load Step Transient

Burst Mode Operation

Start-Up Transient

OUTPUT

VOLTAGE

100mV/DIV

OUTPUT

VOLTAGE

100mV/DIV

OUTPUT

VOLTAGE

500mV/DIV

INDUCTOR

CURRENT

5A/DIV

INDUCTOR

CURRENT

1A/DIV

INDUCTOR

CURRENT

2A/DIV

3418 G16

3418 G17

3418 G18

V

= 3.3V

40µs/DIV

V

= 3.3V

20µs/DIV

V

= 3.3V

1ms/DIV

IN

OUT

IN

OUT

IN

OUT

= 2.5V

LOAD STEP: 3A TO 8A

LOAD: 200mA

LOAD: 8A

U

PI FU CTIO S

all functions are disabled drawing <1.5µA of supply cur-

rent. A capacitor to ground from this pin sets the ramp

time to full output current.

SW (Pins 1, 2, 11, 12, 20, 21, 30, 31): Switch Node

Connection to Inductor. This pin connects to the drains of

the internal main and synchronous power MOSFET

switches.

SGND (Pin 8): Signal Ground. All small-signal compo-

nents and compensation components should connect to

this ground, which in turn connects to PGND at one point.

PV_IN(Pins 3, 4, 9, 10, 22, 23, 28, 29): Power Input

Supply. Decouple this pin to PGND with a capacitor.

PGND (Pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37,

PGOOD (Pin 5): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage is

not within ±7.5% of regulation point.

38): Power Ground. Connect this pin closely to the (–)

terminal of C_INand C_OUT

.

V_REF(Pin 16): Reference Output. Decouple this pin with a

2.2µF capacitor.

R_T(Pin6):OscillatorResistorInput. Connectingaresistor

to ground from this pin sets the switching frequency.

RUN/SS(Pin7):RunControlandSoft-StartInput.Forcing

thispinbelow0.5VshutsdowntheLTC3418. Inshutdown

SV_IN(Pin 24): Signal Input Supply. Decouple this pin to

SGND with a capacitor.

3418f

5

LTC3418

U

PI FU CTIO S

SV_IN. Connecting this pin to a voltage between 0V and 1V

selects Burst Mode operation with the burst clamp set to

the pin voltage.

V_FB(Pin25): FeedbackPin. Receivesthefeedbackvoltage

from a resistive divider connected across the output.

I_TH(Pin 26): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is from 0.2V to

1.4V with 0.4V corresponding to the zero-sense voltage

(zero current).

TRACK(Pin35):VoltageTrackingInput. Feedbackvoltage

will regulate to the voltage on this pin during start-up

power sequencing.

Exposed Pad (Pin 39): The Exposed Pad is PGND and

must be soldered to the PCB ground.

SYNC/MODE (Pin 27): Mode Select and External Clock

Synchronization Input. To select Forced Continuous, tie to

W

BLOCK DIAGRA

24

SV

8

26

PV

IN

29

SGND

I

TH

IN

3

4

9

V

REF

16

35

28

23

22

VOLTAGE

REFERENCE

SLOPE

COMPENSATION

RECOVERY

PMOS CURRENT

COMPARATOR

TRACK

10

ERROR

AMPLIFIER

BCLAMP

BURST

COMPARATOR

+

–

+

–

+

V

FB

25

+

SYNC/MODE

SLOPE

COMPENSATION

0.74V

+

–

SW

OSCILLATOR

1

2

11

20

30

12

21

31

–

+

–

LOGIC

NMOS

0.86V

CURRENT

COMPARATOR

–

+

RUN/SS

PGOOD

RUN

7

5

PGND

13

14

15

17

18

19

32

33

34

36

37

CURRENT

REVERSE

COMPARATOR

R

SYNC/MODE

T

6

27

38

3418 BD

3418f

6

LTC3418

U

OPERATIO

Main Control Loop

Burst Mode Operation

The LTC3418 is a monolithic, constant frequency, current

mode step-down DC/DC converter. During normal opera-

tion, the internal top power switch (P-channel MOSFET) is

turned on at the beginning of each clock cycle. Current in

the inductor increases until the current comparator trips

and turns off the top power MOSFET. The peak inductor

current at which the current comparator shuts off the top

power switch is controlled by the voltage on the I_THpin.

The error amplifier adjusts the voltage on the I_THpin by

comparing the feedback signal from a resistor divider on

the V_FBpin with an internal 0.8V reference. When the load

current increases, it causes a reduction in the feedback

voltage relative to the reference. The error amplifier raises

the I_THvoltage until the average inductor current matches

the new load current. When the top power MOSFET shuts

off, the synchronous power switch (N-channel MOSFET)

turns on until either the bottom current limit is reached or

the beginning of the next clock cycle. The bottom current

limit is set at –8A for force continuous mode and 0A for

Burst Mode operation.

Connecting the SYNC/MODE pin to a voltage in the range

of 0V to 1V enables Burst Mode operation. In Burst Mode

operation, the internal power MOSFETs operate intermit-

tently at light loads. This increases efficiency by minimiz-

ing switching losses. During Burst Mode operation, the

minimum peak inductor current is externally set by the

voltage on the SYNC/MODE pin and the voltage on the I_TH

pin is monitored by the burst comparator to determine

when sleep mode is enabled and disabled. When the

average inductor current is greater than the load current,

the voltage on the I_THpin drops. As the I_THvoltage falls

below 350mV, the burst comparator trips and enables

sleep mode. During sleep mode, the top power MOSFET is

held off while the load current is solely supplied by the

output capacitor. When the output voltage drops, the top

and bottom power MOSFETs begin switching to bring the

output back into regulation. This process repeats at a rate

that is dependent on the load demand.

Pulse skipping operation can be implemented by connect-

ing the SYNC/MODE pin to ground. This forces the burst

clamp level to be at 0V. As the load current decreases, the

peak inductor current will be determined by the voltage on

theI_THpinuntiltheI_THvoltagedropsbelow400mV. Atthis

point, the peak inductor current is determined by the

minimum on-time of the current comparator. If the load

demand is less than the average of the minimum on-time

inductor current, switching cycles will be skipped to keep

the output voltage in regulation.

The operating frequency is externally set by an external

resistor connected between the R_Tpin and ground. The

practical switching frequency can range from 300kHz to

4MHz.

Overvoltage and undervoltage comparators will pull the

PGOOD output low if the output voltage comes out of

regulation by ±7.5%. In an overvoltage condition, the top

powerMOSFETisturnedoffandthebottompowerMOSFET

is switched on until either the overvoltage condition clears

or the bottom MOSFET’s current limit is reached.

Frequency Synchronization

TheinternaloscillatoroftheLTC3418canbysynchronized

toanexternalclockconnectedtotheSYNC/MODEpin.The

frequency of the external clock can be in the range of

300kHz to 4MHz.

Forced Continuous

Connecting the SYNC/MODE pin to SV_INwill disable Burst

Mode operation and force continuous current operation.

At light loads, forced continuous mode operation is less

efficient than Burst Mode operation, but may be desirable

in some applications where it is necessary to keep switch-

ing harmonics out of a signal band. The output voltage

ripple is minimized in this mode.

For this application, the oscillator timing resistor should

be chosen to correspond to a frequency that is 25% lower

than the synchronization frequency. During synchroniza-

tion, the burst clamp is set to 0V, and each switching cycle

begins at the falling edge of the clock signal.

3418f

7

LTC3418

U

OPERATIO

Dropout Operation

Short-Circuit Protection

When the input supply voltage decreases toward the

output voltage, the duty cycle increases toward the maxi-

mum on-time. Further reduction of the supply voltage

forces the main switch to remain on for more than one

cycle eventually reaching 100% duty cycle. The output

voltage will then be determined by the input voltage minus

the voltage drop across the internal P-channel MOSFET

and the inductor.

Whentheoutputisshortedtoground,theinductorcurrent

decays very slowly during a single switching cycle. To

prevent current runaway from occurring, a secondary

current limit is imposed on the inductor current. If the

inductor valley current increases larger than 15A, the top

powerMOSFETwillbeheldoffandswitchingcycleswillbe

skipped until the inductor current is reduced.

Voltage Tracking

Low Supply Operation

Some microprocessors and DSP chips need two power

supplieswithdifferentvoltagelevels. Thesesystemsoften

require voltage sequencing between the core power sup-

ply and the I/O power supply. Without proper sequencing,

latch-up failure or excessive current draw may occur that

could result in damage to the processor’s I/O ports or the

I/O ports of a supporting system device such as memory,

an FPGA or a data converter. To ensure that the I/O loads

are not driven until the core voltage is properly biased,

tracking of the core supply and the I/O supply voltage is

necessary.

The LTC3418 is designed to operate down to an input

supply voltage of 2.25V. One important consideration at

low input supply voltages is that the R_DS(ON)of the

P-channel and N-channel power switches increases. The

user should calculate the power dissipation when the

LTC3418 is used at 100% duty cycle with low input

voltages to ensure that thermal limits are not exceeded.

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant fre-

quency architectures by preventing subharmonic oscilla-

tions at duty cycles greater than 50%. It is accomplished

internally by adding a compensating ramp to the inductor

current signal. Normally, the maximum inductor peak

current is reduced when slope compensation is added. In

the LTC3418, however, slope compensation recovery is

implemented to keep the maximum inductor peak current

constant throughout the range of duty cycles. This keeps

the maximum output current relatively constant regard-

less of duty cycle.

Voltage tracking is enabled by applying a ramp voltage to

the TRACK pin. When the voltage on the TRACK pin is

below 0.8V, the feedback voltage will regulate to this

tracking voltage. When the tracking voltage exceeds 0.8V,

tracking is disabled and the feedback voltage will regulate

to the internal reference voltage.

Voltage Reference Output

The LTC3418 provides a 1.25V reference voltage that is

capable of sourcing up to 5mA of output current. This

reference voltage is generated from a linear regulator and

isintendedforapplicationsrequiringalownoisereference

voltage. To ensure that the output is stable, the reference

voltagepinshouldbedecoupledwithaminimumof2.2µF.

3418f

8

LTC3418

W U U

APPLICATIO S I FOR ATIO

U

The basic LTC3418 application circuit is shown on the

front page of this data sheet. External component selec-

tion is determined by the maximum load current and

begins with the selection of the operating frequency and

Having a lower ripple current reduces the core losses in

the inductor, the ESR losses in the output capacitors and

the output voltage ripple. Highest efficiency operation is

achieved at low frequency with small ripple current. This,

however, requires a large inductor.

inductor value followed by C_INand C_OUT

.

A reasonable starting point for selecting the ripple current

is ∆I_L= 0.4(I_MAX). The largest ripple current occurs at the

highest V_IN. To guarantee that the ripple current stays

below a specified maximum, the inductor value should be

chosen according to the following equation:

Operating Frequency

Selection of the operating frequency is a tradeoff between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

⎛

⎞⎛

⎞

V_OUT

L =

1–

⎜

⎟⎜

⎟

f∆I

V

IN(MAX)

⎝

⎠⎝

⎠

L(MAX)

The inductor value will also have an effect on Burst Mode

operation. The transition from low current operation

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efficiency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency to

increase.

The operating frequency of the LTC3418 is determined by

an external resistor that is connected between the R_Tpin

andground.Thevalueoftheresistorsetstherampcurrent

that is used to charge and discharge an internal timing

capacitor within the oscillator and can be calculated by

using the following equation:

7.3 •10¹⁰

R_OSC

=

Ω – 2.5kΩ

[ ]

f

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3418 imposes a minimum

limit on the operating duty cycle. The minimum on-time is

typically80ns. Therefore, theminimumdutycycleisequal

to:

Inductor Core Selection

Once the value for L is known, the type of inductor must be

selected. Actual core loss is independent of core size for a

fixed inductor value, but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance re-

quires more turns of wire and therefore copper losses will

increase.

100 • 80ns • f(Hz)

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ∆I_Lincreases with higher V_INor V_OUTand

decreases with higher inductance:

Ferritedesignshaveverylowcorelossesandarepreferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

⎛

⎞

⎟

V_OUT

fL

⎛

⎜

V_OUT

⎞

⎟

∆I_L=

1–

⎜

⎝

V

IN

⎠

⎝

⎠

3418f

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APPLICATIO S I FOR ATIO

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy mate-

rials are small and don’t radiate much energy, but gener-

ally cost more than powdered iron core inductors with

similar characteristics. The choice of which style inductor

to use mainly depends on the price vs size requirements

and any radiated field/EMI requirements. New designs for

surface mount inductors are available from Coiltronics,

Coilcraft, Toko and Sumida.

currenthandlingrequirements.Drytantalum,specialpoly-

mer, aluminum electrolytic and ceramic capacitors are all

available in surface mount packages. Special polymer

capacitors offer very low ESR but have lower capacitance

density than other types. Tantalum capacitors have the

highest capacitance density but it is important to only use

types that have been surge tested for use in switching

power supplies. Aluminum electrolytic capacitors have

significantly higher ESR, but can be used in cost-sensitive

applications provided that consideration is given to ripple

current ratings and long term reliability. Ceramic capaci-

tors have excellent low ESR characteristics but can have a

high voltage coefficient and audible piezoelectric effects.

The high Q of ceramic capacitors with trace inductance

can also lead to significant ringing.

C_INand C_OUTSelection

The input capacitance, C_IN, is needed to filter the trapezoi-

dal wave current at the source of the top MOSFET. To

preventlargevoltagetransientsfromoccurring,alowESR

input capacitor sized for the maximum RMS current

should be used. The maximum RMS current is given by:

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at the input and

output. When a ceramic capacitor is used at the input and

thepowerissuppliedbyawalladapterthroughlongwires,

a load step at the output can induce ringing at the input,

V_IN. At best, this ringing can couple to the output and be

mistaken as loop instability. At worst, a sudden inrush of

current through the long wires can potentially cause a

voltage spike at V_INlarge enough to damage the part.

V_OUT

V

IN

V

IN

V_OUT

I_RMS= I_OUT(MAX)

– 1

This formula has a maximum at V_IN= 2V_OUT, where I_RMS

= I_OUT/2. This simple worst-case condition is commonly

usedfordesignbecauseevensignificantdeviationsdonot

offer much relief. Note that ripple current ratings from

capacitor manufacturers are often based on only 2000

hours of life which makes it advisable to further derate the

capacitor, orchooseacapacitorratedatahighertempera-

ture than required. Several capacitors may also be paral-

leled to meet size or height requirements in the design.

When choosing the input and output ceramic capacitors,

choose the X5R or X7R dielectric formulations. These

dielectrics have the best temperature and voltage charac-

teristics of all the ceramics for a given value and size.

The selection of C_OUTis determined by the effective series

resistance (ESR) that is required to minimize voltage

ripple and load step transients as well as the amount of

bulk capacitance that is necessary to ensure that the

control loop is stable. Loop stability can be checked by

viewing the load transient response as described in a later

section. The output ripple, ∆V_OUT, is determined by:

Output Voltage Programming

The output voltage is set by an external resistive divider

according to the following equation:

⎛

1

⎞

R2

R1

⎛

⎝

⎞

⎟

⎠

∆V_OUT≤ ∆I ESR +

⎜

⎟

L

V_OUT= 0.8 1+

⎜

⎝

8fC_OUT

⎠

The output ripple is highest at maximum input voltage

since ∆I_Lincreases with input voltage. Multiple capacitors

placedinparallelmaybeneededtomeettheESRandRMS

The resistive divider allows pin V_FBto sense a fraction of

the output voltage as shown in Figure 1.

3418f

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APPLICATIO S I FOR ATIO

U

V

OUT

SYNC/MODE pin to ground. This sets I_BURSTto 0A. In this

condition, the peak inductor current is limited by the mini-

mum on-time of the current comparator; and the lowest

output voltage ripple is achieved while still operating dis-

continuously.Duringverylightoutputloads,pulseskipping

allowsonlyafewswitchingcyclestobeskippedwhilemain-

taining the output voltage in regulation.

R2

V

FB

LTC3418

SGND

R1

3418 F01

Figure 1. Setting the Output Voltage

Voltage Tracking

Burst Clamp Programming

The LTC3418 allows the user to program how its output

voltagerampsduringstart-upbymeansoftheTRACKpin.

Through this pin, the output voltage can be set up to either

track coincidentally or ratiometrically follow another out-

put voltage as shown in Figure 2. If the voltage on the

TRACK pin is less than 0.8V, voltage tracking is enabled.

During voltage tracking, the output voltage regulates to

the tracking voltage through a resistor divider network.

IfthevoltageontheSYNC/MODEpinislessthanV_INby1V,

Burst Mode operation is enabled. During Burst Mode

operation, the voltage on the SYNC/MODE pin determines

the burst clamp level, which sets the minimum peak

inductorcurrent, I_BURST, foreachswitchingcycle. Agraph

showing the relationship between the minimum peak

inductor current and the voltage on the SYNC/MODE pin

can be found in the Typical Performance Characteristics

section. In the graph, V_BURSTis the voltage on the SYNC/

MODE pin. I_BURSTcan only be programmed in the range of

0A to 10A. For values of V_BURSTless than 0.4V, I_BURSTis

set at 0A. As the output load current drops, the peak

inductor currents decrease to keep the output voltage in

regulation. When the output load current demands a peak

inductor current that is less than I_BURST, the burst clamp

will force the peak inductor current to remain equal to

I_BURSTregardlessoffurtherreductionsintheloadcurrent.

Since the average inductor current is greater than the

output load current, the voltage on the I_THpin will de-

crease. When the I_THvoltage drops to 350mV, sleep mode

is enabled in which both power MOSFETs are shut off and

switching action is discontinued to minimize power con-

sumption. All circuitry is turned back on and the power

MOSFETs begin switching again when the output voltage

dropsoutofregulation. ThevalueforI_BURSTisdetermined

by the desired amount of output voltage ripple. As the

valueofI_BURSTincreases, thesleepperiodbetweenpulses

and the output voltage ripple increase. The burst clamp

voltage, V_BURST, can be set by a resistor divider from the

V_FBpin to the SGND pin as shown in the Typical Applica-

tion on the front page of this data sheet.

V

OUT2

OUT1

3418 F02a

TIME

Figure 2a. Coincident Tracking

V

OUT2

OUT1

3418 F02a

TIME

Pulse skipping, which is a compromise between low out-

put voltage ripple and efficiency during low load current

operation, can be implemented by connecting the

Figure 2b. Ratiometric Sequencing

3418f

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LTC3418

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APPLICATIO S I FOR ATIO

The output voltage during tracking can be calculated with

as shown in Typical Application on the front page of this

data sheet. The soft-start duration can be calculated by

using the following formula:

the following equation:

R2

R1

⎛

⎝

⎞

⎟

⎠

V_OUT= V_TRACK1+

,V_TRACK< 0.8V

⎜

V

IN

t

_SS= R_SS•C_SS•In

Seconds

[

]

V – 1.8V

IN

To implement the coincident tracking in Figure 2a, con-

nect an extra resistor divider to the output of V_OUT2and

connect its midpoint to the TRACK pin of the LTC3418 as

shown in Figure 3a. The ratio of this divider should be

selected the same as that of V_OUT1’s resistor divider. To

implement the ratiometric sequencing in Figure 2b, no

extra resistor divider is necessary. Simply connect the

TRACK pin to V_FB2, as shown in Figure 3b.

When the voltage on the RUN/SS pin is raised above 2V,

the full current range becomes available on I_TH.

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

oftenusefultoanalyzeindividuallossestodeterminewhat

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

V

OUT2

(MASTER)

R2

R1

R4

R3

R2

TRACK

Efficiency = 100% – (L1 + L2 + L3 + ...)

TRACK

V

FB(MASTER)

V

FB(MASTER)

R1

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

3418 F03

(3a) Coincident Setup

(3b) Ratiometric Setup

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses: V_INquiescent current and I²R losses.

Figure 3

Frequency Synchronization

The V_INquiescent current loss dominates the efficiency

loss at very low load currents whereas the I²R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence.

The LTC3418’s internal oscillator can be synchronized to

an external clock signal. During synchronization, the top

MOSFET turn-on is locked to the falling edge of the

externalfrequencysource.Thesynchronizationfrequency

range is 300kHz to 4MHz. Synchronization only occurs if

the external frequency is greater than the frequency set by

the external resistor. Because slope compensation is

generated by the oscillator’s RC circuit, the external fre-

quency should be set 25% higher than the frequency set

by the external resistor to ensure that adequate slope

compensation is present.

1.TheV_INquiescentcurrentisduetotwocomponents:the

DC bias current as given in the Electrical Characteristics

and the internal main switch and synchronous switch gate

charge currents. The gate charge current results from

switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge dQ moves

from V_INto ground. The resulting dQ/dt is the current out

of V_INthat is typically larger than the DC bias current. In

continuous mode, I_GATECHG= f(Q_T+ Q_B) where Q_Tand Q_B

are the gate charges of the internal top and bottom

switches. Both the DC bias and gate charge losses are

proportional to V_INand thus their effects will be more

pronounced at higher supply voltages.

Soft-Start

The RUN/SS pin provides a means to shut down the

LTC3418 as well as a timer for soft-start. Pulling the RUN/

SS pin below 0.5V places the LTC3418 in a low quiescent

current shutdown state (I_Q< 1.5µA).

The LTC3418 contains a soft-start clamp that can be set

externally with a resistor and capacitor on the RUN/SS pin

3418f

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APPLICATIO S I FOR ATIO

U

2. I²R losses are calculated from the resistances of the

internal switches, R_SW, and external inductor R_L. In con-

tinuous mode the average output current flowing through

inductor L is “chopped” between the main switch and the

synchronous switch. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET R_DS(ON)and the duty cycle (DC) as follows:

The junction temperature, T_J, is given by:

T_J= T_A+ T_R

where T_Ais the ambient temperature.

Note that at higher supply voltages, the junction tempera-

ture is lower due to reduced switch resistance (R_DS(ON)).

Checking Transient Response

R_SW= (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current.

The R_DS(ON)for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus, to obtain I²R losses, simply add R_SWto R_L

and multiply the result by the square of the average output

current.

When a load step occurs, V_OUTimmediately shifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

series resistance of C_OUT. ∆I_LOADalso begins to charge or

dischargeC_OUTgeneratingafeedbackerrorsignalusedby

the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability prob-

lem. The I_THpin external components and output capaci-

tor shown in the Typical Application on the front page of

this data sheet will provide adequate compensation for

most applications.

Other losses including C_INand C_OUTESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

Thermal Considerations

In most applications, the LTC3418 does not dissipate

much heat due to its high efficiency.

But, in applications where the LTC3418 is running at high

ambient temperature with low supply voltage and high

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will be turned off and the SW node

will become high impedance.

Design Example

As a design example, consider using the LTC3418 in an

application with the following specifications: V_IN= 3.3V,

V_OUT= 2.5V, I_OUT(MAX)= 8A, I_OUT(MIN)= 200mA, f = 1MHz.

Because efficiency is important at both high and low load

current, Burst Mode operation will be utilized.

To avoid the LTC3418 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

First, calculate the timing resistor:

7.3 •10¹⁰

R_OSC

=

– 2.5k = 70.5k

1•10⁶

Use a standard value of 69.8k. Next, calculate the inductor

value for about 40% ripple current:

T_R= (P_D)(θ_JA)

where P_Dis the power dissipated by the regulator and θ_JA

is the thermal resistance from the junction of the die to the

ambient temperature. For the 38-Lead 5mm × 7mm QFN

package, the θ_JAis 34°C/W.

⎛

⎞

2.5V

1MHz 3.2A

2.5V

3.3V

⎛

⎜

⎝

⎞

⎟

⎠

L =

1–

= 0.19µH

⎜

⎟

(

)(

)

⎝

⎠

3418f

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APPLICATIO S I FOR ATIO

Using a 0.2µH inductor results in a maximum ripple

divider consisting of R2 and R3. A burst clamp voltage of

0.67V will set the minimum inductor current, I_BURST, to

approximately 1.2A.

current of:

⎛

⎞

2.5V

1MHz 0.2µH

2.5V

3.3V

⎛

⎜

⎝

⎞

⎟

⎠

∆I_L=

1–

= 3.03A

If we set the sum of R2 and R3 to 200k, then the following

equations can be solved.

⎜

⎟

(

)(

)

⎝

⎠

C_OUTwill be selected based on the ESR that is required to

satisfy the output voltage ripple requirement and the bulk

capacitance needed for loop stability. For this design, five

100µF ceramic capacitors will be used.

R2 +R3 = 200k

R2 0.8V

1+

=

R3 0.67V

The two equations shown above result in the following

values for R2 and R3: R2 = 33.2k, R3 = 169k. The value

of R1 can now be determined by solving the equation:

C_INshould be sized for a maximum current rating of:

2.5V 3.3V

⎛

⎝

⎞

I_RMS= 8A

– 1 = 3.43A_RMS

(

)

⎜

⎟

⎠

3.3V 2.5V

R1

2.5V

1+

=

202.2k 0.8V

Decoupling the PV_INand SV_INpins with four 100µF

capacitors is adequate for this application.

R1= 430k

The burst clamp and output voltage can now be pro-

grammed by choosing the values of R1, R2 and R3. The

voltageontheMODEpinwillbesetto0.67Vbytheresistor

A value of 432k will be selected for R1. Figure 4 shows the

complete schematic for this design example.

L1

0.2µH

V

2.5V

8A

OUT

3

4

1

V

IN

3.3V

PV

SV

SW

IN

C

OUT

2

IN

100µF

×4

100µF

×5

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C1

R1

22pF

432k

X7R

R

PG

SS

2.2M 100k

R

SVIN

100Ω

V

C

FB

SVIN

1µF

R2

33.2k

LTC3418

TRACK SYNC/MODE

X7R

35

5

27

38

37

36

34

33

32

19

18

16

C

SS

1000pF

X7R

PGOOD

RUN/SS

PGND

7

26

I

TH

R

OSC

69.8k

6

8

R3

169k

R

ITH

7.5k

R

T

C

ITH

820pF

X7R

SGND

PGND

13

14

15

17

C1

47pF

X7R

V

REF

C

REF

2.2µF

X7R

C

, C : AVX 18126D107MAT

IN OUT

3418 F04

L1: TOKO FDV0620-R20M

Figure 4. 2.5V, 8A Regulator at 1MHz, Burst Mode Operation

3418f

14

LTC3418

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APPLICATIO S I FOR ATIO

U

PC Board Layout Checklist

3. Keep the switching node, SW, away from all sensitive

small-signal nodes.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3418. Check the following in your layout.

4. Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of

power components. You can connect the copper areas to

any DC net (PV_IN, SV_IN, V_OUT, PGND, SGND or any other

DC rail in your system).

1. Agroundplaneisrecommended. Ifagroundplanelayer

is not used, the signal and power grounds should be

segregated with all small-signal components returning to

the SGND pin at one point which is then connected to the

PGND pin close to the LTC3418.

5. Connect the V_FBpin directly to the feedback resistors.

The resistor divider must be connected between V_OUTand

SGND.

2. Connect the (+) terminal of the input capacitor(s), C_IN,

as close as possible to the PV_INpin. This capacitor

provides the AC current into the internal power MOSFETs.

6. To minimize switching noise coupling to SV_IN, place a

local filter between SV_INand PV_IN.

Top Layer

Bottom Layer

Figure 5. LTC3418 Layout Diagram

3418f

15

LTC3418

TYPICAL APPLICATIO S

U

3.3V, 8A Step-Down Regulator Synchronized to 1.25MHz

L1

0.33µH

V

3.3V

8A

OUT

3

4

1

V

IN

5V

PV

SV

SW

IN

C

2

IN

OUT

100µF

×2

100µF

×3

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C1

R1

1000pF

6.34k

X7R

R

PG

SS

2.2M 100k

V

FB

C

R

SVIN

100Ω

LTC3418

1µF

35

5

16

38

37

36

34

33

32

19

18

17

C

X7R

SS

V

TRACK

V

REF

1000pF

X7R

C

REF

PGOOD

RUN/SS

PGND

2.2µF

7

X7R

PGND

26

I

TH

R

69.8k

OSC

6

8

R2

2k

R

ITH

R

C

T

ITH

2200pF

X7R

2k

SGND

C1

47pF

X7R

13

14

15

27

PGND

SYNC/MODE

C

, C : TDK C3225X5R0J107M

IN OUT

3418 TA02

L1: VISHAY DALE IHLP-2525CZ-01

1.25MHz CLOCK

1.2V, 8A Step-Down Regulator at 2MHz, Forced Continuous Mode

L1

0.2µH

V

1.2V

8A

OUT

3

4

1

V

IN

3.3V

PV

SV

SW

IN

C

2

OUT

C

IN

100µF

×3

100µF

×4

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C1

1000pF

X7R

R1

1k

R

PG

SS

2.2M 100k

V

FB

C

R

SVIN

100Ω

SVIN

LTC3418

1µF

35

27

5

16

38

37

36

34

33

32

19

18

17

X7R

V

REF

TRACK

V

REF

C

REF

C

SS

SYNC/MODE

PGOOD

PGND

2.2µF

1000pF

X7R

PGND

7

RUN/SS

26

R2

2k

I

TH

R

OSC

30.1k

6

8

R

ITH

4.99k

R

T

C

ITH

2200pF

X7R

SGND

PGND

C1

47pF

X7R

14

15

13

C

, C : AVX 12106D107MAT

IN OUT

3418 TA03

L1: COOPER FP3-R20

3418f

16

LTC3418

U

TYPICAL APPLICATIO S

1.8V, 8A Step-Down Regulator with Tracking

I/O SUPPLY

2.5V

R4

2k

R3

2.55k

L1

0.2µH

V

1.8V

8A

OUT

35

3

1

TRACK

SW

C

2

OUT

V

IN

PV

SW

IN

100µF

×2

3.3V

C

4

11

12

20

21

30

31

25

IN

100µF

×4

9

C1

R1

2.55k

1000pF

10

22

23

29

28

X7R

R

PG

100k

SS

2.2M

V

FB

R

SVIN

LTC3418

100Ω

24

5

16

38

37

36

34

33

32

19

18

17

V

SV

V

REF

IN

C

SVIN

REF

C

SS

PGOOD

PGND

1µF

2.2µF

1000pF

X7R

27

7

X7R

SYNC/MODE

RUN/SS

PGND

26

6

R2

2k

I

TH

R

69.8k

OSC

R

ITH

R

C

T

ITH

3.32k

8

2200pF

X7R

SGND

PGND

C1

47pF

X7R

13

14

15

C

, C : TDK C3225X5R0J107M

IN OUT

3418 TA04

L1: VISHAY DALE IHLP-2525CZ-01

3418f

17

LTC3418

TYPICAL APPLICATIO S

U

1.8V, 16A Step-Down Regulator

L1

0.2µH

3

4

1

V

IN

3.3V

PV

SV

SW

IN

C

2

IN1

100µF

×4

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C2

R1

2.55k

1000pF

X7R

R

SS1

2.2M

PG1

100k

V

FB

C

R

SVIN1

100Ω

LTC3418

1µF

35

5

38

37

36

34

33

32

19

18

17

16

C

X7R

SS1

TRACK

PGND

1000pF

X7R

PGOOD

RUN/SS

V

1.8V

16A

OUT

7

C

OUT

26

I

TH

100µF

×4

C1A

47pF

X7R

R

OSC1

59k

6

8

R

T

R2

2k

SGND

13

14

15

27

PGND

SYNC/MODE

V

C

REF

REF1

2.2µF

X7R

R

ITH

2k

C

ITH

2200pF

X7R

L2

0.2µH

3

4

1

PV

IN

PV

IN

PV

IN

PV

IN

PV

IN

PV

IN

PV

IN

PV

IN

SV

IN

SW

C

IN2

2

100µF

×4

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C3

R3

2.55k

1000pF

X7R

R

PG2

100k

SS2

2.2M

V

FB

C

R

SVIN2

LTC3418

1µF

100Ω

35

5

38

37

36

34

33

32

19

18

17

16

C

X7R

SS2

TRACK

PGOOD

RUN/SS

PGND

1000pF

X7R

7

26

6

I

TH

R

OSC2

69.8k

C1B

47pF

X7R

R

T

R4

2k

8

SGND

13

14

15

27

PGND

SYNC/MODE

V

C

REF

REF2

2.2µF

C

, C , C : TDK C3225X5R0J107M

IN1 IN2 OUT

X7R

L1, L2: VISHAY DALE IHLP-2525CZ-01

3418 TA06

3418f

18

LTC3418

U

PACKAGE DESCRIPTIO

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701)

0.70 ± 0.05

5.50 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

3.15 ± 0.05

(2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.20 ± 0.05 (2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

3.15 ± 0.10

(2 SIDES)

0.75 ± 0.05

5.00 ± 0.10

(2 SIDES)

0.435 0.18

0.18

37 38

0.00 – 0.05

PIN 1

TOP MARK

(SEE NOTE 6)

1

2

0.23

5.15 ± 0.10

(2 SIDES)

7.00 ± 0.10

(2 SIDES)

0.40 ± 0.10

0.200 REF 0.25 ± 0.05

R = 0.115

TYP

(UH) QFN 1203

0.50 BSC

0.200 REF

BOTTOM VIEW—EXPOSED PAD

0.75 ± 0.05

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3418f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC3418

U

TYPICAL APPLICATIO

Low Noise 1.5V, 8A Step-Down Regulator

L1

0.2µH

V

1.5V

8A

OUT

3

4

1

V

IN

2.5V

PV

SV

SW

IN

C

2

IN

OUT

100µF

×4

100µF

×3

9

11

12

20

21

30

31

25

10

22

23

28

29

24

C1

1000pF

X7R

R1

1.78k

R

PG

SS

2.2M 100k

V

FB

C

R

SVIN

100Ω

LTC3418

1µF

35

5

16

38

37

36

34

33

32

19

18

17

C

X7R

SS

V

TRACK

V

REF

1000pF

X7R

C

REF

PGOOD

RUN/SS

PGND

2.2µF

7

X7R

PGND

26

I

TH

R

69.8k

OSC

6

27

8

R2

2k

R

ITH

3.32k

R

C

T

ITH

2200pF

X7R

SYNC/MODE

SGND

C1

47pF

X7R

13

14

15

PGND

C

, C : TDK C3225X5R0J107M

IN OUT

3418 TA05

L1: VISHAY DALE IHLP-2525CZ-01

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Q SD

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95% Efficiency, V : 2.5V to 5.5V, V

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Q SD

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Sink/source), 2MHz, Monolithic Synchronous

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4A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V : 2.25V to 5.5V, V

IN OUT(MIN)

OUT

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Q SD

3418f

LT/TP 0205 1K • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3418
厂家：	Linear
描述：	8A, 4MHz, Monolithic Synchronous Step-Down Regulator 8A ，为4MHz ，单片同步降压型稳压器稳压器
文件：	总20页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3418 [Linear]

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