LTC3541EDD-1#TRPBF [Linear]
LTC3541-1 - High Efficiency Buck + VLDO Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3541EDD-1#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3541-1 - High Efficiency Buck + VLDO Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总22页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3541-1
High Efficiency
Buck + VLDO Regulator
FEATURES
DESCRIPTION
The LTC®3541-1 combines a synchronous buck DC/
DC converter with a very low dropout linear regulator
(VLDO) to provide up to two output voltages from a single
input voltage with minimal external components. When
configuredfordualoutputoperation,theLTC3541-1’sauto
start-upfeaturewillbringtheVLDO/linearregulatoroutput
intoregulationinacontrolledmannerpriortoenablingthe
Buck regulator output without the need for external pin
control. Buck output prior to VLDO/linear regulator output
sequencing may also be obtained via external pin control.
The input voltage range is ideally suited for Li-Ion battery-
powered applications, as well as powering sub-3.3V logic
from 5V or 3.3V rails.
High Efficiency, 500mA Buck Plus 300mA VLDO™
n
Regulator
n
Auto Start-Up Powers VLDO/Linear Regulator
Output Prior to Buck Regulator Output
n
Independent High Efficiency, 500mA Buck
(V : 2.7V to 5.5V)
IN
n
n
n
n
n
n
n
n
n
300mA VLDO Regulator with 30mA Standalone Mode
No External Schottky Diodes Required
Buck Output Voltage Range: 0.8V to 5V
VLDO Input Voltage Range (LV ): 0.9V to 5.5V
IN
VLDO Output Voltage Range VLDO: 0.4V to 4.1V
Selectable Fixed Frequency, Pulse-Skip Operation or
Burst Mode® Operation
Short-Circuit Protected
Thesynchronousbuckconverterprovidesahighefficiency
output, typically 90%, capable of providing up to 500mA
of continuous output current while switching at 2.25MHz,
allowing the use of small surface mount inductors and ca-
pacitors. A mode-select pin allows Burst Mode operation
to be enabled for higher efficiency at light load currents, or
disabledforlowernoise,constantfrequencyoperation.
Current Mode Operation for Excellent Line and Load
Transient Response
Constant Frequency Operation: 2.25MHz
Low Dropout Buck Operation: 100% Duty Cycle
Small, Thermally Enhanced, 10-Lead (3mm × 3mm)
DFN Package
n
n
n
APPLICATIONS
The VLDO regulator provides a low noise, low voltage
output capable of providing up to 300mA of continuous
output current using only a 2.2μF ceramic capacitor. The
n
PDAs/Palmtop PCs
n
Digital Cameras
input supply voltage of the VLDO regulator (LV ) may
n
IN
Cellular Phones
come from the buck regulator or a separate supply.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and VLDO is a
trademark of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.
n
PC Cards
Wireless and DSL Modems
n
n
Other Portable Power Systems
Buck (Burst) Efficiency and Power Loss vs Load Current
TYPICAL APPLICATION
100
90
1
LTC3541-1 Typical Application
EFFICIENCY
V
IN
80
2.9V TO 5.5V
10µF
0.1
V
70
IN
ENBUCK
ENVLDO
60
50
2.2µH
MODE
POWER LOSS
SW
0.01
0.001
0.0001
V
V
OUT2
OUT1
2.5V
LV
LV
OUT
1.5V
IN
40
30
20
10
0
200mA
300mA
LTC3541-1
22pF
412k
243k
BUCKFB
LFB
GND
2.2µF
10µF
115k
150k
V
V
= 3.3V
PGND
IN
OUT
= 2.5V
35411 TA01a
1
10
100
1000
35411 TA01b
LOAD CURRENT (mA)
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For more information www.linear.com/LTC3541-1
LTC3541-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages:
V , LV .................................................. –0.3V to 6V
IN
IN
V
1
2
3
4
5
10 SW
IN
LV – V ..........................................................<0.3V
ENBUCK
BUCKFB
LFB
9
8
7
6
ENVLDO
IN
IN
11
MODE
GND
Pin Voltages:
ENVLDO, ENBUCK, MODE, SW,
LFB, BUCKFB ............................ –0.3V to (V + 0.3V)
LV
OUT
LV
IN
IN
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
Linear Regulator I
Operating Ambient Temperature Range
(Note 2)....................................................–40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range .................. –65°C to 125°C
(100ms) (Note 9) ......100mA
OUT(MAX)
T
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
JMAX
http://www.linear.com/product/LTC3541-1#orderinfo
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 85°C
LTC3541EDD-1#PBF
LTC3541EDD-1#TRPBF
LCWQ
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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For more information www.linear.com/LTC3541-1
LTC3541-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
I
Peak Inductor Current
V
V
V
= 4.2V (Note 8)
0.8
0.95
1.25
A
PK
IN
l
l
l
l
BUCKFB Pin Input Current
LFB Pin Input Current
Input Voltage Range
= 0.9V
50
nA
nA
BUCKFB
LFB
BUCKFB
= 0.45V
–200
2.7
–40
LFB
V
V
(Note 4)
5.5
0.4
V
IN
Buck V Line Regulation
V
IN
= 2.7V to 5.5V, ENBUCK = V ,
0.04
0.6
0.6
0.3
%/V
IN(LINEREG)
IN
IN
ENVLDO = 0V, MODE = V (Note 6)
IN
VLDO V Line Regulation
V
IN
= 2.7V to 5.5V, LV
IN OUT(VLDO)
= 2.7V to 5.5V, LV
= 1.2V, ENBUCK = V ,
= 100mA, LV = 1.5V
= 1.2V, ENBUCK = 0V,
= 10mA
mV/V
mV/V
mV/V
IN
OUT
IN
(Referred to LFB)
ENVLDO = V , I
IN
Linear Regulator V Line
V
IN
IN
OUT
ENVLDO = V , I
IN OUT(LREG)
Regulation (Referred to LFB)
LV
LV Line Regulation
LV = 0.9V to 5.5V, V = 5.5V, LV
= 0.4V,
IN(LINEREG)
IN
IN
IN
OUT
(Referred to LFB)
ENBUCK = V , ENVLDO = V , MODE = V ,
IN
IN
IN
I
= 100mA
OUT(VLDO)
VLDO
LV – LV
Dropout Voltage
LV = 1.5V, ENBUCK = V , ENVLDO = V ,
28
60
mV
DO
IN
OUT
IN
IN
IN
(Note 9)
MODE = V , I
= 50mA, V = 0.3V
IN OUT(VLDO) LFB
V
Buck Output Load Regulation
ENBUCK = V , ENVLDO = 0V, MODE = V (Note 6)
0.5
%
%
LOADREG
IN
IN
l
l
VLDO Output Load Regulation
I
= 1mA – 300mA, LV = 1.5V, LV
OUT
=
IN
0.25
0.5
0.5
OUT(VLDO)
IN
1.2V, ENBUCK = V , ENVLDO = V , MODE = V
IN
IN
Linear Regulator Output Load
I
= 1mA – 30mA, LV
= 1.2V,
0.25
%
OUT(LREG)
OUT
ENBUCK = 0V, ENVLDO = V
IN
V
V
Reference Regulation Voltage
(Note 6)
ENBUCK = V , ENVLDO = 0V, T = 25°C
0.784
0.782
0.78
0.8
0.8
0.8
0.4
0.4
0.4
85
0.816
0.818
0.82
V
V
BUCKFB
IN
A
ENBUCK = V , ENVLDO = 0V, 0°C ≤ T ≤ 85°C
IN
A
l
l
ENBUCK = V , ENVLDO = 0V, –40°C ≤ T ≤ 85°C
V
IN
A
Reference Regulation Voltage
(Note 7)
ENBUCK = 0V, ENVLDO = V , T = 25°C
0.392
0.391
0.390
0.408
0.409
0.410
V
LFB
IN
A
ENBUCK = 0V, ENVLDO = V , 0°C ≤ T ≤ 85°C
V
IN
A
ENBUCK = 0V, ENVLDO = V , –40°C ≤ T ≤ 85°C
V
IN
A
I
S
Buck + VLDO
LV = 1.5V, LV
= 1.2V, ENBUCK = V ,
μA
IN
OUT
IN
Burst Mode Sleep
ENVLDO = V , MODE = 0V, I
= 10μA,
IN
OUT(VLDO)
V
IN
Quiescent Current
V
= 0.9V
BUCKFB
Buck + VLDO
LV = 1.5V, LV
= 1.2V, ENBUCK = V ,
315
300
55
µA
µA
µA
µA
µA
µA
IN
OUT
IN
Burst Mode Active
ENVLDO = V , MODE = 0V, I
= 10µA,
IN
OUT(VLDO)
V
IN
Quiescent Current
V
= 0.7V
BUCKFB
Buck + VLDO
LV = 1.5V, LV
= 1.2V, ENBUCK = V ,
OUT IN
IN
Pulse-Skip Mode Active
ENVLDO = V , MODE = V , I
= 10µA,
IN
IN OUT(VLDO)
V
IN
Quiescent Current
V
V
= 0.7V
BUCKFB
Buck
= 0.9V, I
ENVLDO = 0V, MODE = 0V
= 0A, ENBUCK = V ,
OUT(BUCK) IN
BUCKFB
Burst Mode Sleep
V
IN
Quiescent Current
Buck
V
= 0.7V, I
= 0A, ENBUCK = V ,
300
285
50
BUCKFB
OUT(BUCK)
IN
Burst Mode Active
ENVLDO = 0V, MODE = 0V
= 0.7V, I = 0A, ENBUCK = V ,
OUT(BUCK) IN
V
IN
Quiescent Current
Buck
V
BUCKFB
Pulse-Skip Mode Active
ENVLDO = 0V, MODE = V
IN
V
IN
Quiescent Current
Linear Regulator V Quiescent
Current
LV
= 1.2V, ENBUCK = 0V, ENVLDO = V ,
IN
OUT IN
I
= 10µA
OUT(LREG)
V
Shutdown Quiescent Current ENBUCK = 0V, ENVLDO = 0V
2.5
0.1
µA
µA
IN
LV Shutdown Quiescent Current LV = 3.6V, ENBUCK = 0V, ENVLDO = 0V
IN
IN
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For more information www.linear.com/LTC3541-1
LTC3541-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
f
Oscillator Frequency
1.8
2.25
2.7
MHz
OSC
R
R
R
R
of P-Channel MOSFET
of N-Channel MOSFET
I
I
= 100mA
= 100mA
0.25
0.35
0.01
Ω
Ω
µA
V
PFET
NFET
LSW
DS(ON)
DS(ON)
SW
SW
I
SW Leakage
Enable = 0V, V = 0V or 6V, V = 6V
1
SW
IN
l
l
l
V
V
Input Pin High Threshold
Input Pin Low Threshold
Input Pin Current
MODE, ENBUCK, ENVLDO
0.9
IH
MODE, ENBUCK, ENVLDO
0.3
1
V
IL
I
I
I
,
0.01
µA
MODE
ENBUCK
ENVLDO
,
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3541-1 is guaranteed to meet performance specifications
from 0°C to 85°C. VLDO/linear regulator output is tested and specified
Note 6: The LTC3541-1 is tested in a proprietary test mode that connects
VBUCKFB to the output of the error amplifier. For the reference regulation
and line regulation tests, the output of the error amplifier is set to the
midpoint. For the load regulation test, the output of the error amplifier is
driven to minimum and maximum of the signal range.
Note 7: Measurement made in closed loop linear regulator configuration
under pulse load conditions such that T ≈ T , and are 100% production
J
A
with LV
= 1.2V, I
= 10µA.
OUT
LOAD
tested at 25°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 8: Measurement made in a proprietary test mode with slope
compensation disabled.
Note 9: Measurement is assured by design, characterization and statistical
process control.
Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: Minimum operating LV voltage required for VLDO regulator
IN
regulation is:
LV ≥ LV
IN
+ V
and LV ≥ 0.9V
DROPOUT IN
OUT
Note 4: Minimum operating VIN voltage required for VLDO regulator and
linear regulator regulation is:
V
IN
≥ LV
+ 1.4V and V ≥ 2.7V
OUT IN
Note 5: TJ is calculated from the ambient temperature, T , and power
A
dissipation, P , according to the following formula:
D
T = T + (P • 43°C/W)
J
A
D
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For more information www.linear.com/LTC3541-1
LTC3541-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Input Voltage for
Buck (Burst)
Efficiency vs Input Voltage for
Buck (Pulse Skip)
Efficiency vs Load Current for
Buck (Burst)
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
= 1.8V
V
= 1.8V
OUT
OUT
V
= 2.7V
IN
I
= 500mA
V
= 4.2V
I
I
= 500mA
= 30mA
OUT
IN
OUT
V
= 3.6V
IN
I
= 100mA
OUT
OUT
I
= 100mA
OUT
I
= 30mA
OUT
V
= 1.8V
1
OUT
2
3
4
5
6
2
3
4
5
6
0.1
10
100
1000
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
35411 G01
35411 G02
35411 G03
Efficiency vs Load Current for
Buck (Burst)
Efficiency vs Load Current for
Buck (Pulse Skip)
Efficiency vs Load Current for
Buck (Pulse Skip)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 2.5V
V
IN
= 2.7V
V
= 1.8V
OUT
OUT
V
= 2.7V
IN
V
= 4.2V
V
= 2.7V
IN
IN
V
IN
= 3.6V
V
IN
= 3.6V
V
IN
= 3.6V
V
= 4.2V
V
= 4.2V
IN
IN
V
= 2.5V
1
OUT
0.1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
35411 G05
35411 G06
35411 G04
Buck (Burst) Plus VLDO Bias
Current vs VLDO Load Current
Output (Auto Start-Up Sequence,
Buck in Pulse Skip) vs Time
VLDO Dropout Voltage vs
Load Current
100
80
250
200
150
100
50
V
= 1.5V
OUT
V
= 3.6V
IN
V
OUT
2V/DIV
I
I
= 0
LOAD(BUCK)
BIAS VIN LVIN LOAD
V
= 3V
IN
= I + I
– I
V
= 3.6V
IN
LV
OUT
2V/DIV
60
V
= 4.2V
IN
V
IN
2V/DIV
40
35411 G09
4ms/DIV
I
I
= 400mA
LVOUT
20
0
VOUT
= 30mA
0
1
10
100
0.1
1000
0
100
150
200
250
300
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
35411 G08
35411 G07
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For more information www.linear.com/LTC3541-1
LTC3541-1
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Supply Voltage
VLDO/Linear Regulator Reference
vs Temperature
0.410
0.408
0.406
0.404
0.402
0.400
0.398
0.396
0.394
0.392
0.390
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
2.5
2.4
2.3
2.2
2.1
2.0
V
= 3.6V
V
IN
= 3.6V
V
= 3.6V
IN
IN
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–25
4
5
6
3
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
53411 G12
35411 G10
35411 G11
Buck (Burst) and VLDO Output
Buck Reference vs Temperature
RDS(ON) vs Temperature
0.820
0.816
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.784
0.780
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0
V
= 3.6V
IN
LV
OUT
10mV/DIV
AC COUPLED
V
OUT
10mV/DIV
SYNCH SWITCH
MAIN SWITCH
AC COUPLED
35411 G15
2μs/DIV
V
= 3.6V
OUT
IN
LV
V
IN
V
IN
V
IN
= 2.5V
= 3.6V
= 5.5V
= 1.5V
V
= 1.8V
= 50mA
OUT
I
LOAD
–50
0
25
50
75 100 125
–25
Burst Mode OPERATION
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
53411 G13
35411 G14
Buck (Pulse Skip) Load Step from
1mA to 500mA
Buck (Burst) Load Step from
1mA to 500mA
VLDO Load Step from
1mA to 300mA
V
V
OUT
OUT
100mV/DIV
100mV/DIV
LV
OUT
AC COUPLED
AC COUPLED
20mV/DIV
AC COUPLED
I
I
L
L
500mA/DIV
500mA/DIV
I
I
I
LOAD
LOAD
LOAD
250mA/DIV
500mA/DIV
500mA/DIV
35411 G16
35411 G18
35411 G17
40μs/DIV
= 1.8V
= 1mA TO 500mA
V
V
I
= 3.6V
400μs/DIV
= 1mA TO 300mA
V
= 3.6V
OUT
40μs/DIV
= 1.8V
= 1mA TO 500mA
V
V
I
= 3.6V
IN
OUT
IN
IN
OUT
LV
I
= 1.5V
LOAD
LOAD
LOAD
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For more information www.linear.com/LTC3541-1
LTC3541-1
TYPICAL PERFORMANCE CHARACTERISTICS
VLDO Load Step from
100mA to 300mA
Linear Regulator to VLDO
Transition, Load = 1mA
Linear Regulator to VLDO
Transition, Load = 30mA
L
VOUT
10mV/DIV
LV
LV
OUT
OUT
AC COUPLED
20mV/DIV
10mV/DIV
AC COUPLED
AC COUPLED
V
OUT
10mV/DIV
AC COUPLED
I
LOAD
50mA/DIV
I
LOAD
250mA/DIV
35411 G19
35411 G20
35411 G21
400μs/DIV
= 100mA TO 300mA
40μs/DIV
V
= 3.6V
OUT
V
= 3.6V
IN
V
LV
V
= 3.6V
2μs/DIV
IN
IN
LV
I
= 1.5V
LV
I
= 1.5V
= 1.5V
OUT
OUT
= 1.875V
= 50mA
= 1mA
LOAD
LOAD
OUT
I
LOAD
Burst Mode OPERATION
VLDO to Linear Regulator
Transition, Load = 1mA
VLDO to Linear Regulator
Transition, Load = 30mA
LV
LV
OUT
OUT
10mV/DIV
10mV/DIV
AC COUPLED
AC COUPLED
I
LOAD
50mA/DIV
I
LOAD
50mA/DIV
35411 G22
35411 G23
40μs/DIV
V
= 3.6V
40μs/DIV
V
= 3.6V
IN
IN
LV
I
= 1.5V
LV
I
= 1.5V
OUT
OUT
= 1mA
= 30mA
LOAD
LOAD
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For more information www.linear.com/LTC3541-1
LTC3541-1
PIN FUNCTIONS
V
(Pin 1): Main Supply Pin. This pin must be closely
MODE (Pin 8): Buck Mode Selection Pin. This pin enables
buck Pulse-Skip operation when driven to a logic high
and enables buck Burst Mode operation when driven to
a logic low.
IN
decoupled to GND with a 10µF or greater capacitor.
ENBUCK (Pin 2): Buck Enable Pin. This pin enables the
buck regulator when driven to a logic high.
ENVLDO(Pin9):VLDO/LinearRegulatorEnablePin.When
driven to a logic high, this pin enables the linear regulator
when the ENBUCK pin is driven to a logic low, and enables
the VLDO when the ENBUCK pin is driven to a logic high.
BUCKFB (Pin 3): Buck Regulator Feedback Pin. This pin
receives the buck regulator’s feedback voltage from an
external resistive divider.
LFB (Pin 4): VLDO/Linear Regulator Feedback Pin. This
pin receives either the VLDO or linear regulator’s feedback
voltage from an external resistive divider.
SW (Pin 10): Switch Node Pin. This pin connects the
internal main and synchronous power MOSFET switches
to the external inductor for the buck regulator.
LV
(Pin 5): VLDO/Linear Regulator Output Pin. This
OUT
Exposed Pad (Pin 11): Ground Pin. This pin must be
soldered to the PCB to provide both electrical contact to
ground and good thermal contact to the PCB.
pin provides the regulated output voltage from the VLDO
or linear regulator.
LV (Pin 6): VLDO/Linear Regulator Input Supply Pin.
IN
Note: Table 1 details the truth table for the control pins
of the LTC3541-1.
This pin provides the input supply voltage for the VLDO
power FET.
GND (Pin 7): Analog Ground Pin.
Table 1. LTC3541-1 Control Pin Truth Table
PIN NAME
ENBUCK ENVLDO MODE OPERATIONAL DESCRIPTION
0
0
0
1
X
X
LTC3541-1 Powered Down
Buck Powered Down, VLDO Regulator
Powered Down, Linear Regulator
Enabled
1
1
1
1
0
0
1
1
0
1
0
1
Buck Enabled, VLDO Regulator Powered
Down, Linear Regulator Powered Down,
Burst Mode Operation
Buck Enabled, VLDO Regulator Powered
Down, Linear Regulator Powered Down,
Pulse-Skip Mode Operation
Buck Enabled, VLDO Regulator Enabled,
Linear Regulator Powered Down, Burst
Mode Operation
Buck Enabled, VLDO Regulator Enabled,
Linear Regulator Powered Down, Pulse-
Skip Mode Operation
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LTC3541-1
BLOCK DIAGRAM
2.2µH
I
= 500mA
OUT(BUCK)
V
LV
+ 1.4V
OUT
IN(MIN)
10µF
10
SW
V
IN
10µF
1
500mA BUCK
SW
V
IN
22pF
REF
FB
GND
BUCKFB
3
6
PGND
LV
IN
VLDO/LINEAR REG
V
IN
LV
IN
REF
REF
LV
< V – 1.4V
IN
ENBUCK
ENVLDO
MODE
OUT(MAX)
+
2
9
8
I
I
= 300mA (VLDO REG)
= 30mA (LINEAR REG)
OUT
OUT
CONTROL
LOGIC
LFB
LV
–
OUT
5
4
CNTRL
GND
2.2µF
LFB
GND
7
PGND
11
35411 F01
Figure 1. LTC3541-1 Functional Block Diagram
OPERATION
The LTC3541-1 contains a high efficiency synchronous
buck converter, a very low dropout regulator (VLDO) and
a linear regulator. It can be used to provide up to two
output voltages from a single input voltage making the
LTC3541-1idealforapplicationswithlimitedboardspace.
The combination and configuration of these major blocks
within the LTC3541-1 is determined by way of the control
pins ENBUCK and ENVLDO as defined in Table 1.
into consideration when using the buck regulator to pro-
vide the power for both the VLDO and for external loads.
With the ENBUCK pin driven to a logic low and ENVLDO
driven to a logic high, the LTC3541-1 enables the linear
regulator, providing a low noise regulated output voltage
at the LV
pin while drawing minimal quiescent current
OUT
from the V input pin. This feature allows output voltage
IN
LV
to be brought into regulation without the presence
of the LV voltage.
OUT
With the ENBUCK pin driven to a logic high and ENVLDO
driven to a logic low, the LTC3541-1 enables the buck
converter to efficiently reduce the voltage provided at
IN
With the ENBUCK and ENVLDO pins both driven to a
logic high, the LTC3541-1 enables the high efficiency
buck converter and VLDO regulator, providing dual output
operation from a single input voltage. When configured in
this manner, the LTC3541-1’s auto start-up sequencing
feature will bring the VLDO/linear regulator output into
regulation in a controlled manner prior to enabling the
the V input pin to an output voltage which is set by an
IN
external feedback resistor network. The buck regulator
can be configured for Pulse-Skip or Burst Mode opera-
tion by driving the MODE pin to a logic high or logic low
respectively. The buck regulator is capable of providing a
maximum output current of 500mA, which must be taken
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LTC3541-1
OPERATION
buck regulator without the need for external pin control.
A detailed discussion of the transitions between the VLDO
and linear regulator can be found in the VLDO/Linear
Regulator Loop section.
WhentheMODEpinisdriventoalogichightheLTC3541-1
operatesinPulse-Skipmodeforlowoutputvoltageripple.
In this mode, the LTC3541-1 continues to switch at a
constant frequency down to very low currents, where it
will begin skipping pulses used to control the main (top)
switch to maintain the proper average inductor current.
Buck Regulator Control Loop
The LTC3541-1 internal buck regulator uses a constant
frequency,currentmode,step-downarchitecture.Boththe
main(top,P-channelMOSFET)andsynchronous(bottom,
N-channel MOSFET) switches are internal. During normal
operation, the internal main switch is turned on at the be-
ginning of each clock cycle provided the internal feedback
voltage to the buck is less than the reference voltage. The
current into the inductor provided to the load increases
until the current limit is reached. Once the current limit is
reached the main switch turns off and the energy stored
in the inductor flows through the bottom synchronous
switch into the load until the next clock cycle.
If the input supply voltage is decreased to a value ap-
proaching the output voltage, the duty cycle of the buck
is increased toward maximum on-time and 100% duty
cycle. The output voltage will then be determined by the
input voltage minus the voltage drop across the main
switch and the inductor.
VLDO/Linear Regulator Loop
In the LTC3541-1, the VLDO and linear regulator loops
consist of an amplifier and N-channel MOSFET output
stages that, when connected with the proper external
components, will servo the output to maintain a regula-
The peak inductor current is determined by comparing the
buck feedback signal to an internal 0.8V reference. When
the load current increases, the output of the buck and
hence the buck feedback signal decrease. This decrease
causesthepeakinductorcurrenttoincreaseuntiltheaver-
age inductor current matches the load current. While the
main switch is off, the synchronous switch is turned on
until either the inductor current starts to reverse direction
or the beginning of a new clock cycle.
tor output voltage, LV . The internal reference voltage
OUT
provided to the amplifier is 0.4V allowing for a wide range
ofoutputvoltages.LoopconfigurationsenablingtheVLDO
orthelinearregulatorarestablewithanoutputcapacitance
as low as 2.2μF and as high as 100μF. Both the VLDO
and the linear regulators are capable of operating with an
input voltage, V , as low as 2.7V, but are subject to the
IN
constraint that V must be greater than LV
+ 1.4V.
IN
OUT
The VLDO is designed to provide up to 300mA of output
current at a very low LV to LV voltage. This allows
WhentheMODEpinisdriventoalogiclow, theLTC3541-1
buck regulator operates in Burst Mode operation for high
efficiency. In this mode, the main switch operates based
upon load demand. In Burst Mode operation the peak
inductor current is set to a fixed value, where each burst
eventcanlastfromafewclockcyclesatlightloadstonearly
continuouscyclingatmoderateloads.Betweenburstevents
the main switch and any unneeded circuitry are turned off,
reducing the quiescent current. In this sleep state, the load
is being supplied solely from the output capacitor. As the
output voltage droops, an internal error amplifier’s output
rises until a wake threshold is reached causing the main
switch to again turn on. This process repeats at a rate that
is dependent upon the load current demand.
IN
OUT
a clean, secondary, analog supply voltage to be provided
with a minimum drop in efficiency. The VLDO is provided
with thermal protection that is designed to disable the
VLDOfunctionwhentheoutput, passtransistor’sjunction
temperature reaches approximately 160°C. In addition to
thermal protection, short-circuit detection is provided to
disable the VLDO function when a short-circuit condition
is sensed. This circuit is designed such that an output
current of approximately 1A can be provided before this
circuit will trigger. As detailed in the Electrical Character-
istics, the VLDO regulator will be out of regulation when
thiseventoccurs. Boththethermalandshort-circuitfaults
when detected are treated as catastrophic fault condi-
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LTC3541-1
OPERATION
tions. The LTC3541-1 will be reset upon the detection of
either event. The N-channel MOSFET incorporated in the
Transitioning from linear regulator mode to VLDO mode,
accomplished by bringing ENBUCK from a logic low to a
logic high while ENVLDO is a logic high, is designed to be
as seamless and transient free as possible. The precise
VLDO has its drain connected to the LV pin as shown
IN
in Figure 1. To ensure reliable operation, the LV voltage
IN
must be stable before the VLDO is enabled. For the case
transient response of LV
due to this transition is a
OUT
where the voltage on the LV pin is supplied by the buck
function of C
and the load current. Waveforms given
IN
OUT
regulator, the internal power supply sequencing logic as-
sures voltages are applied in the appropriate manner. For
the case where an external supply is used to power the
in the Typical Performance Characteristics show typical
transientresponsesusingtheminimumC of2.2μFand
loadcurrentsof1mAand30mArespectively.Generally,the
amplitude of any transients present will decrease as C
OUT
is increased. To ensure reliable operation and adherence
to the load regulation limits presented in the Electrical
Characteristics table, the load current must not exceed
OUT
LV pin, the voltage on the LV pin must be stable before
IN
IN
the ENVLDO pin is brought from a low to a high. Further,
the external LV voltage must be reduced in conjunction
IN
with V whenever V is pulled low or removed.
IN
IN
the linear regulator I
limit of 30mA within 20ms after
OUT
The linear regulator is designed to provide a lower output
current (30mA) than that available from the VLDO. The
linear regulator’s output pass transistor has its drain tied
ENBUCK has transitioned to a logic high. The 300mA I
OUT
limitofVLDOappliesthereafter. Further, forconfigurations
that do not use the LTC3541-1’s buck regulator to provide
to the V rail. This allows the linear regulator to be turned
IN
the VLDO input voltage (LV ), the user must ensure a
IN
on prior to, and independent of, the buck regulator which
would ordinarily drive the VLDO in a typical application.
Thelinearregulatorisprovidedwiththermalprotectionthat
is designed to disable the linear regulator function when
the output pass transistor’s junction temperature reaches
approximately 160°C. In addition to thermal protection,
short-circuit detection is provided to disable the linear
regulatorfunctionwhenashort-circuitconditionissensed.
This circuit is designed such that an output current of
approximately 120mA can be provided before this circuit
will trigger. As detailed in the Electrical Characteristics, the
linear regulator will be out of regulation when this event
occurs.Boththethermalandshort-circuitfaultsaretreated
as catastrophic fault conditions. The LTC3541-1 will be
reset upon the detection of either event.
stable LV voltage is present no less than 1ms prior to
IN
ENBUCK transitioning to a logic high.
In a similar manner, transitioning from VLDO mode to
linearregulatormode, accomplishedbybringingENBUCK
from a logic high to a logic low while ENVLDO is a logic
high, is designed to be as seamless and transient free as
possible. Again, the precise transient response of LV
OUT
and the load
due to this transition is a function of C
OUT
current. Waveforms given in the Typical Performance
Characteristics show typical transient responses using
the minimum C
of 2.2μF and load currents of 1mA
OUT
and 30mA respectively. Generally, the amplitude of any
transients present will decrease as C is increased. To
OUT
ensurereliableoperationandadherencetotheloadregula-
tion limits presented in the Electrical Characteristics table,
TheN-channelMOSFETincorporatedinthelinearregulator
the load current must not exceed the linear regulator I
OUT
hasitsdrainconnectedtotheV pinasshowninFigure 1.
IN
limitof30mA1mspriortoENBUCKtransitioningtoalogic
low and thereafter. Further, for configurations that do not
use the LTC3541-1’s buck regulator to provide the VLDO
The size of this MOSFET and its associated power bus-
sing is designed to accommodate 30mA of DC current.
Currents above this can be supported for short periods
as stipulated in the Absolute Maximum Ratings section.
input voltage (LV ), the user must continue to ensure a
IN
stable LV voltage no less than 1ms after ENBUCK has
IN
transitioned to a logic low.
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LTC3541-1
APPLICATIONS INFORMATION
The basic LTC3541-1 application circuit is shown on the
first page of this data sheet. External component selection
isdrivenbytheloadrequirementandrequirestheselection
Table 2. Representative Surface Mount Inductors
PART
NUMBER
VALUE
(µH)
DCR
MAX DC
SIZE
3
(Ω MAX) CURRENT (A) W × L × H (mm )
Sumida
CDRH3D23
1.0
1.5
2.2
3.3
0.025
0.029
0.038
0.048
2.0
1.5
1.3
1.1
3.9 × 3.9 × 2.4
of L, followed by C , C , and feedback resistor values
IN OUT
for the buck and the selection of the output capacitor and
feedback values for the VLDO and linear regulator.
Sumida
2.2
3.3
0.116
0.174
0.950
0.770
3.5 × 4.3 × 0.8
2.5 × 3.2 × 2.0
CMD4D06
BUCK REGULATOR
Inductor Selection
Coilcraft
ME3220
1.0
1.5
2.2
3.3
0.058
0.068
0.104
0.138
2.7
2.2
1.0
1.3
For most applications, the appropriate inductor value will
be in the range of 1.5μH to 3.3μH with 2.2μH the most
commonly used. The exact inductor value is chosen
largely based on the desired ripple current and burst
ripple performance. Generally, large value inductors re-
duce ripple current, and conversely, small value inductors
Murata
LQH3C
1.0
2.2
0.060
0.097
1.00
0.79
2.5 × 3.2 × 2.0
3.2 × 3.2 × 1.2
Sumida
CDRH2D11/HP
1.5
2.2
0.06
0.10
1.00
0.72
C and C
IN
Selection
OUT
produce higher ripple current. Higher V or V
may
IN
OUT
also increase the ripple current as shown in Equation 1.
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle V /V . To prevent large
voltage transients, a low ESR input capacitor sized for the
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
A reasonable starting point for setting ripple current is
OUT IN
ΔI = 200mA (40% of 500mA).
L
VOUT
1
ΔIL =
V
1−
(1)
OUT
f L
( )( )
VIN
1/2
VOUT V − V
(
)
IN
OUT
CIN required IRMS ≅IOMAX
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 600mA rated
inductor should be enough for most applications (500mA
+ 100mA). For better efficiency, choose a low DC resis-
tance inductor.
VIN
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
monly used for design. Note that the capacitor manu-
facturer’s ripple current ratings are often based on 2000
hours of life. This makes it advisable to further derate the
capacitor or choose a capacitor rated at a higher tempera-
ture than required. Always consult the manufacturer with
any question regarding proper capacitor choice.
Inductor Core Selection
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar elec-
trical characteristics. The choice of which style inductor
to use often depends more on the price vs size require-
ment and any radiated field/EMI requirements rather than
what the LTC3541-1 requires to operate. Table 2 shows
some typical surface mount inductors that work well in
LTC3541-1 applications.
The selection of C
the desired buck loop transient response, required effec-
tive series resistance (ESR) and burst ripple performance.
for the buck regulator is driven by
OUT
TheLTC3541-1minimizestherequirednumberofexternal
components by providing internal loop compensation
for the buck regulator loop. Loop stability, transient re-
sponse and burst performance can be tailored by choice
of output capacitance. For many applications, desirable
stability, transient response and ripple performance can
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LTC3541-1
APPLICATIONS INFORMATION
be obtained by choosing an output capacitor value of
10μF to 22μF. Typically, once the ESR requirement for
COUT has been met, the RMS current rating generally far
exceeds the IRIPPLE(P-P) requirement. The output ripple
ΔVOUT is determined by:
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
Output Voltage Programming
1
ΔVOUT ≅ ΔI ESR+
L
The output voltage is set by tying BUCKFB to a resistive
divider according to the following formula:
8fCOUT
where f = operating frequency, C
= output capacitance
OUT
R2
R1
and ΔI = ripple current in the inductor. For a fixed output
L
V
OUT =0.8V 1+
voltage, the output ripple is highest at maximum input
voltage since ΔI increases with input voltage.
L
SincetheimpedanceattheBUCKFBpinisdependentupon
the resistor divider network used, and phase shift due to
this impedance directly impacts the transient response of
the buck, R1 should be chosen <125k. In addition, stray
capacitance at this pin should be minimized (<5pF) to
prevent excessive phase shift. Finally, special attention
should be given to any stray capacitances that can couple
external signals onto the BUCKFB pin producing undesir-
able output ripple. For optimum performance connect
the BUCKFB pin to R1 and R2 with a short PCB trace and
minimize all other stray capacitance to the BUCKFB pin.
Aluminumelectrolyticanddrytantalumcapacitorsareboth
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Using Ceramic Input and Output Capacitors
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 6.
Highvalue,lowcostceramiccapacitorsarenowbecoming
available in smaller case sizes. Their high ripple current,
high voltage rating, and low ESR make them ideal for
switching regulator applications. Since the LTC3541-1’s
controlloopdoesnotdependontheoutputcapacitor’sESR
forstableoperation, ceramiccapacitorscanbeusedfreely
to achieve very low output ripple and small circuit size.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
immediately shifts by an amount
OUT
However, care must be taken when ceramic capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
equal to (ΔI
• ESR), where ESR is the effective series
LOAD
0.8V V
5V
OUT
R2
induce ringing at the input, V . At best, this ringing can
BUCKFB
LTC3541-1
GND
IN
couple to the output and be mistaken as loop instability. At
R1
worst, a sudden inrush of current through the long wires
35411 F06
can potentially cause a voltage spike at V , large enough
IN
to damage the part.
Figure 6. Setting the LTC3541-1 Output Voltage
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LTC3541-1
APPLICATIONS INFORMATION
resistance of C . ΔI
also begins to charge or dis-
R2
R1
OUT
LOAD
LV
V
= 0.4V 1 +
OUT
LTC3541-1
LFB
OUT
(
)
chargeC , whichgeneratesafeedbackerrorsignal. The
R2
R1
OUT
regulator loop then acts to return V
value. During this recovery time V
to its steady-state
can be monitored
C
OUT
OUT
OUT
GND
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory see Application Note 76.
35411 F07
Figure 7. Programming the LTC3541-1
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
for the linear regulator. To calculate the change referred
to the output simply multiply by the gain of the feedback
network (i.e., 1 + R2/R1). For example, to program the
output for 1.2V choose R2/R1 = 2. In this example, an
outputcurrentchangeof1mAto300mAproduces1.05mV
• (1 + 2) = 3.15mV drop at the output.
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 • C
). Thus, a 10μF capacitor charging to 3.3V
LOAD
Since the LFB pin is relatively high impedance (depend-
ing on the resistor divider used), stray capacitance at this
pin should be minimized (<10pF) to prevent phase shift
in the error amplifier loop. Additionally, special attention
should be given to any stray capacitances that can couple
external signals onto the LFB pin producing undesirable
output ripple. For optimum performance connect the LFB
pin to R1 and R2 with a short PCB trace and minimize all
other stray capacitance to the LFB pin.
would require a 250μs rise time, limiting the charging
current to about 130mA.
VLDO/LINEAR REGULATOR
Adjustable Output Voltage
The LTC3541-1 LV
output voltage is set by the ratio of
OUT
two external resistors as shown in Figure 7. The device
servosLV tomaintaintheLFBpinvoltageat0.4V(refer-
OUT
Output Capacitance and Transient Response
enced to ground). Thus, the current in R1 is equal to 0.4V/
R1. For good transient response, stability, and accuracy,
the current in R1 should be at least 2μA, thus the value of
R1 should be no greater than 200k. The current in R2 is
the current in R1 plus the LFB pin bias current. Since the
LFB pin bias current is typically <10nA, it can be ignored
in the output voltage calculation. The output voltage can
be calculated using the formula in Figure 8. Note that in
shutdown the output is turned off and the divider current
The LTC3541-1 is designed to be stable with a wide
range of ceramic output capacitors. The ESR of the out-
put capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 2.2μF with an
ESR of 0.05Ω or less is recommended to ensure stability.
The LTC3541-1 VLDO is a micropower device and output
transientresponsewillbeafunctionofoutputcapacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes. Note that bypass capacitors
used to decouple individual components powered by the
LTC3541-1 will increase the effective output capacitor
value. High ESR tantalum and electrolytic capacitors may
beused, butalowESRceramiccapacitormustbeinparal-
lel at the output. There is no minimum ESR or maximum
capacitor size requirement.
will be zero once C
is discharged.
OUT
The LTC3541-1 VLDO and linear regulator loops operate
at a relatively high gain of –3.5μV/mA and –3.4μV/mA
respectively, referred to the LFB input. Thus, a load cur-
rent change of 1mA to 300mA produces a 1.05mV drop
at the LFB input for the VLDO and a load current change
of 1mA to 30mA produces a 0.1mV drop at the LFB input
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LTC3541-1
APPLICATIONS INFORMATION
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U
and Y5V dielectrics are good for providing high capaci-
tances in a small package, but exhibit large voltage and
temperature coefficients as shown in Figures 8 and 9.
When used with a 2V regulator, a 1μF Y5V capacitor can
lose as much as 75% of its initial capacitance over the
operatingtemperaturerange.TheX5RandX7Rdielectrics
result in more stable characteristics and are usually more
suitable for use as the output capacitor. The X7R type has
better stability across temperature, while the X5R is less
expensive and is available in higher values. In all cases,
the output capacitance should never drop below 1µF or
instability or degraded performance may occur.
EFFICIENCY CONSIDERATIONS
Generally, the efficiency of a regulator is equal to the out-
put power divided by the input power times 100%. It is
often useful to analyze individual loss terms to determine
which terms are limiting efficiency and what if any change
would yield the greatest improvement. Efficiency can be
expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual loss terms as a per-
centage of input power.
20
BOTH CAPACITORS ARE 1μF,
10V, 0603 CASE SIZE
0
Although all dissipative elements in the circuit produce
losses,threemainsourcestypicallyaccountforthemajority
X5R
–20
–40
of the losses in the LTC3541-1 circuits: V quiescent cur-
IN
2
rent,I RlossesandlossacrossVLDOoutputdevice.When
Y5V
operating with both the buck and VLDO active (ENBUCK
–60
–80
and ENVLDO equal to logic high), V quiescent current
IN
loss and loss across the VLDO output device dominate
2
the efficiency loss at low load currents, whereas the I R
–100
loss and loss across the VLDO output device dominate
the efficiency loss at medium to high load currents. At
low load currents with the part operating with the linear
regulator (ENBUCK equal to logic low, ENVLDO equal to
logic high), efficiency is typically dominated by the loss
0
8
2
4
6
10
DC BIAS VOLTAGE (V)
35411 F08
Figure 8. Change in Capacitor vs Bias Voltage
acrossthelinearregulatoroutputdeviceandV quiescent
IN
20
current. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of little consequence.
0
X5R
–20
Y5V
1. The V quiescent current loss in the buck is due
IN
–40
–60
to two components: the DC bias current as given in
the Electrical Characteristics and the internal main
switch and synchronous switch gate charge currents.
The gate charge current results from switching the
gate capacitance of the internal power switches.
Each time the gate is switched from high to low to
–80
BOTH CAPACITORS ARE 1μF,
10V, 0603 CASE SIZE
–100
–50
0
25
50
75
–25
TEMPERATURE (°C)
high again, a packet of charge, d , moves from V
q
IN
35411 F09
to ground. The resulting d /d is the current out of
q
t
Figure 9. Change in Capacitor vs Temperature
V
that is typically larger than the DC bias current
IN
35411fb
15
For more information www.linear.com/LTC3541-1
LTC3541-1
APPLICATIONS INFORMATION
and proportional to frequency. Both the DC bias
For surface mount devices, heat sinking is accomplished
by using the heat-spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat gener-
ated by power devices.
and gate charge losses are proportional to V and
IN
thus their effects will be more pronounced at higher
supply voltages.
2
2. I R losses are calculated from the resistances of the
internal switches, R , and external inductor R . In con-
To avoid the LTC3541-1 exceeding the maximum junction
temperature, some thermal analysis is required. The goal
of the thermal analysis is to determine whether the power
dissipated exceeds the maximum junction temperature of
the part. The temperature rise is given by:
SW
L
tinuousmode, theaverageoutputcurrentflowingthrough
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
and the duty cycle (DC) as follows:
DS(ON)
T = P • θ
JA
R
D
R
SW
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
where P is the power dissipated by the regulator and θ
D
JA
The R
for both the top and bottom MOSFETs can
is the thermal resistance from the junction of the die to
DS(ON)
be obtained from the Typical Performance Characteristics
the ambient temperature.
2
curves. Thus, to obtain I R losses, simply add R to
SW
The junction temperature, T , is given by:
J
R and multiply the result by the square of the average
L
T = T + T
R
output current.
J
A
where T is the ambient temperature.
3.LossesintheVLDO/linearregulatorareduetotheDCbias
currentsasgivenintheElectricalCharacteristicsandtothe
A
As an example, consider the LTC3541-1 with an input
(V –V )voltagedropacrosstheinternaloutputdevice
IN
OUT
voltage V of 2.9V, an LV voltage of 1.8V, an LV
IN
IN
OUT
transistor.
voltage of 1.5V, a load current of 200mA for the buck,
a load current of 300mA for the VLDO and an ambient
temperature of 85°C. From the typical performance graph
Other losses when the buck and VLDO are in operation
(ENBUCK and ENVLDO equal logic high), including C
IN
of switch resistance, the R
of the P-channel switch
and C
ESR dissipative losses and inductor core losses,
DS(ON)
OUT
at 85°C is approximately 0.25Ω. The R
of the N-
generally account for less than 2% total additional loss.
DS(ON)
channel switch is approximately 0.4Ω. Therefore, power
dissipated by the part is approximately:
THERMAL CONSIDERATIONS
2
P =(I
) •R +(I
)•
D
LOADBUCK
SW
LOADVLDO
The LTC3541-1 requires the package backplane metal
(GND pin) to be well soldered to the PC board. This gives
the DFN package exceptional thermal properties. The
power handling capability of the device will be limited
by the maximum rated junction temperature of 125°C.
The LTC3541-1 has internal thermal limiting designed to
protectthedeviceduringmomentaryoverloadconditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
(LV –LV )=167mW
IN
OUT
For the 3mm × 3mm DFN package, the θ is 43°C/W.
JA
Thus, the junction temperature of the regulator is:
T = 85°C + (0.167)(43) = 92°C
J
which is well below the maximum junction temperature
of 125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R
.
DS(ON)
35411fb
16
For more information www.linear.com/LTC3541-1
LTC3541-1
APPLICATIONS INFORMATION
PC BOARD LAYOUT CHECKLIST
ing up to 0.3A of current. With this information we can
calculate L using Equation 2:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3541-1. Check the following in your layout:
1
VOUT
L =
V
1−
(2)
OUT
f ΔI
( )
VIN
(
)
L
1. The power traces, consisting of the GND trace, the SW
traceandtheV traceshouldbekeptshort,directandwide.
Substituting V
= 1.8V, V = 3.6V (typ), ΔI = 0.2A and
IN L
IN
OUT
f = 2.25MHz in Equation 3 gives:
2. Does the LFB pin connect directly to the feedback re-
sistors? The resistive divider R1/R2 must be connected
1.8V
2.25MHz(200mA)
1.8V
3.6V
L =
1−
=2µH
between the (+) plate of C
and ground.
(3)
OUT
3. Does the (+) plate of C connect to V as closely as
IN
IN
A 2.2μH inductor works well for this application. For best
efficiency choose a 600mA or greater inductor with less
than 0.2Ω series resistance.
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
LFB node.
C will require an RMS current rating of at least 0.25A =
IN
I
/2 at temperature . C
for the buck is chosen
LOAD(MAX)
OUT
5. Keep the (–) plates of C and C
as close as possible.
IN
OUT
as 22µF with an ESR of less than 0.2Ω. In most cases, a
ceramic capacitor will satisfy this requirement.
DESIGN EXAMPLE
For the feedback resistors of the buck, choose R1 = 80k.
R2 can then be calculated from Equation 4 to be:
As a design example, assume the LTC3541-1 is used in
a single lithium-ion battery powered cellular phone ap-
VOUT
0.8
plication. The V will be operating from a maximum of
IN
R2=
−1 R1=100k
(4)
4.2V down to about 3V. The load current requirement is
a maximum of 0.5A for the buck output but most of the
time it will be in standby mode, requiring only 2mA. Ef-
ficiency at both low and high load currents is important.
The output voltage for the buck is 1.8V. The requirement
for the output voltage of the VLDO is 1.5V while provid-
Forthe feedback resistors ofthe VLDO, choose R1 =200k.
R2 can then be calculated from Equation 5 to be:
VOUT
0.4
R2=
−1 R1=550k
C
OUT
for the VLDO is chosen as 2.2μF.
35411fb
17
For more information www.linear.com/LTC3541-1
LTC3541-1
TYPICAL APPLICATIONS
Dual Output with Minimal External Components Using Auto Start-Up Sequence,
Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents
V
IN
3.2V TO 4.2V
10µF
V
OUT
V
IN
2V/DIV
ENBUCK
ENVLDO
2.2µH
MODE
SW
LV
2V/DIV
V
OUT1
V
OUT2
OUT
LV
LV
OUT
1.8V
2.5V
400mA
IN
30mA
LTC3541-1
BUCKFB
PGND
22pF
576k
154k
LFB
GND
2.2µF
10µF
V
IN
2V/DIV
73k
165k
35411 TA02a
35411 TA02b
4ms/DIV
I
I
= 400mA
LVOUT
VOUT
= 30mA
Dual Output with Minimal External Components Using Auto Start-Up
Sequence, Buck in Pulse Skip Mode for Low Noise Operation
V
IN
3.2V TO 4.2V
10µF
V
V
IN
OUT
2V/DIV
ENBUCK
ENVLDO
MODE
2.2µH
SW
V
V
OUT2
1.8V
30mA
OUT1
2.5V
LV
OUT
2V/DIV
LV
LV
IN
OUT
400mA
LTC3541-1
BUCKFB
PGND
22pF
576k
154k
LFB
GND
2.2µF
10µF
V
IN
2V/DIV
73k
165k
35411 TA03a
3541 TA03b
4ms/DIV
I
I
= 400mA
LVOUT
VOUT
= 30mA
35411fb
18
For more information www.linear.com/LTC3541-1
LTC3541-1
TYPICAL APPLICATIONS
Dual Output Using Minimal External Components with VOUT2 Controlled by External Logic
Signal, Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents
V
IN
3.2V TO 4.2V
10µF
V
OUT
V
IN
2V/DIV
ENBUCK
ENVLDO
2.2µH
MODE
SW
LV
2V/DIV
V
OUT1
V
OUT2
OUT
LV
LV
OUT
1.8V
2.5V
200mA
IN
300mA
LTC3541-1
BUCKFB
PGND
22pF
576k
154k
LFB
GND
2.2µF
10µF
V
IN
2V/DIV
73k
165k
35411 TA04b
35411 TA04a
4ms/DIV
I
I
= 200mA
LVOUT
VOUT
= 300mA
Dual Output Using Minimal External Components with VOUT1 Controlled by External Logic
Signal, Buck in Burst Mode Operation for High Efficiency Down to Low Load Currents
V
IN
3.2V TO 4.2V
10µF
V
OUT
V
IN
2V/DIV
ENVLDO
ENBUCK
2.2µH
MODE
SW
V
OUT1
V
OUT2
LV
2V/DIV
OUT
LV
LV
OUT
1.5V
1.8V
200mA
IN
300mA
LTC3541-1
22pF
412k
143k
BUCKFB
LFB
GND
2.2µF
10µF
V
IN
2V/DIV
115k
150k
PGND
35411 TA05b
35411 TA05a
4ms/DIV
I
I
= 200mA
LVOUT
VOUT
= 30mA
35411fb
19
For more information www.linear.com/LTC3541-1
LTC3541-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3541-1#packaging for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ±0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ±0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
35411fb
20
For more information www.linear.com/LTC3541-1
LTC3541-1
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
04/16 Revised Typical Application circuit
1
9
Added 10µF capacitor to V line
IN
Revised top and bottom schematics
18, 19
35411fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3541-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®3023
Dual, 2x100mA, Low Noise Micropower LDO
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 40μA, I < 1μA,
IN
OUT(MIN)
DO
Q
SD
V
= ADJ, DFN, MS Packages, Low Noise < 20μV
, Stable with
OUT
RMS(P-P)
1μF Ceramic Capacitors
LT3024
Dual, 100mA/500mA, Low Noise Micropower LDO
300mA, Micropower VLDO Linear Regulator
V : 1.8V to 20V, V
OUT
with 1μF Ceramic Capacitors
= 1.22V, V = 0.30V, I = 60μA, I < 1μA,
OUT(MIN) DO Q SD
IN
V
= ADJ, DFN, TSSOP Packages, Low Noise < 20μV
, Stable
RMS(P-P)
LTC3025
V : 0.9V to 5.5V, V = 0.4V, 2.7V to 5.5V Bias Voltage Required,
IN
DO
OUT(MIN)
V
= 45mV, I = 50μA, I < 1μA, V
= ADJ, DFN Packages, Stable
Q
SD
OUT
with 1μF Ceramic Capacitors
LTC3407
LTC3407-2
LTC3445
Dual Synchronous 600mA Synchronous Step-Down 1.5MHz Constant Frequency Current Mode Operation, V from 2.5V to
IN
DC/DC Regulator
5.5V, V
Down to 0.6V, DFN, MS Packages
OUT
Dual Synchronous 800mA Synchronous Step-Down 2.25MHz Constant Frequency Current Mode Operation, V from 2.5V to
IN
DC/DC Regulator, 2.25MHz
5.5V, V
Down to 0.6V, DFN, MS Packages
OUT
2
2
I C Controllable Buck Regulator with Two LDOs and
600mA, 1.5MHz Current Mode Buck Regulator, I C Programmable
V from 0.85V to 1.55V, two 50mA LDOs, Backup Battery Input with
OUT
Backup Battery Input
PowerPath Control, QFN Package
LTC3446
LTC3448
LTC3541
LTC3541-2
LTC3541-3
LTC3547
Triple Output Step-Down Converter 1A Output Buck, V : 2.7V to 5.5V, V
Buck = 0.8V, V
VLDO = 0.4V
,
OUT(MIN)
IN
OUT(MIN)
OUT(MIN)
Two Each 300mA VDLOs
14-Pin DFN Package
V : 2.7V to 5.5V, V = 0.6V, Switches to LDO Mode at ≤3A,
OUT(MIN)
600mA (I ), High Efficiency, 1.5MHz/2.25MHz
OUT
IN
Synchronous Step-Down Regulator with LDO Mode
DD8, MS8/E Packages
High Efficiency Buck + VLDO Regulator
V : 2.7V to 5.5V, V
Buck = 0.8V, V
VLDO = 0.4V,
IN
OUT(MIN)
OUT(MIN)
3mm × 3mm 10-Pin DFN Package
High Efficiency Buck plus VLDO Regulator
High Efficiency Buck plus VLDO Regulator
V : 2.9V to 5.5V, V = 1.875V, V
= 1.5V, 3mm × 3mm
IN
OUT(BUCK)
OUT(VLDO)
10-Pin DFN Package
V : 3V to 5.5V, V
= 1.8V, V = 1.575V, 3mm × 3mm
OUT(VLDO)
IN
OUT(BUCK)
10-Pin DFN Package
Dual 300mA (I ), 2.25MHz, Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
Step-Down DC/DC Converter
8-Pin DFN Package
LTC3548/LTC3548-1/ Dual 800mA/400mA (I ), 2.25MHz, Synchronous
LTC3548-2
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA, I < 1μA,
Q SD
OUT
IN
Step-Down DC/DC Converter
DFN and 10-Pin MS Packages
LTC3700
Step-Down DC/DC Controller with LDO Regulator
V from 2.65V to 9.8V, Constant Frequency 550kHz Operation
IN
35411fb
LT 0416 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
l
l
LINEAR TECHNOLOGY CORPORATION 2007
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3541-1
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