LTC3548EMSE#PBF [Linear]
暂无描述;
Linear 
LTC3548
Dual Synchronous,
400mA/800mA, 2.25MHz
Step-Down DC/DC Regulator
FEATURES
DESCRIPTION
The LTC®3548 is a dual, constant frequency, synchronous
step down DC/DC converter. Intended for low power ap-
plications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1.2mm. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 0.7A/1.2A
power switches provide high efficiency without the need
for external Schottky diodes.
n
High Efficiency: Up to 95%
n
Very Low Quiescent Current: Only 40μA
n
2.25MHz Constant Frequency Operation
n
High Switch Current: 0.7A and 1.2A
No Schottky Diodes Required
n
n
Low R
Internal Switches: 0.35Ω
DS(ON)
n
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: I < 1μA
n
n
n
n
n
n
n
A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while Pulse Skip Mode provides low noise ripple at light
loads.
Q
Output Voltages from 5V down to 0.6V
Power-On Reset Output
Externally Synchronizable Oscillator
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages
To further maximize battery runtime, the P-channel
MOSFETs are turned on continuously in dropout (100%
duty cycle), and both channels draw a total quiescent cur-
rent of only 40μA. In shutdown, the device draws <1μA.
, LTC, LT, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
APPLICATIONS
■
PDAs/Palmtop PCs
■
Digital Cameras
■
Cellular Phones
■
Portable Media Players
■
PC Cards
■
Wireless and DSL Modems
TYPICAL APPLICATION
LTC3548 Efficiency Curve
V
= 2.8V
IN
TO 5.5V
100
95
90
85
80
75
70
65
60
1000
100
10
10μF
100k
RUN2
V
IN
RUN1
MODE/SYNC
POR
RESET
EFFICIENCY
LTC3548
4.7μH
2.2μH
V
= 2.5V
V
= 1.8V
OUT1
OUT2
SW2
SW1
AT 400mA
AT 800mA
POWER LOSS
68pF
887k
33pF
604k
1
V
FB1
V
FB2
V
= 3.3V, V
= 1.8V
OUT
IN
GND
Burst Mode OPERATION
280k
301k
4.7μF
10μF
CHANNEL 1, NO LOAD ON CHANNEL 2
0.1
1
10
100
1000
3548 TA01
LOAD CURRENT (mA)
3548 TA02
Figure 1. 2.5V/1.8V at 400mA/800mA Step-Down Regulators
3548fa
1
LTC3548
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V Voltages.................................................–0.3V to 6V
FB1 FB2
Ambient Operating Temperature
IN
V
, V , RUN1, RUN2
Range (Note 2) .................................... –40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range...................– 65°C to 125°C
Lead Temperature (Soldering, 10 sec)
Voltages....................................... –0.3V to V + 0.3V
IN
MODE/SYNC Voltage........................ –0.3V to V + 0.3V
IN
SW1, SW2 Voltage........................... –0.3V to V + 0.3V
IN
POR Voltage................................................. –0.3V to 6V
MSE only .......................................................... 300°C
PIN CONFIGURATION
TOP VIEW
V
1
2
3
4
5
10
9
V
FB2
FB1
TOP VIEW
RUN1
V
RUN2
POR
V
1
2
3
4
5
10
9
V
FB2
FB1
IN
11
8
RUN1
RUN2
POR
SW1
GND
7
SW2
V
SW1
GND
11
8
IN
7
6
SW2
MODE/
SYNC
6
MODE/
SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
MSE PIN 11, EXPOSED PAD: PGND
MUST BE CONNECTED TO GND
DD PIN 11, EXPOSED PAD: PGND
MUST BE CONNECTED TO GND
T
= 125°C, θ = 45°C/W, θ = 3°C/W
T
= 125°C, θ = 45°C/W, θ = 10°C/W
JMAX
JA
JC
JMAX JA JC
(Soldered to a 4-layer board)
(Soldered to a 4-layer board)
ORDER INFORMATION
LEAD FREE FINISH
LTC3548EDD#PBF
LTC3548IDD#PBF
LTC3548EMSE#PBF
LTC3548IMSE#PBF
TAPE AND REEL
PART MARKING*
LBNJ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3548EDD#TRPBF
LTC3548IDD#TRPBF
LTC3548EMSE#TRPBF
LTC3548IMSE#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LBNJ
–40°C to 85°C
LTBNH
–40°C to 85°C
LTBNH
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
l
l
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage (Note 3)
2.5
IN
I
FB
30
nA
V
0°C ≤ T ≤ 85°C
0.588
0.585
0.6
0.6
0.612
0.612
V
V
FB
A
l
–40°C ≤ T ≤ 85°C
A
ΔV
Reference Voltage Line Regulation
V
IN
= 2.5V to 5.5V (Note 3)
0.3
0.5
%V
LINE REG
3548fa
2
LTC3548
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
ΔV
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Load Regulation
(Note 3)
0.5
%
LOAD REG
I
S
Input DC Supply Current
Active Mode
V
V
= V = 0.5V
700
40
0.1
950
60
1
μA
μA
μA
FB1
FB1
FB2
Sleep Mode
= V = 0.63V, MODE/SYNC = 3.6V
FB2
Shutdown
RUN = 0V, V = 5.5V, MODE/SYNC = 0V
IN
l
f
f
I
Oscillator Frequency
V
= 0.6V
1.8
2.25
2.25
2.7
MHz
MHz
OSC
SYNC
LIM
FB
Synchronization Frequency
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
V
V
= 3V, V = 0.5V, Duty Cycle <35%
= 3V, V = 0.5V, Duty Cycle <35%
0.95
0.6
1.2
0.7
1.6
0.9
A
A
IN
IN
FB
FB
R
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
DS(ON)
I
Switch Leakage Current
Power-On Reset Threshold
Power-On Reset On-Resistance
Power-On Reset Delay
RUN Threshold
V
= 5V, V
= 0V, V = 0V
0.01
–8.5
100
1
μA
%
SW(LKG)
IN
RUN
FB
POR
V
Ramping Down, MODE/SYNC = 0V
FB
200
Ω
262,144
1
Cycles
V
l
l
V
0.3
1.5
1
RUN
I
RUN Leakage Current
0.01
μA
RUN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3548 is tested in a proprietary test mode that connects V
to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
FB
Note 2: The LTC3548 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3548I is guaranteed to meet
specified performance over the full –40°C to 85°C temperature range.
Note 5: T is calculated from the ambient T and power dissipation P
D
J
A
according to the following formula: T = T + (P • θ ).
J
A
D
JA
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TA = 25°C unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
Load Step
SW
5V/DIV
SW
5V/DIV
V
OUT
200mV/DIV
V
I
OUT
L
V
OUT
20mV/DIV
500mA/DIV
10mV/DIV
I
I
LOAD
L
I
500mA/DIV
200mA/DIV
L
200mA/DIV
3548 G01
3548 G02
3548 G03
V
V
LOAD
= 3.6V
2μs/DIV
V
V
LOAD
= 3.6V
1μs/DIV
V
V
= 3.6V
IN
20μs/DIV
IN
IN
= 1.8V
= 1.8V
= 1.8V
OUT
OUT
OUT
I
= 180mA
I
= 30mA
I
LOAD
= 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
CHANNEL 1; CIRCUIT OF FIGURE 3
CHANNEL 1; CIRCUIT OF FIGURE 3
3548fa
3
LTC3548
TA = 25°C unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Oscillator Frequency vs Supply
Voltage
Efficiency vs Input Voltage
Temperature
10
8
100
95
90
85
80
75
70
65
60
2.5
2.4
2.3
2.2
2.1
2.0
V
= 3.6V
IN
6
100mA
4
10mA
1mA
2
0
800mA
–2
–4
–6
–8
–10
V
= 1.8V, CHANNEL 1
OUT
Burst Mode OPERATION
CIRCUIT OF FIGURE 3
4
5
6
2
3
4
5
6
50
TEMPERATURE (°C)
100 125
2
3
–50 –25
0
25
75
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
3548 G06
3548 G04
3548 G05
Reference Voltage vs Temperature
RDS(ON) vs Input Voltage
RDS(ON) vs Junction Temperature
0.615
0.610
0.605
0.600
0.595
0.590
0.585
500
450
400
350
300
250
200
550
500
450
400
350
300
250
200
150
100
V
= 3.6V
V
= 2.7V
IN
T
= 25°C
IN
A
V
= 3.6V
IN
V
= 4.2V
IN
MAIN
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
3
2
50
TEMPERATURE (°C)
100 125
5
7
50
100 125 150
–50 –25
0
25
75
1
4
6
–50 –25
0
25
75
V
(V)
JUNCTION TEMPERATURE (°C)
IN
3548 G07
3548 G08
3548 G09
Efficiency vs Load Current
Load Regulation
Line Regulation
2.0
1.5
0.5
0.4
100
95
90
85
80
75
70
65
60
V
I
A
= 1.8V
OUT
OUT
= 200mA
T
= 25°C
0.3
Burst Mode OPERATION
PULSE SKIP MODE
1.0
Burst Mode OPERATION
0.2
0.5
0.1
0
0
PULSE SKIP MODE
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
V
= 3.6V, V
= 1.8V
V
= 3.6V, V
= 1.8V
OUT
IN
OUT
IN
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
CHANNEL 1; CIRCUIT OF FIGURE 3
CHANNEL 1; CIRCUIT OF FIGURE 3
1
10
100
1000
1
10
100
1000
2
6
3
4
5
LOAD CURRENT (mA)
LOAD CURRENT (mA)
V
(V)
IN
3548 G12
3548 G11
3548 G15
3548fa
4
LTC3548
TA = 25°C unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Efficiency vs Load Current
100
90
80
70
60
50
40
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
3.6V
2.7V
3.6V
2.7V
4.2V
3.6V
2.7V
4.2V
4.2V
V
= 2.5V, CHANNEL 1
V
= 1.5V, CHANNEL 1
V
= 1.2V, CHANNEL 1
OUT
OUT
OUT
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
1
10
100
1000
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3548 G10
3548 G14
3548 G13
PIN FUNCTIONS
V
(Pin1):OutputFeedback.Receivesthefeedbackvolt-
FB1
synchronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.
age from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to V
IN
Inductor. This pin swings from V to GND.
IN
enablesregulator1,whileforcingittoGNDcausesregulator
POR (Pin 8): Power-On Reset . This common-drain logic
outputispulledtoGNDwhentheoutputvoltagefallsbelow
–8.5% of regulation and goes high after 117ms when both
channels are within regulation.
1 to shut down. This pin must be driven; do not float.
V (Pin3):MainPowerSupply.Mustbecloselydecoupled
IN
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to V
IN
Inductor. This pin swings from V to GND.
IN
enablesregulator2,whileforcingittoGNDcausesregulator
2 to shut down. This pin must be driven; do not float.
GND (Pin 5): Main Ground. Connect to the (–) terminal
of C , and (–) terminal of C .
OUT
IN
V
(Pin 10): Output Feedback. Receives the feedback
FB2
voltagefromtheexternalresistivedivideracrosstheoutput.
Nominal voltage for this pin is 0.6V.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the opera-
tion of the device. When tied to V or GND, Burst Mode
IN
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
operationorpulseskippingmodeisselected,respectively.
the (–) terminal of C , and (–) terminal of C . Must be
OUT
IN
Do not float this pin. The oscillation frequency can be
connected to electrical ground on PCB.
3548fa
5
LTC3548
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
V
IN
SLOPE
COMP
EN
BURST
–
+
+
–
0.6V
SLEEP
–
+
I
TH
5Ω
EA
I
COMP
0.35V
V
FB1
1
S
R
Q
RS
LATCH
Q
0.55V
–
+
SWITCHING
LOGIC
UV
OV
UVDET
OVDET
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
4
SW1
+
–
0.65V
+
–
I
RCMP
SHUTDOWN
11 GND
V
IN
3
8
V
IN
PGOOD1
POR
2
9
RUN1
RUN2
POR
COUNTER
0.6V REF
OSC
OSC
5
7
GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
10
SW2
V
FB2
3548 BD
OPERATION
The LTC3548 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit a
variety of applications, the selectable Mode pin allows the
user to choose between low noise and high efficiency.
Main Control Loop
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V voltage is below the the reference voltage.
FB
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The output voltage is set by an external divider returned
to the V pins. An error amplfier compares the divided
FB
outputvoltagewithareferencevoltageof0.6Vandadjusts
the peak inductor current accordingly. An undervoltage
comparator will pull the POR output low if the output
voltage is not above –8.5% of the reference voltage. The
POR output will go high after 262,144 clock cycles (about
117ms) of achieving regulation.
The peak inductor current is controlled by the internally
compensated I voltage, which is the output of the er-
TH
ror amplifier.This amplifier compares the V pin to the
FB
0.6V reference. When the load current increases, the
V
voltage decreases slightly below the reference. This
FB
3548fa
6
LTC3548
OPERATION
decrease causes the error amplifier to increase the I
mode can be used. In this mode, the LTC3548 continues
to switch at a constant frequency down to very low cur-
rents, where it will begin skipping pulses. The efficiency in
pulse skip mode can be improved slightly by connecting
the SW node to the MODE/SYNC input which reduces the
clock frequency by approximately 30%.
TH
voltage until the average inductor current matches the
new load current.
The main control loop is shut down by pulling the RUN
pin to ground.
Low Current Operation
Dropout Operation
ByselectingMODE/SYNC(pin6), twomodesareavailable
tocontroltheoperationoftheLTC3548atlowcurrents.Both
modesautomaticallyswitchfromcontinuousoperationto
the selected mode when the load current is low.
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turnedoncontinuouslywiththeoutputvoltagebeingequal
to the input voltage minus the voltage drops across the
internal p-channel MOSFET and the inductor.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3548
automaticallyswitchesintoBurstModeoperation,inwhich
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are domi-
nated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
An important design consideration is that the R
DS(ON)
of the P-channel switch increases with decreasing input
supplyvoltage(SeeTypicalPerformanceCharacteristics).
Therefore, the user should calculate the power dissipation
when the LTC3548 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica-
tions Information Section).
voltagecomparatortripswhenI isbelow0.35V,shutting
TH
off the switch and reducing the power. The output capaci-
Low Supply Operation
tor and the inductor supply the power to the load until I
TH
To prevent unstable operation, the LTC3548 incorporates
an Under-Voltage Lockout circuit which shuts down the
part when the input voltage drops below about 1.65V.
exceeds 0.65V, turning on the switch and the main control
loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
APPLICATIONS INFORMATION
Accepting larger values of ΔI allows the use of low
A general LTC3548 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
L
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
inductor L. Once the inductor is chosen, C and C
IN
OUT
ΔI = 0.3 • I
, where I
is 800mA for chan-
can be selected.
L
OUT(MAX)
OUT(MAX)
nel 1 and 400mA for channel 2. The largest ripple current
Inductor Selection
ΔI occurs at the maximum input voltage. To guarantee
L
Although the inductor does not influence the operat-
ing frequency, the inductor value has a direct effect on
that the ripple current stays below a specified maximum,
the inductor value should be chosen according to the
following equation:
ripple current. The inductor ripple current ΔI decreases
L
with higher inductance and increases with higher V or
ꢁ
ꢄ
IN
VOUT
fO • ꢀIL
VOUT
ꢃ
ꢆ
V
:
L=
• 1–
OUT
ꢃ
ꢂ
IN(MAX) ꢆ
ꢅ
V
ꢁ
ꢄ
VOUT
fO •L
V
V
OUT ꢆ
• 1–
ꢃ
ꢀIL =
ꢂ
ꢅ
IN
3548fa
7
LTC3548
APPLICATIONS INFORMATION
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
Table 1. Representation Surface Mount Inductors
PART
NUMBER
VALUE
(μH)
DCR
MAX DC
SIZE
3
(ΩMAX) CURRENT (A) W × L × H (mm )
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
4.4 × 5.8 × 1.2
2.5 × 3.2 × 2.0
2.5 × 3.2 × 2.0
4.5 × 5.4 × 1.2
CDRH2D11
Inductor Core Selection
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characterisitics. The choice of which style
inductor to use often depends more on the price vs size
requirementsandanyradiatedfield/EMIrequirementsthan
on what the LTC3548 requires to operate. Table 1 shows
some typical surface mount inductors that work well in
LTC3548 applications.
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.079
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients. Typically,
once the ESR requirement is satisfied, the capacitance
Input Capacitor (C ) Selection
IN
is adequate for filtering. The output ripple (ΔV ) is
OUT
In continuous mode, the input current of the converter is a
determined by:
square wave with a duty cycle of approximately V /V .
OUT IN
Topreventlargevoltagetransients, alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
ꢂ
ꢅ
ꢇ
ꢆ
1
ꢀVOUT ꢁ ꢀI ESR+
L ꢄ
8fO COUT
ꢃ
where f = operating frequency, C
= output capacitance
OUT
and ΔI = ripple current in the inductor. The output ripple
VOUT(V – VOUT
)
L
IN
IRMS ≈IMAX
is highest at maximum input voltage since ΔI increases
L
V
IN
with input voltage. With ΔI = 0.3 • I
the output
L
OUT(MAX)
where the maximum average output current I
equals
MAX
ripple will be less than 100mV at maximum V and
IN
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
f = 2.25MHz with:
O
MAX
LIM
L
ESR
< 150mΩ
COUT
This formula has a maximum at V = 2V , where I
RMS
Once the ESR requirements for C
have been met, the
IN
OUT
OUT
= I
. This simple worst-case is commonly used to
RMS current rating generally far exceeds the I
OUT/2
RIPPLE(P-P)
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1μF to 1μF ceramic capacitor is also recommended on
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantulum capacitors are all available in surface mount
packages.TheOS-CONsemiconductordielectriccapacitor
available from Sanyo has the lowest ESR(size) product
3548fa
8
LTC3548
APPLICATIONS INFORMATION
of any aluminum electrolytic at a somewhat higher price. ESLbeforeESRbecomeseffective. Also, ceramiccapsare
Special polymer capacitors, such as Sanyo POSCAP, prone to temperature effects which requires the designer
to check loop stability over the operating temperature
range. To minimize their large temperature and voltage
coefficients, only X5R or X7R ceramic capacitors should
beused.Agoodselectionofceramiccapacitorsisavailable
from Taiyo Yuden, AVX, Kemet, TDK, and Murata.
Panasonic Special Polymer (SP), and Kemet A700, of-
fer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density, but they have a larger ESR and it
is critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heightsrangingfrom2mmto4mm.Aluminumelectrolytic
capacitors have a significantly larger ESR, and are often
usedinextremelycost-sensitiveapplicationsprovidedthat
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coefficient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
can induce ringing at the V pin. At best, this ringing can
IN
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
looptorespondisdependentonthecompensationandthe
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
V = 2.5V
IN
TO 5.5V
C
R5
IN
RUN2
V
RUN1
POR
IN
BM*
POWER-ON
RESET
MODE/SYNC
PS*
LTC3548
L1
L2
V
OUT2
SW2
SW1
V
OUT1
C5
R4
C4
R2
output drop linearly. The output droop, V , is usually
DROOP
about 2-3 times the linear drop of the first cycle. Thus,
a good place to start is with the output capacitor size of
approximately:
V
V
FB2
FB1
GND
R1
C
C
OUT2
R3
OUT1
3548 F02
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V : Burst Mode
IN
ΔIOUT
fO • VDROOP
COUT ≈ 2.5
Figure 2. LTC3548 General Schematic
More capacitance may be required depending on the duty
cycle and load step requirements.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3548 in parallel with the
main capacitors for high frequency decoupling.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
comingavailableinsmallercasesizes. Thesearetempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stabilityproblems.SolidtantalumcapacitorESRgenerates
aloop“zero”at5kHzto50kHzthatisinstrumentalingiving
acceptableloopphasemargin. Ceramiccapacitorsremain
capacitivetobeyond300kHzandusuallyresonatewiththeir
Setting the Output Voltage
The LTC3548 develops a 0.6V reference voltage between
the feedback pin, V , and the ground as shown in
FB
Figure 2. The output voltage is set by a resistive divider
according to the following formula:
3548fa
9
LTC3548
APPLICATIONS INFORMATION
Checking Transient Response
ꢀ
ꢃ
R2
R1
VOUT =0.6V 1+
ꢂ
ꢅ
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
ꢁ
ꢄ
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
When a load step occurs, V
immediately shifts by an
OUT
amount equal to ΔI
• ESR, where ESR is the effective
LOAD
series resistance of C . ΔI
also begins to charge
OUT
LOAD
or discharge C , generating a feedback error signal
OUT
Toimprovethefrequencyresponse,afeed-forwardcapaci-
used by the regulator to return V
to its steady-state
can be monitored
OUT
OUT
tor C may also be used. Great care should be taken to
F
value. During this recovery time, V
route the V line away from noise sources, such as the
FB
for overshoot or ringing that would indicate a stability
problem.
inductor or the SW line.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
Power-On Reset
ThePORpinisanopen-drainoutputwhichpullslowwhen
eitherregulatorisoutofregulation.Whenbothoutputvolt-
agesareabove–8.5%ofregulation,atimerisstartedwhich
phase margin. In addition, a feed-forward capacitor, C ,
F
can be added to improve the high frequency response, as
18
releases POR after 2 clock cycles (about 117ms). This
shown in Figure 2. Capacitor C provides phase lead by
F
delay can be significantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse skipping
modeduringareset.Inaddition,iftheoutputvoltagefaults
duringBurstModesleep,PORcouldhaveaslightdelayfor
an undervoltage output condition. This can be avoided by
using pulse skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.
creating a high frequency zero with R2, which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be
caused by switching loads with large (>1μF) load input
capacitors. The discharged load input capacitors are ef-
fectively put in parallel with C , causing a rapid drop in
OUT
Mode Selection and Frequency Synchronization
V
OUT
. No regulator can deliver enough current to prevent
TheMODE/SYNCpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit
the turn-on speed of the load switch driver. A Hot Swap™
controller is designed specifically for this purpose and
usuallyincorporatescurrentlimiting, short-circuitprotec-
tion, and soft-starting.
ing this pin to V enables Burst Mode operation, which
IN
provides the best low current efficiency at the cost of a
higheroutputvoltageripple.Connectingthispintoground
selects pulse skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.
Efficiency Considerations
The LTC3548 can also be synchronized to an external
2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse skipping and
the top switch turn-on is synchronized to the rising edge
of the external clock.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
Hot Swap is a trademark of Linear Technology Corporation.
3548fa
10
LTC3548
APPLICATIONS INFORMATION
produce the most improvement. Percent efficiency can
be expressed as:
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
% Efficiency = 100% – (L1 + L2 + L3 + ...)
can be minimized by making sure that C has adequate
IN
where L1, L2, etc. are the individual losses as a percent-
age of input power.
chargestorageandverylowESRattheswitchingfrequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3548 circuits: 1)V quiescent current,
IN
Thermal Considerations
2
2) switching losses, 3) I R losses, 4) other losses.
In a majority of applications, the LTC3548 does not dis-
sipate much heat due to its high efficiency. However, in
applicationswheretheLTC3548isrunningathighambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will turn off and the SW node will become high
impedance.
1) The V current is the DC supply current given in the
IN
Electrical Characteristics which excludes MOSFET driver
andcontrolcurrents.V currentresultsinasmall(<0.1%)
IN
loss that increases with V , even at no load.
IN
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V to
IN
To prevent the LTC3548 from exceeding the maximum
junctiontemperature,theuserwillneedtodosomethermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
ground. The resulting dQ/dt is a current out of V that is
IN
typically much larger than the DC bias current. In continu-
ous mode, I
= f (Q + Q ), where Q and Q are
GATECHG
O T B T B
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
and thus their effects will be more pronounced at higher
supply voltages.
T
= P • θ
D JA
RISE
2
3) I R losses are calculated from the DC resistances of
where P is the power dissipated by the regulator and θ
D JA
is the thermal resistance from the junction of the die to
the ambient temperature.
the internal switches, R , and external inductor, R . In
SW
L
continuousmode,theaverageoutputcurrentflowsthrough
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
The junction temperature, T , is given by:
J
T = T
J
+ T
AMBIENT
RISE
R
and the duty cycle (D) as follows:
DS(ON)
As an example, consider the case when the LTC3548 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 400mA and 800mA and an ambi-
ent temperature of 70°C. From the Typical Performance
R
SW
= (R
)(D) + (R
)(1 – D)
DS(ON)TOP
DS(ON)BOT
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Characteristics
Characteristics graph of Switch Resistance, the R
DS(ON)
2
curves. Thus, to obtain I R losses:
resistance of the main switch is 0.425Ω. Therefore, power
2
I R losses = I
(R + R )
OUT2 SW L
dissipated by each channel is:
2
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
P = I • R
= 272mW and 68mW
D
DS(ON)
3548fa
11
LTC3548
APPLICATIONS INFORMATION
The MS package junction-to-ambient thermal resistance,
JA
the regulator operating in a 70°C ambient temperature is
approximately:
The PGOOD pin is a common drain output and re-
quires a pull-up resistor. A 100k resistor is used for
adequate speed.
θ , is 45°C/W. Therefore, the junction temperature of
Figure 3 shows the complete schematic for this design
example.
T = (0.272 + 0.068) • 45 + 70 = 85.3°C
J
which is below the absolute maximum junction tempera-
ture of 125°C.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3548. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
Design Example
As a design example, consider using the LTC3548 in an
portable application with a Li-Ion battery. The battery pro-
vides a V = 2.8V to 4.2V. The load requires a maximum
IN
of 800mA in active mode and 2mA in standby mode. The
1. Does the capacitor C connect to the power V (Pin
IN
IN
output voltage is V
= 2.5V. Since the load still needs
OUT
3) and GND (exposed pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the inductor value for about 30% ripple
2. Are the C
OUT
and L1 closely connected? The (–) plate of
OUT
current at maximum V :
IN
C
returns current to GND and the (–) plate of C .
IN
ꢀ
ꢃ
2.5V
2.25MHz •240mA
2.5V
4.2V
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense line
L=
• 1–
=1.9μH
ꢂ
ꢅ
ꢁ
ꢄ
OUT
terminatednearGND(exposedpad). Thefeedbacksignals
should be routed away from noisy components and
traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.
Choosing a vendor’s closest inductor value of 2.2μH,
results in a maximum ripple current of:
V
FB
ꢂ
ꢅ
2.5V
2.25MHz •2.2μ
2.5V
4.2V
ꢀIL =
• 1ꢁ
=204mA
ꢄ
ꢇ
ꢃ
ꢆ
4.KeepsensitivecomponentsawayfromtheSWpins.The
input capacitor C and the resistors R1 to R4 should be
IN
For cost reasons, a ceramic capacitor will be used. C
OUT
routed away from the SW traces and the inductors.
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
5. A ground plane is preferred, but if not available, keep
thesignalandpowergroundssegregatedwithsmallsignal
components returning to the GND pin at one point and
800mA
2.25MHz •(5%•2.5V)
COUT ≈ 2.5
=7.1μF
should not share the high current path of C or C
.
OUT
IN
Agoodstandardvalueis10μF.Sincetheoutputimpedance
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
of a Li-Ion battery is very low, C is typically 10μF.
IN
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μAwiththe0.6VfeedbackvoltagemakesR1~300k.Aclose
standard 1% resistor is 280k, and R2 is then 887k.
V or GND.
IN
3548fa
12
LTC3548
APPLICATIONS INFORMATION
V
IN
= 2.5V*
TO 5.5V
V
IN
R5
100k
C1
10μF
C
IN
RUN2
V
RUN1
IN
RUN2
V
RUN1
IN
POWER-ON
RESET
MODE/SYNC
POR
MODE/SYNC
POR
L2
L1
LTC3548
LTC3548
4.7μH
2.2μH
V
= 2.5V*
V
= 1.8V
OUT1
OUT2
L1
L2
SW2
SW1
AT 400mA
AT 800mA
V
OUT2
SW2
SW1
V
OUT1
C5, 68pF
C4, 33pF
C5
R4
C4
V
V
FB1
FB2
V
FB1
R4
887k
R2
604k
V
FB2
GND
C3
4.7μF
C2
10μF
R3
280k
R1
301k
R2
GND
R1
C
C
OUT2
R3
OUT1
3548 F03
C1, C2, C3: TAIYO YUDEN JMK212BJ106MG
C3: TAIYO YUDEN JMK212BJ475MG
L1: MURATA LQH32CN2R2M11
L2: MURATA LQH32CN4R7M23
3548 F04
BOLD LINES INDICATE HIGH CURRENT PATHS
*V
CONNECTED TO V FOR V ≤ 2.8V (DROPOUT)
IN IN
OUT
Figure 4. LTC3548 Layout Diagram (See Board Layout Checklist)
Figure 3. LTC3548 Typical Application
U
TYPICAL APPLICATIO S
Low Ripple Buck Regulators Using Ceramic Capacitors
V = 2.5V
IN
TO 5.5V
R5
100k
C1
10μF
RUN2
V
RUN1
IN
POWER-ON
RESET
POR
LTC3548
L2
10μH
L1
4.7μH
V
= 1.8V
OUT2
AT 400mA
V
= 1.2V
OUT1
SW2
SW1
AT 800mA
C5, 68pF
C4, 33pF
V
V
FB1
FB2
R4
887k
R2
604k
MODE/SYNC GND
C3
10μF
C2
10μF
R3
442k
R1
604k
C1, C2, C3: TDK C2012X5R0J106M
L1: SUMIDA CDRH2D18/HP-4R7NC
L2: SUMIDA CDRH2D18/HP-100NC
3548 TA03
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
1.8V
1.2V
V
= 3.3V
IN
PULSE SKIP MODE
NO LOAD ON OTHER CHANNEL
10
100
1000
LOAD CURRENT (mA)
3548 TA03b
3548fa
13
LTC3548
U
TYPICAL APPLICATIO S
1mm Profile Core and I/O Supplies
V
= 3.6V
IN
TO 5.5V
R5
100k
C1*
10μF
RUN2
V
RUN1
IN
POWER-ON
RESET
MODE/SYNC
POR
LTC3548
L2
4.7μH
L1
2.2μH
V
= 3.3V
V
= 1.8V
OUT1
OUT2
SW2
SW1
AT 400mA
AT 800mA
C5, 68pF
C4, 33pF
V
FB1
V
FB2
R4
887k
R2
604k
GND
C3
4.7μF
C2
10μF
R3
196k
R1
301k
3548 TA07
C1, C2: MURATA GRM219R60J106KE19
C3: MURATA GRM219R60J475KE19
L1: COILTRONICS LPO3310-222MX
L2: COILTRONICS LPO3310-472MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
3.3V
1.8V
V
= 5V
IN
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
1
10
100
1000
LOAD CURRENT (mA)
3548 TA08
3548fa
14
LTC3548
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
0.38 ± 0.10
TYP
6
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
REF
2.06 ± 0.102
(.081 ± .004)
1
10 9
8
7 6
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
DETAIL “A”
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
4.90 ± 0.152
(.193 ± .006)
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1
2
3
4
5
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.86
(.034)
REF
DETAIL “A”
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
0.18
(.007)
NOTE:
SEATING
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
0.50
(.0197)
BSC
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MSOP (MSE) 0307 REV B
3548fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3548
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
V
= 2.8V
IN
TO 4.2V
R5
100k
C1
10μF
RUN2
V
RUN1
IN
POWER-ON
RESET
MODE/SYNC
POR
L2
15μH
L1
2.2μH
LTC3548
D1
V
= 3.3V
OUT2
AT 100mA
V
= 1.8V
OUT1
SW2
SW1
AT 800mA
C5, 22pF
C4, 33pF
M1
+
C6
22μF
V
FB1
V
FB2
R4
887k
R2
604k
GND
C3
4.7μF
C2
10μF
R3
196k
R1
301k
3548 TA04
C1, C2: TAIYO YUDEN JMK316BJ106ML
C3: MURATA GRM21BR60J475KA11B
C6: KEMET C1206C226K9PAC
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-150M (D52LC SERIES)
M1: SILICONIX Si2302DS
D1: PHILIPS PMEG2010
Efficiency vs Load Current
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
90
80
70
60
50
40
30
2.8V
4.2V
3.6V
2.8V
4.2V
3.6V
V
= 1.8V
V
= 3.3V
OUT
OUT
Burst Mode OPERATION
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3548 TA06
3548 TA05
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PART NUMBER
DESCRIPTION
COMMENTS
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Q
OUT
IN
OUT(MIN)
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I
<1μA, MSOP-8 Package
SD
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Q
SD
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= 0.9V to 1.6V,
OUT
IN
OUT(MIN)
I = 60μA, I < 1μA, DFN-12 Package
Q SD
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LT3407/LT3407-2
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96% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 20μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Synchronous Step-Down DC/DC Converters
I
<1μA, ThinSOT Package
600mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converters
I
SD
<1μA, ThinSOT Package
600mA/1.5MHz, 800mA/2.25MHz
Dual Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA,
Q
IN
I
SD
<1μA, MSE, DFN Package
1.25A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
SD
<1μA, MSOP-10 Package
LTC3412
2.5A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
SD
<1μA, TSSOP-16E Package
LTC3414
4A (I ), 4MHz,
95% Efficiency, V : 2.25V to 5.5V, V
SD
= 0.8V, I = 64μA,
OUT(MIN) Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
<1μA, TSSOP-28E Package
LTC3440
600mA (I ), 2MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 2.5V, I = 25μA,
OUT(MIN) Q
OUT
IN
Synchronous Buck-Boost DC/DC Converter
I
<1μA, MSOP-10 Package
3548fa
LT 0208 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
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© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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