LTC3560ES6#TRPBF [Linear]
暂无描述;型号: | LTC3560ES6#TRPBF |
厂家: | Linear |
描述: | 暂无描述 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管 |
文件: | 总16页 (文件大小:324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3560
2.25MHz, 800mA
Synchronous Step-Down
Regulator in ThinSOT
U
DESCRIPTIO
FEATURES
■
High Efficiency: Up to 95%
The LTC®3560 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 16µA, dropping to <1µA in shutdown. The 2.5V to
5.5VinputvoltagerangemakestheLTC3560ideallysuited
forsingleLi-Ion/Li-Polymerbattery-poweredapplications.
100% duty cycle provides low dropout operation, extend-
ing battery life in portable systems.
Low Output Ripple (<20mVP-P): Burst Mode®
■
Operation: IQ = 16µA
■
■
■
■
■
■
■
■
■
■
2.5V to 5.5V Input Voltage Range
2.25MHz Constant Frequency Operation
Synchronizable to External Clock
No Schottky Diode Required
Stable with Ceramic Capacitors
Low Dropout Operation: 100% Duty Cycle
0.6V Reference Allows Low Output Voltages
Shutdown Mode Draws <1µA Supply Current
±2% Output Voltage Accuracy
Switching frequency is internally set at 2.25MHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC3560 can be
externally synchronized from 1MHz to 3MHz. Burst Mode
operation is inhibited during synchronization or when the
SYNC/MODE pin is pulled high, preventing low frequency
ripple from interfering with audio circuitry.
Current Mode Operation for Excellent Line and
Load Transient Response
■
■
Overtemperature Protected
Low Profile (1mm) ThinSOTTM Package
U
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.6V feed-
back reference voltage. The LTC3560 is available in a low
profile (1mm) ThinSOT package.
, LTC, LT and Burst Mode are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6580258, 5481178, 5994885,
6304066, 6498466, 6611131
APPLICATIO S
■
Cellular Telephones
■
Wireless and DSL Modems
■
Digital Still Cameras
■
Media Players
■
Portable Instruments
U
TYPICAL APPLICATIO
100
90
80
70
60
50
40
30
20
10
0
1
0.1
2.2µH
V
IN
V
OUT
2.7V
0.01
0.001
0.0001
V
SW
IN
2.5V
10pF
C
TO 5.5V
IN
C
OUT
LTC3560
RUN
10µF
10µF
CER
CER
SYNC/MODE V
GND
FB
V
V
V
= 3.6V
= 4.2V
= 5.5V
IN
IN
IN
806k
255k
3405A F01a
0.1
1
10
100
1000
LOAD CURRENT (mA)
3560 F01b
Figure 1a. High Efficiency Step-Down Converter
Figure 1b. Efficiency vs Load Current
3560f
1
LTC3560
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Input Supply Voltage .................................. –0.3V to 6V
SYNC/MODE, RUN, VFB Voltages............... –0.3V to VIN
SW Voltage (DC) ......................... –0.3V to (VIN + 0.3V)
P-Channel Switch Source Current (DC) (Note 6) ... 1.2A
N-Channel Switch Sink Current (DC) (Note 6) ....... 1.2A
Peak SW Sink and Source Current (Note 6)........... 2.1A
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
RUN 1
GND 2
SW 3
6 SYNC/MODE
5 V
FB
IN
4 V
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 125°C, θJA = 250°C/ W
ORDER PART NUMBER
S6 PART MARKING
LTCFY
LTC3560ES6
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
IN
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 3.6V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
±30
2.0
UNITS
nA
A
I
I
Feedback Current
●
VFB
PK
Peak Inductor Current
Regulated Feedback Voltage
Reference Voltage Line Regulation
Output Voltage Load Regulation
Input Voltage Range
V
= 3V, V = 0.5V, Duty Cycle < 35%
1.0
1.5
0.6
IN
FB
V
(Note 4)
= 2.5V to 5.5V (Note 4)
●
●
0.588
0.612
0.4
V
FB
∆V
FB
V
0.04
0.5
%/V
%
IN
V
V
LOADREG
IN
●
2.5
5.5
V
I
Input DC Bias Current
Pulse Skipping Mode
Burst Mode® Operation
Shutdown
(Note 5)
S
V
V
V
= 0.63V, Mode = High, I
= 0.63V, Mode = Low, I
= 0A
= 0A
200
16
0.1
300
30
1
µA
µA
µA
FB
LOAD
LOAD
FB
= 0V, V = 5.5V
RUN
IN
f
f
Oscillator Frequency
V
= 0.6V
●
●
1.8
1
2.25
2.7
3
MHz
MHz
Ω
OSC
FB
SYNC Frequency Range
SYNC
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA
0.23
0.21
± 0.01
1
0.35
0.35
±1
PFET
NFET
LSW
DS(ON)
DS(ON)
SW
SW
= –100mA
Ω
I
SW Leakage
V
= 0V, V = 0V or 5.5V, V = 5.5V
µA
V
RUN
SW
IN
V
RUN Threshold
●
●
●
●
0.3
0.3
0.6
1.5
±1
RUN
I
RUN Leakage Current
SYNC/MODE Threshold
SYNC/MODE Leakage Current
Soft-Start Time
± 0.01
1.0
µA
V
RUN
V
1.5
±1
SYNC/MODE
SYNC/MODE
SOFTSTART
I
t
± 0.01
0.9
µA
ms
V
from 10% to 90% Full Scale
1.2
FB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3560E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
3560f
2
LTC3560
ELECTRICAL CHARACTERISTICS
Note 3: T is calculated from the ambient temperature T and power
Note 6: Guaranteed by long-term current density limitations.
J
A
dissipation P according to the following formula:
D
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
LTC3560: T = T + (P )(250°C/W)
J
A
D
Note 4: The LTC3560 is tested in a proprietary test mode that connects
to the output of the error amplifier.
V
FB
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure1a Except for the Resistive Divider Resistor Values)
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V
OUT
I
= 100mA
= 1mA
OUT
I
= 10mA
OUT
I
OUT
I
= 900mA
OUT
I
= 0.1mA
OUT
V
IN
V
IN
V
IN
V
IN
= 2.7V
= 3.6V
= 4.2V
= 5.5V
V
V
V
= 3.6V
= 4.2V
= 5.5V
IN
IN
IN
V
= 3.3V
1
V
= 1.8V
OUT
OUT
0.1
10
100
1000
2.5
3
4
4.5
5
5.5
3.5
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
3560 G24
3560 G02
3560 G01
Reference Voltage vs
Temperature
Efficiency vs Output Current
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.615
0.610
0.605
0.600
V
= 1.3V
V
= 3.6V
IN
OUT
Burst Mode OPERATION
PULSE SKIP MODE
0.595
0.590
0.585
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
V
= 4.2V
= 3.6V
IN
IN
V
V
= 1.8V
1
OUT
0.1
1
10
100
1000
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0.1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3560 G03
3560 G04
3560 G05
3560f
3
LTC3560
TYPICAL PERFOR A CE CHARACTERISTICS
U W
(From Figure 1a Except for the Resistive Divider Resistor Values)
Oscillator Frequency vs
Temperature
Oscillator Frequency vs
Supply Voltage
Output Voltage vs Load Current
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.84
1.83
1.82
1.81
1.80
1.79
1.78
2.4
2.3
2.2
2.1
2.0
1.9
1.8
V
= 3.6V
IN
V
= 3.6V
IN
Burst Mode OPERATION
PULSE SKIP MODE
–50
0
25
50
75 100 125
–25
0
400
600
800
1000 1200
200
4.5
INPUT VOLTAGE (V)
5
2
2.5
3
3.5
4
5.5
6
TEMPERATURE (°C)
LOAD CURRENT (mA)
3560 G06
3560 G08
3560 G07
R
DS(ON
) vs Input Voltage
R
vs Temperature
Dynamic Supply Current
DS(ON)
0.40
0.35
0.30
0.25
0.40
300
250
200
150
100
50
V
LOAD
= 1.2V
= 0A
OUT
I
0.35
0.30
V
= 3.6V
IN
V
= 2.7V
IN
0.25
0.20
0.15
0.10
0.05
PULSE SKIPPING MODE
MAIN SWITCH
V
= 4.2V
IN
SYNCHRONOUS
SWITCH
0.20
0.15
0.10
SYNCHRONOUS SWITCH
MAIN SWITCH
Burst Mode OPERATION
0
0
4
6
7
0
1
2
3
5
4.5
INPUT VOLTAGE (V)
5
–25
0
50
75 100 125
2
2.5
3
3.5
4
5.5
6
–50
25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3560 G10
3560 G09
3560 G12
Dynamic Supply Current
vs Temperature
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
300
250
200
150
140
120
1000
900
800
700
600
500
400
300
200
100
0
V
V
LOAD
= 3.6V
RUN = 0V
IN
= 1.2V
= 0A
OUT
I
100
80
PULSE SKIPPING MODE
MAIN SWITCH
MAIN SWITCH
60
100
50
0
40
SYNCHRONOUS
SWITCH
SYNCHRONOUS
SWITCH
20
Burst Mode OPERATION
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
1
3
4
5
6
2
INPUT VOLTAGE (V)
3560 G11
3560 G13
3560 G14
3560f
4
LTC3560
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure 1a Except for the Resistive Divider Resistor Values)
Burst Mode Operation
Pulse Skipping Mode Operation
Start-Up from Shutdown
RUN
SW
2V/DIV
SW
2V/DIV
2V/DIV
V
OUT
1V/DIV
V
OUT
V
OUT
20mV/DIV
20mV/DIV
AC COUPLED
AC COUPLED
I
L
I
L
500mA/DIV
I
L
200mA/DIV
200mA/DIV
3560 G16
3560 G17
3560 G15
V
V
I
= 3.6V
500ns/DIV
V
V
I
= 3.6V
500µs/DIV
V
V
I
= 3.6V
2µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 25mA
= 800mA
= 25mA
LOAD
LOAD
LOAD
Load Step
Load Step
Load Step
V
V
OUT
OUT
200mV/DIV
200mV/DIV
V
OUT
AC COUPLED
AC COUPLED
200mV/DIV
AC COUPLED
I
I
I
L
L
L
1A/DIV
1A/DIV
1A/DIV
I
I
I
LOAD
LOAD
LOAD
1A/DIV
1A/DIV
1A/DIV
3560 G19
3560 G18
3560 G20
V
V
I
= 3.6V
20µs/DIV
V
V
I
= 3.6V
20µs/DIV
V
V
I
= 3.6V
20µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 50mA TO 800mA
= 0A TO 800mA
= 100mA TO 800mA
LOAD
LOAD
LOAD
PULSE SKIPPING MODE
PULSE SKIPPING MODE
PULSE SKIPPING MODE
Load Step
Load Step
Load Step
V
V
V
OUT
OUT
OUT
200mV/DIV
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
AC COUPLED
I
I
I
L
L
L
1A/DIV
1A/DIV
1A/DIV
I
I
I
LOAD
LOAD
LOAD
1A/DIV
1A/DIV
1A/DIV
3560 G21
3560 G22
3560 G23
V
V
I
= 3.6V
20µs/DIV
V
V
I
= 3.6V
20µs/DIV
V
V
I
= 3.6V
20µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 0A TO 800mA
= 50mA TO 800mA
= 100mA TO 800mA
LOAD
LOAD
LOAD
Burst Mode OPERATION
Burst Mode OPERATION
Burst Mode OPERATION
3560f
5
LTC3560
U
U
U
PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1µA supply current. Do not leave RUN floating.
V
FB (Pin 5): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
SYNC/MODE (Pin 6): External Clock Synchronization and
Mode Select Input. To synchronize with an external clock,
apply a clock with a frequency between 1MHz and 3MHz.
To select pulse skipping mode, tie to VIN. Grounding this
pin selects Burst Mode operation. Do not leave this pin
floating.
GND (Pin 2): Ground Pin.
SW (Pin 3): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
VIN (Pin 4): Main Supply Pin. Must be closely decoupled
to GND, Pin 2, with a 10µF or greater ceramic capacitor.
U
U
W
FU CTIO AL DIAGRA
SYNC/MODE
6
SLOPE
COMP
0.65V
OSC
OSC
V
4
IN
FREQ
–
+
SHIFT
V
FB
EN
–
+
5
SLEEP
+
–
5Ω
0.6V
+
–
0.4V
I
COMP
EA
BURST
Q
Q
S
R
SWITCHING
LOGIC
AND
RS LATCH
V
IN
ANTI-
SHOOT-
THRU
BLANKING
CIRCUIT
RUN
1
SW
3
0.6V REF
+
–
SHUTDOWN
I
RCMP
2
GND
3560 BD
3560f
6
LTC3560
U
OPERATIO
(Refer to Functional Diagram)
Main Control Loop
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 150mA re-
gardlessoftheoutputload. Eachburstevent canlastfrom
a few cycles at light loads to almost continuously cycling
with short sleep intervals at moderate loads. In between
theseburstevents,thepowerMOSFETsandanyunneeded
circuitry are turned off, reducing the quiescent current to
16µA. In this sleep state, the load current is being supplied
solely from the output capacitor. As the output voltage
droops, the EA amplifier’s output rises above the sleep
thresholdsignalingtheBURSTcomparatortotripandturn
the top MOSFET on. This process repeats at a rate that is
dependent on the load demand.
The LTC3560 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel MOS-
FET) and synchronous (N-channel MOSFET) switches are
internal. During normal operation, the internal top power
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the current comparator,
ICOMP, resets the RS latch. The peak inductor current at
whichICOMP resetstheRSlatch,iscontrolledbytheoutput
oferroramplifierEA.TheVFB pin,describedinthePinFunc-
tions section, allows EA to receive an output feedback
voltage from an external resistive divider. When the load
current increases, it causes a slight decrease in the feed-
back voltage relative to the 0.6V reference, which in turn,
causes the EA amplifier’s output voltage to increase until
the average inductor current matches the new load cur-
rent. While the top MOSFET is off, the bottom MOSFET is
turnedonuntileithertheinductorcurrentstartstoreverse,
as indicated by the current reversal comparator IRCMP, or
the beginning of the next clock cycle.
Frequency Synchronization
When the LTC3560 is clocked by an external source, Burst
Mode operation is disabled; the LTC3560 then operates in
PWMpulse-skippingmode. Inthismode, whentheoutput
load is very low, current comparator ICOMP may remain
trippedforseveralcyclesandforcethemainswitchtostay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while provid-
ing reasonable low current efficiency.
The main control loop is shut down by grounding RUN,
resetting the internal soft-start. Re-enabling the main
control loop by pulling RUN high activates the internal
soft-start, which slowly ramps the output voltage over
approximately 0.9ms until it reaches regulation.
Dropout Operation
Burst Mode Operation
Astheinputsupplyvoltagedecreasestoavalueapproach-
ing the output voltage, the duty cycle increases toward the
maximumontime. Furtherreductionofthesupplyvoltage
forcesthemainswitchtoremainonformorethanonecycle
untilitreaches100%dutycycle.Theoutputvoltagewillthen
be determined by the input voltage minus the voltage drop
across the P-channel MOSFET and the inductor.
The LTC3560 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
connect the SYNC/MODE pin to GND. To disable Burst
Mode operation and enable PWM pulse skipping mode,
connect the SYNC/MODE pin to VIN or drive it with a logic
high (VMODE > 1.5V). In this mode, the efficiency is lower
at light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 100mA. The
advantage of pulse skipping mode is lower output ripple
and less interference to audio circuitry.
Another important detail to remember is that at low input
supply voltages, the RDS(ON) of the P-channel switch
increases(seeTypicalPerformanceCharacteristics).There-
fore, the user should calculate the power dissipation when
the LTC3560 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
3560f
7
LTC3560
U
OPERATIO
(Refer to Functional Diagram)
Slope Compensation and Inductor Peak Current
results in a reduction of maximum inductor peak current
for duty cycles >40%. However, the LTC3560 uses a
patentedschemethatcounteractsthiscompensatingramp,
which allows the maximum inductor peak current to
remain unaffected throughout all duty cycles.
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
W U U
U
APPLICATIO S I FOR ATIO
ThebasicLTC3560applicationcircuitisshowninFigure 1.
Externalcomponentselectionisdrivenbytheloadrequire-
ment and begins with the selection of L followed by CIN and
current to prevent core saturation. Thus, a 960mA rated
inductor should be enough for most applications (800mA
+ 160mA). For better efficiency, choose a low DC-resis-
tance inductor.
COUT
.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
200mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Selection
For most applications, the value of the inductor will fall in
the range of 1µH to 3.3µH. Its value is chosen based on the
desired ripple current. Large value inductors lower ripple
current and small value inductors result in higher ripple
currents. Higher VIN or VOUT also increases the ripple
currentasshowninequation1. Areasonablestartingpoint
for setting ripple current is ∆IL = 320mA (40% of 800mA).
Inductor Core Selection
⎛
⎝
VOUT
V
IN
⎞
1
∆IL =
VOUT 1−
⎜
⎟
⎠
(1)
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
aresmallanddon’tradiatemuchenergy, butgenerallycost
f L
( )( )
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
Table 1. Representative Surface Mount Inductors
MAX DC
MANUFACTURER PART NUMBER
VALUE CURRENT DCR HEIGHT
Toko
A960AW-1R2M-518LC 1.2µH
A960AW-2R3M-518LC 2.3µH
A997AS-3R3M-DB318L 3.3µH
1.8A
1.5A
1.2A
46mΩ 1.8mm
63mΩ 1.8mm
70mΩ 1.8mm
Sumida
CDRH2D11/HP-1R5
CDRH3D11/HP-1R5
CDRH2D18/HP-2R2
CDRH2D14-3R3
1.5µH
1.5µH
2.2µH
3.3µH
1.35A
2A
1.6A
1.2A
64mΩ 1.2mm
80mΩ 1.2mm
48mΩ 2.0mm
100mΩ 1.55mm
TDK
VLF3010AT-1R5M1R2
VLF3010AT-2R2M1R0
1.5µH
2.2µH
1.2A
1.0A
68mΩ 1.0mm
100mΩ 1.0mm
Coilcraft
D01608C-222
LP01704-222M
2.2µH
2.2µH
2.3A
2.4A
70mΩ 3.0mm
120mΩ 1.0mm
Cooper
EPCO
SD3112-2R2
2.2µH
2.2µH
1.1A
1.6A
140mΩ 1.2mm
90mΩ 1.2mm
B82470A1222M
3560f
8
LTC3560
W U U
APPLICATIO S I FOR ATIO
U
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
whattheLTC3560requirestooperate.Table1showssome
typical surface mount inductors that work well in LTC3560
applications.
supplies. An excellent choice is the AVX TPS series of
surface mount tantalum. These are specially constructed
and tested for low ESR so they give the lowest ESR for a
given volume. Other capacitor types include Sanyo
POSCAP, KemetT510andT495series, andSprague593D
and 595D series. Consult the manufacturer for other
specific recommendations.
CIN and COUT Selection
Using Ceramic Input and Output Capacitors
In continuous mode, the source current of the top MOS-
FET is a square wave of duty cycle VOUT/VIN. To prevent
large voltage transients, a low ESR input capacitor sized
for the maximum RMS current must be used. The maxi-
mum RMS capacitor current is given by:
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3560’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
1/2
]
V
V − V
OUT
(
)
[
OUT IN
CIN required IRMS ≅ IOMAX
V
IN
However, care must be taken when ceramic capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at VIN, large enough
to damage the part.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the manufac-
turer if there is any question.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for COUT has been met, the RMS current rating
generally far exceeds the IRIPPLE(P-P) requirement. The
output ripple ∆VOUT is determined by:
Output Voltage Programming
⎛
⎝
1
⎞
The output voltage is set by a resistive divider according
to the following formula:
∆VOUT ≅ ∆I ESR +
⎜
⎟
⎠
L
8fCOUT
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ∆IL increases with input voltage.
R2
R1
⎛
⎝
⎞
VOUT = 0.6V 1+
(2)
⎜
⎟
⎠
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 2.
If tantalum capacitors are used, it is critical that the
capacitors are surge tested for use in switching power
3560f
9
LTC3560
APPLICATIO S I FOR ATIO
W U U
U
0.6V ≤ V
≤ 5.5V
OUT
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from VIN to ground. The resulting
dQ/dtisthecurrentoutofVINthatistypicallylargerthan
R2
V
FB
LTC3560
R1
GND
3560 F02
Figure 2. Setting the LTC3560 Output Voltage
Efficiency Considerations
the DC bias current. In continuous mode, IGATECHG
=
f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3560 circuits: VIN quiescent current and I2R
losses. The VIN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 3.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
beobtainedfromtheTypicalPerformanceCharateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
1
V
= 2.5V
OUT
Burst Mode OPERATION
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
0.1
0.01
Thermal Considerations
0.001
0.0001
In most applications the LTC3560 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3560 is running at high ambient
temperature with low supply voltage and high duty
cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
V
V
V
= 3.6V
= 4.2V
= 5.5V
IN
IN
IN
0.1
1
10
100
1000
LOAD CURRENT (mA)
3560 F03
Figure 3. Power Lost vs Load Current
3560f
10
LTC3560
W U U
APPLICATIO S I FOR ATIO
U
both power switches will be turned off and the SW node
value.DuringthisrecoverytimeVOUTcanbemonitoredfor
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
will become high impedance.
To avoid the LTC3560 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
PC Board Layout Checklist
As an example, consider the LTC3560 in dropout at an
input voltage of 2.7V, a load current of 800mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the RDS(ON) of the
P-channel switch at 70°C is approximately 0.31Ω. There-
fore, power dissipated by the part is:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3560. These items are also illustrated graphically in
Figures 4 and 5. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the VIN trace should be kept short, direct and
wide.
PD = ILOAD2 • RDS(ON) = 198mW
For the SOT-23 package, the θJA is 250°C/W. Thus, the
2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of COUT and ground.
junction temperature of the regulator is:
TJ = 70°C + (0.198)(250) = 120°C
3. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
4. Keep the (–) plates of CIN and COUT as close as possible.
5. Keep the switching node, SW, away from the sensitive
VFB node.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then acts to return VOUT to its steady-state
Design Example
As a design example, assume the LTC3560 is used in a
single lithium-ion battery-powered cellular phone
application. The VIN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.8A but most of the time it will be in
3560f
11
LTC3560
W U U
U
APPLICATIO S I FOR ATIO
1
2
3
6
5
4
RUN SYNC/MODE
LTC3560
GND
V
FB
–
C
V
R2
R1
OUT
OUT
SW
V
IN
+
L1
C
FWD
C
IN
V
IN
3560 F04
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 4. LTC3560 Layout Diagram
VIA TO GND
R1
V
OUT
V
IN
VIA TO V
LTC3560
IN
VIA TO V
OUT
R2
PIN 1
L1
C
FWD
SW
C
OUT
C
IN
GND
3560 F05
Figure 5. LTC3560 Suggested Layout
standbymode, requiringonly2mA. Efficiencyatbothlow
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
CIN will require an RMS current rating of at least 0.4A ≅
ILOAD(MAX)/2 at temperature and COUT will require an ESR
of less than 0.1Ω. In most cases, a ceramic capacitor will
satisfy this requirement.
For the feedback resistors, choose R1 = 309k. R2 can
then be calculated from equation (2) to be:
1
f ∆I
⎛
⎝
VOUT
V
IN
⎞
L =
VOUT 1−
⎜
⎟
⎠
(3)
( )(
)
L
V
⎛
⎞
OUT
Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 320mA and
f = 2.25MHz in equation (3) gives:
R2=
−1 R1= 978.5k; use 976k
⎜
⎝
⎟
⎠
0.6
Figure 6 shows the complete circuit along with its effi-
ciency curve.
2.5V
2.25MHz(320mA)
2.5V
4.2V
⎛
⎞
L =
1−
≅1.4µH
⎜
⎝
⎟
⎠
A 1.5µH inductor works well for this application. For best
efficiency choose a 960mA or greater inductor with less
than 0.2Ω series resistance.
3560f
12
LTC3560
W U U
APPLICATIO S I FOR ATIO
U
100
V
= 2.5V
OUT
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
PULSE
1.5µH**
V
IN
4
3
5
V
SKIPPING
OUT
2.5V
2.7V
V
SW
IN
10pF
C
*
TO 4.2V
IN
LTC3560
RUN
C
*
10µF
OUT
1
6
10µF
CER
CER
SYNC/MODE V
FB
976k
309k
GND
2
V
V
= 3.6V
IN
IN
= 4.2V
3560 F06a
0.1
1
10
100
1000
*TDK C2012X5R0J106M
**TDK VLF3010AT-1R5N1R2
OUTPUT CURRENT (mA)
3560 F06b
Figure 6a
Figure 6b
V
V
OUT
OUT
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
1A/DIV
1A/DIV
I
I
LOAD
LOAD
1A/DIV
1A/DIV
3560 F06d
3560 F06c
V
= 3.6V
20µs/DIV
V
= 3.6V
20µs/DIV
IN
IN
V
I
= 2.5V
V
= 2.5V
OUT
OUT
= 100mA TO 800mA
I
= 100mA TO 800mA
LOAD
LOAD
PULSE SKIPPING MODE
Burst Mode OPERATION
Figure 6c
Figure 6d
3560f
13
LTC3560
APPLICATIO S I FOR ATIO
W U U
U
100
90
80
70
60
50
1µH**
V
IN
4
3
5
V
OUT
1.2V
2.7V
V
SW
IN
C
*
10pF
IN
TO 4.2V
LTC3560
RUN
10µF
40
30
20
10
0
C
*
OUT
1
6
CER
10µF
CER
SYNC/MODE V
3MHz CLK
FB
V
IN
V
IN
V
IN
= 2.7V
= 3.6V
= 4.2V
301k
GND
2
301k
3560 F07a
1
10
100
1000
*TDK C2012X5R0J106M
**MURATA LQH32CN1R0M33
LOAD CURRENT (mA)
3560 F07b
Figure 7a
Figure 7b
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
500mA/DIV
500mA/DIV
I
LOAD
I
LOAD
500mA/DIV
500mA/DIV
3560 F07d
3560 F07c
V
= 3.6V
20µs/DIV
V
V
I
= 3.6V
20µs/DIV
IN
IN
OUT
V
I
= 1.2V
= 1.2V
OUT
= 0mA TO 500mA
= 300A TO 800mA
LOAD
LOAD
Figure 7c
Figure 7d
3560f
14
LTC3560
U
PACKAGE DESCRIPTIO
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3560f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3560
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
95% Efficiency, V : 2.5V to 5.5V, V
LTC3405/LTC3405A
300mA (I ), 1.5MHz, Synchronous Step-Down
= 0.8V, I = 20µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
DC/DC Converters
I
= <1µA, ThinSOT Package
SD
LTC3406/LTC3406B
LTC3407/LTC3407-2
LTC3409
600mA (I ), 1.5MHz, Synchronous Step-Down
96% Efficiency, V : 2.5V to 5.5V, V
I
= 0.6V, I = 20µA,
Q
OUT
IN
DC/DC Converters
= <1µA, ThinSOT Package
SD
Dual 600mA/800mA (I ), 1.5MHz/2.25MHz,
Synchronous Step-Down DC/DC Converters
95% Efficiency, V : 2.5V to 5.5V, V
I
= 0.6V, I = 40µA,
Q
OUT
IN
= <1µA, MS10E, DFN Packages
SD
600mA (I ), 1.7MHz/2.6MHz, Synchronous
96% Efficiency, V : 1.6V to 5.5V, V
I
= 0.6V, I = 65µA,
Q
OUT
IN
Step-Down DC/DC Converter
= <1µA, DFN Package
SD
LTC3410/LTC3410B
LTC3411
300mA (I ), 2.25MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
I
= 0.8V, I = 26µA,
Q
OUT
IN
DC/DC Converters
= <1µA, SC70 Package
SD
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
I
= 0.8V, I = 60µA,
Q
OUT
IN
DC/DC Converter
= <1µA, MS10, DFN Packages
SD
LTC3412
2.5A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
I
= 0.8V, I = 60µA,
OUT
IN
Q
DC/DC Converter
= <1µA, TSSOP-16E Package
SD
LTC3441/LTC3442
LTC3443
1.2A (I ), 2MHz, Synchronous Buck-Boost
95% Efficiency, V : 2.4V to 5.5V, V
: 2.4V to 5.25V,
OUT
IN
DC/DC Converters
I = 50µA, I = <1µA, DFN Package
Q SD
LTC3531/LTC3531-3
LTC3531-3.3
200mA (I ), 1.5MHz, Synchronous Buck-Boost
DC/DC Converters
95% Efficiency, V : 1.8V to 5.5V, V
: 2V to 5V, I = 16µA,
OUT
IN
OUT(MIN)
Q
I
= <1µA, ThinSOT, DFN Packages
SD
LTC3532
500mA (I ), 2MHz, Synchronous Buck-Boost
DC/DC Converter
95% Efficiency, V : 2.4V to 5.5V, V
I = 35µA, I = <1µA, MS10, DFN Packages
Q SD
: 2.4V to 5.25V,
OUT
IN
OUT(MIN)
LTC3548/LTC3548-1
LTC3548-2
Dual 400mA/800mA (I ), 2.25MHz, Synchronous
Step-Down DC/DC Converters
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
I
= <1µA, MS10E, DFN Packages
SD
LTC3561
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 240µA,
Q
OUT
IN
DC/DC Converter
I
= <1µA, DFN Package
SD
3560f
LT 1106 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
相关型号:
LTC3560IS6#PBF
LTC3560 - 2.25MHz, 800mA Synchronous Step-Down Regulator in ThinSOT; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC3560IS6#TRMPBF
LTC3560 - 2.25MHz, 800mA Synchronous Step-Down Regulator in ThinSOT; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC3560IS6#TRPBF
LTC3560 - 2.25MHz, 800mA Synchronous Step-Down Regulator in ThinSOT; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC3561AEDD#PBF
LTC3561A - 1A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC3561AEDD#TRPBF
LTC3561A - 1A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明