LTC3569EUD#TRPBF [Linear]
LTC3569 - Triple Buck Regulator with 1.2A and Two 600mA Outputs and Individual Programmable References; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C;型号: | LTC3569EUD#TRPBF |
厂家: | Linear |
描述: | LTC3569 - Triple Buck Regulator with 1.2A and Two 600mA Outputs and Individual Programmable References; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C 开关 |
文件: | 总26页 (文件大小:389K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3569
Triple Buck Regulator with
1.2A and Two 600mA Outputs and
Individual Programmable References
FeaTures
DescripTion
The LTC®3569 contains three monolithic, synchronous
step-downDC/DCconverters.Intendedformediumpower
applications, it operates over a 2.5V to 5.5V input voltage
range. The operating frequency is adjustable from 1MHz
to 3MHz, allowing the use of tiny, low cost capacitors and
inductors. The three output voltages are independently
programmable by toggling the EN pins up to 15 times,
loweringthe800mVFBreferencesby25mVpercycle. The
first buck regulator sources load currents up to 1200mA.
The other two buck regulators each provide 600mA.
n
Three Independent Current Mode Buck DC/DC
Regulators (1.2A and 2 × 600mA)
n
n
Single Pin Programmable V Servo Voltages from
FB
800mV Down to 425mV (in 25mV Steps)
Pull V High to Make Each 600mA Buck a Slave for
FB
Higher Current Operation
Pulse-Skipping or Burst Mode® Operation
Programmable Switching Frequency
(1MHz to 3MHz) or Fixed 2.25MHz
Synchronizable (1.2MHz to 3MHz)
n
n
n
n
n
n
n
V Range 2.5V to 5.5V
IN
The two 600mA buck regulators can also be configured
to operate as slave power stages, running in parallel with
another internal buck regulator to supply higher load
currents. When operating as parallel, slave output stages,
discrete external components are shared and available
output currents sum together.
All Regulators Internally Compensated
PGOOD Output Flag
Quiescent Current <100µA (All Regulators in Burst
Mode Operation)
Zero Shutdown Current
n
n
n
Overtemperature and Short-Circuit Protection
Tiny 3mm × 3mm, 3mm × 4mm 20-Lead QFN and
Thermally Enhanced TSSOP FE-16 Packages
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 6127815, 6304066,
6498466, 6580258, 6611131, 7170195.
applicaTions
n
Portable Applications with Multiple Supply Rails
n
General Purpose Step-Down DC/DC
n
Dynamic Voltage Scaling Applications
Typical applicaTion
V
IN
2.2µH*
2.5µH**
2.5µH**
OUT1 = 2.5V
SV
PV
SW1
Efficiency vs Load Current
IN
IN
22µF
1200mA
510k
240k
20pF
20pF
20pF
10µF
4.7µF
4.7µF
100
90
80
70
60
50
40
30
20
10
0
V
= 3V
IN
EN1
EN2
EN3
FB1
LTC3569
V
= 5V
IN
OUT2 = 1.8V
600mA
SW2
FB2
MODE
300k
240k
R
T
PGOOD
OUT3 = 1.2V
600mA
SW3
FB3
Burst Mode OPERATION
PULSE-SKIPPING
OUT1 = 2.5V
150k
* WURTH 7440430022
** WURTH 744031002
0.01
0.1
1
10
(mA)
100 1000 10000
300k
SGND PGND
I
LOAD
3569 TA01b
3569 TA01a
3569fe
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For more information www.linear.com/LTC3569
LTC3569
(Notes 1, 6)
absoluTe MaxiMuM raTings
SV Voltage .........................–0.3V to 6V (7V Transient)
Operating Junction Temperature Range
IN
PV Voltage.........................S – 0.3V to S + 0.3V
(Notes 6, 7)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Peak Reflow Temperature .....................................260°C
INX
VIN
VIN
ENx, MODE, PGOOD, SWx, FBx ..... –0.3V to S + 0.3V
VIN
R Voltage.................................................... –0.3V to 6V
T
PGOOD Current...................................................... 1mA
pin conFiguraTion
TOP VIEW
TOP VIEW
TOP VIEW
FB3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB1
FB2
20 19 18 17
SV
IN
20 19 18 17 16
PGND2
SW2
1
2
3
4
5
6
16 SW3
15 PGND3
14 EN1
SGND
R
T
SW3
PGND3
EN1
15
14
13
12
11
SW2
1
2
3
4
5
EN3
EN2
EN1
SW3
MODE
PV
IN2
17
PV
IN2
21
GND
PGOOD
21
PGOOD
PGOOD
MODE
13 EN2
EN2
MODE
PV
IN2
12 EN3
EN3
R
SW2
SW1
T
R
11 SGND
T
6
7
8
9 10
*PV
IN1
7
8
9 10
FE PACKAGE
UD PACKAGE
20-LEAD (3mm × 3mm) PLASTIC QFN
= 125°C, θ = 68°C/W
16-LEAD PLASTIC TSSOP
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
T
= 125°C, θ = 38°C/W
JA
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
*SHARES POWER WITH PV
JMAX
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
IN3
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3569EUD#PBF
LTC3569IUD#PBF
LTC3569EUDC#PBF
LTC3569IUDC#PBF
LTC3569EFE#PBF
LTC3569IFE#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTC3569EUD#TRPBF
LTC3569IUD#TRPBF
LTC3569EUDC#TRPBF
LTC3569IUDC#TRPBF
LTC3569EFE#TRPBF
LTC3569IFE#TRPBF
LDQF
20-Lead (3mm × 3mm) Plastic QFN
20-Lead (3mm × 3mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
20-Lead (3mm × 4mm) Plastic QFN
16-Lead Plastic TSSOP
LDQF
LFYW
LFYW
3569FE
3569FE
16-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3569fe
2
For more information www.linear.com/LTC3569
LTC3569
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted (Notes 2, 7).
SYMBOL
SV
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
l
Input Supply Voltage
2.5
IN
I
I
I
Input Current Pulse-Skipping Mode
EN1 = SV , EN2, EN3 = MODE = 0V,
OUT1
230
47
365
µA
VIN
IN
I
, = 0A, FB1 = 0.9V (Note 3)
Input Current Burst Mode Operation
EN1 = MODE = SV , EN2, EN3 = 0V,
82
225
36
1
µA
µA
µA
µA
IN
I
, = 0A, FB1 = 0.9V (Note 3)
OUT1
Additional Input Current per Buck,
Pulse Skipping
MODE = 0V, I
(Note 3)
, = 0A, FBx = 0.9V
OUTX
140
22
QX
Additional Input Current per Buck,
Burst Mode Operation
MODE = SV , I
, = 0A,
IN OUTX
FBx = 0.9V (Note 3)
Quiescent Current in Shutdown Mode
EN1, EN2, EN3 = 0V
0.1
QSHDN
PK1
V
= V
= V
= 0V
SW3
SW1
SW2
I
I
Peak Inductor Current SW1
Peak Inductor Current SW2, SW3
Maximum Feedback Voltage
Feedback Reference Step Size
Minimum Feedback Voltage
Feedback Programming Range
Feedback Pin Input Current
Switch Pin Leakage Current
1.8
2.0
1.0
2.5
1.3
A
A
, I
0.780
0.784
PK2 PK3
l
l
l
V
V
V
V
0.8
0.816
V
FBX(MAX)
FBX(STEP)
FBX(MIN)
PROGFBX
FBX
Each Toggle on ENx
ENx Toggle 15 Times
25
mV
V
0.405
0.425
0.425
0.44
0.8
0.2
1
V
I
I
V
= 0.8V
µA
µA
FB
V
V
= 1.8V, V
SWX
= 0.9V
FBX
= SV ,
ENX IN
LKSWX
D
R
R
R
R
Maximum Duty Cycle
FBx = 0V
100
%
mΩ
mΩ
mΩ
mΩ
kΩ
X
R
DSON
R
DSON
R
DSON
R
DSON
of PSW for SW1
I
I
I
I
= 100mA (Note 5)
= –100mA (Note 5)
195
180
265
250
2.3
P1
N1
SW1
SW1
of NSW for SW1
, R
of PSW for SW2, SW3
of NSW for SW2, SW3
, I
= 100mA (Note 5)
, I = –100mA (Note 5)
SW2 SW3
P2 P3
SW2 SW3
, R
N2 N3
RSWx_PD
SWx Pull-Down in Shutdown
ENx = 0V, V
(FBx < SV
= 1.2V,
SWX
IN
)
Reference Voltage Line Regulation
Output Voltage Load Regulation
Soft-Start Reference Ramp Rate
Enable Turn-On Delay
SV = 2.5V to 5.5V
0.04
0.5
0.2
%/V
%
∆V
IN
LINEREG
Pulse-Skipping Mode (Note 4)
∆V
LOADREG
t
t
0.75
125
V/ms
µs
SS
EN
From Last ENx Rise to Begin of
Soft-Start Ramp
240
t
t
I
I
Enable Turn-Off Delay
Enable Pulse Width
Enable Leakage Current
Mode Leakage Current
Input Low Voltage
From ENx Fall to Shutdown
170
330
55
µs
µs
µA
µA
V
OFF
0.06
PW
V
V
= 3.6V
0.02
0.02
ENX
MODE
ENX
= 3.6V
MODE
V
V
MODE, ENx
MODE, ENx
0.4
IL
Input High Voltage
1.2
V
IH
T
Pulse Width Applied to MODE Pin for
Synchronizing
100
ns
MODEPW
PGOOD
Power Good Threshold
V
V
Ramping Up
Ramping Down
–8
–12
%
%
FBX
FBX
T
PGOOD Delay
Turn-On
Turn-Off
8
2
µs
µs
PGOOD
3569fe
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For more information www.linear.com/LTC3569
LTC3569
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted (Notes 2, 7).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
525
2.5
UNITS
Ω
R
PGOOD Pull-Down On-Resistance
Undervoltage Lockout
Fixed Oscillator Frequency
V
< 0.4V
FBX
380
PGOOD
l
l
l
l
UVLO
V
f
f
f
f
V
= SV
IN
1.9
3.0
2.25
2.8
MHz
MHz
MHz
MHz
MHz
OSC
RT
Maximum Programmable Oscillator Frequency R = 100k
CLK(MAX)
CLK(MIN)
SYNC
T
Minimum Programmable Oscillator Frequency R = 453k
1.0
3
T
Sync Frequency
V
= SV
RT IN
R = 453k
T
1.2
Note 6: This IC includes overtemperature protection that is intended
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
to protect the device during momentary overload conditions. Junction
temperature exceeds 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: Current into a pin is positive and current out of a pin is negative.
Note 7: The LTC3569 is tested under pulsed load conditions such that
All voltages referenced to SGND.
T ≈ T . The LTC3569E is guaranteed to meet specified performance from
J
A
Note 3: Dynamic supply current is higher due to the internal gate charge
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design characterization and correlation
with statistical process controls. The LTC3569I is guaranteed to meet
specified performance over the full –40°C to 125°C operating junction
temperature range.
being delivered at the switching frequency.
Note 4: Specification is guaranteed by design and not 100% tested in
production.
Note 5: Switch on-resistance verified by correlation to wafer level
measurements.
Typical perForMance characTerisTics
TA = 25°C, unless otherwise noted.
Efficiency vs Load Current
OUT2 = 1.8V
Efficiency vs Load Current
OUT3 = 1.2V
ISVIN vs Temperature
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 3V
IN
V
= 3V
IN
BUCK1 ONLY PULSE-SKIPPING V = 3.5V
IN
V
= 5V
IN
SLOPE ≅ 185nA/°C
V
= 5V
IN
BUCK1 ONLY Burst Mode OPERATION
V
= 3.5V
IN
Burst Mode OPERATION
PULSE-SKIPPING
Burst Mode OPERATION
PULSE-SKIPPING
SLOPE ≅ 132nA/°C
NO LOAD
100 150
0
–50
0
50
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
TEMPERATURE (°C)
I
(mA)
I
(mA)
LOAD
LOAD
3569 G01
3569 G02
3569 G03
3569fe
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For more information www.linear.com/LTC3569
LTC3569
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Efficiency vs VSUPPLY
OUT1 = 1.8V
Efficiency vs VSUPPLY
OUT2 = 1.2V
Efficiency vs VSUPPLY
OUT3 = 1.5V
95
90
85
80
75
70
65
95
90
85
80
75
70
65
95
90
85
80
75
70
65
BUCK1 ONLY
BUCK2 ONLY
BUCK3 ONLY
I
I
I
I
= 270mA
= 220mA
= 170mA
= 120mA
I
I
I
I
= 210mA
= 170mA
= 110mA
= 70mA
I
I
I
I
= 210mA
= 170mA
= 110mA
= 70mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
V
(V)
V
(V)
V
(V)
SUPPLY
SUPPLY
SUPPLY
3569 G04
3569 G05
3569 G06
Oscillator Frequency
vs Temperature
RDS(ON) SW1
RDS(ON) SW2 and SW3
vs VSUPPLY and Temperature
vs VSUPPLY and Temperature
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
2.40
2.30
2.20
2.10
2.00
0.35
0.30
0.25
0.20
0.15
0.10
NSW2 & 3
PSW3 & 3
NSW1
PSW1
V
= 5.5V
IN
100°C
25°C
100°C
25°C
V
= 3.5V
IN
V
= 2.5V
IN
–50°C
–50°C
V
= SV
IN
RT
2
3
4
5
6
–50
0
50
100
150
2
3
4
5
6
V
(V)
TEMPERATURE (°C)
V
(V)
SUPPLY
SUPPLY
3569 G09
3569 G07
3569 G08
ISVIN
VFB vs Temperature
ISVIN vs VSUPPLY Pulse-Skipping
vs VSUPPLY Burst Mode Operation
120
100
80
60
40
20
0
0.3
0.2
700
600
500
400
300
200
100
0
V
SET TO MAX
REF
ALL 3
ALL 3
0.1
2 BUCKS ENABLED
2 BUCKS ENABLED
0.0
1 BUCK ENABLED
1 BUCK ENABLED
–0.1
–0.2
–0.3
V
V
V
FB1
FB2
FB3
NO LOAD
NO LOAD
2
3
4
5
6
–50
0
50
100
150
2
3
4
5
6
V
(V)
TEMPERATURE (°C)
V
(V)
SUPPLY
SUPPLY
3569 G12
3569 G10
3569 G11
3569fe
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LTC3569
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Buck1 Load Regulation
Buck2 Load Regulation
0.6
0.4
0.6
0.4
BUCK1, 3 OFF
BUCK2, 3 OFF
V
= 5.5V
V
= 5.5V
IN
IN
V
V
= 4.5V
V
= 4.5V
0.2
IN
0.2
IN
PULSE-SKIPPING
PULSE-SKIPPING
0.0
0.0
–0.2
–0.4
–0.6
V
= 2.5V
IN
–0.2
–0.4
–0.6
V
= 2.5V
V
= 3.5V
IN
= 3.5V
IN
IN
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.2
0.4
0.6
0.8
1
1.2
I
(A)
I
(A)
LOAD
LOAD
3569 G14
3569 G13
Line Regulation
Buck3 Load Regulation
0.6
0.4
0.15
0.10
BUCK1, 2 OFF
EACH BUCK TESTED INDIVIDUALLY
BUCK2 = 1.2V
BUCK1 = 1.8V
0.2
0.05
0.0
0.00
PULSE-SKIPPING
BUCK3 = 1.5V
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
PULSE-SKIPPING MODE
I
I
= 200mA
= 150mA
LOAD1
LOAD2, 3
V
= 1.5V
OUT3
0
0.1
0.2
0.3
0.4
0.5
0.6
2
3
4
5
6
I
(A)
V
(V)
SUPPLY
LOAD
3569 G15
3569 G16
FB Pin Leakage
IQSD vs Temperature
1000
100
10
10000
1000
100
10
V
= 5.5V
V
= 5.5V
IN
IN
SLAVE
DETECTOR = 250nA
I
1
FB2,3
I
0.1
FB1
1
0.01
0.001
0.1
0
1
2
3
4
5
6
–50
0
50
100
150
V
(V)
TEMPERATURE (°C)
FB
3569 G17
3569 G18
3569fe
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LTC3569
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Load Step Cross Talk, Pulse-Skipping,
Load Step Cross Talk, Pulse-Skipping,
VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2
,
VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2
,
CH3 = VOUT3, CH4 = ILOAD1
CH3 = VOUT3, CH4 = ILOAD2
CH1
P-P
20mV/DIV
100mV/DIV
CH1
P-P
9.6mV
310mV
CH2
100mV/DIV
CH2
246mV
P-P
16.8mV
20mV/DIV
20mV/DIV
P-P
CH3
CH3
20mV/DIV
12mV
8mV
P-P
P-P
CH4
1.2A
CH4
600mA
500mA/DIV
500mA/DIV
3569 G19
3569 G20
20µs/DIV
20µs/DIV
Load Step Cross Talk, Pulse-Skipping,
VIN = 3.6V, CH1 = VOUT1, CH2 = VOUT2
,
ISW Leakage vs VSUPPLY Buck 1
CH3 = VOUT3, CH4 = ILOAD3
10000
1000
100
10
V
V
= 3.6V
= 0.9V
IN
FB
CH1
P-P
20mV/DIV
20mV/DIV
11.6mV
BUCK2, BUCK3 OFF
CH2
11.2mV
P-P
85°C
CH3
100mV/DIV
500mA/DIV
266mV
P-P
1
25°C
CH4
600mA
0.1
–50°C
3569 G21
0.01
0.001
20µs/DIV
0
1
2
3
3.6
V
(V)
SW
3569 G22
Soft-Start Into Heavy Load, PS, VIN
=
Soft-Start Into Light Load, PS, VIN =
3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3
= VOUT3, CH4 = IIN, R3 = PGOOD
3.6V, CH1 = VOUT1, CH2 = VOUT2, CH3
= VOUT3, CH4 = IIN, R2 = PGOOD
CH1 500mV/DIV
CH1 500mV/DIV
CH3 500mV/DIV
CH2 500mV/DIV
CH3 500mV/DIV
CH2 500mV/DIV
R2
2V/DIV
R3
2V/DIV
CH4
500mA/DIV
CH4
50mA/DIV
3569 G23
3569 G24
400µs/DIV
400µs/DIV
3569fe
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For more information www.linear.com/LTC3569
LTC3569
pin FuncTions
EN1: Enable Pin for Buck 1. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
PGND2: Main Power Ground Pin for Buck 2. Connect to
the (–) terminal of the output capacitor for Buck2, and (–)
terminalofC .Decouplingcapacitorsshouldbesummed
IN2
where power supply pins are shared.
EN2: Enable Pin for Buck 2. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
PGND3: Main Power Ground Pin for Buck 3. Connect to
the (–) terminal of the output capacitor for Buck3, and (–)
terminalofC .Decouplingcapacitorsshouldbesummed
IN3
EN3: Enable Pin for Buck 3. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
where power supply pins are shared.
PGOOD: The Power Good Pin. This open-drain output is
released when an enabled output has risen to within 8% of
theregulationvoltage.Whenmultipleoutputsareenabled,
PGOOD is the logical AND of each internal PGOOD.
FB1: Receives the feedback voltage from the external
resistive divider across the output of Buck 1. Nominal
voltage for this pin is programmed with the EN1 pin from
800mV down to 425mV.
PV : Main Supply Pin for Buck 1. Decouple to PGND1
IN1
with a low ESR 4.7µF capacitor, C . Decoupling ca-
IN1
FB2: Receives the feedback voltage from the external
resistive divider across the output of Buck 2. Nominal
voltage for this pin is programmed with the EN2 pin from
800mV down to 425mV. When pulled to SV , Buck 2 is
put into slave mode, following Buck 1.
pacitors should be summed where power supply pins
are shared.
PV : Main Supply Pin for Buck 2. Decouple to PGND2
IN
IN2
with a low ESR 4.7µF capacitor, C . Decoupling ca-
IN2
pacitors should be summed where power supply pins
FB3: Receives the feedback voltage from the external
resistive divider across the output of Buck 3. Nominal
voltage for this pin is programmed with the EN3 pin from
800mV down to 425mV. When pulled to SV , Buck 3 is
put into slave mode, following Buck 2.
are shared.
PV : Main Supply Pin for Buck 3. Decouple to PGND3
IN3
withalowESR4.7µFcapacitor,C .Decouplingcapacitors
IN
IN3
should be summed where power supply pins are shared.
For 16-lead plastic TSSOP FE package, PV and PV
IN1
IN3
GND (Exposed Pad): The exposed pad must be connected
to PCB ground for rated thermal performance and for
electrical connection in the TSSOP package.
share pin 8.
R : Timing Resistor Pin. The free-running oscillator
T
frequency is programmed by connecting a resistor from
MODE: Combination Mode Selection and Oscillator Syn-
this pin to ground. Tie to SV to get a fixed 2.25MHz
IN
chronization Pin. This pin controls the operating mode
operating frequency.
of the device. When tied to SV , Burst Mode operation
IN
is selected. When tied to SGND, pulse-skipping mode is
selected. The internal clock frequency synchronizes to an
external oscillator applied to this pin. When synchronizing
to an external clock, drive this pin with a logic-level signal
with high and low pulse widths of at least 100ns. When
synchronizing to an external clock, pulse-skipping mode
is automatically selected.
SGND: Main Ground Pin. Decouple to SV .
IN
SV : Main Supply Pin. Decouple to SGND with a low ESR
IN
1µF capacitor.
SW1: Buck 1 Switch. Connect to the Inductor for Buck 1.
This pin swings from PV to PGND1.
IN1
SW2: Buck 2 Switch. Connect to the Inductor for Buck 2.
This pin swings from PV to PGND2.
PGND1: Main Power Ground Pin for Buck 1. Connect to
IN2
the (–) terminal of the output capacitor for Buck1, and (–)
SW3: Buck 3 Switch. Connect to the Inductor for Buck 3.
terminalofC .Decouplingcapacitorsshouldbesummed
IN1
This pin swings from PV to PGND3.
IN3
where power supply pins are shared.
3569fe
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LTC3569
block DiagraM
SV
IN
PV
IN1
EN1
ON1
P-CHANNEL
N-CHANNEL
PG1
REF1
+
–
SW1
DAC1
EA1
EA2
EA3
BUCK 1.2A
FB1
NG1
PGND1
OFF
PGOOD1
PON1
NOFF1
PV
IN2
EN2
FB2
ON2
P-CHANNEL
N-CHANNEL
PG2
REF2
+
–
SW2
DAC2
BUCK 0.6A
NG2
OFF
PGND2
BG
PGOOD2
PON2
NOFF2
PV
IN3
EN3
ON3
P-CHANNEL
N-CHANNEL
PG3
REF3
+
–
DAC3
SW3
BUCK 0.6A
OFF
FB3
NG3
CLK
RPGOOD
PGND3
ISLOPE1
OSC ISLOPE2
ISLOPE3
MODE/SYNC
PGOOD3
PGOOD
800mV
PGOOD1
PGOOD2
PGOOD3
PGOODB
R
T
R
T
GND
3569BD
Figure 1. Detailed Block Diagram
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Introduction
Each of the buck regulators supports 100% duty cycle
operation (low dropout mode) when their input voltage
drops very close to their output voltage. The switching
regulators also include soft-start to limit inrush current
when powering on, and short-circuit current protection.
The LTC3569 contains three constant-frequency, current
mode buck DC/DC regulators. Both the P-channel and
synchronous rectifier (N-channel) switches are internal
to each buck. The operating frequency is determined by
the value of the R resistor, or is fixed to 2.25MHz by pull-
T
Main Control Loop
ing the R pin to SV , or is synchronized to an external
T
IN
During normal operation, the top power switch (P-chan-
nel MOSFET) is turned on at the beginning of a clock
cycle. The P-channel current ramps up as the inductor
charges. The peak inductor current is controlled by the
internally compensated error amplifier output, ITH. The
currentcomparator(PCOMP)turnsofftheP-channeland
turns on the N-channel synchronous rectifier when the
inductor current reaches the ITH level minus the offset of
the slope compensation ramp. The energy stored in the
inductor continues to flow through the bottom switch
(N-channel) and into the load until either the inductor
current approaches zero, or the next clock cycle begins.
If the inductor current approaches zero the N comparator
oscillator tied to the MODE pin. Users may select pulse-
skippingorBurstModeoperationtotradeoffoutputripple
forefficiency.Independentprogrammablereferencelevels
allow the LTC3569 to suit a variety of applications.
The LTC3569 offers different power levels, a single 1.2A
buck as well as two 600mA bucks. These three bucks
may be configured in different parallel configurations,
for versatile high current operation. The power stage of
buck 2 can be configured as a slave to buck 1, by pulling
FB2 to SV . The power stage of buck 3, can be configured
IN
to be a slave to buck 2, by pulling the FB3 pin to SV . To
IN
enable the slave power stage, pull the respective EN pin
high. However if the master is disabled, the slave power
stage is Hi-Z.
BURST
CLAMP
MODE
ON
SLOPE
+
–
+
–
V
REF
P COMP
I
LIM
SOFT
START
P
VIN
SLAVE
SD
CLK
I
LIM
P-CHANNEL
I
S
Q
NOR
TH
SWITCHING
LOGIC,
BLANKING,
EA
SW
P-LATCH
V
FB
NAND
GATE
R
ANTI SHOOT-THRU
S
VIN
SLAVE
SLAVE
N-CHANNEL
P
ON
FROM MASTER
SLEEP
N
OFF
P
GND
PGOOD
ON
SLAVE
V
REF
NOR
N
COMP
–
+
3569 F02
Figure 2. Buck Block Diagram
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LTC3569
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(NCOMP) signals to turn-off the N-channel switch, so
that is does not discharge the output capacitor. When a
rising clock edge occurs, the P-channel switch turns on
repeating the cycle.
Pulse-skipping mode is intended for lower output voltage
ripple at light load currents. Here, the peak P-channel cur-
rent is compared with the value determined by the error
amplifier output. Then, the P-channel is turned off and the
N-channel switch is turned on until either the next cycle
beginsortheN-channelcomparator(NCOMP)turnsoffthe
N-channel switch. If the NCOMP trips, the SW node goes
Hi-Zandthebuckoperatesdiscontinuously.Inpulse-skip-
ping mode the LTC3569 continues to switch at a constant
frequency down to very low currents; where it eventually
begins skipping pulses. Because the LTC3569 remains
active at lighter load currents in pulse-skipping mode, the
efficiencyperformanceistradedoffagainstoutputvoltage
ripple and electromagnetic interference (EMI).
Thepeakinductorcurrentiscontrolledbytheerroramplifier
(EA)andisinfluencedbytheslopecompensation.Theerror
amplifier compares the FB pin voltage to the programmed
internal reference (REF). When the load current increases,
the FB voltage decreases. When the FB voltage falls below
the reference voltage, the error amplifier output rises
to increase the peak inductor current until the average
inductor current matches the new load current. With the
inductor current equal to the load current, the duty cycle
will stabilize to a value equal to V /V .
OUT IN
Dropout Operation
Low Current Operation
When the input supply voltage decreases towards the out-
putvoltagethedutycycleautomaticallyincreasesto100%;
which is the dropout condition. In dropout, the P-channel
switch is turned on continuously with the output voltage
being equal to the input voltage minus the voltage drop
across the internal P-channel switch and the inductor.
At light loads, the FB voltage may rise above the refer-
ence voltage. If this occurs the error amplifier signals
the control loop to go to sleep, and the P-channel turns
off immediately. The inductor current then discharges
through the N-channel switch until the inductor current
approaches zero; whereupon the SW goes Hi-Z, and the
output capacitor supplies power to the load. When the
load discharges the output capacitor the feedback voltage
falls and the error amp wakes up the buck, restarting the
main control loop as if a clock cycle has just begun. This
sleep cycle helps minimize the switching losses which are
dominatedbythegatechargelossesofthepowerdevices.
Twooperatingmodesareavailabletocontroltheoperation
of the LTC3569 at low currents, Burst Mode operation and
pulse-skipping mode.
Low Supply Operation
TheLTC3569incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below 2.5V to prevent unstable operation. The UVLO
function does not reset the reference voltage DAC. (See
Programming the Reference.)
Slave Power Stage
WhentheFBpinofoneofthetwo600mAregulatorsistied
Select Burst Mode operation to optimize efficiency at low
outputcurrents. InBurstModeoperationtheinductorcur-
rent reaches a fixed current before the P-channel switch
compares inductor current against the value determined
to SV that regulator’s control circuits are disabled and
IN
the regulator’s switch pin is configured to follow a master
regulator; either the first 600mA regulator (regulator 2) or
the 1.2A regulator (regulator 1). In this way, two regula-
tor power stages are ganged together (e.g., switch pins
shorted together to a single inductor) to support higher
current levels. This permits three permutations of power
levels: three independent regulators at 1.2A, 600mA and
by I . This burst clamp causes the output voltage to rise
TH
above the regulation voltage and forces a longer sleep
cycle. This greatly reduces switching losses and aver-
age quiescent current at light loads, at the cost of higher
ripple voltage.
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PGOOD Pin
600mA; two independent regulators at 1.2A each, where
regulator 3 is placed in slave mode to regulator 2 and
regulator 1 operates independently; or one 1.8A regula-
tor and a second 600mA regulator, where regulator 2 is
placed in slave mode to regulator 1, and regulator 3 is
independent.
ThePGOODpinisanopen-drainoutputthatindicateswhen
all of the enabled regulator’s output voltages have risen to
within 92% of their programmed levels. The three bucks
each have separate PGOOD comparators with hysteresis.
The PGOOD flag drops if one of the enabled regulator’s
output voltages drops below 88% of the programmed
level. Output voltage transient drops of duration less than
2µs are blanked and not reported at the PGOOD pin. The
PGOOD pin open-drain driver is disabled if PGOOD is
Whenregulator2isoperatingasaslave, pullpinsEN2and
FB2 up to SV to enable the slave power stage. Likewise
IN
when regulator 3 is operated as a slave, pull pins EN3 and
FB3 up to SV to enable the slave power stage. If the EN
IN
pulled up to a voltage above SV .
pin of the slave device is pulled low, then the slave power
IN
stage is disabled and that SW pin is Hi-Z.
Programming the Reference
Shutdown and Soft-Start
The full-scale reference voltage for each regulator is 0.8V.
The reference can be programmed in –25mV steps by
toggling the respective EN pin up to 15 times for a range
from800mVdownto425mV.ThisisillustratedinFigure3.
The EN pins require a minimum pulse width of 60ns, but
no more than 55µs, as the toggle counter times out after
ThemaincontrolloopisshutdownafterpullingtheENxpin
to ground and waiting for the t delay period to expire.
When in shutdown, but not in slave mode, a 2k resistor
to PGND discharges the output capacitor. When all three
regulators are turned off the LTC3569 enters low power
shutdown where all functions are disabled, and quiescent
current drops to below 1µA.
OFF
the EN pin remains high for around 125µs (t ). After the
EN
t
timeout, the counter state is latched and sent on to
EN
the reference voltage DAC, and the counter is reset to full
scale. If the EN pin begins to toggle again, the counter
decrements on each falling edge. If the EN pin is toggled
more than 15 times, the counter remains fixed at the
lowest DAC reference level. To reprogram the DAC to full
A soft-start is enabled when any buck is initially turned
on, or following a thermal shutdown. Soft-start ramps the
programmedinternalreferenceatarateofabout0.75V/ms.
The output voltage follows the internal reference voltage
ramp throughout the soft-start period. While in soft-start,
the LTC3569 is forced into pulse-skipping mode until the
PGOOD flag indicates that the output voltage is nearing
the programmed regulation voltage. Once the PGOOD flag
has tripped, if the MODE pin is high the regulator then
operates in Burst Mode, otherwise the LTC3569 continues
to operate in pulse-skipping mode.
scale, hold the EN pin low for 170µs (t ), turning off the
OFF
buck, and then pull EN high once. The buck then initiates
a soft-start as V ramps up to the full-scale value.
REF
If the DAC is reprogrammed without forcing a shutdown,
the soft-start ramp is not engaged and the reference
steps to the new value. Avoid using the full-scale 0.8V
reference in programmable output voltage applications
if the application cannot tolerate the transition through
shutdownandsoft-startwhenswitchingbetweendifferent
reference levels.
Thermal Protection
If the die junction temperature exceeds 150°C, a thermal
shutdown circuit disables all functions in the LTC3569,
and the SW nodes will be pulled low with 2k pull-downs.
After the die temperature drops below 125°C the LTC3569
restartswithoutchangingtheprogrammedreferencevolt-
age DAC; but a soft-start is initiated upon exiting thermal
shutdown.
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t
170µs (TYP)
OFF
t
EN
t
EN
60ns < WIDTH < 55µs
EN
t
= 125µs (TYP)
EN
COUNTER INCREMENTS ON COUNTER RESETS TO FULL-SCALE IF EN COUNTER RESETS TO FULL-SCALE IF EN
FALLING EDGES OF EN
STAYS HIGH FOR MORE THAN 125µs
STAYS LOW FOR MORE THAN 170µs
V
REF
15
14
15 15
15
14
14
COUNTER
(15:0)
13
13
12
11
10
9
DAC LOADS COUNTER VALUE IF
EN STAYS HIGH FOR MORE THAN 125µs
13
15
15
DAC
(15:0)
9
COUNT15 = 800mV
COUNT13 = 750mV
COUNT9
= 650mV
SOFT-START
0mV
0mV
V
REF
SOFT-START
SHUTDOWN
BUCK ON
BUCK ON
BUCK OFF
BUCK OFF
3569 TD
Figure 3. VREF and ENx Timing Diagram
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applicaTions inForMaTion
Operating Frequency
Minimum On-Time And Duty-Cycle
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allowsforsmallerinductorandcapacitorvalues.Operation
at lower frequencies improves the efficiency by reducing
internal gate charge losses but requires larger inductance
values and/or capacitance to maintain low output ripple
voltage.
The maximum usable operating frequency is limited by
the minimum on-time and the required duty cycle. In buck
regulators, the duty cycle (DC) is the ratio of output to
input voltage: DC = V /V = t /(t + t ). At low duty
OUT IN ON OFF ON
cycles, the SW node is high for a small fraction of the total
clock period. As this time period approaches the speed
of the gate drive circuits and the comparators internal to
the LTC3569, the dynamic loop response suffers. To avoid
minimum on-time issues it is recommended to adjust the
operating frequency down so as to keep the minimum
duty cycle pulse width above 80ns. Thus, the maximum
operating frequency should be selected such that the duty
cycle does not demand SW pulse widths below the mini-
Theoperatingfrequency,f ,oftheLTC3569isdetermined
CLK
by an external resistor that is connected between the R
T
pin and ground. The value of the resistor sets the ramp
current that charges and discharges an internal timing
capacitor within the oscillator. The relationship between
oscillator frequency and R is calculated by the following
T
mum on-time. The maximum clock frequency, f
,
CLKMAX
equation:
is selected from either the internal fixed frequency clock,
–1.027
R = (5.1855 • 10ˆ11) • (f
)
CLK
or a timing resistor at the R pin, or synchronizing clock
applied to the MODE pin. The minimum on-time require-
T
T
Or may be selected following the graph in Figure 4.
ment is met by adhering to the following formula:
4.1
f
= (V /V
)/t
V
A
= 3.6V
IN
CLKMAX
OUT IN(MAX) MIN-ON
T
= 25°C
3.6
3.1
2.6
2.1
1.6
1.1
0.6
0.1
For example, if V
is 0.8V and V ranges up to 5.5V,
IN
OUT
the maximum clock frequency is limited to no more than
1.8MHz.
Mode Selection And Frequency Synchronization
The MODE pin is a multi-purpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to SV enables Burst Mode operation, which
IN
0
0.1
0.2
0.3
0.4
0.5
0.6
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse-skipping operation is selected which
provides the lowest output voltage and current ripple at
the cost of low current efficiency.
R
T
(MΩ)
3569 F04
Figure 4. fCLK vs RT
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of R .
T
Synchronize the LTC3569 to an external clock signal by
tying a clock source to the MODE pin. Select the R pin
If the R pin is tied to SV the oscillation frequency is
T
T
IN
resistance so that the internal oscillator frequency is set
to 20% lower than the applied external clock frequency to
ensure adequate slope compensation, since slope com-
pensation is derived from the internal oscillator. During
synchronization, the mode is set to pulse skipping.
fixed at 2.25MHz.
Keep excess capacitance and noise (e.g., from the SW
pins) away from the R pin. It is recommended to remove
T
the GND plane beneath the R pin trace, and to route the
T
R pin PCB trace away from the SW pins.
T
TheexternalclocksourceappliedtotheMODEpinrequires
minimum low and high pulse widths of about 100ns.
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Setting the Output Voltages
A reasonable starting point for setting ripple current is
∆I = 0.3•I
, where I
is the maximum
L
OUT(MAX)
OUT(MAX)
The LTC3569 develops independent internal reference
voltages for each of the feedback pins. These reference
voltages are programmed from 0.8V down to 0.425V in
–25mV increments by toggling the appropriate EN pin.
The output voltage is set by a resistive divider according
to the following formula (refer to Figure 9 for resistor
designations):
load current. The largest ripple current ∆I occurs at the
L
maximuminputvoltage.Toguaranteethattheripplecurrent
stays below a specified maximum, choose the inductor
value according to the following equation:
L = V /(f •∆I )•(1 – V /V )
OUT IN(MAX)
OUT CLK
L
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values increase the burst frequency and
reduces efficiency.
V
OUT1
= V
(1 + R1/R2),
REF1
where V
is programmed by toggling the EN1 pin.
REF1
V
OUT2
= V
(1 + R3/R4),
REF2
where V
is programmed by toggling the EN2 pin.
REF2
V
OUT3
= V
(1 + R5/R6),
REF3
where V
is programmed by toggling the EN3 pin.
REF3
Choose an inductor with a DC current rating at least 1.5
times larger than the maximum load current to ensure
that the inductor core does not saturate during normal
operation.Ifanoutputshort-circuitisapossiblecondition,
select an inductor that is rated to handle the maximum
peak current specified for the regulators. To maximize
efficiency, choose an inductor with a low DC resistance;
Keeping the current small (<5µA) in these resistors
maximizes efficiency, but making the current too small
may allow stray capacitance to cause noise problems and
reduce the phase margin of the error amp loop.
To improve the frequency response, use a feedforward
capacitor, C , on the order of 20pF across the leading
F
feedback resistor (R1, R3, and R5). Take care to route
each FB line away from noise sources, such as the induc-
tor or the SW line. Remove the ground plane from below
the FB PCB routes to limit stray capacitance to GND on
these pins.
2
as power loss in the inductor is due to I R losses. Where
2
I is the square of the average output current and R is the
ESR of the inductor.
Table 1. Low Profile Inductors
VENDOR/
PART NUMBER
VALUE
(µH)
IDC
(APPROX.)
RDC
(Ω)
HEIGHT
(mm)
Inductor Selection
Wurth
7440430022
744031002
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
2.2
2.5
2.50
1.45
0.023
0.050
2.80
1.65
MuRata
LQH55PN1R2
LQH55PN2R2
current. The inductor ripple current ∆I decreases with
L
1.2
2.2
2.60
2.10
0.021
0.031
1.85
1.85
higher inductance and increases with higher V or V
:
OUT
IN
Toko, DEV518C
1124BS-1R8N
1124BS-2R4M
∆I = V /(f •L )•(1–V /V )
L
OUT CLK
OUT IN
1.8
2.4
2.70
2.30
0.047
0.054
1.80
1.80
Accepting larger values of ∆I allows the use of low
L
inductances, but results in higher output voltage ripple,
EPCOS
B824691152M000
B824691221M000
1.5
2.2
1.70
1.55
0.046
0.065
1.20
1.20
greater core losses, and lower output current capability.
3569fe
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Input/Output Capacitor Selection
Thesecondfactorthatinfluencestheselectionoftheoutput
capacitoristheeffectofoutputcapacitorESRontheoutput
voltage ripple as a result of the inductor ripple current.
Use low equivalent series resistance (ESR) ceramic
capacitors at the switching regulator outputs as well as
at the input supply pins. It is recommended to use only
X5R or X7R ceramic capacitors because they retain their
capacitance over wider voltage and temperature ranges
than other ceramic types.
The amplitude of voltage ripple, ∆V , is determined by:
OUT
∆V
≈ ∆I (ESR + 1/(8•f •C ))
L CLK OUT
OUT
Where ∆I is the ripple current in the inductor, and ESR
L
is the equivalent series resistance of the output capacitor.
Using ceramic capacitors, this voltage ripple is usually
negligible.
For good transient response and stability the input and
output capacitors should retain at least 50% of rated ca-
pacitance value over temperature and bias voltage. Check
with capacitor data sheets to ensure that bias voltage and
temperature derating is taken into account when selecting
capacitors.
Table 2. Capacitors
VENDOR/PART NUMBER
Murata: GRM21BR71A106KE51
Murata: 06036D475KAT
VALUE (µF)
10
4.7
In continuous mode, the input supply current is a square
TDK: C1608X5R0J106M
C1608X7R1C105K
10
1
waveofdutycycleV /V .Themaximuminputcapacitor
OUT IN
ripple current is approximated by:
1/2
C required I
≈ I
(V (V –V )) /V
IN
RMS
OUT(MAX) OUT IN OUT
IN
Printed Circuit Board Layout Considerations
This formula’s maximum is approximately I
OUT(MAX)
=
RMS
There are three main considerations to take into account
while designing a PCB layout for the LTC3569. The first
consideration is regarding switching noise coupling onto
I
/2.
In an output short-circuit situation, the input capacitor
ripple current is approximately:
the FB pin traces and the R pin trace, or causing radiated
T
electromagnetic induction (EMI). The noise is mitigated
by placing the inductors and input decoupling capacitors
as close as possible to the LTC3569. Furthermore, careful
placement of a contiguous ground plane directly under
the high frequency switching node traces of the LTC3569
mitigates EMI; since high frequency eddy currents follow
the ground plane in loops. The larger the area of the cur-
rent return loops the larger EMI that is radiated. Placing
input decoupling capacitors close to the corresponding
C required I
≈ I /√3
PK
IN
RMS
Thus, the ripple current in an output short-circuit is about
2.5 times larger than for nominal operation. Take care
in selecting the input capacitor so as not to exceed the
capacitormanufacturer’sspecificationforselfheatingdue
to the ripple current.
Two factors influence the selection of the output capacitor.
The first is load voltage droop, V
output capacitor ESR effect on ripple voltage.
, the second is the
DROOP
PV /PGND pins directly reduces the area (and therefore
IN
the inductance) of ground returns. Also, place a group of
vias directly under the grounded backside of the package
leading to an internal ground plane. Place the ground
plane on the second layer of the PCB to minimize parasitic
inductance.
Load voltage droops on a load current step, ∆I , where
OUT
the output capacitor supports the output voltage for typi-
cally 2 to 3 clock cycles until the inductor current charges
up to the load step current level. A good estimate of output
capacitor value required to maintain a droop of less than
V
is given by:
DROOP
C
OUT
≈ 2.5•∆I /(f •V
)
OUT CLK DROOP
3569fe
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LTC3569
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The second consideration is stray capacitance on the FB
The junction temperature, T , is given by:
J
pin traces and the R pin trace to GND. This is taken into
T
T = t
+ T .
A
J
RISE
account by cutting the ground plane beneath these traces.
However, wherever the ground plane is cut, add additional
decoupling capacitors across the break to provide a path
for high-frequency ground return currents to flow.
Where T is the ambient temperature.
A
As an example, consider the case when the LTC3569 is
in dropout at an input voltage of 2.7V with load currents
of 1000mA, 500mA and 500mA for bucks 1, 2 and 3
respectively, at an ambient temperature of 85°C. From
the Typical Performance Characteristics, the R
buck1 is 0.190Ω, and for buck2 and buck3 it is 0.265Ω.
Therefore, power dissipated by the LTC3569 is:
Finally,thethirdconsiderationisstrayimpedancebetween
the SW node and the inductor when operating with a slave
powerstage. Itisimportanttokeepthestrayinductanceof
the slave power device to a minimum, by keeping the trace
from slave SW to the main SW as short as possible. This
requirement is necessary to ensure that the slave power
device’sshareoftheinductorcurrentdoesnotexceedthat
of the master as well as to keep the current density in the
slave device under control. The inductor should be placed
close to the master SW pin to minimize stray impedance
and allow the master to control the inductor current.
of
DS(ON)
2
2
2
P = I
D
R
+ I
R
+ I
R
3 DS(ON)3
1
DS(ON)1
2
DS(ON)2
= 190mV + 66.25mW + 66.25mV
= 322.5mW
At 85°C ambient the junction temperature is:
T = 322.5mW•68°C/W + 85°C = 106.9°C.
J
Thermal Considerations
Thisjunctiontemperatureisbelowtheabsolutemaximum
junction temperature of 125°C.
In the majority of applications, the LTC3569 does not dis-
sipate much heat due to its high efficiency. However, in
applicationswheretheLTC3569isrunningathighambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, the LTC3569
will be turned off and 2k resistive pull-downs are tied to
all the SW nodes.
Design Example 1: 2.5V, 1.8V and 1.2V From a
Li-Ion Battery
As a design example, consider using the LTC3569 in a
portable application with a Li-Ion battery source. The bat-
tery provides an SV from 2.9V to 4.2V. The loads require
IN
2.5V, 1.8V and 1.2V with current requirements of up to
800mA, 400mA and 400mA respectively when active. The
first load, with the 2.5V rail has no standby requirements,
however loads 2 and 3 each require a current of 1mA in
standby. Since two of the loads require low current opera-
To prevent the LTC3569 from exceeding maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whetherthepowerdissipatedexceedsthemaximumjunc-
tion temperature of the part. Temperature rise is:
tion, Burst Mode operation is selected. With V
at
IN(MAX)
4.2V and V
= 1.2V, the maximum clock frequency
OUT(MIN)
is 3.57MHz based on minimum on-time requirements.
To simplify the board layout, the fixed 2.25MHz internal
frequency is selected.
t
= P •θ
D JA
RISE
Where P is the power dissipated by the regulator and
D
θ
is the thermal resistance from the junction of the die
JA
to the ambient temperature.
3569fe
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LTC3569
applicaTions inForMaTion
Selecting The Inductors
The output capacitor values are calculated as:
Calculating the inductor values for 30% ripple current at
C
C
C
= 2.5•800mA/(2.25MHz•125mV) = 7.1µF
= 2.5•400mA/(2.25MHz•90mV) = 4.9µF
= 2.5•400mA/(2.25MHz•60mV) = 7.4µF
OUT1
OUT2
OUT3
maximum SV :
IN
L1 = 2.5V/(2.25MHz•240mA)•(1–2.5V/4.2V)= 1.9µH
L2 = 1.8V/(2.25MHz•120mA)•(1–1.8V/4.2V)= 3.8µH
L3 = 1.2V/(2.25MHz•120mA)•(1–1.2V/4.2V)= 3.1µH
Choosing the closest standard values gives, C
OUT2
= 10µF,
OUT1
C
= 4.7µF and C
= 10µF.
OUT3
Choosing a vendor’s closest values gives L1 = 2.2µH, L2
= L3 = 3.3µH. These values result in the maximum ripple
currents of:
A 22µF input capacitor is selected since the Li-Ion battery
has sufficiently low output impedance.
Setting The Output Voltages
∆I = 2.5V/(2.25MHz•2.2µH)•(1–2.5V/4.2V) = 204mA
L1
Without toggling the EN pins the LTC3569 develops a 0.8V
referencevoltageforeachofthefeedbackpins. Theoutput
voltages are set by a resistive divider as follows:
∆I = 1.8V/(2.25MHz•3.3µH)•(1–1.8V/4.2V) = 139mA
L2
∆I = 1.2V/(2.25MHz•3.3µH)•(1–1.2V/4.2V) = 115mA
L3
V
OUT
= 0.8•(1 + R1/R2)
Selecting The Output Capacitors
The resistors in Figure 5 are selected as the nearest 1%
standard resistor values. To improve frequency response
feedforward capacitors of 10pF and 20pF are used.
The value of the output capacitors are calculated based
on a 5% load droop for maximum load current step. The
output droop is usually about 2.5 times the linear drop
of the first cycle and is estimated based on the following
formula:
C
OUT
= 2.5•I
/(f •V
OUT(MAX) CLK DROOP
)
V
2.9V TO 4.2V
22µF
IN
L1
2.2µH*
OUT1
2.5V AT 800mA
OUT1
10µF
SV
PV
SW1
FB1
IN
IN
Design Example 1: Burst Mode Operation
C
243k
115k
10pF
20pF
20pF
100
V
= 2.9V TO 4.2V
EN1
EN2
EN3
IN
LTC3569
L2
3.3µH**
90
80
70
60
50
OUT2
1.8V AT 400mA
OUT2
4.7µF
SW2
FB2
R
T
C
187k
150k
MODE
470k
PGOOD
L3
3.3µH**
OUT3
1.2V AT 400mA
OUT3
10µF
SW3
FB3
BUCK1 = 2.5V
BUCK2 = 1.8V
BUCK3 = 1.2V
C
187k
374k
SGND PGND
0.1
1
10
100
(mA)
1000
10000
I
LOAD
3569 F05a
3569 F05b
* WURTH 7447745022
** WURTH 7447745033
Figure 5. Triple Buck DC/DC Regulators: 800mA, 400mA, 400mA
3569fe
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LTC3569
applicaTions inForMaTion
Design Example 2: Dual Bucks, 1.8V at 1.8A and 1.5V
at 600mA
Calculating the value of the output capacitors:
C
OUT1
C
OUT2
= 2.5•1800mA/(2.25MHz•90mV) = 22µF
For this example, the LTC3569 is configured to deliver two
fixed voltages of 1.8V and 1.5V from a generic supply over
the full operating range, 2.5V to 5.5V. The load require-
ments range from <1mA in standby mode up to 1.8A for
the 1.8V supply and 600mA for the 1.5V supply.
= 2.5•600mA/(2.25MHz•75mV) = 8.9µF
An input capacitor of 22µF is selected to support the
maximum ripple current of 1.2A. An additional 0.1µF low
ESR capacitor is placed between SV and SGND.
IN
The resistor values shown in Figure 6 are selected as the
closest standard 1% resistors to obtain the correct output
voltages with the full-scale reference voltages of 0.8V. And
20pFfeedforwardcapacitorsareplacedacrosstheleading
feedback resistors.
The fixed internal clock frequency of 2.25MHz meets the
minimum on-time requirements. Burst Mode operation
is selected for high efficiency at the low standby current
level. Calculating the inductor values for 30% ripple cur-
rent at max SV :
IN
L1 = 1.8V/(2.25MHz•540mA)•(1–1.8V/5.5V) = 1.0µH
L2 = 1.5V/(2.25MHz•180mA)•(1–1.5V/5.5V) = 2.2µH
V
2.5V TO 5.5V
22µF
IN
Design Example 2: 1.8A Load Step on Buck1
with Buck2 Slave, Burst Mode Operation
1µH
OUT1
1.8V AT 1.8A
PV
SW1
SW2
FB1
IN
187k
150k
20pF
22µF
CH1
SW1/2
EN1
2V/DIV
EN2
EN3
LTC3569
CH3
OUT1
200mV/DIV
V
336mV
V
FB2
R
T
P-P
IN
CH2
LOAD
1.8A
MODE
2.2µH
I
OUT3
511k
SW3
FB3
1.5V AT 600mA
1A/DIV
1A/DIV
PGOOD
174k
200k
20pF
10µF
CH4
V
I
SV
IN
IN
L1
1.94A
3569 F06b
0.1µF
10µs/DIV
SGND PGND
3569 F06a
Figure 6. Dual Buck DC/DC Regulators: 1.8V at 1800mA, and 1.5V at 600mA
3569fe
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LTC3569
applicaTions inForMaTion
Design Example 3: Dual Programmable Bucks
standby voltages: 1.8V/1.2V = 1.5. The 0.75V and 0.5V
reference levels mach this ratio. The resistors shown in
Figure 7 are selected to obtain the correct feedback ratio
fromstandard1%resistors.Calculatingtheinductorvalues
In this example consider two buck regulators operating
from a 2.5V to 5.5V unregulated supply that are required
togeneratetwoindependentlyprogrammablesuppliesthat
must step from 1.2V in standby up to 1.8V when active,
with a maximum load current of 1.2A when active and
1mA in standby. Additionally, this application anticipates
possible output short circuits, and is required to operate
without damage in such a situation.
for 30% ripple current at maximum SV :
IN
L = 1.8V/(2.25MHz•360mA)•(1–1.8V/5.5V)= 1.5µH.
The output capacitor values are selected as the nearest
standard value to obtain 5% voltage droop at maximum
load current step.
Buck 1 is selected for the first regulator, and buck 3 is
configured as a slave power stage in parallel with buck 2
C
= 2.5•1200mA/(2.25MHz•90mV) ≈ 15µF.
OUT
Select an output capacitor with an ESR of less than 50mΩ
to obtain an output voltage ripple of less than 30mV.
Finally select an input capacitor rated for the worst-case
short-circuit ripple current of 2 I /√3 ≈ 2.5A, when both
outputs are shorted to GND.
bypullingFB3uptoV toobtaintherequiredcurrentlevel
IN
for the second regulator. Burst Mode operation is selected
to achieve high efficiency during standby operation. The
internal2.25MHzclockfrequencyisselected,asitsatisfies
the minimum on-time requirement. Next, two reference
voltages are selected to match the ratio of the active to
PK
V
2.5V TO 5.5V
IN
Design Example 3: Soft-Start to Standby (1.2V)
1.5µH
1.5µH
OUT1 1200mA
1.2V STANDBY
1.8V ACTIVE
22µF
SV
PV
SW1
FB1
IN
IN
294k
210k
20pF
20pF
15µF
15µF
500mV/DIV
500mV/DIV
EN1
EN2
EN3
DIGITAL
CONTROL
LTC3569
CH1
OUT1
V
IN
OUT2 1200mA
1.2V STANDBY
1.8V ACTIVE
SW2
SW3
FB2
MODE
CH2
2V/DIV
2V/DIV
OUT2
294k
210k
R
T
CH3
PGOOD
CH4
511k
PGOOD
EN1 = EN2
FB3
V
IN
3569 F07b
SGND PGND
200µs/DIV
3569 F07a
Figure 7. Dual Programmable Buck DC/DC Regulators: 1200mA, 1200mA
3569fe
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Design Example 4: Dual Programmable Bucks
tolerate a voltage droop when switching from standby to
active,the0.7Vand0.525Vreferencesareselectedtomatch
the ratio of output voltages. With this ratio, the buck does
not need to be shutdown as it would if the full-scale 0.8V
referencelevelwaschosen.TheresistorsshowninFigure8
are selected to obtain the nearest feedback ratio from
standard 1% resistors. Calculating the inductor values
In this example consider two buck regulators operating
from a 2.5V to 5.5V unregulated supply that are required
togeneratetwoindependentlyprogrammablesuppliesthat
must step from 1.2V in standby up to 1.6V when active,
withamaximumloadcurrentof0.8Awhenactiveand1mA
in standby. Furthermore, when switching between active
and standby, the load voltage should not droop.
for 30% ripple current at maximum SV :
IN
L = 1.6V/(2.25MHz•240mA)•(1–1.6V/5.5V) ≈ 2.2µH.
Buck 1 is selected for the first regulator, and buck 3 is
configured as a slave power stage in parallel with buck 2
The output capacitor values are selected as the nearest
standard value to obtain 5% voltage droop at maximum
load current step.
bypullingFB3uptoV toobtaintherequiredcurrentlevel
IN
for the second regulator. Burst Mode operation is selected
to achieve high efficiency during standby operation. The
internal2.25MHzclockfrequencyisselected,asitsatisfies
the minimum on-time requirement. Next, two reference
voltages are selected to match the ratio of the active to
standby voltages: 1.6V/1.2V = 1.3333. There are three
reference value ratios that match this ratio: 0.8V and 0.6V,
0.7V and 0.525V, and 0.6V and 0.45V. As the load cannot
C
OUT
= 2.5•800mA/(2.25MHz•90mV) ≈ 10µF.
Select an output capacitor with an ESR of less than 50mΩ
to obtain an output voltage ripple of less than 30mV.
Finally select an input capacitor rated for the worst-case
short-circuit ripple current of 2 I /√3 ≈ 2.5A, when both
PK
outputs are shorted to GND.
Design Example 4: Dual 1A Bucks
VOUT = 1.6V, Burst Mode Operation
V
2.5V TO 5.5V
IN
2.2µH
2.2µH
OUT1 800mA
1.2V STANDBY
1.6V ACTIVE
100
90
80
70
60
50
40
22µF
SV
PV
SW1
FB1
IN
IN
210k
162k
20pF
20pF
10µF
10µF
V
= 2.5V
IN
EN1
EN2
EN3
DIGITAL
CONTROL
LTC3569
V
IN
V
= 5.5V
IN
OUT2 800mA
1.2V STANDBY
1.6V ACTIVE
SW2
SW3
FB2
MODE
210k
162k
R
T
511k
PGOOD
FB3
V
IN
BUCK 1
BUCK 2, 3
SGND PGND
3569 F08
0.1
1
10
100
(mA)
1000
10000
I
LOAD
3569 F08b
Figure 8. Dual Programmable Buck DC/DC Regulators
3569fe
21
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LTC3569
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
20-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1720 Rev A)
0.70 ±0.05
3.50 ± 0.05
(4 SIDES)
1.65 ± 0.05
2.10 ± 0.05
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 TYP
OR 0.25 × 45°
CHAMFER
R = 0.115
TYP
0.75 ± 0.05
3.00 ± 0.10
(4 SIDES)
R = 0.05
TYP
19 20
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
1.65 ± 0.10
(4-SIDES)
(UD20) QFN 0306 REV A
0.200 REF
0.20 ± 0.05
0.00 – 0.05
0.40 BSC
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3569fe
22
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LTC3569
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
2.65 ± 0.05
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ± 0.05
× 45° CHAMFER
1.50 REF
19 20
R = 0.05 TYP
3.00 ± 0.10
0.40 ± 0.10
1
2
PIN 1
TOP MARK
(NOTE 6)
2.65 ± 0.10
1.65 ± 0.10
4.00 ± 0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3569fe
23
For more information www.linear.com/LTC3569
LTC3569
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
9
6.60 0.10
4.50 0.10
2.74
(.108)
6.40
(.252)
BSC
SEE NOTE 4
2.74
(.108)
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BA) TSSOP REV K 0913
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3569fe
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For more information www.linear.com/LTC3569
LTC3569
revision hisTory (Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
01/11 Added UDC package. Reflected throughout the data sheet
1 to 26
E
04/14 Added spec for PGOOD Current to Absolute Maximum Ratings
Clarified Pin Configuration for FE package
2
2
8
Clarified Pin Description for PV for FE package
IN3
3569fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LTC3569
Typical applicaTion
L1
V
IN
2.2µH
OUT1
22µF
SV
PV
SW1
FB1
IN
IN
1200mA
OUT1
10µF
C
R1
R2
20pF
20pF
20pF
EN1
EN2
EN3
DIGITAL
CONTROL
LTC3569
L2
2.2µH
OUT2
600mA
OUT2
4.7µF
SW2
FB2
MODE
C
R3
R4
R
T
511k
PGOOD
L3
2.2µH
OUT3
600mA
OUT3
4.7µF
SW3
FB3
C
R5
R6
SGND PGND
3569 TA02
Figure 9. Triple Programmable Buck DC/DC Regulators
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
95% Efficiency, V : 2.5V to 5.5V, V
LTC3406A/
LTC3406AB
600mA, 1.5MHz, Synchronous Step-Down DC/DC Converter
= 0.6V, I = 20µA,
Q
IN
OUT(MIN)
OUT(MIN)
I
<1µA, ThinSOT™ Package
SD
LTC3407A/
LTC3407A-2
Dual 600mA/600mA 1.5MHz, Synchronous Step-Down DC/DC 95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
IN
Converter
I
<1µA, MS10E, 3mm × 3mm DFN-10 Package
SD
LTC3411A
LTC3412A
LTC3417A-2
1.25A, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 60µA,
Q
IN
OUT(MIN)
OUT(MIN)
I
<1µA, MS10, 3mm × 3mm DFN-10 Package
2.5A, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
IN
I
<1µA, 4mm × 4mm QFN-16, TSSOP-16E Package
SD
Dual 1.5A/1A, 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, V : 2.3V to 5.5V, V
= 0.8V, I = 125µA,
Q
IN
OUT(MIN)
I
<1µA, TSSOP-16E, 3mm × 5mm DFN-16 Package
SD
LTC3419/LTC3419-1 Dual 600mA/600mA 2.25MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.6V, I = 35µA,
Q
IN
OUT(MIN)
I
<1µA, MS10, 3mm × 3mm DFN-10 Package
LTC3544/LTC3544B Quad 100mA/200mA/200mA/300mA, 2.25MHz Synchronous 95% Efficiency, V : 2.3V to 5.5V, V
= 0.8V, I = 70µA,
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Q
Step-Down DC/DC Converter
I
<1µA, 3mm × 3mm QFN-16 Package
SD
LTC3545/LTC3545-1
95% Efficiency, V : 2.3V to 5.5V, V
SD
= 0.6V, I = 58µA,
Triple, 800mA × 3, 2.25MHz Synchronous Step-Down DC/DC
Converter
IN
Q
I
<1µA, 3mm × 3mm QFN-16 Package
LTC3547/LTC3547B Dual 300mA, 2.25MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.6V, I = 40µA,
Q
IN
I
<1µA, DFN-8 Package
LTC3548/LTC3548-1/ Dual 400mA and 800mA I , 2.25MHz, Synchronous Step-
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
OUT
IN
LTC3548-2
Down DC/DC Converter
I
<1µA, MS10E, 3mm × 3mm DFN-10 Package
SD
LTC3561
1.25A, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 240µA,
Q
IN
OUT(MIN)
I
<1µA, 3mm × 3mm DFN-8 Package
2
LTC3562
Quad, I C Interface, 600mA/600mA/400mA/400mA, 2.25MHz 95% Efficiency, V : 2.9V to 5.5V, V
= 0.425V, I = 100µA,
Q
IN
OUT(MIN)
Synchronous Step-Down DC/DC Converter
I
<1µA, 3mm × 3mm QFN-20 Package
SD
3569fe
LT 0414 REV E • PRINTED IN USA
26 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3569
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