LTC3577-3_技术文档

LTC3577-3/LTC3577-4

Highly Integrated

Portable Product PMIC

FEATURES

DESCRIPTION

The LTC^®3577-3/LTC3577-4 are highly integrated power

managementICsforsinglecellLi-Ion/Polymerbatteryap-

plications.ItincludesaPowerPathmanagerwithautomatic

load prioritization, a battery charger, an ideal diode, input

overvoltage protection and numerous other internal pro-

tection features. The LTC3577-3/LTC3577-4 are designed

toaccuratelychargefromcurrentlimitedsuppliessuchas

USB by automatically reducing charge current such that

the sum of the load current and the charge current does

notexceedtheprogrammedinputcurrentlimit(100mAor

500mAmodes).TheLTC3577-3/LTC3577-4reducethebat-

teryvoltageatelevatedtemperaturestoimprovesafetyand

reliability. The three step-down switching regulators and

two LDOs provide a wide range of available supplies. The

LTC3577-3/LTC3577-4 also include a pushbutton input to

controlpowersequencingandsystemreset. Theonboard

LED backlight boost circuitry can drive up to 10 series

LEDs and includes versatile digital dimming via the I²C

input.TheLTC3577-3/LTC3577-4aredesignedtosupport

the SiRF Atlas IV processor and has pushbutton timing

and sequencing different from other LTC3577 versions.

The LTC3577-3/LTC3577-4 are available in a low proﬁle

4mm × 7mm × 0.75mm 44-pin QFN package.

n

Full Featured Li-Ion/Polymer Charger/PowerPath™

Control with Instant-On Operation

n

Triple Adjustable High Efﬁciency Step-Down

Switching Regulators (800mA, 500mA, 500mA I

)

OUT

2

n

I C Adjustable SW Slew Rates for EMI Reduction

n

High Temperature Battery Voltage Reduction

Improves Safety and Reliability

n

Overvoltage Protection Controller for USB (V )/Wall

BUS

Inputs Provide Protection to 30V

n

Integrated 40V Series LED Back Light Driver with 60dB

2

Brightness Control and Gradation via I C

n

1.5A Maximum Charge Current with Thermal Limiting

Battery Float Voltage: 4.2V (LTC3577-3)

4.1V (LTC3577-4)

n

Pushbutton ON/OFF Control with System Reset

Dual 150mA Current Limited LDOs

Start-Up Timing Compatible with SiRF Atlas IV

Processor

n

Small 4mm × 7mm 44-pin QFN package

APPLICATIONS

n

PNDs, DMB/DVB-H, Digital/Satellite Radio,

Media Players

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. PowerPath is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6522118, 6700364, 7511390, 5481178, 6580258. Other

patents pending.

n

Portable Industrial/Medical Products

Other USB-Based Handheld Products

n

TYPICAL APPLICATION

5V

10-LED Driver Efﬁciency

ADAPTER

OPTIONAL

90

80

70

60

100mA/500mA

1000mA

USB

V

OUT

0V

OVERVOLTAGE

PROTECTION

CC/CV

MAX PWM

CONSTANT

CURRENT

CHARGER

+

50

40

30

20

10

0

SINGLE CELL

Li-Ion

CHARGE

NTC

LTC3577-3/LTC3577-4

2

0.8V to 3.6V/150mA

DUAL LDO

2

I C PORT

REGULATORS

LED BACKLIGHT WITH DIGITALLY

CONTROLLED DIMMING

4 TO 10 LED

BOOST

TRIPLE HIGH

0.8V to 3.6V/800mA

0.8V to 3.6V/500mA

EFFICIENCY

PUSHBUTTON

CONTROL

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

PB

STEP-DOWN

LED CURRENT (A)

SWITCHING

REGULATORS

357734 TA01b

357734 TA01a

357734fa

1

LTC3577-3/LTC3577-4

TABLE OF CONTENTS

FEATURES....................................................................................................................................................................1

APPLICATIONS ............................................................................................................................................................1

TYPICAL APPLICATION................................................................................................................................................1

DESCRIPTION..............................................................................................................................................................1

ABSOLUTE MAXIMUM RATINGS.................................................................................................................................3

ORDER INFORMATION ................................................................................................................................................3

PIN CONFIGURATION ..................................................................................................................................................3

ELECTRICAL CHARACTERISTICS ................................................................................................................................4

TYPICAL PERFORMANCE CHARACTERISTICS ..........................................................................................................10

PIN FUNCTIONS.........................................................................................................................................................16

BLOCK DIAGRAM ......................................................................................................................................................19

OPERATION ...............................................................................................................................................................20

PowerPath OPERATION.........................................................................................................................................20

LOW DROPOUT LINEAR REGULATOR OPERATION...............................................................................................29

STEP-DOWN SWITCHING REGULATOR OPERATION ............................................................................................30

LED BACKLIGHT/BOOST OPERATION ...................................................................................................................34

2

I C OPERATION .....................................................................................................................................................37

PUSHBUTTON INTERFACE OPERATION ................................................................................................................43

LAYOUT AND THERMAL CONSIDERATIONS .........................................................................................................47

TYPICAL APPLICATION..............................................................................................................................................49

PACKAGE DESCRIPTION............................................................................................................................................51

RELATED PARTS........................................................................................................................................................52

357734fa

2

LTC3577-3/LTC3577-4

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2, 3)

V

............................................................ –0.3V to 45V

BUS OUT IN12 IN3 INLDO1 INLDO2

t < 1ms and Duty Cycle < 1% .................. –0.3V to 7V

Steady State............................................. –0.3V to 6V

SW

TOP VIEW

, V , V

, V

, WALL

CHRG, BAT, LED_FS, LED_OV,

PWR_ON, EXTPWR, PBSTAT, PGOOD,

FB1, FB2, FB3, LDO1, LDO1_FB, LDO2,

I

1

2

37 IDGATE

36 PROG

35 NTC

34 NTCBIAS

33 SW1

LIM0

I

LIM1

LED_FS 3

WALL 4

SW3 5

LDO2_FB, DV , SCL, SDA, EN3.................. –0.3V to 6V

CC

V

6

32 V

IN3

IN12

NTC, PROG, CLPROG, ON, I

, I

LIM0 LIM1

45

FB3 7

OVSENS 8

LED_OV 9

DV 10

SDA 11

SCL 12

OVGATE 13

PWR_ON 14

ON 15

31 SW2

30 V

(Note 4)............................................–0.3V to V + 0.3V

INLD02

CC

29 LDO2

28 LDO1

27 V

INLDO1

26 FB1

25 FB2

24 LDO2_FB

23 LDO1_FB

I

, I

, I .........................................................2A

VBUS VOUT BAT

SW3

SW2 SW1

LDO1 LDO2

CHRG ACPR EXTPWR PBSTAT PGOOD

OVSENS

CLPROG PROG LED_FS LED_OV

CC

(Continuous)................................................850mA

, I

(Continuous).......................................600mA

(Continuous).....................................200mA

, I

....................75mA

...................................................................10mA

, I

...............................2mA

Maximum Junction Temperature........................... 110°C

Operating Temperature Range.................. –40°C to 85°C

Storage Temperature Range................... –65°C to 125°C

UFF PACKAGE

44-LEAD (7mm s 4mm) PLASTIC QFN

T

JMAX

= 110°C, θ = 45°C/W

JA

EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3577EUFF-3#PBF

LTC3577EUFF-4#PBF

TAPE AND REEL

PART MARKING

35773

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3577EUFF-3#TRPBF

LTC3577EUFF-4#TRPBF

–40°C to 85°C

44-Lead (4mm × 7mm) Plastic QFN

35774

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

357734fa

3

LTC3577-3/LTC3577-4

Power Manager. The l denotes the speciﬁcations which apply over the

ELECTRICAL CHARACTERISTICS

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_BUS= 5V, V_BAT= 3.8V, I_LIM0= I_LIM1= 5V, WALL = 0V,

V_INLDO2= V_INLOD1= V_IN12= V_IN3= V_OUT, R_PROG= 2k, R_CLPROG= 2.1k, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Power Supply

V

Input Supply Voltage

4.35

5.5

V

BUS

l

I

Total Input Current (Note 5)

I

= 5V, I

= 0V, I

= 5V (1x Mode)

= 0V (5x Mode)

= 5V (10x Mode)

80

450

900

90

475

950

100

500

1000

mA

BUS_LIM

LIM0

LIM1

I

Input Quiescent Current, POFF State

1x, 5x, 10x Modes

= 5V, I = 0V (Suspend Mode)

0.42

0.05

mA

BUSQ

I

0.1

LIM0

LIM1

h

Ratio of Measured V

Current to

1000

mA/mA

CLPROG

BUS

CLPROG Program Current

V

CLPROG Servo Voltage in Current

Limit

1x Mode

5x Mode

10x Mode

0.2

1.0

2.0

V

CLPROG

V

Undervoltage Lockout

Rising Threshold

Falling Threshold

3.8

3.7

3.9

V

UVLO

BUS

3.5

to V

Differential Undervoltage Rising Threshold

Falling Threshold

50

–50

100

mV

DUVLO

BUS

OUT

Lockout

R

Input Current Limit Power FET On-

Resistance (Between V and V

200

mΩ

ON_ILIM

)

OUT

BUS

Battery Charger

V

Regulated Output Voltage

BAT

LTC3577-3

LTC3577-3, 0 ≤ T ≤ 85°C

A

4.179

4.165

4.200

4.221

4.235

V

FLOAT

LTC3577-4

4.079

4.065

4.1

4.121

4.135

V

LTC3577-4, 0 ≤ T ≤ 85°C

A

l

I_CHG

Constant-Current Mode Charge Current

IC Not in Thermal Limit

R

PROG

R

PROG

R

PROG

= 1k, Input Current Limit = 2A

= 2k, Input Current Limit = 1A

= 5k, Input Current Limit = 0.4A

950

465

180

1000

500

200

1050

535

220

mA

I_{BATQ_OFF}

I_{BATQ_ON}

Battery Drain Current, POFF State,

Buck3 Disabled, No Load (Note 15)

V

= 4.3V, Charger Time Out

= 0V

6

27

μA

BAT

BUS

55

100

Battery Drain Current, PON State,

Buck3 Enabled (Notes 10, 15)

V

= 0V, I

= 0μA, No Load On

OUT

130

200

μA

BUS

Supplies, Burst Mode Operation

V

PROG Pin Servo Voltage

V

> V

< V

1.000

0.100

V

PROG,CHG

BAT

TRKL

PROG Pin Servo Voltage in Trickle

Charge

PROG,TRKL

h

Ratio of I

to PROG Pin Current

1000

50

mA/mA

mA

PROG

BAT

I

Trickle Charge Current

V

< V

40

60

TRKL

BAT

TRKL

V

Trickle Charge Rising Threshold

Trickle Charge Falling Threshold

V

Rising

Falling

2.9

3.0

V

TRKL

BAT

2.5

–75

3.2

2.75

ΔV

Recharge Battery Threshold Voltage

Safety Timer Termination Period

Bad Battery Termination Time

Threshold Voltage Relative to V

–100

4

–125

4.8

mV

Hour

RECHRG

FLOAT

t

Timer Starts when V

= V

– 50mV

TERM

BADBAT

BAT

FLOAT

V

BAT

< V

0.4

0.5

0.1

200

0.6

Hour

TRKL

h

End-of-Charge Indication Current Ratio (Note 6)

Battery Charger Power FET On-

0.085

0.11

mA/mA

mΩ

C/10

R

ON_CHG

Resistance (Between V

and BAT)

OUT

T

Junction Temperature in Constant

Temperature Mode

110

°C

LIM

357734fa

4

LTC3577-3/LTC3577-4

ELECTRICAL CHARACTERISTICS ^{Power Manager}. The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_BUS= 5V, V_BAT= 3.8V, I_LIM0= I_LIM1= 5V, WALL = 0V,

V_INLDO2= V_INLOD1= V_IN12= V_IN3= V_OUT, R_PROG= 2k, R_CLPROG= 2.1k, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

NTC, Battery Discharge Protection

V

Cold Temperature Fault Threshold

Voltage

Rising NTC Voltage

Hysteresis

75

34

76

77

36

%V

COLD

HOT

NTCBIAS

1.3

Hot Temperature Fault Threshold

Voltage

Falling NTC Voltage

Hysteresis

35

1.3

%V

NTCBIAS

V

_

NTC Discharge Threshold Voltage

Falling NTC Voltage

Hysteresis

24.5

–50

25.5

50

26.5

50

%V

TOO HOT

NTCBIAS

mV

I

NTC Leakage Current

BAT Discharge Current

BAT Discharge Threshold

V

= V = 5V

BUS

nA

mA

V

NTC

BAT

= 4.1V, NTC < V

170

3.9

BAT2HOT

TOO_HOT

V

I

< 0.1mA, NTC < V

TOO_HOT

BAT2HOT

BAT

Ideal Diode

V

Forward Voltage Detection

Diode On-Resistance, Dropout

Diode Current Limit

I

= 10mA

5

15

200

3.6

25

mV

mΩ

A

FWD

OUT

R

= 200mA

DROPOUT

MAX

OUT

I

(Note 7)

Overvoltage Protection

V

Overvoltage Protection Threshold

OVGATE Output Voltage

Rising Threshold, R

= 6.2k

OVSENS

6.10

6.35

6.70

12

V

OVCUTOFF

OVGATE

Input Below V

Input Above V

1.88 • V

0

V

OVCUTOFF

OVSENS

I

t

OVSENS Quiescent Current

V

C

= 5V

40

μA

OVSENSQ

RISE

OVSENS

OVGATE

OVGATE Time to Reach Regulation

= 1nF

2.5

ms

Wall Adapter and High Voltage Buck Output Control

V

ACPR Pin Output High Voltage

ACPR Pin Output Low Voltage

I

= 0.1mA

= 1mA

V

OUT

– 0.3

V

OUT

0

V

ACPR

0.3

V

Absolute Wall Input Threshold Voltage

V

WALL

Rising

Falling

4.3

3.2

4.45

V

W

WALL

V

3.1

0

Differential Wall Input Threshold

Voltage

V

WALL

– V Falling

25

75

mV

ΔV

WALL

BAT

W

V

– V Rising

100

0.4

BAT

I

Wall Operating Quiescent Current

I

+ I

, I = 0mA,

= 5V

440

μA

QWALL

WALL

VOUT BAT

WALL = V

OUT

Logic (I

, I

and CHRG)

LIM0 LIM1

V

Input Low Voltage

I

, I

LIM0 LIM1

V

IL

IH

Input High Voltage

, I

1.2

LIM0 LIM1

I

Static Pull-Down Current

CHRG Pin Output Low Voltage

CHRG Pin Input Current

, I ; V = 1V

LIM0 LIM1 PIN

2

0.15

0

μA

V

PD

V

= 10mA

CHRG

0.4

1

CHRG

I

V

= 4.5V, V

= 5V

CHRG

μA

BAT

357734fa

5

LTC3577-3/LTC3577-4

2

I C Interface. The l denotes the speciﬁcations which apply over the full

ELECTRICAL CHARACTERISTICS

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. DV_CC= 3.3V, V_OUT= 3.8V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DV

Input Supply Voltage

1.6

5.5

V

CC

I

DV Supply Current

CC

SCL = 400kHz

SCL = SDA = 0kHz

10

1

μA

DVCC

V

DV UVLO

1.0

50

V

DVCC,UVLO

CC

Input HIGH Voltage

70

%DV

IH

IL

CC

Input LOW Voltage

30

–1

I

IH

I

IL

Input HIGH Leakage Current

Input LOW Leakage Current

SDA Output LOW Voltage

SDA = SCL = DV = 5.5V

1

μA

V

CC

SDA = SCL = 0V, DV = 5.5V

CC

V

OL

I

= 3mA

0.4

SDA

Timing Characteristics (Note 8) (All Values are Referenced to V and V )

IH

IL

f

t

SCL Clock Frequency

400

kHz

μs

ns

SCL

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

Bus Free Time Between Stop and Start Condition

Hold Time After (Repeated) Start Condition

Setup Time for a Repeated Start Condition

Stop Condition Set-Up Time

1.3

0.6

1.3

0.6

0

LOW

HIGH

BUF

HD,STA

SU,STA

SU,STO

HD,DATO

HD,DATI

SU,DAT

SP

Output Data Hold Time

900

50

Input Data Hold Time

0

Data Set-Up Time

100

Input Spike Suppression Pulse Width

LED Boost Switching Regulator. The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. V_IN3= V_OUT= 3.8V, R_OV= 10M, R_{LED_FS}= 20k, boost regulator disabled unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

(Note 9)

MIN

TYP

MAX

UNITS

l

V

, V

IN3 OUT

Operating Supply Range

2.7

5.5

V

I

Operating Quiescent Current

Shutdown Quiescent Current

(Notes 10, 14)

560

0.01

μA

VOUT_LED

V

LED Overvoltage Threshold

LED_OV Rising

LED_OV Falling

1.0

1.25

V

LED_OV

0.6

800

18

0.85

I

Peak NMOS Switch Current

1000

20

1200

22

mA

dB

LIM

I

Pin Full-Scale Operating Current

Pin Full-Scale Dimming Range

LED(FS)

LED(DIM)

LED

64 Steps

60

LED

R

of NMOS Switch

240

0.01

1.125

800

4

mΩ

μA

NSWON

NSWOFF

OSC

DS(ON)

I

f

NMOS Switch Off Leakage Current

Oscillator Frequency

V

SW

= 5.5V

1

0.95

780

3.8

1.3

820

4.2

MHz

mV

μA

l

V

LED_FS Pin Voltage

LED_FS

LED_OV

I

LED_OV Pin Current

D

BOOST

Maximum Duty Cycle

I

= 0

97

%

LED

l

V

Boost Mode Feedback Voltage

775

800

825

mV

BOOSTFB

357734fa

6

LTC3577-3/LTC3577-4

ELECTRICAL CHARACTERISTICS ^{Step-Down Switching Regulators.}The l denotes the speciﬁcations

which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_OUT= V_IN12= V_IN3= 3.8V, all

regulators enabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Step-Down Switching Regulators (Buck1, Buck2 and Buck3)

l

V

, V

Input Supply Voltage

(Note 9)

and V Connected to V Through

OUT

2.7

2.5

5.5

2.9

V

IN12 IN3

UVLO

V

Falling

Rising

V

2.7

2.8

V

OUT

IN12

IN3

Low Impedance. Switching Regulators are

Disabled Below V UVLO

OUT

f

Oscillator Frequency

1.91

2.25

2.59

MHz

OSC

800mA Step-Down Switching Regulator 3 (Buck3-Enabled via EN3, Disabled in PON and POFF States)

I

Pulse-Skipping Mode Input Current

Burst Mode Input Current

Shutdown Input Current

Peak PMOS Current Limit

Feedback Voltage

(Note 10)

EN3 = 0

100

20

μA

VIN3Q

35

1

0.01

1400

μA

I

(Note 7)

1000

1700

mA

LIM3

l

V

Pulse-Skipping Mode

Burst Mode Operation

0.78

0.8

0.82

0.824

V

FB3

I

FB3 Input Current

Max Duty Cycle

(Note 10)

FB3 = 0V

–0.05

100

0.05

μA

%

Ω

kΩ

V

FB3

D3

R

of PMOS

of NMOS

0.3

0.4

10

P3

DS(ON)

N3

SW3 Pull-Down in Shutdown

EN3 Input Low Voltage

EN3 Input High Voltage

EN3 = 0

SW3_PD

IL,EN3

IH,EN3

V

0.4

1.2

V

500mA Step-Down Switching Regulator 2 (Buck2-Pushbutton Enabled, Third in Sequence)

I

Pulse-Skipping Mode Input Current

Burst Mode Input Current

Shutdown Input Current

Peak PMOS Current Limit

Feedback Voltage

(Note 10)

POFF State

(Note 7)

100

20

μA

VIN12Q

0.01

900

1

μA

I

650

1200

mA

LIM2

l

V

Pulse-Skipping Mode

Burst Mode Operation

0.78

0.8

0.82

0.824

V

FB2

I

FB2 Input Current

Max Duty Cycle

(Note 10)

FB2 = 0V

–0.05

100

0.05

μA

%

FB2

D2

R

of PMOS

of NMOS

I

= 100mA

0.6

10

Ω

P2

DS(ON)

SW2

= –100mA

Ω

N2

SW2 Pull-Down in Shutdown

POFF State

kΩ

SW2_PD

500mA Step-Down Switching Regulator 1 (Buck1-Pushbutton Enabled, Second in Sequence)

I

Pulse-Skipping Mode Input Current

Burst Mode Input Current

Shutdown Input Current

Peak PMOS Current Limit

Feedback Voltage

(Note 10)

100

20

μA

VIN12Q

0.01

900

1

μA

I

(Note 7)

650

1200

mA

LIM1

l

V

Pulse Skip Mode

Burst Mode Operation

0.78

0.8

0.82

0.824

V

FB1

I

FB1 Input Current

Max Duty Cycle

(Note 10)

FB1 = 0V

–0.05

100

0.05

μA

%

FB1

D1

R

of PMOS

of NMOS

I

= 100mA

0.6

10

Ω

P1

DS(ON)

SW1

= –100mA

Ω

N1

SW1 Pull-Down in Shutdown

POFF State

kΩ

SW1_PD

357734fa

7

LTC3577-3/LTC3577-4

ELECTRICAL CHARACTERISTICS ^{LDO Regulators.}The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_INLDO1= V_INLDO2= V_OUT= 3.8V, LDO1 and LDO2 enabled

unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

≤ V + 0.3V

OUT

MIN

TYP

MAX

UNITS

LDO Regulator 1 (LDO1-Always On)

l

V

Input Voltage Range

V

1.65

2.5

5.5

V

INLDO1

V

OUT

V

OUT

Falling

Rising

LDO1 is Disabled Below V UVLO

OUT

2.7

2.8

V

OUT_UVLO

2.9

V

LDO1_FB Regulated Feedback Voltage

LDO1_FB Line Regulation (Note 11)

LDO1_FB Load Regulation (Note 11)

Available Output Current

I

= 1mA

0.78

0.8

0.4

5

0.82

V

mV/V

μV/mA

mA

LDO1_FB

LDO1

= 1mA, V = 1.65V to 5.5V

IN

= 1mA to 150mA

l

I

150

LDO1_OC

Short-Circuit Output Current

270

mA

LDO1_SC

V

Dropout Voltage (Note 12)

I

= 150mA, V

= 3.6V

= 2.5V

160

200

170

260

320

280

mV

DROP1

LDO1

INLDO1

= 75mA, V

= 1.8V

INLDO1

R

Output Pull-Down Resistance in Shutdown LDO1 Disabled

LDO_FB1 Input Current

10

kꢀ

nA

LDO1_PD

I

–50

50

LDO_FB1

LDO Regulator 2 (LDO2-Pushbutton Enabled, First in Sequence)

l

V

Input Voltage Range

V

≤ V + 0.3V

OUT

1.65

2.5

5.5

V

INLDO2

V

OUT

V

OUT

Falling

Rising

LDO2 is Disabled Below V UVLO

OUT

2.7

2.8

V

OUT_UVLO

2.9

V

LDO2_FB Regulated Output Voltage

LDO2_FB Line Regulation (Note 11)

LDO2_FB Load Regulation (Note 11)

Available Output Current

I

= 1mA

0.78

0.8

0.4

5

0.82

V

mV/V

μV/mA

mA

LDO2_FB

LDO2

= 1mA, V = 1.65V to 5.5V

IN

= 1mA to 150mA

l

I

150

LDO2_OC

Short-Circuit Output Current

270

mA

LDO2_SC

V

Dropout Voltage (Note 12)

I

= 150mA, V

= 3.6V

= 2.5V

160

200

170

260

320

280

mV

DROP2

LDO2

LDO1

INLDO2

= 75mA, V

= 1.8V

INLDO1

R

Output Pull-Down Resistance in Shutdown LDO2 Disabled

LDO_FB2 Input Current

14

kꢀ

nA

LDO2_PD

I

–50

50

LDO_FB2

357734fa

8

LTC3577-3/LTC3577-4

ELECTRICAL CHARACTERISTICS ^{Pushbutton Controller.}The l denotes the speciﬁcations which apply

over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_OUT= 3.8V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Pushbutton Pin (ON)

l

V

Pushbutton Operating Supply Range

(Note 9)

2.7

2.5

5.5

V

OUT

UVLO

V

Falling

Rising

Pushbutton is Disabled Below V

UVLO

2.7

2.8

V

OUT

2.9

1.2

V

ON Threshold Rising

ON Threshold Falling

0.8

0.7

V

ON_TH

0.4

I

ON

ON Input Current

V

ON

V

ON

= V

OUT

= 0V

–1

–4

1

–14

ꢁA

–9

Power-On Input Pin (PWR_ON)

V

PWR_ON Threshold Rising

PWR_ON Threshold Falling

0.8

0.7

1.2

1

V

PWR_ON

0.4

–1

I

PWR_ON Input Current

V

= 3V

ꢁA

PWR_ON

Status Output Pins (PBSTAT, EXTPWR, PGOOD)

I

PBSTAT Output High Leakage Current

PBSTAT Output Low Voltage

EXTPWR Pin Input Current

= 3V

–1

1

0.4

1

ꢁA

V

PBSTAT

V

I

= 3mA

0.1

0

PBSTAT

I

V

= 3V

ꢁA

V

EXTPWR

V

EXTPWR Pin Output Low Voltage

PGOOD Output High Leakage Current

PGOOD Output Low Voltage

I

= 2mA

0.15

0.4

1

EXTPWR

I

V

= 3V

–1

ꢁA

V

PGOOD

V

I

= 3mA

0.1

–8

0.4

PGOOD

V

PGOOD Threshold Voltage

(Note 13)

%

THPGOOD

Pushbutton Timing Parameters

t

ON Low Time to PBSTAT Low

ON High to PBSTAT High

50

900

50

14

1.8

1

ms

ꢁs

ON_PBSTAT1

ON_PBSTAT2

PBSTAT_PW

ON_PUP

PBSTAT Low > t

PBSTAT_PW

PBSTAT Minimum Pulse Width

ON Low Time for Power Up

40

12

ms

ON Low to PGOOD Reset Low

PGOOD Reset Low Pulse Width

Minimum Time from Power Up to Down

Minimum Time from Power Down to Up

PWR_ON High to Power Up

16.5

Seconds

ms

ON_RST

ON_RST_PW

PUP_PDN

Seconds

ms

1

PDN_PUP

50

1

PWR_ONH

PWR_ONL

PWR_ONBK1

PWR_ONBK2

PGOODH

PWR_ON Low to Power Down

PWR_ON Power-Up Blanking

PWR_ON Power-Down Blanking

From Regulation to PGOOD High

Bucks Disabled to PGOOD Low

LDO2 Enable to Buck Enable

ms

PWR_ON Low Recognized from Power Up

PWR_ON High Recognized from Power Down

Buck1, 2 and LDO1 Within PGOOD Threshold

Bucks Disabled

Seconds

ms

1

230

44

14.5

μs

PGOODL

12.5

17.5

ms

LDO2_BK1

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3577-3/LTC3577-4 are guaranteed to meet performance

speciﬁcations from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

Note 3: This IC includes over temperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 110°C when over temperature protection is

active. Continuous operation above the speciﬁed maximum operating

junction temperature may result in device degradation or failure.

Note 4: V is the greater of V , V

or BAT.

CC

BUS OUT

357734fa

9

LTC3577-3/LTC3577-4

ELECTRICAL CHARACTERISTICS

Note 5: Total input current is the sum of quiescent current, I

, and

BUSQ

Note 11: Measured with the LDO running unity gain with output tied to

measured current given by V

/R

• (h

+ 1).

feedback pin.

CLPROG CLPROG

CLPROG

Note 6: h

with indicated PROG resistor.

Note 7: The current limit features of this part are intended to protect the

IC from short term or intermittent fault conditions. Continuous operation

above the maximum speciﬁed pin current rating may result in device

degradation or failure.

is expressed as a fraction of measured full charge current

Note 12: Dropout voltage is the minimum input to output voltage

differential needed for an LDO to maintain regulation at a speciﬁed output

current. When an LDO is in dropout, its output voltage will be equal to

C/10

V

IN

– V

.

DROP

Note 13: PGOOD threshold is expressed as a percentage difference

from the Buck1, Buck2 and LDO1 regulation voltages. The threshold is

measured from Buck1, Buck2 and LDO1 output rising.

Note 8: The serial port is tested at rated operating frequency. Timing

parameters are tested and/or guaranteed by design.

Note 14: I

is the sum of V and V current due to LED driver.

OUT IN3

VOUT_LED

Note 9: V

Note 10: Buck FB high, not switching.

not in UVLO.

Note 15: The I

speciﬁcations represent the total battery load assuming

OUT

BATQ

V

, V

and V are tied directly to V

.

INLDO1 INLDO2 IN12

IN3

OUT

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

Input Supply Current vs

Temperature

Input Supply Current vs

Battery Drain Current vs

Temperature

Temperature (Suspend Mode)

0.10

0.08

0.06

0.04

0.02

0

450

400

350

300

250

200

150

100

50

0.8

ALL SUPPLIES ENABLED (EXCEPT BOOST)

PULSE-SKIP MODE

V

= 5V

V

BUS

= 5V

BUS

1x MODE

0.7

0.6

NO LOAD ON

ALL SUPPLIES

V

BAT

V

BUS

= 3.8V

= 0V

0.5

0.4

0.3

0.2

0.1

ALL SUPPLIES ENABLED

(EXCEPT BOOST)

Burst Mode OPERATION

ALL SUPPLIES DISABLED EXCEPT LDO1

25 75 100 125

50

TEMPERATURE (°C)

0

–25

0

50

75 100 125

–50 –25

0

25

50

75

125

–50

0

–50

25

100

–25

TEMPERATURE (°C)

357734 G01

357734 G02

357734 G03

Input Current Limit vs

Temperature

Charge Current vs Temperature

(Thermal Regulation)

Input R_ONvs Temperature

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

300

280

260

240

220

180

160

140

120

100

0

600

500

400

300

I

= 400mA

V

R

= 5V

CLPROG

OUT

BUS

= 2.1k

10x MODE

V

= 4.5V

BUS

V

= 5V

BUS

5x MODE

V

= 5.5V

BUS

200

100

0

V

= 5V

BUS

10x MODE

= 2k

1x MODE

R

PROG

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

–25

TEMPERATURE (°C)

357734 G06

357734 G04

357734 G05

357734fa

10

LTC3577-3/LTC3577-4

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

Battery Float Voltage Load

Regulation (LTC3577-3)

Battery Current and Voltage

vs Time

Battery Regulation (Float)

Voltage vs Temperature

600

500

400

300

200

100

0

6

5

4

3

2

1

0

4.24

4.22

4.24

4.22

4.20

4.18

4.16

4.14

4.12

4.10

4.08

4.06

4.04

V

= 5V

I

= 2mA

BAT

BUS

10x MODE

CHRG

LTC3577-3

V

BAT

4.20

4.18

4.16

4.14

4.12

4.10

SAFETY

TIMER

TERMINATION

LTC3577-4

1450mAhr

CELL

C/10

V

= 5V

BUS

PROG

R

= 2k

I

BAT

CLPROG

0

2

3

4

5

6

0

200

400

I

600

(mA)

800

1000

1

–50 –25

0

25

50

75 100 125

TIME (HOUR)

TEMPERATURE (°C)

BAT

357734 G07

357734 G08

357734 G09

Forward Voltage vs Ideal Diode

Current (No External FET)

I_BATvs V_BAT(LTC3577-3)

I_BATvs V_BAT(LTC3577-4)

600

500

400

300

200

100

0

600

500

400

300

200

100

0

0.25

0.20

0.15

0.10

V

T

= 0V

R

= 2.1k

BUS

A

CLPROG

PROG

= 25°C

= 2k

V

= 3.2V

BAT

V

= 5V

BUS

10x MODE

V

= 3.6V

BAT

V

BAT

= 4.2V

RISING

V

BAT

FALLING

V

BAT

V

= 5V

BUS

0.05

0

10x MODE

R

= 2k

PROG

CLPROG

= 2k

2.0

2.8

3.2

(V)

3.6

4.0

4.4

2.0

2.4

2.8

3.2

3.6

4.0

4.4

0

0.4

0.6

(A)

0.8

1.0

1.2

2.4

0.2

V

(V)

I

BAT

357734 G10

357734 G54

357734 G11

Forward Voltage vs Ideal Diode

Current (with Si2333DS External FET)

Input Connect Waveform

Input Disconnect Waveform

40

35

30

25

V

T

= 3.8V

= 0V

BAT

BUS

= 25°C

V

BUS

5V/DIV

A

V

OUT

5V/DIV

I

BUS

0.5A/DIV

20

15

I

BAT

0.5A/DIV

10

5

357734 G25

357734 G26

V

I

= 3.75V

= 100mA

= 2k

1ms/DIV

V

I

= 3.75V

= 100mA

= 2k

1ms/DIV

BAT

OUT

R

CLPROG

0

R

= 2k

R = 2k

PROG

0.2

0.4

I

0.8

0

1.0

0.6

(A)

BAT

357734 G12

357734fa

11

LTC3577-3/LTC3577-4

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

Switching from Suspend Mode to

5x Mode

WALL Connect Waveform

Switching from 1x to 5x Mode

I

WALL

5V/DIV

LIM0

5V/DIV

I

/I

LIM0 LIM1

5V/DIV

V

OUT

5V/DIV

I

WALL

BUS

0.5A/DIV

I

BAT

0.5A/DIV

357734 G27

357734 G28

357734 G29

V

I

= 3.75V

= 50mA

= 2k

1ms/DIV

V

I

= 3.75V

= 100mA

= 2k

100μs/DIV

V

I

= 3.75V

= 100mA

= 2k

1ms/DIV

BAT

OUT

BAT

OUT

BAT

OUT

R

CLPROG

PROG

R

= 2k

R

= 2k

PROG

I

= 5V

LIM1

Oscillator Frequency vs

Temperature

Step-Down Switching Regulator 1

3.3V Output Efﬁciency vs I_OUT1

WALL Disconnect Waveform

100

90

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

Burst Mode

OPERATION

WALL

5V/DIV

80

V

OUT

70

5V/DIV

PULSE SKIP

60

50

I

WALL

V

= 5V

OUT

0.5A/DIV

40

30

20

10

0

V

= 3.8V

OUT

I

BAT

0.5A/DIV

V

= 3.3V

OUT1

357734 G30

V

= 3.75V

1ms/DIV

BAT

OUT

V

= 3.8V

= 5V

IN12

I

= 100mA

V

R

= 2k

PROG

–50

0

25

50

75 100 125

–25

0.01

0.1

1

10

(mA)

100

1000

TEMPERATURE (°C)

I

OUT

357734 G14

357734 G13

Step-Down Switching Regulator 2

1.8V Output Efﬁciency vs I_OUT2

Step-Down Switching Regulator 3

1.2V Ooutput Efﬁciency vs I_OUT3

Step-Down Switching Regulator 3

2.5V Output Efﬁciency

100

90

100

90

100

90

Burst Mode

OPERATION

Burst Mode

OPERATION

Burst Mode

OPERATION

80

70

PULSE SKIP

60

50

60

50

60

50

PULSE SKIP

40

30

20

10

0

40

30

20

10

0

40

30

20

10

0

V

= 2.5V

= 3.8V

= 5V

V

= 1.8V

V

= 1.2V

= 3.8V

= 5V

OUT3

OUT2

OUT3

V

= 3.8V

= 5V

V

IN3

IN12

IN3

0.01

0.1

1

I

10

(mA)

100

1000

0.01

0.1

1

I

10

(mA)

100

1000

0.01

0.1

1

I

10

(mA)

100

1000

OUT

357734 G15

357734 G17

357734 G16

357734fa

12

LTC3577-3/LTC3577-4

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

Step-Down Switching Regulator

Output Transient (Burst Mode

Operation)

Step-Down Switching Regulator

Output Transient (Pulse Skip)

Step-Down Switching Regulator

Short-Circuit Current vs Temperature

1500

1400

1300

1200

1100

1000

900

V

OUT1

V

OUT1

50mV/DIV

(AC)

50mV/DIV

(AC)

V

OUT2

V

800mA BUCK

500mA BUCK

OUT2

50mV/DIV

(AC)

50mV/DIV

(AC)

V

OUT3

V

OUT3

100mV/DIV

(AC)

100mV/DIV

(AC)

800

500mA

I

OUT3

700

5mA

357734 G19

357734 G20

V

= 3.3V

= 10mA

= 1.8V

= 20mA

= 1.2V

50μs/DIV

V

= 3.3V

= 30mA

= 1.8V

= 20mA

= 1.2V

50μs/DIV

OUT1

V

= 3.8V

= 5V

INx

600

I

V

I

V

I

500

OUT2

V

OUT3

–25

0

50

75 100 125

–50

25

V

OUT3

TEMPERATURE (°C)

V

= V

= 3.8V

V

= V

= 3.8V

OUT

BAT

OUT

BAT

357734 G18

800mA Step-Down Switching

Regulator Feedback Voltage vs

Output Current

500mA Step-Down Switching

Regulator Feedback Voltage vs

Output Current

Step-Down Switching Regulator

Switch Impedance vs Temperature

0.85

0.84

0.83

0.82

0.81

0.80

0.79

0.78

0.77

0.76

0.75

0.85

0.84

0.83

0.82

0.81

0.80

0.79

0.78

0.77

0.76

0.75

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

V

= 3.2V

INX

500mA

PMOS

500mA

NMOS

Burst Mode

OPERATION

Burst Mode

OPERATION

PULSE SKIP

800mA PMOS

800mA NMOS

V

= 3.8V

V

= 3.8V

IN3

IN12

= 5V

0

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

–50 –25

0

25

125

50

75 100

I

OUT

TEMPERATURE (°C)

OUT

357732 G22

357734 G23

357734 G21

Step-Down Switching Regulator 3

Soft-Start and Shutdown

OVP Connection Waveform

OVP Protection Waveform

V

OUT1

100mV/DIV

(AC)

V

BUS

5V/DIV

V

BUS

2V

5V/DIV

1V

0V

V

OUT3

OVGATE

5V/DIV

OVGATE

5V/DIV

400mA

200mA

0mA

OVP

INPUT

I

L3

OVP

INPUT

VOLTAGE

5V TO 10V

STEP 5V/DIV

0V TO 5V

STEP 5V/DIV

357734 G31

357734 G24

357734 G32

500μs/DIV

V

= 1.8V

= 100mA

= 3ꢀ

50μs/DIV

500μs/DIV

OUT1

OUT3

I

R

357734fa

13

LTC3577-3/LTC3577-4

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

OVSENS Quiescent Current

vs Temperature

Rising Overvoltage Threshold

vs Temperature

OVP Reconnection Waveform

6.280

6.275

6.270

6.265

6.260

6.255

37

35

33

31

29

27

V

= 5V

OVSENS

V

BUS

5V/DIV

OVGATE

5V/DIV

OVP

INPUT

VOLTAGE

10V TO 5V

STEP 5V/DIV

357734 G33

500μs/DIV

–40

–15

10

35

60

85

–40

–15

10

35

60

85

TEMPERATURE (°C)

357734 G35

357734 G34

OVGATE vs OVSENS

LED Driver Efﬁciency 10 LEDs

LED Driver Efﬁciency 8 LEDs

90

85

80

75

70

65

60

55

50

12

10

OVSENS CONNECTED

TO INPUT THROUGH

6.2k RESISTOR

85

80

75

70

65

60

55

50

8

6

4

2

0

3V

3.6V

4.2V

4.8V

5.5V

3.6V

4.2V

4.8V

5.5V

0

2

4

6

8

I

10 12 14 16 18 20

(mA)

0

2

4

6

8

0

2

4

6

8

I

10 12 14 16 18 20

(mA)

INPUT VOLTAGE (V)

LED

357734 G38

357734 G36

357734 G39

DAC Code vs LED Current

LED Driver Efﬁciency 4 LEDs

LED Driver Efﬁciency 6 LEDs

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

70

60

50

40

30

20

10

3V

3.6V

4.2V

4.8V

5.5V

3.6V

4.2V

4.8V

5.5V

0dB = 20μA

60dB = 20mA

R

= 20kꢀ

LED_FS

0

2

4

6

8

I

10 12 14 16 18 20

(mA)

40

30

DAC CODE

60

70

0

2

4

6

8

I

10 12 14 16 18 20

(mA)

0

50

10

20

LED

357734 G40

357734 G50

357734 G41

357734fa

14

LTC3577-3/LTC3577-4

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C unless otherwise speciﬁed}

LED Boost Switch Impedance

vs Temperature

LED Boost Maximum Duty Cycle

vs Temperature

LED Boost Start-Up Transient

96.6

96.5

96.4

96.3

96.2

96.1

96.0

95.9

95.8

400

350

300

250

200

150

100

50

I

LED

10mA/DIV

V

BOOST

20V/DIV

I

3V

L

200mA/DIV

3.6V

4.2V

4.8V

5.5V

3V

3.6V

4.2V

5.5V

0

95.7

357734 G42

2ms/DIV

40 60

–40 –20

0

20

80 100 120 140

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

357734 G44

357734 G45

LED Boost Current Limit

vs Temperature

10-LED Driver Efﬁciency

LDO Load Step

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

90

80

70

60

50

40

30

20

10

0

LDO1

50mV/DIV

(AC)

MAX PWM

CONSTANT

CURRENT

LDO2

20mV/DIV

(AC)

100mA

I

OUT1

5mA

357734 G48

LDO1 = 1.2V

LDO2 = 2.5V

20μs/DIV

I

= 40mA

LDO2

OUT

V

= V

= 3.8V

–40 –20

0

20 40 60 80 100 120

TEMPERATURE (°C)

357734 G46

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

BAT

LED CURRENT (A)

357734 TA01b

Input and Battery Current vs

Output Current

Battery Discharge vs

Too Hot BAT Discharge

Temperature

200

180

160

140

120

100

80

600

500

400

300

200

100

0

200

R

= 2k

V

< V

TOO_HOT

= 0V

PROG

CLPROG

NTC

BUS

I

= 2k

IN

175

V

= 5V

= 0V

BUS

150

I

LOAD

125

100

75

I

BAT

(CHARGING)

60

50

V

= 4.1V

BAT

NTC

40

< V

TOO_HOT

5x MODE

25

I

20

BAT

I

= 0mA

VOUT

(DISCHARGING)

WALL = 0V

100

0

–100

0

600

3.8

3.9

4.0

(V)

4.1

4.2

60

70

90 100 110 120

0

200

300

(mA)

400

500

50

80

V

I

TEMPERATURE (°C)

BAT

OUT

357734 G49

357734 G37

357734 G51

357734fa

15

LTC3577-3/LTC3577-4

PIN FUNCTIONS

2

I

, I

LIM1

(Pins 1, 2): Input Current Control Pins. I

SCL (Pin 12): I C Clock Input. The logic level for SCL is

LIM0 LIM1 LIM0

and I

control the input current limit. See Table 1 in

referenced to DV .

CC

“USB PowerPath Controller” section. Both pins are pulled

low by a weak current sink.

OVGATE (Pin 13): Overvoltage Protection Gate 0utput.

Connect OVGATE to the gate pin of an external N-channel

MOS pass transistor. The source of the transistor should

LED_FS (Pin 3): A resistor between this pin and ground

sets the full-scale output current of the I

pin.

be connected to V

and the drain should be connected

LED

BUS

to the product’s DC input connector. In the absence of an

overvoltage condition, this pin is connected to an internal

charge pump capable of creating sufﬁcient overdrive to

fully enhance this transistor. If an overvoltage condition

is detected, OVGATE is brought rapidly to GND to prevent

damage. OVGATE works in conjunction with OVSENSE to

provide this protection.

WALL (Pin 4): Wall Adapter Present Input. Pulling this

pin above 4.3V will disconnect the power path from V

BUS

to V . The ACPR pin will also be pulled low to indicate

OUT

that a wall adapter has been detected.

SW3 (Pin 5): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 3 (Buck3).

V_IN3(Pin6):PowerInputforStep-DownSwitchingRegu-

PWR_ON(Pin14):LogicInputUsedtoKeepBuck1,Buck2

and LDO2 Enabled After Power Up. May also be used to

enable regulators directly (sequence = LDO2 → Buck1 →

Buck2). See “Pushbutton Interface Operation” section for

more information.

lator 3. This pin should be connected to V_OUT

.

FB3 (Pin 7): Feedback Input for Step-Down Switching

Regulator 3 (Buck3). This pin servos to a ﬁxed voltage of

0.8V when the control loop is complete.

ON (Pin 15): Pushbutton Input. A weak internal pull-up

forces ON high when left ﬂoating. A normally open push-

button is connected from ON to ground to force a low

state on this pin.

OVSENSE (Pin 8): Overvoltage Protection Sense Input.

OVSENSE should be connected through a 6.2k resistor

to the input power connector and the drain of an external

N-channel MOS pass transistor. When the voltage on

this pin exceeds a preset level, the OVGATE pin will be

pulled to GND to disable the pass transistor and protect

downstream circuitry.

PBSTAT (Pin 16): Open-drain output is a debounced

and buffered version of ON to be used for processor

interrupts.

LED_OV(Pin9):Aresistorbetweenthispinandtheboosted

LED backlight voltage sets the overvoltage limit on the

boostoutput.Iftheboostvoltageexceedstheprogrammed

limit the LED boost converter will be disabled.

EN3 (Pin 17): Enable Pin for Step-Down Switching

Regulator 3 (Buck3)

.

SW (Pins 18, 19, 20): Power Transmission (Switch)

Pin for LED Boost Converter. See “LED Backlight/Boost

Operation” section for circuit hook-up and component

2

DV (Pin 10): Supply Voltage for I C Lines. This pin sets

CC

2

the logic reference level of the LTC3577-3/LTC3577-4. A

selection. I C is used to control LED driver enable. I C

default is LED driver off.

UVLO circuit on the DV pin forces all registers to all

CC

0s whenever DV is <1V. Bypass to GND with a 0.1μF

CC

PGOOD(Pin21):Open-DrainOutput.PGOODindicatesthat

Buck1, Buck2 and LDO1 are within 8% of ﬁnal regulation

value. There is a 230ms delay from all regulators reaching

regulation and PGOOD going high.

capacitor.

2

SDA (Pin 11): I C Data Input. Serial data is shifted one bit

per clock to control the LTC3577-3/LTC3577-4. The logic

level for SDA is referenced to DV .

CC

357734fa

16

LTC3577-3/LTC3577-4

PIN FUNCTIONS

V

(Pin 32): Power Input for Step-Down Switching

I

(Pin 22): Series LED Backlight Current Sink Output.

IN12

LED

Regulators 1 and 2. This pin will generally be connected

This pin is connected to the cathode end of the series LED

backlightstring.ThecurrentdrawnthroughtheseriesLEDs

is programmed via a 6-bit 60dB DAC and can be further

to V

.

OUT

SW1 (Pin 33): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 1 (Buck1).

2

dimmedviaaninternalPWMfunction.I Cisusedtocontrol

LEDdriverenable, brightness, gradation(softon/softoff).

2

NTCBIAS (Pin 34): Output Bias Voltage for NTC. A

resistor from this pin to the NTC pin will bias the NTC

thermistor.

I C default is LED driver off, current = 0mA.

LDO1_FB (Pin 23): Feedback Voltage Input for Low Drop-

out Linear Regulator 1 (LDO1). LDO1 output voltage is

set using an external resistor divider between LDO1 and

LDO1_FB.

NTC (Pin 35): The NTC pin connects to a battery’s therm-

istor to determine if the battery is too hot or too cold

to charge. If the battery’s temperature is out of range,

charging is paused until it drops back into range. A low

drift bias resistor is required from NTCBIAS to NTC and

a thermistor is required from NTC to ground.

LDO2_FB (Pin 24): Feedback Voltage Input for Low Drop-

out Linear Regulator 2 (LDO2). LDO2 output voltage is

set using an external resistor divider between LDO2 and

LDO2_FB.

PROG (Pin 36): Charge Current Program and Charge

Current Monitor Pin. Connecting a resistor from PROG

to ground programs the charge current:

FB2 (Pin 25): Feedback Input for Step-Down Switching

Regulator 2 (Buck2). This pin servos to a ﬁxed voltage of

0.8V when the control loop is complete.

1000V

R_PROG

FB1 (Pin 26): Feedback Input for Step-Down Switching

Regulator 1 (Buck1). This pin servos to a ﬁxed voltage of

0.8V when the control loop is complete.

I_CHG

=

A

( )

If sufﬁcient input power is available in constant-current

mode, this pin servos to 1V. The voltage on this pin always

represents the actual charge current.

V

(Pin 27): Input Supply of Low Dropout Linear

INLDO1

Regulator1(LDO1).Thispinshouldbebypassedtoground

with a 1μF or greater ceramic capacitor.

IDGATE (Pin 37): Ideal Diode Gate Connection. This

pin controls the gate of an optional external P-channel

MOSFET transistor used to supplement the internal ideal

diode. The source of the P-channel MOSFET should be

connected to V

BAT. It is important to maintain high impedance on this

pin and minimize all leakage paths.

LDO1(Pin28):OutputofLowDropoutLinearRegulator 1.

LDO1 is an always-on LDO and will be enabled whenever

the part is not in V

UVLO. This pin must be bypassed

OUT

and the drain should be connected to

OUT

to ground with a 1μF or greater ceramic capacitor.

LDO2(Pin29):OutputofLowDropoutLinearRegulator 2.

This pin must be bypassed to ground with a 1μF or greater

ceramic capacitor.

BAT (Pin 38): Single Cell Li-Ion Battery Pin. Depending

on available power and load, a Li-Ion battery on BAT will

either deliver system power to V

diode or be charged from the battery charger.

V

(Pin 30): Input Supply of Low Dropout Linear

INLDO2

through the ideal

OUT

Regulator2(LDO2).Thispinshouldbebypassedtoground

with a 1μF or greater ceramic capacitor.

SW2 (Pin 31): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 2 (Buck2).

357734fa

17

LTC3577-3/LTC3577-4

PIN FUNCTIONS

V

(Pin39):OutputVoltageofthePowerPathController

signalWALLpresent, WALLmustexceedtheabsoluteand

OUT

and Input Voltage of the Battery Charger. The majority of

differential WALL input thresholds. The EXTPWR signal is

the portable product should be powered from V . The

independentoftheI

andI

pins. Thus, itispossible

OUT

LIM1

LIM0

LTC3577-3/LTC3577-4 will partition the available power

to have the input current limit circuitry in suspend with

EXTPWR showing a valid charging level on V

between the external load on V

and the internal battery

.

OUT

BUS

charger. Priority is given to the external load and any extra

CLPROG (Pin 43): Input Current Program and Input

Current Monitor Pin. A resistor from CLPROG to ground

determines the upper limit of the current drawn from the

power is used to charge the battery. An ideal diode from

BAT to V

ensures that V

is powered even if the load

OUT

exceeds the allotted input current from V

or if the V

BUS

V

pin (i.e., the input current limit). A precise fraction

BUS

power source is removed. V

should be bypassed with

OUT

of the input current, h

, is sent to the CLPROG pin.

CLPROG

a low impedance multilayer ceramic capacitor.

The input PowerPath delivers current until the CLPROG

pin reaches 2V (10x mode), 1V (5x mode) or 0.2V (1x

V

BUS

(Pin 40): USB Input Voltage. V will usually be

BUS

connected to the USB port of a computer or a DC output

mode). Therefore, the current drawn from V

will be

. In

BUS

wall adapter. V

ance multilayer ceramic capacitor.

should be bypassed with a low imped-

limited to an amount given by h

USB applications the resistor R

no less than 2.1k.

and R

BUS

CLPROG

should be set to

ACPR(Pin41):WallAdapterPresentOutput(ActiveLow).

A low on this pin indicates that the wall adapter input com-

parator has had its input pulled above its input threshold

(typically 4.3V). This pin can be used to drive the gate of

an external P-channel MOSFET to provide power to V

from a power source other than a USB port.

CHRG (Pin 44): Open-Drain Charge Status Output. The

CHRG pin indicates the status of the battery charger. If

CHRG is high then the charger is near the ﬂoat voltage

(charge current less than 1/10th programmed charge cur-

rent)orchargingiscompleteandchargerisdisabled.Alow

on CHRG indicates that the charger is enabled. For more

information see the “Charge Status Indication” section.

OUT

EXTPWR (Pin 42): External Power Present Output (Active

Low, Open-Drain Output). A low on this pin indicates that

externalpowerispresentateithertheV

For EXTPWR to signal V

the V

orWALLinput.

present, V must exceed

BUS

Exposed Pad (Pin 45): Ground. The exposed package pad

is ground and must be soldered to the PC board for proper

functionality and for maximum heat transfer.

BUS

undervoltage lockout threshold. For EXTPWR to

BUS

357734fa

18

LTC3577-3/LTC3577-4

BLOCK DIAGRAM

8

13

42

EXTPWR

4

41

OVSENS

OVGATE

WALL

ACPR

OVERVOLTAGE

PROTECTON

EXTERNAL

POWER DETECT

WALL

DETECT

V

OUT

BUS

40

43

39

37

+

–

IDGATE

INPUT

CURRENT

LIMIT

CC/CV

IDEAL

DIODE

CLPROG

CHARGER

–

+

NTCBIAS

NTC

15mV

34

35

BATTERY

TEMP

BAT

OVERTEMP BATTERY

SAFETY DISCHARGER

38

36

MONITOR

PROG

UVLO

I

LIM0

LIM1

1

2

I

LIM

V

INLD02

LDO2

LOGIC

EN

30

–

+

0.8V

CHRG

14ms

RISING

DELAY

150mA

LDO2

44

29

24

CHARGE

STATUS

LDO2_FB

V

IN12

EN

32

33

500mA, 2.25MHz

BUCK REGULATOR 1

PWR_ON

ON

SW1

FB1

14

PUSH-

BUTTON

INPUT

0.8V

+

15

16

–

PBSTAT

PG

EN

26

31

EN3

17

DV

CC

500mA, 2.25MHz

BUCK REGULATOR 2

10

11

12

2

SDA

I C

SW2

FB2

LOGIC

0.8V

+

SCL

–

PGOOD

21

PG

EN

25

6

230ms FALLING

DELAY

V

IN3

800mA, 2.25MHz

BUCK REGULATOR 3

LED_OV

SW3

9

40V LED BACKLIGHT

BOOST CONVERTER

5

0.8V

+

SW

18,19,20

–

FB3

7

DAC

V

INLD01

ENB

PG

27

–

+

I

0.8V

LED

0.8V

22

3

LDO1

LED_FS

28

23

150mA

LDO1

LDO1_FB

GND

45

357734 BD

357734fa

19

LTC3577-3/LTC3577-4

OPERATION

PowerPath OPERATION

current speciﬁcation. The ideal diode from BAT to V

guarantees that ample power is always available to V

OUT

Introduction

even if there is insufﬁcient or absent power at V . The

BUS

LTC3577-3/LTC3577-4 also have the ability to receive

power from a wall adapter or other non-current-limited

power source. Such a power supply can be connected

The LTC3577-3/LTC3577-4 are highly integrated power

management IC that includes the following features:

– PowerPath controller

– Battery charger

– Ideal diode

– Input overvoltage protection

– Pushbutton controller

– Three step-down switching regulators

– Two low dropout linear regulators

– 40V LED backlight controller

to the V

pin of the LTC3577-3/LTC3577-4 through an

OUT

external device such as a power Schottky or FET as shown

in Figure 1. The LTC3577-3/LTC3577-4 have the unique

ability to use the output, which is powered by an external

supply, to charge the battery while providing power to

the load. A comparator on the WALL pin is conﬁgured to

detect the presence of the wall adapter and shut off the

connection to the USB. This prevents reverse conduction

from V

to V

when a wall adapter is present.

OUT

BUS

The LTC3577-3/LTC3577-4 also include a pushbutton

inputtocontrolthepowersequencingoftwosynchronous

step-down switching regulators (Buck1 and Buck2), a low

dropout regulator (LDO2) and system reset. The three

DesignedspeciﬁcallyforUSBapplications,thePowerPath

controller incorporates a precision input current limit

which communicates with the battery charger to ensure

that input current does not violate the USB average input

FROM AC ADAPTER

4.3V

–

+

(RISING)

3.2V

(FALLING)

WALL

4

ACPR

41

+

–

75mV (RISING)

+

–

25mV (FALLING)

FROM

ENABLE

V

OUT

USB

BUS

OUT

40

39

37

SYSTEM

LOAD

USB CURRENT LIMIT

IDEAL

DIODE

OPTIONAL

EXTERNAL

IDEAL DIODE

PMOS

+

–

IDGATE

CONSTANT-CURRENT

CONSTANT-VOLTAGE

BATTERY CHARGER

–

+

15mV

BAT

38

+

Li-Ion

357734 F01

Figure 1. Simpliﬁed PowerPath Block Diagram

357734fa

20

LTC3577-3/LTC3577-4

OPERATION

2.25MHz constant frequency current mode step-down

switching regulators provide 500mA, 500mA and 800mA

each and support 100% duty cycle operation as well as

operating in Burst Mode operation for high efﬁciency at

light load. No external compensation components are

requiredfortheswitchingregulators.Thetwolowdropout

regulators can output up to 150mA.

CLPROG to GND, the voltage on CLPROG represents the

input current:

V_CLPROG

R_CLPROG

I_VBUS= I_BUSQ

+

•h_CLPROG

where I

and h

are given in the Electrical

CLPROG

BUSQ

Characteristics table.

The onboard LED backlight boost circuitry can drive up

to 10 series LEDs and includes versatile digital dimming

via the I C input. The I C input also provides additional

regulator controls as well as status read-back.

TheinputcurrentlimitisprogrammedbytheI

andI

LIM0

LIM1

pins.TheLTC3577-3/LTC3577-4canbeconﬁguredtolimit

input current to one of several possible settings as well as

be deactivated (USB suspend). The input current limit will

be set by the appropriate servo voltage and the resistor on

CLPROG according to the following expression:

2

All regulators can be programmed for a minimum output

voltage of 0.8V and can be used to power a microcon-

troller core, microcontroller I/O, memory or other logic

circuitry.

0.2V

R_CLPROG

I_VBUS= I_BUSQ

+

•h_CLPROG1x Mode

(

)

USB PowerPath Controller

1V

R_CLPROG

•h_CLPROG5x Mode

(

)

The input current limit and charge control circuits of the

LTC3577-3/LTC3577-4 are designed to limit input current

as well as control battery charge current as a function of

2V

R_CLPROG

•h_CLPROG10x Mode

(

)

I

. V

drives the combination of the external load,

VOUT OUT

the three step-down switching regulators, two LDOs, LED

backlight and the battery charger.

Under worst-case conditions, the USB speciﬁcation for

average input current will not be violated with an R

CLPROG

If the combined load does not exceed the programmed

resistor of 2.1k or greater. Table 1 shows the available

settings for the I and I pins:

inputcurrentlimit,V

willbeconnectedtoV

through

OUT

BUS

LIM0

LIM1

an internal 200mꢀ P-channel MOSFET. If the combined

load at V exceeds the programmed input current limit,

Table 1. Controlled Input Current Limit

OUT

the battery charger will reduce its charge current by the

amountnecessarytoenabletheexternalloadtobesatisﬁed

while maintaining the programmed input current. Even if

the battery charge current is set to exceed the allowable

USB current, the average input current USB speciﬁcation

I

BUS(LIM)

LIM1

LIM0

1

100mA (1x)

1A (10x)

1

0

1

0

Suspend

500mA (5x)

will not be violated. Furthermore, load current at V

OUT

Notice that when I

is low and I

is high, the input

LIM0

LIM1

will always be prioritized and only excess available cur-

rent will be used to charge the battery. The current out

current limit is set to a higher current limit for increased

charging and current availability at V . This mode is

OUT

of the CLPROG pin is a fraction (1/h

) of the V

BUS

CLPROG

typically used when there is a higher power, non-USB

current. When a programming resistor is connected from

source available at the V

pin.

BUS

357734fa

21

LTC3577-3/LTC3577-4

OPERATION

Ideal Diode from BAT to V

Using the WALL Pin to Detect the Presence of an

External Power Source

OUT

The LTC3577-3/LTC3577-4 have an internal ideal diode as

wellasacontrollerforanoptionalexternalidealdiode.Both

the internal and the external ideal diodes respond quickly

The WALL input pin can be used to identify the presence

of an external power source (particularly one that is not

whenever V

drops below BAT. If the load increases

subject to a ﬁxed current limit like the USB V

input).

OUT

BUS

beyond the input current limit, additional current will be

Typically, such a power supply would be a 5V wall adapter

output or the low voltage output of a high voltage buck

regulator. When the wall adapter output (or buck regulator

output)isconnecteddirectlytotheWALLpin,andthevolt-

age exceeds the WALL pin threshold, the USB power path

pulledfromthebatteryviatheidealdiodes.Furthermore,if

power to V

(USB) or V

(external wall power or high

BUS

OUT

voltage regulator) is removed, then all of the application

power will be provided by the battery via the ideal diodes.

The ideal diodes are fast enough to keep V

from drop-

(from V

to V ) will be disconnected. Furthermore,

OUT

BUS

OUT

ping signiﬁcantly below V with just the recommended

the ACPR pin will be pulled low. In order for the presence

of an external power supply to be acknowledged, both of

the following conditions must be satisﬁed:

BAT

output capacitor (see Figure 2). The ideal diode consists

of a precision ampliﬁer that enables an on-chip P-channel

MOSFET whenever the voltage at V

is approximately

OUT

1. The WALL pin voltage must exceed approximately

4.3V.

15mV (V ) below the voltage at BAT. The resistance of

FWD

the internal ideal diode is approximately 200mꢀ. If this is

sufﬁcientfortheapplication,thennoexternalcomponents

are necessary. However, if lower resistance is needed, an

external P-channel MOSFET can be added from BAT to

2. TheWALLpinvoltagemustbegreaterthan75mVabove

the BAT pin voltage.

The input power path (between V

and V ) is re-

OUT

BUS

V

. TheIDGATEpinoftheLTC3577-3/LTC3577-4drives

OUT

enabled and the ACPR pin is pulled high when either of

the gate of the external P-channel MOSFET for automatic

the following conditions is met:

ideal diode control. The source of the MOSFET should be

connected to V

1. The WALL pin voltage falls to within 25mV of the BAT

pin voltage.

and the drain should be connected to

OUT

BAT. Capable of driving a 1nF load, the IDGATE pin can

control an external P-channel MOSFET having extremely

low on-resistance.

2. The WALL pin voltage falls below 3.2V.

Each of these thresholds is suitably ﬁltered in time to

prevent transient glitches on the WALL pin from falsely

triggering an event.

4.0V

V

3.8V

3.6V

OUT

Suspend Mode

500mA

When I

is pulled high and I

is pulled low the

LIM0

LIM1

CHARGE

LTC3577-3/LTC3577-4 enters suspend mode to comply

with the USB speciﬁcation. In this mode, the power path

I

0

BAT

DISCHARGE

–500mA

1A

between V

and V

is put in a high impedance state

BUS

OUT

I

VOUT

LOAD

to reduce the V

input current to 50ꢁA. If no other

BUS

0A

357734 F02

power source is available to drive WALL and V , the

V

= 3.8V

= 5V

10μs/DIV

BAT

BUS

5x MODE

OUT

system load connected to V

is supplied through the

OUT

C

= 10μF

OUT

ideal diodes connected to BAT.

Figure 2. Ideal Diode Transient Response

357734fa

22

LTC3577-3/LTC3577-4

OPERATION

BUS

Current Limit (UVCL)

V

Undervoltage Lockout (UVLO) and Undervoltage

detects that it has entered constant voltage mode, the

four hour safety timer is started. After the safety timer

expires, charging of the battery will terminate and no

more current will be delivered.

An internal undervoltage lockout circuit monitors V

and keeps the input current limit circuitry off until V

BUS

rises above the rising UVLO threshold (3.8V) and at least

50mV above V . Hysteresis on the UVLO turns off the

Automatic Recharge

OUT

After the battery charger terminates, it will remain off

drawing only microamperes of current from the battery.

If the portable product remains in this state long enough,

thebatterywilleventuallyselfdischarge.Toensurethatthe

battery is always topped off, a charge cycle will automati-

inputcurrentlimitifV

dropsbelow3.7Vor50mVbelow

BUS

V

. When this happens, system power at V

will be

OUT

drawn from the battery via the ideal diode. To minimize the

possibility of oscillation in and out of UVLO when using

resistive input supplies, the input current limit is reduced

cally begin when the battery voltage falls below V

as V

falls below 4.45V (typ).

RECHRG

BUS

(typically 4.1V for LTC3577-3 and 4V for LTC3577-4). In

Battery Charger

the event that the safety timer is running when the battery

voltage falls below V

, the timer will reset back to

RECHRG

The LTC3577-3/LTC3577-4 include a constant-current/

constant-voltagebatterychargerwithautomaticrecharge,

automatic termination by safety timer, low voltage trickle

charging,badcelldetectionandthermistorsensorinputfor

outoftemperaturechargepausing. Whenabatterycharge

cycle begins, the battery charger ﬁrst determines if the

batteryisdeeplydischarged.Ifthebatteryvoltageisbelow

zero. To prevent brief excursions below V

from re-

RECHRG

setting the safety timer, the battery voltage must be below

formorethan1.3ms. Thechargecycleandsafety

V

RECHRG

timerwillalsorestartiftheV

UVLOcycleslowandthen

BUS

high (e.g., V , is removed and then replaced).

BUS

Charge Current

V , typically 2.85V, an automatic trickle charge feature

TRKL

The charge current is programmed using a single resistor

from PROG to ground. 1/1000th of the battery charge cur-

rent is delivered to PROG which will attempt to servo to

1.000V. Thus, the battery charge current will try to reach

1000 times the current in the PROG pin. The program

resistor and the charge current are calculated using the

following equations:

setsthebatterychargecurrentto10%oftheprogrammed

value. If the low voltage persists for more than 1/2 hour,

the battery charger automatically terminates. Once the

battery voltage is above 2.85V, the battery charger begins

charginginfullpowerconstant-currentmode. Thecurrent

delivered to the battery will try to reach 1000V/R

.

PROG

Depending on available input power and external load

conditions, the battery charger may or may not be able to

charge at the full programmed rate. The external load will

always be prioritized over the battery charge current. The

USB current limit programming will always be observed

and only additional current will be available to charge the

battery. When system loads are light, battery charge cur-

rent will be maximized.

1000V

I_CHG

1000V

R_PROG

=

, I_CHG=

Ineithertheconstant-currentorconstant-voltagecharging

modes, the PROG pin voltage will be proportional to the

actual charge current delivered to the battery. Therefore,

the actual charge current can be determined at any time

by monitoring the PROG pin voltage and using the fol-

lowing equation:

Charge Termination

The battery charger has a built-in safety timer. When the

battery voltage approaches the ﬂoat voltage, the charge

current begins to decrease as the LTC3577-3/LTC3577-4

enters constant-voltage mode. Once the battery charger

V_PROG

R_PROG

I_BAT

=

•1000

357734fa

23

LTC3577-3/LTC3577-4

OPERATION

In many cases, the actual battery charge current, I , will

Battery Charger Stability Considerations

BAT

belowerthanI

duetolimitedinputcurrentavailableand

CHG

TheLTC3577-3/LTC3577-4’sbatterychargercontainsboth

a constant-voltage and a constant-current control loop.

The constant-voltage loop is stable without any compen-

sation when a battery is connected with low impedance

leads. Excessive lead length, however, may add enough

series inductance to require a bypass capacitor of at least

1μF from BAT to GND. Furthermore, a 4.7μF capacitor in

series with a 0.2Ω to 1Ω resistor from BAT to GND is

required to keep ripple voltage low when the battery is

disconnected.

prioritization with the system load drawn from V

.

OUT

Thermal Regulation

To prevent thermal damage to the IC or surrounding

components, an internal thermal feedback loop will

automatically decrease the programmed charge current

if the die temperature rises to approximately 110°C.

Thermal regulation protects the LTC3577-3/LTC3577-4

from excessive temperature due to high power operation

or high ambient thermal conditions and allows the user

to push the limits of the power handling capability with a

given circuit board design without risk of damaging the

LTC3577-3/LTC3577-4orexternalcomponents.Thebeneﬁt

oftheLTC3577-3/LTC3577-4thermalregulationloopisthat

charge current can be set according to actual conditions

rather than worst-case conditions with the assurance that

the battery charger will automatically reduce the current

in worst-case conditions.

High value, low ESR multilayer ceramic chip capacitors

reduce the constant-voltage loop phase margin, possibly

resulting in instability. Ceramic capacitors up to 22μF may

beusedinparallelwithabattery,butlargerceramicsshould

be decoupled with 0.2Ω to 1Ω of series resistance.

In constant-current mode, the PROG pin is in the feed-

back loop rather than the battery voltage. Because of the

additional pole created by any PROG pin capacitance,

capacitance on this pin must be kept to a minimum. With

no additional capacitance on the PROG pin, the battery

charger is stable with program resistor values as high

as 25k. However, additional capacitance on this node

reduces the maximum allowed program resistor. The pole

frequency at the PROG pin should be kept above 100kHz.

Therefore, if the PROG pin has a parasitic capacitance,

Charge Status Indication

The CHRG pin indicates the status of the battery charger.

An open-drain output, the CHRG pin can drive an indica-

tor LED through a current limiting resistor for human

interfacing or simply a pull-up resistor for microproces-

sor interfacing. When charging begins, CHRG is pulled

low and remains low for the duration of a normal charge

cycle. When charging is complete, i.e., the charger enters

constantvoltagemodeandthechargecurrenthasdropped

to one-tenth of the programmed value, the CHRG pin is

released (high impedance). The CHRG pin does not re-

spond to the C/10 threshold if the LTC3577-3/LTC3577-4

areininputcurrentlimit.Thispreventsfalseend-of-charge

indicationsduetoinsufﬁcientpoweravailabletothebattery

charger. Even though charging is stopped during an NTC

fault the CHRG pin will stay low indicating that charging

is not complete.

C

, the following equation should be used to calculate

PROG

the maximum resistance value for R

:

PROG

1

R_PROG

≤

2π •100kHz •C_PROG

NTC Thermistor and Battery Voltage Reduction

The battery temperature is measured by placing a nega-

tive temperature coefﬁcient (NTC) thermistor close to

the battery pack. To use this feature connect the NTC

357734fa

24

LTC3577-3/LTC3577-4

OPERATION

thermistor, R , between the NTC pin and ground and a

(for a Vishay “Curve 1” thermistor, this corresponds to

approximately 50°C) the NTC enables circuitry to moni-

tor the battery voltage. If the battery voltage is above the

battery discharge threshold (about 3.9V) then the battery

dischargecircuitryisenabledanddrawsabout140mAfrom

NTC

bias resistor, R

, from NTCBIAS to NTC. R

should

NOM

be a 1% resistor with a value equal to the value of the

chosen NTC thermistor at 25°C (R25). The LTC3577-3/

LTC3577-4 will pause charging when the resistance of the

NTC thermistor drops to 0.54 times the value of R25 or

approximately 54k (for a Vishay “Curve 1” thermistor, this

correspondstoapproximately40°C).Ifthebatterycharger

is in constant voltage (ﬂoat) mode, the safety timer also

pauses until the thermistor indicates a return to a valid

temperature. As the temperature drops, the resistance

of the NTC thermistor rises. The LTC3577-3/LTC3577-4

are also designed to pause charging when the value of

the NTC thermistor increases to 3.25 times the value of

R25. For a Vishay “Curve 1” thermistor this resistance,

325k, correspondstoapproximately0°C. Thehotandcold

comparators each have approximately 3°C of hysteresis

to prevent oscillation about the trip point. The typical NTC

circuit is shown in Figure 3.

the battery when V

= 0V and about 180mA when V

BUS

= 5V. The battery discharge current is disabled below the

battery discharge threshold.

When the charger is disabled an internal watchdog timer

samples the NTC thermistor for about 150μs every 150ms

and will enable the battery monitoring circuitry if the bat-

tery temperature exceeds the NTC TOO_HOT threshold.

If adding a capacitor to the NTC pin for ﬁltering the time

constant must be much less than 150μs so that the NTC

pin can settle to its ﬁnal value during the sampling period.

A time constant less than 10μs is recommended. Once

the battery monitoring circuitry is enabled it will remain

enabledandmonitoringthebatteryvoltageuntilthebattery

temperature falls back below the discharge temperature

threshold. The battery discharge circuitry is only enabled

if the battery voltage is greater than the battery discharge

threshold.

To improve safety and reliability the battery voltage is re-

ducedwhenthebatterytemperaturebecomesexcessively

high. When the resistance of the NTC thermistor drops to

about 0.35 times the value of R25 or approximately 35k

NTCBIAS

34

LTC3577-3/

NTC BLOCK

LTC3577-4

0.76 • NTCBIAS

R

NOM

–

100k

TOO_COLD

NTC

35

+

R

NTC

100k

–

TOO_HOT

0.35 • NTCBIAS

0.26 • NTCBIAS

+

BATTERY

OVERTEMP

–

357734 F03

Figure 3. Typical NTC Thermistor Circuit

357734fa

25

LTC3577-3/LTC3577-4

OPERATION

Alternate NTC Thermistors and Biasing

NTC thermistors have temperature characteristics which

areindicatedonresistance-temperatureconversiontables.

TheVishay-DalethermistorNTHS0603N011-N1003F,used

in the following examples, has a nominal value of 100k

and follows the Vishay “Curve 1” resistance-temperature

characteristic.

The LTC3577-3/LTC3577-4 provide temperature qualiﬁed

charging if a grounded thermistor and a bias resistor are

connected to NTC. By using a bias resistor whose value is

equal to the room temperature resistance of the thermis-

tor (R25) the upper and lower temperatures are pre-pro-

grammed to approximately 40°C and 0°C, respectively

(assuming a Vishay “Curve 1” thermistor).

In the explanation below, the following notation is used.

R25 = Value of the thermistor at 25°C

The upper and lower temperature thresholds can be ad-

justed by either a modiﬁcation of the bias resistor value

or by adding a second adjustment resistor to the circuit.

If only the bias resistor is adjusted, then either the upper

or the lower threshold can be modiﬁed but not both. The

other trip point will be determined by the characteristics

of the thermistor. Using the bias resistor in addition to an

adjustmentresistor,boththeupperandthelowertempera-

ture trip points can be independently programmed with

the constraint that the difference between the upper and

lowertemperaturethresholdscannotdecrease.Examples

of each technique are given below.

R

= Value of thermistor at the cold trip point

= Value of the thermistor at the hot trip

NTC|COLD

NTC|HOT

point

r

= Ratio of R

to R25

COLD

NTC|COLD

= Ratio of R

to R25

HOT

NTC|HOT

R

NOM

= Primary thermistor bias resistor (see Figure 3)

R1 = Optional temperature range adjustment resistor

(see Figure 4)

NTCBIAS

34

LTC3577-3/

LTC3577-4

NTC BLOCK

0.76 • NTCBIAS

R

NOM

–

+

105k

TOO_COLD

NTC

35

R1

12.7k

–

+

R

NTC

TOO_HOT

100k

0.35 • NTCBIAS

0.26 • NTCBIAS

+

–

BATTERY

OVERTEMP

357734 F04

Figure 4. NTC Thermistor Circuit with Additional Bias Resistor

357734fa

26

LTC3577-3/LTC3577-4

OPERATION

ThetrippointsfortheLTC3577-3/LTC3577-4’stemperature

where r

and r

are the resistance ratios at the

COLD

HOT

qualiﬁcation are internally programmed at 0.35 • V

for

desired hot and cold trip points. Note that these equations

are linked. Therefore, only one of the two trip points can

be chosen, the other is determined by the default ratios

designed in the IC.

NTC

the hot threshold and 0.76 • V

for the cold threshold.

NTC

Therefore, the hot trip point is set when:

R_NTC|HOT

Consider an example where a 60°C hot trip point is

desired. From the Vishay Curve 1 R-T characteristics,

•NTCBIAS = 0.35 •NTCBIAS

R_NOM+R_NTC|HOT

r

is 0.2488 at 60°C. Using the above equation, R

HOT

NOM

and the cold trip point is set when:

R_NTC|COLD

should be set to 46.4k. With this value of R

, the cold

NOM

trip point is about 16°C. Notice that the span is now 44°C

rather than the previous 40°C. This is due to the decrease

in “temperature gain” of the thermistor as absolute tem-

perature increases.

•NTCBIAS = 0.76 •NTCBIAS

R_NOM+R_NTC|COLD

SolvingtheseequationsforR

in the following:

andR

results

NTC|COLD

NTC|HOT

The upper and lower temperature trip points can be inde-

pendentlyprogrammedbyusinganadditionalbiasresistor

as shown in Figure 4. The following formulas can be used

R

= 0.538 • R

NTC|HOT

NOM

to compute the values of R

and R1:

and

NOM

r_COLD–r_HOT

R

= 3.17 • R

NTC|COLD

NOM

R_NOM

=

•R25

2.714

By setting R

equal to R25, the above equations result

NOM

in r

= 0.538 and r

= 3.17. Referencing these ratios

HOT

COLD

R1= 0.536 •R_NOM–r_HOT•R25

to the Vishay Resistance-Temperature Curve 1 chart gives

a hot trip point of about 40°C and a cold trip point of about

0°C. The difference between the hot and cold trip points

is approximately 40°C.

For example, to set the trip points to 0°C and 45°C with

a Vishay Curve 1 thermistor choose:

3.266 – 0.4368

R_NOM

=

•100k = 104.2k

By using a bias resistor, R

, different in value from R25,

NOM

2.714

the hot and cold trip points can be moved in either direc-

tion. The temperature span will change somewhat due to

the non-linear behavior of the thermistor. The following

equations can be used to easily calculate a new value for

the bias resistor:

the nearest 1% value is 105k.

R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k

the nearest 1% value is 12.7k. The ﬁnal solution is shown

in Figure 4 and results in an upper trip point of 45°C and

a lower trip point of 0°C.

r_HOT

0.538

R_NOM

=

•R25

r

^COLD•R25

3.17

357734fa

27

LTC3577-3/LTC3577-4

OPERATION

Overvoltage Protection (OVP)

√P

• 6.2k = 24V applied across its terminals. With the

MAX

6VatOVSENS,themaximumovervoltagemagnitudethat

this resistor can withstand is 30V. A 1/4W 6.2k resistor

raises this value to 45V.

The LTC3577-3/LTC3577-4 can protect themselves from

the inadvertent application of excessive voltage to V

or

BUS

WALL with just two external components: an N-channel

FET and a 6.2k resistor. The maximum safe overvoltage

magnitude will be determined by the choice of the external

NMOS and its associated drain breakdown voltage.

The charge pump output on OVGATE has limited output

drive capability. Care must be taken to avoid leakage on

this pin, as it may adversely affect operation.

The overvoltage protection module consists of two pins.

Theﬁrst,OVSENS,isusedtomeasuretheexternallyapplied

voltagethroughanexternalresistor.Thesecond,OVGATE,

is an output used to drive the gate pin of an external FET.

The voltage at OVSENS will be lower than the OVP input

Dual Input Overvoltage Protection

It is possible to protect both V

and WALL from

BUS

overvoltage damage with several additional components,

as shown in Figure 5. Schottky diodes D1 and D2 pass the

larger of V1 and V2 to R1 and OVSENS. If either V1 or V2

voltage by (I

• 6.2kΩ) due to the OVP circuit’s

OVSENS

exceeds 6V plus V , OVGATE will be pulled to

F(SCHOTTKY)

quiescent current. The OVP input will be 200mV to 400mV

higher than OVSENS under normal operating conditions.

When OVSENS is below 6V, an internal charge pump will

drive OVGATE to approximately 1.88 • OVSENS. This will

enhance the N-channel FET and provide a low impedance

GND and both the WALL and USB inputs will be protected.

Each input is protected up to the drain-source breakdown,

BVDSS, of MN1 and MN2. R1 must also be rated for the

power dissipated during maximum overvoltage. See the

“OvervoltageProtection”sectionforanexplanationofthis

calculation. Table 2 shows some NMOS FETs that maybe

suitable for overvoltage protection.

connection to V

or WALL which will, in turn, power

BUS

the LTC3577-3/LTC3577-4. If OVSENS should rise above

6V (6.35V OVP input) due to a fault or use of an incorrect

wall adapter, OVGATE will be pulled to GND, disabling the

external FET to protect downstream circuitry. When the

voltage drops below 6V again, the external FET will be

re-enabled.

Table 2. Recommended Overvoltage FETs

NMOS FET

Si1472DH

BVDSS

30V

R

PACKAGE

SC70-6

SOT-23

ON

82mΩ

60mΩ

65mΩ

80mΩ

35mΩ

Si2302ADS

Si2306BDS

Si2316BDS

IRLML2502

20V

In an overvoltage condition, the OVSENS pin will be

clamped at 6V. The external 6.2k resistor must be

sized appropriately to dissipate the resultant power.

For example, a 1/10W 6.2k resistor can have at most

30V

20V

MN1

WALL

V1

LTC3577-3/

LTC3577-4

OVGATE

V2

V

BUS

MN2

D2

D1

C1

R1

OVSENS

357734 F05

Figure 5. Dual Input Overvoltage Protection

357734fa

28

LTC3577-3/LTC3577-4

OPERATION

Reverse Input Voltage Protection

When disabled all LDO circuitry is powered off leaving

only a few nanoamps of leakage current on the LDO sup-

ply. Both LDO outputs are individually pulled to ground

through internal resistors when disabled.

The LTC3577-3/LTC3577-4 can also be easily protected

against the application of reverse voltage as shown in

Figure 6. D1 and R1 are necessary to limit the maximum

VGSseenbyMP1duringpositiveovervoltageevents.D1’s

breakdownvoltagemustbesafelybelowMP1’sBVGS.The

circuitshowninFigure 6offersforwardvoltageprotection

up to MN1’s BVDSS and reverse voltage protection up to

MP1’s BVDSS.

The power good status bits of LDO1 and LDO2 are avail-

2

able in I C through the read-back registers PGLDO[1] and

PGLDO[2] for LDO1 and LDO2 respectively. The power

good comparators for both LDOs are sampled when the

2

I C port receives the correct I C read address.

Figure 7 shows the LDO application circuit. The full-scale

outputvoltageforeachLDOisprogrammedusingaresistor

divider from the LDO output (LDO1 or LDO2) connected

to the feedback pins (LDO1_FB or LDO2_FB) such that:

MP1

MN1

USB/WALL

ADAPTER

V

BUS

C1

D1

LTC3577-3/

LTC3577-4

R1

500k

R2

6.2k

OVGATE

OVSENS

⎛

⎞

R1

R2

357734 F06

V_LDOx= 0.8V •

+ 1

D1: 5.6V ZENER

MP1: Si2323 DS, BVDSS = 20V

⎜

⎝

⎟

⎠

V

POSITIVE PROTECTION UP TO BVDSS OF MN1

NEGATIVE PROTECTION UP TO BVDSS OF MP1

BUS

Forstability,eachLDOoutputmustbebypassedtoground

with a minimum 1ꢁF ceramic capacitor (C ).

Figure 6. Dual Polarity Voltage Protection

LOW DROPOUT LINEAR REGULATOR OPERATION

LDO Operation and Voltage Programming

OUT

V

INLDOx

MP

0

1

LDOxEN

TheLTC3577-3/LTC3577-4containtwo150mAadjustable

output LDO regulators. The ﬁrst LDO (LDO1) is always on

LDOx

OUTPUT

R1

C

OUT

and will be enabled whenever V

is greater than V

LDOx_FB

0.8V

OUT

UVLO. The second LDO (LDO2) is controlled by the push-

button and is the ﬁrst supply to sequence up in response

to pushbutton application. Both LDOs are disabled when

R2

GND

357734 F07

V

is less than V

UVLO and LDO2 is further disabled

OUT

when the pushbutton circuity is in the power down or

power off states. Both LDOs contain a soft-start function

to limit inrush current when enabled. The soft-start func-

tion works by ramping up the LDO reference over a 200μs

period (typical) when the LDO is enabled.

Figure 7. LDO Application Circuit

357734fa

29

LTC3577-3/LTC3577-4

OPERATION

STEP-DOWN SWITCHING REGULATOR OPERATION

V

IN

Introduction

EN

MP

L

SWx

FBx

MODE

SLEW

PWM

V

OUTx

The LTC3577-3/LTC3577-4 include three 2.25MHz

constant-frequency current mode step-down switching

regulators providing 500mA, 500mA and 800mA each.

All step-down switching regulators can be programmed

for a minimum output voltage of 0.8V and can be used to

poweramicrocontrollercore,microcontrollerI/O,memory

orotherlogiccircuitry. Allstep-downswitchingregulators

support 100% duty cycle operation (low dropout mode)

when the input voltage drops very close to the output

voltage and are also capable of Burst Mode operation for

highest efﬁciencies at light loads. Burst Mode operation

is individually selectable for each step-down switching

CONTROL

MN

C

OUT

C

R1

FB

0.8V

R2

GND

357734 F08

Figure 8. Step-Down Switching Regulator Application Circuit

resistor divider from the step-down switching regulator

output connected to the feedback pins (FB1, FB2 and

FB3) such that:

2

regulatorthroughtheI CregisterbitsBK1BRST,BK2BRST

⎛

⎞

R1

R2

and BK3BRST. The step-down switching regulators also

include soft-start to limit inrush current when powering

on, short-circuit current protection, and switch node slew

limiting circuitry to reduce EMI radiation. No external

compensation components are required for the switch-

ing regulators. Switching regulators 1 and 2 (Buck1 and

Buck2) are sequenced up and down together through the

pushbutton interface (see “Pushbutton Interface” section

for more information), while Buck3 has an individual en-

able pin (EN3) that is active when the pushbutton is in

the power up or power on states. Buck3 is disabled in the

power down and power off states. It is recommended that

V_OUTx= 0.8V •

+ 1

⎜

⎝

⎟

⎠

Typical values for R1 are in the range of 40k to 1M. The

capacitor C cancels the pole created by feedback resis-

FB

tors and the input capacitance of the FB pin and also helps

to improve transient response for output voltages much

greater than 0.8V. A variety of capacitor sizes can be used

for C but a value of 10pF is recommended for most ap-

FB

plications. Experimentation with capacitor sizes between

2pF and 22pF may yield improved transient response.

Operating Modes

the step-down switching regulator input supplies (V

IN12

OUT

and V ) be connected to the system supply pin (V ).

The step-down switching regulators include two possible

operatingmodestomeetthenoise/powerneedsofavariety

of applications. In pulse-skipping mode, an internal latch

is set at the start of every cycle, which turns on the main

P-channel MOSFET switch. During each cycle, a current

comparator compares the peak inductor current to the

output of an error ampliﬁer. The output of the current

comparatorresetstheinternallatch,whichcausesthemain

P-channel MOSFET switch to turn off and the N-channel

MOSFET synchronous rectiﬁer to turn on. The N-channel

MOSFET synchronous rectiﬁer turns off at the end of the

2.25MHz cycle or if the current through the N-channel

MOSFET synchronous rectiﬁer drops to zero. Using this

method of operation, the error ampliﬁer adjusts the peak

IN3

This is recommended because the undervoltage lockout

circuit on the V pin (V UVLO) disables the step-

OUT

down switching regulators when the V

voltage drops

OUT

below the V

UVLO threshold. If driving the step-down

OUT

switching regulator input supplies from a voltage other

than V the regulators should not be operated outside

OUT

thespeciﬁedoperatingrangeasoperationisnotguaranteed

beyond this range.

Output Voltage Programming

Figure 8 shows the step-down switching regulator ap-

plication circuit. The full-scale output voltage for each

step-down switching regulator is programmed using a

357734fa

30

LTC3577-3/LTC3577-4

OPERATION

inductor current to deliver the required output power. All

necessary compensation is internal to the step-down

switching regulator requiring only a single ceramic output

capacitorforstability.Atlightloadsinpulse-skippingmode,

the inductor current may reach zero on each pulse which

will turn off the N-channel MOSFET synchronous rectiﬁer.

In this case, the switch node (SW1, SW2 or SW3) goes

high impedance and the switch node voltage will “ring”.

Thisisdiscontinuousoperation,andisnormalbehaviorfor

a switching regulator. At very light loads in pulse-skipping

mode, the step-down switching regulators will automati-

cally skip pulses as needed to maintain output regulation.

step-down switching regulators allow mode transition

on-the-ﬂy, providing seamless transition between modes

even under load. This allows the user to switch back and

forth between modes to reduce output ripple or increase

low current efﬁciency as needed. Burst Mode operation

is individually selectable for each step-down switching

2

regulatorthroughtheI CregisterbitsBK1BRST,BK2BRST

and BK3BRST.

Shutdown

The step-down switching regulators (Buck1, Buck2 and

Buck3) are shut down when the pushbutton circuitry is in

the power-down or power-off state. Step-down switching

regulator 3 (Buck3) can also be shut down by bringing the

EN3 input low. In shutdown all circuitry in the step-down

switching regulator is disconnected from the switching

regulator input supply leaving only a few nanoamps of

leakage current. The step-down switching regulator out-

puts are individually pulled to ground through internal 10k

resistors on the switch pin (SW1, SW2 or SW3) when in

shutdown.

At high duty cycle (V

approaching V ) it is possible

OUTX

INX

for the inductor current to reverse at light loads causing

the stepped down switching regulator to operate continu-

ously. When operating continuously, regulation and low

noise output voltage are maintained, but input operating

current will increase to a few milliamps.

In Burst Mode operation, the step-down switching regula-

tors automatically switch between ﬁxed frequency PWM

operation and hysteretic control as a function of the load

current. At light loads the step-down switching regulators

control the inductor current directly and use a hysteretic

control loop to minimize both noise and switching losses.

While operating in Burst Mode operation, the output

capacitor is charged to a voltage slightly higher than the

regulation point. The step-down switching regulator then

goes into sleep mode, during which the output capacitor

provides the load current. In sleep mode, most of the

switching regulator’s circuitry is powered down, helping

conserve battery power. When the output voltage drops

below a pre-determined value, the step-down switching

regulator circuitry is powered on and another burst cycle

begins. The sleep time decreases as the load current

increases. Beyond a certain load current point (about

1/4 rated output load current) the step-down switching

regulators will switch to a low noise constant frequency

PWM mode of operation, much the same as pulse-skip-

ping operation at high loads.

Dropout Operation

It is possible for a step-down switching regulator’s input

voltagetoapproachitsprogrammedoutputvoltage(e.g.,a

battery voltage of 3.4V with a programmed output voltage

of 3.3V). When this happens, the PMOS switch duty cycle

increasesuntilitisturnedoncontinuouslyat100%.Inthis

dropoutcondition,therespectiveoutputvoltageequalsthe

regulator’s input voltage minus the voltage drops across

the internal P-channel MOSFET and the inductor.

Soft-Start Operation

Soft-startisaccomplishedbygraduallyincreasingthepeak

inductor current for each step-down switching regulator

overa500ꢁsperiod.Thisallowseachoutputtoriseslowly,

helping minimize inrush current required to charge up the

switching regulator output capacitor. A soft-start cycle

occurs whenever a given switching regulator is enabled.

A soft-start cycle is not triggered by changing operating

modes. This allows seamless output transition when

actively changing between operating modes.

For applications that can tolerate some output ripple

at low output currents, Burst Mode operation provides

better efﬁciency than pulse-skipping at light loads. The

357734fa

31

LTC3577-3/LTC3577-4

OPERATION

Slew Rate Control

UVLO prevents the step-down switching regulators from

operating at low supply voltages where loss of regula-

tion or other undesirable operation may occur. If driving

the step-down switching regulator input supplies from

The step-down switching regulators contain new patent

pending circuitry to limit the slew rate of the switch node

(SW1, SW2 and SW3). This new circuitry is designed to

transition the switch node over a period of a few nanosec-

onds, signiﬁcantly reducing radiated EMI and conducted

supply noise while maintaining high efﬁciency. Since

slowingtheslewrateoftheswitchnodescausesefﬁciency

loss, the slew rate of the step-down switching regulators

a voltage other than the V

pin, the regulators should

OUT

not be operated outside the speciﬁed operating range as

operation is not guaranteed beyond this range.

Inductor Selection

2

Many different sizes and shapes of inductors are available

fromnumerousmanufacturers.Choosingtherightinductor

fromsuchalargeselectionofdevicescanbeoverwhelming,

butfollowingafewbasicguidelineswillmaketheselection

process much simpler. The step-down switching regula-

tors are designed to work with inductors in the range of

2.2ꢁH to 10ꢁH. For most applications a 4.7ꢁH inductor is

suggested for step-down switching regulators providing

up to 500mA of output current while a 3.3ꢁH inductor is

suggested for step-down switching regulators providing

upto800mA.Largervalueinductorsreduceripplecurrent,

which improves output ripple voltage. Lower value induc-

tors result in higher ripple current and improved transient

responsetime,butwillreducetheavailableoutputcurrent.

To maximize efﬁciency, choose an inductor with a low DC

resistance. For a 1.2V output, efﬁciency is reduced about

2% for 100mꢀ series resistance at 400mA load current,

and about 2% for 300mꢀ series resistance at 100mA load

current. Choose an inductor with a DC current rating at

least 1.5 times larger than the maximum load current to

is adjustable via the I C registers SLEWCTL1 and SLEW-

CTL2. This allows the user to optimize efﬁciency or EMI as

necessarywithfourdifferentslewratesettings.Thepower

up default is the fastest slew rate (highest efﬁciency) set-

ting. Figures 9 and 10 show the efﬁciency and power loss

graph for Buck3 programmed for 1.2V and 2.5V outputs.

Note that the power loss curves remain fairly constant for

both graphs yet changing the slew rate has a larger effect

on the 1.2V output efﬁciency. This is mainly because for

a given output current the 2.5V output is delivering more

than 2x the power than the 1.2V output. Efﬁciency will

always decrease and show more variation to slew rate as

the programmed output voltage is decreased.

Low Supply Operation

An undervoltage lockout circuit on V

shutsdownthestep-downswitchingregulatorswhenV

drops below about 2.7V. It is recommended that the step-

down switching regulator input supplies (V , V ) be

connected to the power path output (V ) directly. This

(V

UVLO)

OUT

IN12 IN3

OUT

100

90

80

70

60

50

40

30

20

10

1.00E+00

1.00e-01

1.00E-02

1.00E-03

1.00E-04

1.00E-05

100

90

80

70

60

50

40

30

20

10

1.00E+00

1.00e-01

1.00E-02

1.00E-03

1.00E-04

1.00E-05

Burst Mode

OPERATION

IN

Burst Mode

OPERATION

IN

V

= 3.8V

V

= 3.8V

SW[1:0] =

00

01

10

11

00

01

10

11

0

1.00E-05

1.00E-0.3

1.00E-01

1.00E-05

1.00E-0.3

1.00E-01

I

(mA)

I

(mA)

OUT3

357734 F09

357734 F10

Figure 9. V_OUT3(1.2V) Efﬁciency and Power Loss vs I_OUT3

Figure 10. V_OUT3(2.5V) Efﬁciency and Power Loss vs I_OUT3

357734fa

32

LTC3577-3/LTC3577-4

OPERATION

ensure that the inductor does not saturate during normal

operation. If output short circuit is a possible condition,

the inductor should be rated to handle the maximum peak

current speciﬁed for the step-down converters. Different

core materials and shapes will change the size/current

and price/current relationship of an inductor. Toroid or

shielded pot cores in ferrite or Permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

electrical characteristics. Inductors that are very thin or

have a very small volume typically have much higher core

and DCR losses, and will not give the best efﬁciency. The

choice of which style inductor to use often depends more

on the price versus size, performance, and any radiated

EMI requirements than on what the step-down switching

regulatorsrequirestooperate. Theinductorvaluealsohas

an effect on Burst Mode operation. Lower inductor values

will cause Burst Mode switching frequency to increase.

Table 3 shows several inductors that work well with the

step-down switching regulators. These inductors offer a

good compromise in current rating, DCR and physical

size. Consult each manufacturer for detailed information

on their entire selection of inductors.

Input/Output Capacitor Selection

LowESR(equivalentseriesresistance)ceramiccapacitors

should be used at both step-down switching regulator

outputs as well as at each step-down switching regulator

input supply. Only X5R or X7R ceramic capacitors should

be used because they retain their capacitance over wider

voltage and temperature ranges than other ceramic types.

A 10ꢁF output capacitor is sufﬁcient for the step-down

switching regulator outputs. For good transient response

and stability the output capacitor for step-down switching

regulators should retain at least 4ꢁF of capacitance over

operating temperature and bias voltage. Each switching

regulator input supply should be bypassed with a 2.2ꢁF

capacitor. Consult with capacitor manufacturers for de-

tailed information on their selection and speciﬁcations

of ceramic capacitors. Many manufacturers now offer

Table 3. Recommended Inductors for Step-Down Switching Regulators

INDUCTOR TYPE

L (μH)

MAX I (A)

MAX DCR (Ω)

SIZE in mm (L × W × H) MANUFACTURER

DC

DB318C

4.7

3.3

4.7

3.3

4.7

3.3

1.07

1.20

0.79

0.90

1.15

1.37

0.1

0.07

Toko

www.toko.com

3.8 × 3.8 × 1.8

3.6 × 3.6 × 1.2

3.0 × 2.8 × 1.2

D312C

0.24

0.20

0.13*

0.105*

DE2812C

CDRH3D16

CDRH2D11

4.7

3.3

4.7

3.3

4.7

0.9

1.1

0.11

0.085

0.17

Sumida

4 × 4 × 1.8

www.sumida.com

0.5

3.2 × 3.2 × 1.2

4.9 × 4.9 × 1

0.6

0.75

0.123

0.19

CLS4D09

SD3118

4.7

3.3

4.7

3.3

4.7

3.3

4.7

3.3

1.3

1.59

0.8

0.97

1.29

1.42

1.08

1.31

0.162

0.113

Cooper

www.cooperet.com

3.1 × 3.1 × 1.8

3.1 × 3.1 × 1.2

5.2 × 5.2 × 1.2

5.2 × 5.2 × 1.0

SD3112

SD12

0.246

0.165

0.117*

0.104*

0.153*

0.108*

SD10

LPS3015

4.7

3.3

1.1

1.3

0.2

0.13

Coil Craft

www.coilcraft.com

3.0 × 3.0 × 1.5

*Typical DCR

357734fa

33

LTC3577-3/LTC3577-4

OPERATION

very thin (<1mm tall) ceramic capacitors ideal for use in

height-restricted designs. Table 4 shows a list of several

ceramic capacitor manufacturers.

LED Boost Operation

The LED boost converter is designed for very high duty

cycle operation and can boost from 3V to 40V out for load

currents up to 20mA. The boost converter also features

overvoltage protection to protect the output in case of an

open circuit in the LED string. The overvoltage protection

threshold is set by adjusting R1 in Figure 11 such that:

Table 4. Ceramic Capacitor Manufacturers

AVX

www.avxcorp.com

www.murata.com

www.t-yuden.com

www.vishay.com

www.tdk.com

Murata

Taiyo Yuden

Vishay Siliconix

TDK

R1

BOOST(MAX) = 800mV •

+LED_OV

10 •R2

where LED_OV is approximately 1.0V.

LED BACKLIGHT/BOOST OPERATION

Introduction

In the case of Figure 11 BOOST(MAX) is set to 40V for a

10-LED string.

The LED driver uses a constant frequency, current mode

boost converter to supply power for up to 10 series LEDs.

As shown in Figure 11 the series string of LEDs is con-

nected from the output of the boost converter (BOOST) to

Capacitor C3 provides soft-start, limiting the inrush cur-

rentwhentheboostconverterisﬁrstenabled. C3provides

feedback to the I pin. This feedback limits the rise time

LED

of output voltage and the inrush current while the output

capacitor, C2, is charging.

the I

pin. Under normal operation the boost converter

LED

BOOST output will be driven to a voltage where the I

pin regulates at approximately 300mV to 400mV. The I

LED

The boost converter will be operated in either continuous

conduction mode, discontinuous conduction mode or

pulse-skipping mode depending on the inductor current

required for regulation.

LED

2

pin is a constant current sink that is programmed via I C

“LED DAC register”. The LED can be further controlled

2

using I C to program brightness levels and soft turn-on/

2

turn-off effects. See the “I C Interface” section for more

LED Constant Current Sink

information on programming the I

current. The boost

LED

converter also includes an overvoltage protection feature

to limit the BOOST output voltage as well as variable slew

rate control of the SW pin to reduce EMI.

TheLEDdriverusesaprecisioncurrentsinktoregulatethe

LED current up to 20mA. The current sink is programmed

2

via I C “LED DAC Register” and utilizes a 6-bit 60dB expo-

nential DAC. This DAC provides accurate current control

from 20ꢁA to 20mA with approximately 1dB per step for

LED(FS)

C1

I

= 20mA. The LED current can be approximated

22μF

39

V

by the following equations:

OUT

L1

LTC3577-3/

10μH

⎛

⎞

DAC – 63

63

LTC3577-4

LPS4018-103ML

D12

ZLLS400

I_LED= I_LED(FS)•10^⎜^⎝^{3 •}

⎟

⎠

18

19

20

SW

(1)

BOOST

R1

10M

0.8V

R2

I_LED(FS)

=

• 500

9

LED_OV

C2

C3

22nF

50V

R2

20k

D1 D2 D3 D4 D5

D10 D9 D8 D7 D6

1μF

3

2

50V

I

LED_FS

where DAC is the decimal value programmed into the I C

“LED DAC register”. For example with I

= 20mA

22

LED(FS)

I

LED

357734 F11

and DAC[5:0] = 000000 (0 decimal) I equates to 20ꢁA,

LED

while DAC[5:0] = 111111 (63 decimal) I

20mA.AsaﬁnalexampleDAC[5:0]=101010is42decimal

equates to

LED

Figure 11. LED Boost Application Circuit

357734fa

34

LTC3577-3/LTC3577-4

OPERATION

and equates to I

= 2mA for I

= 20mA. The DAC

current may be adjusted but the accuracy of the output

current will be degraded the further it is programmed

from 20mA. The LED_FS pin is current limited and will

only source about 80μA. This protects the pin and limits

LED

LED(FS)

approximates Equation 1 using the nominal values in

Table 5. The differences between the approximation

equation and the table are due to design of the DAC using

eight linear segments that approximate the exponential

function.

the I

current in a case where LED_FS is shorted to

LED

ground, it is not recommended to program the LED cur-

rent above 25mA.

Table 5. LED DAC Codes to Output Current

DAC Codes

Output Current

20.0μA

23.5μA

27.0μA

30.5μA

34.0μA

37.6μA

41.1μA

44.6μA

48.1μA

56.5μA

65.0μA

73.4μA

81.9μA

90.3μA

98.7μA

107μA

116μA

136μA

156μA

177μA

197μA

217μA

237μA

258μA

278μA

327μA

376μA

424μA

473μA

522μA

571μA

DAC Codes

Output Current

668μA

LED Gradation

0

1

2

3

4

5

6

7

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

786μA

903μA

The LED driver features an automatic gradation circuit.

The gradation circuit ramps the LED current up when

the LED driver is enabled and ramps the current down

when the LED driver is disabled. The DAC is enabled and

1.02mA

1.14mA

1.26mA

1.37mA

1.49mA

1.61mA

1.89mA

2.17mA

2.45mA

2.74mA

3.02mA

3.30mA

3.58mA

3.86mA

4.54mA

5.22mA

5.90mA

6.58mA

7.26mA

7.93mA

8.61mA

9.29mA

10.8mA

12.4mA

13.9mA

15.4mA

17.0mA

18.5mA

20.0mA

2

disabled with the EN bit of the I C “LED control register”.

The gradation function is automatic when enabling and

disablingtheLEDdriver;onlythegradationspeedneedsto

be programmed to use this function. The gradation speed

8

9

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

is set by the GR1 and GR2 bits of the I C “LED control

register” which allows transitions times of approximately

15ms, one-half second, one second and two seconds.

2

See the “I C Interface” section for more information. The

gradation function allows the LEDs to turn on and off

gradually as opposed to an abrupt step.

LED PWM vs Constant Current Operation

The LED driver provides both linear LED current mode as

wellasPWMLEDcurrentmode.Thesemodesareselected

2

through the MD1 and MD2 bits of the I C “LED control

register”. When both bits are “0” the LED boost converter

is in constant current (CC) mode and the I current sink

LED

is constant whose value is set by the DAC[5:0] bits of the

2

I C“LED DAC register”.

Setting MD1 to “0” and MD2 to “1” selects the LED PWM

mode. In this mode the LED driver is pulsed using an

internally generated PWM signal. The PWM mode may be

used to reduce the LED intensity for a given programmed

current.

620μA

The full-scale LED current is set using a resistor (R2 in

Figure 11)connectedbetweentheLED_FSpinandground.

Typically R2 should be set to 20k to give 20mA of LED

current at full scale. The resistance may be increased to

decrease the current or the resistance may be decreased

to increase the LED current. The DAC has been optimized

for best performance at 20mA full scale. The full-scale

WhendimmingviaPWMtheLEDdriverandboostconverter

are both turned on and off together. This allows some

degree of additional control over the LED current, and in

somecasesmayofferamoreefﬁcientmethodofdimming

since the boost could be operated at an optimal efﬁciency

point and pulsed for the desired LED intensity.

357734fa

35

LTC3577-3/LTC3577-4

OPERATION

The PWM mode, if enabled, is set up using 3 values,

Fixed Boost Output

2

PWMNUM [3:0] and PWMDEN [3:0] in the I C “LED PWM

Setting MD1 to 1 and MD2 to 0 selects the ﬁxed high

voltage boost mode. This mode can be used to generate

output voltages at or greater than V . When conﬁgured

as a boost converter the I

pin, and the boost will regulate the output voltage such

that the voltage on the I pin is 800mV.

Register” and PWMCLK, set by PWMC2 and PWMC1 in

2

the I C “LED Control Register.”

OUT

pin becomes the feedback

PWMNUM

Duty Cycle =

LED

PWMDEN

LED

PWMCLK

Frequency =

Figure 12 shows a ﬁxed 12V output generated using the

boost converter in the ﬁxed high voltage boost mode. Any

output voltage up to 40V may be programmed by select-

ing appropriate values for the R1 and R2 voltage divider

from the equation:

PWMDEN

Table 6. PWM Clock Frequency

PWMC2

PWMC1

PWMCLK

8.77kHz

4.39kHz

2.92kHz

2.19kHz

0

1

0

1

0

1

⎛

⎞

R1

R2

V_BOOST= 0.8V •

+ 1

⎜

⎝

⎟

⎠

Values for R2 should be kept below 24.3k to keep the pole

at the I pin beyond cross over.

UsingthePWMcontrol,a4-bitinternallygeneratedPWMis

possible as additional dimming. Using these control bits a

number of PWM duty cycles and frequencies are available

in the 100Hz to 500Hz range. This range was selected to

be below the audio range and above the frequency where

the PWM is visible.

LED

The boost is designed primarily as a high voltage and high

duty cycle converter. When operating with a lower boost

ratio, a larger output capacitor, 10μF, should be used. Op-

erating with a very low duty cycle will cause cycle skipping

which will increase ripple.

For example, given PWMC2 = 1, PWMC1 = 0,

PWMNUM[3:0] = 0111 and PWMDEN[3:0] = 1100 then

the duty cycle will be 58.3% and PWM frequency will be

243Hz.

C1

22μF

39

V

OUT

LED_FS

3

L4

I

If PWMNUM is set to 0 then the duty cycle will be 0% and

the current sink will effectively be off. If PWMNUM is ever

programmed to a value larger than PWMDEN the duty

cycle will be 100% and the current sink will effectively be

constant. PWMDEN and PWMNUM may both be changed

to result in 73 different duty cycle possibilities and 41 dif-

ferent PWM frequencies between 8.77kHz and 100Hz.

10μH

LTC3577-3/

LTC3577-4

LPS4018-103ML

D12

ZLLS400

18

19

20

SW

BOOST

C2

R1

10μF

10V

301k

800mV V

REF

22

9

I

LED

R2

21.5k

LED_OV

357734 F12

WhenPWMmodeisenabledasmall(2μA)standbycurrent

source is always enabled on the LED pin. The purpose of

thisistohavesomecurrentﬂowingintheLED’satalltimes.

This helps to reduce the magnitude of the voltage swing

on the LED pin as the current is pulsed on and off.

Figure 12. Fixed 12V/75mA Boost Output Application

357734fa

36

LTC3577-3/LTC3577-4

OPERATION

To keep the average steady-state inductor current below

300mA the maximum output current is reduced as pro-

grammed output voltage increases. The output current

available is given by:

Diode Selection

When boosting to increasingly higher voltages, parasitic

capacitance at the switch pin becomes an increasing

large component of the switching loses. For this reason

it is important to minimize the capacitance on the switch

node. The diode selected should be sized to handle the

peak inductor current and the average output current.

At high boost voltages a diode with the lowest possible

junction capacitance will often result in a more efﬁcient

solution than one with a lower forward drop.

V_OUT(MIN)

I_BOOST(MAX)= 300mA •

V_BOOST

Note that the maximum boost output current must be

set by the minimum V

converter is allowed to operate down to the V

operating voltage. If the boost

OUT

UVLO

OUT

then 2.5V must be assumed as the minimum operating

voltage.

2

I C OPERATION

V

OUT

2

I C Interface

Inductor Selection

The LTC3577-3/LTC3577-4 may communicate with a

The LED boost converter is designed to work with a 10ꢁH

inductor. The inductor must be able to handle a peak

current of 1A and should have a low ESR value for good

efﬁciency. Table 7 shows several inductors that work

well with the LED boost converter. These inductors offer

a good compromise in current rating, DCR and physical

size. Consult each manufacturer for detailed information

on their entire selection of inductors.

2

bus master using the standard I C 2-wire interface. The

Timing Diagram shows the relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources, such as the LTC1694 SMBus accelerator,

arerequiredontheselines.TheLTC3577-3/LTC3577-4are

2

both a slave receiver and slave transmitter. The I C control

signals, SDA and SCL are scaled internally to the DV

CC

supply. DV should be connected to the same power

CC

supply as the bus pull-up resistors.

Table 7. Recommended Inductors for Boost Switching Reguators

INDUCTOR TYPE

L (μH)

MAX I (A)

MAX DCR (Ω)

SIZE in mm (L × W × H) MANUFACTURER

DC

LPS4018-103

10

1.1

0.200

Coil Craft

www.coilcraft.com

4.0 × 4.0 × 1.8

DB62LCB

10

1.22

1.05

1.28

0.118

0.155

Toko

6.2 × 6.2 × 2

www.toko.com

CDRH4D16NP-100M

SD18-100-R

*Typical

Sumida

www.sumida.com

4.8 × 4.8 × 1.8

5.2 × 5.2 × 1.8

0.158*

Cooper

www.cooperet.com

357734fa

37

LTC3577-3/LTC3577-4

OPERATION

2

The I C port has an undervoltage lockout on the DV pin.

I C Byte Format

CC

2

When DV is below approximately 1V, the I C serial port

CC

EachbytesenttoorreceivedfromtheLTC3577-3/LTC3577-4

must be 8 bits long followed by an extra clock cycle for the

acknowledgebit.ThedatashouldbesenttotheLTC3577-3/

LTC3577-4 most signiﬁcant bit (MSB) ﬁrst.

is cleared and registers are set to the default conﬁgura-

tion of all zeros.

2

I C Bus Speed

2

The I C port is designed to be operated at speeds of up

I C Acknowledge

to 400kHz. It has built-in timing delays to ensure correct

operation when addressed from an I C compliant master

device. It also contains input ﬁlters designed to suppress

glitches should the bus become corrupted.

The acknowledge signal is used for handshaking between

themasterandtheslave.WhentheLTC3577-3/LTC3577-4

are written to (write address), they acknowledge their

write address as well as the subsequent two data bytes.

When they are read from (read address), the LTC3577-3/

LTC3577-4 acknowledge their read address only. The bus

master should acknowledge receipt of information from

the LTC3577-3/LTC3577-4.

2

I C START and STOP Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3577-3/LTC3577-4, the master may transmit a STOP

condition which commands the LTC3577-3/LTC3577-4 to

actuponitsnewcommandset.ASTOPconditionissentby

the master by transitioning SDA from LOW to HIGH while

SCL is HIGH. The bus is then free for communication with

Anacknowledge(activeLOW)generatedbytheLTC3577-3/

LTC3577-4 let the master know that the latest byte of

information was received. The acknowledge related clock

pulse is generated by the master. The master releases the

SDA line (HIGH) during the acknowledge clock cycle. The

LTC3577-3/LTC3577-4 pull down the SDA line during the

write acknowledge clock pulse so that it is a stable LOW

during the HIGH period of this clock pulse.

2

another I C device.

I²C Timing Diagram

DATA BYTE A

DATA BYTE B

ADDRESS

WR

0

1

0

1

A7

1

A6

2

A5

3

A4

A3

A2

6

A1

7

A0

8

B7

1

B6

2

B5

3

B4

4

B3

5

B2

6

B1

7

B0

8

START

STOP

SDA

SCL

0

1

0

8

ACK

9

ACK

9

ACK

9

1

2

3

4

5

6

7

4

5

SDA

t

BUF

SU, DAT

SU, STA

t

LOW

HD, STA

SU, STO

HD, DAT

357734 TD

SCL

t

HD, STA

HIGH

SP

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

t

f

r

357734fa

38

LTC3577-3/LTC3577-4

OPERATION

When the LTC3577-3/LTC3577-4 are read from, they re-

lease the SDA line so that the master may acknowledge

receipt of the data. Since the LTC3577-3/LTC3577-4 only

transmit one byte of data, a master not acknowledging the

datasentbytheLTC3577-3/LTC3577-4hasnoI Cspeciﬁc

consequence on the operation of the I C port.

the sub-address. Again the LTC3577-3/LTC3577-4 ac-

knowledge and the cycle is repeated for the data byte.

The data byte is transferred to an internal holding latch

upon the return of its acknowledge by the LTC3577-3/

LTC3577-4. This procedure must be repeated for each

sub-address that requires new data. After one or more

cyclesof[ADDRESS][SUB-ADDRESS][DATA],themaster

may terminate the communication with a STOP condition.

Alternatively, a REPEAT-START condition can be initiated

2

I C Slave Address

The LTC3577-3/LTC3577-4 respond to a 7-bit address

whichhasbeenfactoryprogrammedtob’0001001[R/W]’.

The LSB of the address byte, known as the read/write bit,

shouldbe0whenwritingdatatotheLTC3577-3/LTC3577-4

and 1 when reading data from it. Considering the address

an eight bit word, then the write address is 0x12 and the

read address is 0x13. The LTC3577-3/LTC3577-4 will

acknowledge both its read and write address.

2

by the master and another chip on the I C bus can be

addressed. This cycle can continue indeﬁnitely and the

LTC3577-3/LTC3577-4willrememberthelastinputofvalid

data that it received. Once all chips on the bus have been

addressed and sent valid data, a global STOP can be sent

and the LTC3577-3/LTC3577-4 will update their command

latches with the data that they had received.

2

I C Bus Read Operation

I C Sub-Addressed Writing

The bus master reads the status of the LTC3577-3/

LTC3577-4 with a START condition followed by the

LTC3577-3/LTC3577-4 read address. If the read address

matchesthatoftheLTC3577-3/LTC3577-4,theLTC3577-3/

LTC3577-4returnanacknowledge.Followingtheacknowl-

edgementoftheirreadaddress,theLTC3577-3/LTC3577-4

return one bit of status information for each of the next

8 clock cycles. A STOP command is not required for the

bus read operation.

The LTC3577-3/LTC3577-4 have four command registers

2

forcontrolinput.TheyareaccessedbytheI Cportviaasub-

addressed writing system.

Each write cycle of the LTC3577-3/LTC3577-4 consists of

exactlythreebytes. TheﬁrstbyteisalwaystheLTC3577-3/

LTC3577-4’swriteaddress.Thesecondbyterepresentsthe

LTC3577-3/LTC3577-4’ssub-address.Thesubaddressisa

pointer which directs the subsequent data byte within the

LTC3577-3/LTC3577-4. The third byte consists of the data

to be written to the location pointed to by the sub-address.

TheLTC3577-3/LTC3577-4containcontrolregistersatonly

four sub-address locations: 0x00, 0x01, 0x02 and 0x03.

Writing to sub-addresses outside the four sub-addresses

listed is not recommended as it can cause data in one of

the four listed sub-addresses to be overwritten.

2

I C Input Data

There are 4 bytes of data that can be written to on the

LTC3577-3/LTC3577-4. The bytes are accessed through

the sub-addresses 0x00 to 0x03. At ﬁrst power applica-

tion (V , WALL or BAT) all bits default to 0. Addition-

BUS

ally all bits are cleared to 0 when DV drops below its

CC

2

undervoltage lock out or if the pushbutton enters the

I C Bus Write Operation

power down (PDN) state.

The master initiates communication with the LTC3577-3/

LTC3577-4 with a START condition and the LTC3577-3/

LTC3577-4’s write address. If the address matches that

of the LTC3577-3/LTC3577-4, the LTC3577-3/LTC3577-4

return an acknowledge. The master should then deliver

Table 8 shows the ﬁrst byte of data that can be written to

at sub-address 0x00. This byte of data is referred to as

the “buck control register”.

357734fa

39

LTC3577-3/LTC3577-4

OPERATION

Table 8. Buck Control Register

BUCK CONTROL

REGISTER

BitB0enablesanddisablestheLEDboostcircuitry.Writing

a 1 to B0 enables the LED boost circuitry, while writing a

0 disables the LED boost circuitry.

ADDRESS: 00010010

SUB-ADDRESS: 00000000

BIT NAME

B0 N/A

FUNCTION

Bits B1 and B2 are the LED gradation which sets the ramp

up and down time of the LED current when enabled or

disabled. The gradation function allows the LEDs to turn

on/off gradually as opposed to an abrupt step.

Not Used—No Effect on Operation

Buck1 Burst Mode Enable

Buck2 Burst Mode Enable

B1 N/A

B2 BK1BRST

B3 BK2BRST

B4 BK3BRST

B5 SLEWCTL1

B6 SLEWCTL2

B7 N/A

Bits B3 and B4 set the operating mode of the LED boost

circuitry. The operating modes are: B4:B3 = 00 LED con-

stant current (CC) boost operation; B4:B3 = 10 LED PWM

boostoperation;B4:B3=01ﬁxedhighvoltage(HV)output

boost operation; B4:B3 = 11, not supported, do not use.

See the “LED Backlight/Boost Operation” section for more

information on the operating modes.

Buck SW Slew Rate: 00 = 1ns,

01 = 2ns, 10 = 4ns, 11 = 8ns

Not Used—No Effect on Operation

Bits B2, B3, and B4 set the operating modes of the

step-down switching regulators (bucks). Writing a 1 to

any of these three registers will put that respective buck

converter in the high efﬁciency Burst Mode of operation,

while a 0 will enable the low noise “pulse-skipping” mode

of operation.

Bits B5 and B6 set the PWM clock speed as shown in

Table 5 of the “LED Backlight/Boost Operation” section.

Bit B7 sets the slew rate of the LED boost SW pin. Setting

B7 to 0 results in the fastest slew rate and provides the

most efﬁcient mode of operation. Setting B7 to 1 should

only be used in cases where EMI due to SW slewing is an

issue as the slower slew rate causes a loss in efﬁciency.

The B5 and B6 bits adjust the slew rate of all SW pins

together so they all slew at the same rate. It is recom-

mended that the fastest slew rate (B6:B5 = 00) be used

unless EMI is an issue in the application as slower slew

rates cause reduced efﬁciency.

See “LED Backlight/Boost Operation” section for more

detailed operating information.

Table 9 shows the second byte of data that can be written

to at sub-address 0x01. This byte of data is referred to as

the “LED control register”.

Table 10 shows the third byte of data that can be written

to at sub-address 0x02. This byte of data is referred to as

the “LED DAC register”. The LED current source utilizes a

6-bit 60dB exponential DAC. This DAC provides accurate

current control from 20ꢁA to 20mA with approximately

Table 9. I²C LED Control Register

LED CONTROL

REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000001

1dB per step with I

programmed to 20mA. The LED

LED(FS)

BIT NAME

B0 EN

FUNCTION

current can be approximated by the following equation:

Enable: 1 = Enable 0 = Off

B1 GR2

Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,

10 = 930ms, 11 = 1.85 Seconds

⎛

⎞

DAC – 63

63

I_LED= I_LED(FS)•10^⎜^⎝^{3 •}

⎟

⎠

B2 GR1

B3 MD1

Mode MD[2:1]: 00 = CC Boost,

10 = PWM Boost; 01 = HV Boost,

B4 MD2

2

where DAC is the decimal value programmed into the I C

“LEDDACregister”. ForexamplewithI =20mAand

DAC[5:0] = 101010 (42 decimal) I

B5 PWMC1

B6 PWMC2

B7 SLEWLED

PWM CLK PWMC[2:1]: 00 = 8.77kHz,

01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz

LED(FS)

equates to 2mA.

LED

LED SW Slew Rate: 0/1 = Fast/Slow

357734fa

40

LTC3577-3/LTC3577-4

OPERATION

Table 10. I²C LED DAC Register

2

I C Output Data

ADDRESS: 00010010

One status byte may be read from the LTC3577-3/

LTC3577-4 as shown in Table 12. A 1 read back in the any

of the bit positions indicates that the condition is true. For

example, 1 read back from bit A3 indicate that LDO1 is

enabled and regulating correctly. A status read from the

LTC3577-3/LTC3577-4 captures the status information

when the LTC3577-3/LTC3577-4 acknowledge its read

address.

LED DAC REGISTER

BIT NAME

B0 DAC[0]

B1 DAC[1]

B2 DAC[2]

B3 DAC[3]

B4 DAC[4]

B5 DAC[5]

B6 N/A

SUB-ADDRESS: 00000010

FUNCTION

6-Bit Log DAC Code

Table 12. I²C READ Register

Not Used—No Effect On Operation

ADDRESS: 00010011

B7 N/A

STATUS REGISTER

BIT NAME

SUB-ADDRESS: None

Table 11 shows the ﬁnal byte of data that can be written

to at sub-address 0x03. This byte of data is referred to as

the “LED PWM register”. See the “LED PWM vs Constant

Current Operation” section for detailed information on

how to set the values of this register.

FUNCTION

A0 CHARGE

A1 STAT[0]

A2 STAT[1]

Charge Status (1 = Charging)

STAT[1:0]; 00 = No Fault

01 = TOO COLD/HOT

10 = BATTERY OVERTEMP

11 = BATTERY FAULT

A3 PGLDO[1]

A4 PGLDO[2]

A5 PGBCK[1]

A6 PGBCK[2]

A7 PGBCK[3]

LDO1 Power Good

LDO2 Power Good

Buck1 Power Good

Buck2 Power Good

Buck3 Power Good

Table 11. LED PWM Register

ADDRESS: 00010010

LED PWM REGISTER

BIT NAME

SUB-ADDRESS: 00000011

FUNCTION

B0 PWMDEN[0]

B1 PWMDEN[1]

B2 PWMDEN[2]

B3 PWMDEN[3]

B4 PWMNUM[0]

B5 PWMNUM[1]

B6 PWMNUM[2]

B7 PWMNUM[3]

PWM DENOMINATOR

BitA7showsthepowergoodstatusofBuck3.A1indicates

that Buck3 is enabled and is regulating correctly. A 0 indi-

cates that either Buck3 is not enabled, or that the Buck3 is

enabled, but is out of regulation by more than 8%.

PWM NUMERATOR

BitA6showsthepowergoodstatusofBuck2.A1indicates

that Buck2 is enabled and is regulating correctly. A 0 indi-

cates that either Buck2 is not enabled, or that the Buck2 is

enabled, but is out of regulation by more than 8%.

357734fa

41

LTC3577-3/LTC3577-4

OPERATION

2

BitA5showsthepowergoodstatusofBuck1.A1indicates

that Buck1 is enabled and is regulating correctly. A 0 indi-

cates that either Buck1 is not enabled, or that the Buck1 is

enabled, but is out of regulation by more than 8%.

I C Write Register Map (see “I C Input Data” section for

more details, all registers default to 0 when reset)

BUCK CONTOL

REGISTER

ADDRESS: 00010010

SUB-ADDRESS: 00000000

BIT NAME

FUNCTION

BitA4showsthepowergoodstatusofLDO2. A1indicates

that LDO2 is enabled and is regulating correctly. A 0 indi-

cates that either LDO2 is not enabled, or that the LDO2 is

enabled, but is out of regulation by more than 8%.

B0 N/A

B1 N/A

Not Used—No Effect On Operation

Buck1 Burst Mode Enable

Buck2 Burst Mode Enable

B2 BK1BRST

B3 BK2BRST

B4 BK3BRST

B5 SLEWCTL1

B6 SLEWCTL2

B7 N/A

BitA3showsthepowergoodstatusofLDO1. A1indicates

that LDO1 is enabled and is regulating correctly. A 0 indi-

cates that either LDO1 is not enabled, or that the LDO1 is

enabled, but is out of regulation by more than 8%.

Buck SW Slew Rate: 00 = 1ns,

01 = 2ns, 10 = 4ns, 11 = 8ns

Not Used—No Effect On Operation

LED CONTROL

REGISTER

BIT NAME

B0 EN

B1 GR2

B2 GR1

B3 MD1

B4 MD2

ADDRESS: 00010010

Bits A2 and A1 indicate the fault status of the charger

measurementcircuitandaredecodedinTable12.The“too

cold/hot”stateindicatesthatthethermistortemperatureis

out of the valid charging range (either below 0°C or above

40°Cforacurve1thermistor)andthatcharginghaspaused

untilthebatteryreturnstovalidchargingtemperature.The

batteryovertempstateindicatesthatthebattery’sthermis-

tor has reached a critical temperature (about 50°C for a

curve 1 thermistor) and that long-term battery capacity

may be seriously compromised if the condition persists.

The battery fault state indicates that an attempt was made

to charge a low battery (typically < 2.85V) but that the low

voltage condition persisted for more than 1/2 hour. In this

case charging has terminated.

SUB-ADDRESS: 00000001

FUNCTION

Enable: 1= Enable 0 = Off

Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,

10 = 930ms, 11 = 1.85 Seconds

Mode MD[2:1]: 00 = CC Boost,

10 = PWM Boost, 01 = HV Boost

B5 PWMC1

B6 PWMC2

B7 SLEWLED

PWM CLK PWMC[2:1]: 00 = 8.77kHz,

01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz

LED SW Slew Rate: 0/1 = Fast/Slow

ADDRESS: 00010010

SUB-ADDRESS: 00000010

FUNCTION

6-Bit Log DAC Code

LED DAC REGISTER

BIT NAME

B0 DAC[0]

B1 DAC[1]

B2 DAC[2]

B3 DAC[3]

B4 DAC[4]

B5 DAC[5]

B6 N/A

Bit A0 indicates the status of the battery charger. A 1

indicates that the charger is enabled and is in the con-

stant-current charge state. In this case the battery is

being charged unless the NTC thermistor is outside its

valid charge range in which case charging is temporarily

suspended but not complete. Charging will continue once

the battery has returned to a valid charging temperature.

A 0 in bit A0 indicates that charger has reached end-of-

Not Used—No Effect On 0peration

B7 N/A

ADDRESS: 00010010

SUB-ADDRESS: 00000011

FUNCTION

PWM DENOMINATOR

LED PWM REGISTER

BIT NAME

charge(h )andisnearV

orthatcharginghasbeen

C/10

FLOAT

B0 PWMDEN[0]

B1 PWMDEN[1]

B2 PWMDEN[2]

B3 PWMDEN[3]

B4 PWMNUM[0]

B5 PWMNUM[1]

B6 PWMNUM[2]

B7 PWMNUM[3]

terminated. Charging can be terminated by reaching the

end of the charge timer or by a battery fault as described

previously.

PWM NUMERATOR

357734fa

42

LTC3577-3/LTC3577-4

OPERATION

PUSHBUTTON INTERFACE OPERATION

PBSTAT Operation

PBSTAT goes low 50ms after the initial pushbutton ap-

plication (ON low) and will stay low for 50ms minimum.

PBSTAT will go high coincident with ON going high unless

ON goes high before the 50ms minimum low time.

State Diagram/Operation

Figure 13 shows the LTC3577-3/LTC3577-4 pushbutton

statediagram.Uponﬁrstapplicationofpower(V ,WALL

or BAT) an internal power-on reset (POR) signal places

the pushbutton circuitry into the power-off (POFF) state.

The following events cause the state machine to transition

out of POFF into the power-up (PUP) state:

BUS

Hard Reset and PGOOD Operation

The hard reset event is generated by pressing and holding

the pushbutton (ON input low) for 14 seconds. For a valid

hardreseteventtooccurtheinitialpushbuttonapplication

must start in the PUP or PON state. This avoids causing a

hard reset from occurring if the user hangs on the push-

button during initial power up. If a valid hard reset event

is present then the PGOOD output will transition low for

about 1.8ms to allow the microprocessor to reset. The

hard reset event does not affect the operating state or

regulator operation.

1) ON input low for 50ms (PB50MS)

2) PWR_ON input going high (PWR_ON)

Upon entering the PUP state, the pushbutton circuitry will

sequence up LDO2, Buck1 and Buck2 in that order. The

LED backlight is enabled via I C and does not take part in

the power-up sequence of the pushbutton. One second

after entering the PUP state, the pushbutton circuitry will

transition into the power-on (PON) state. Note that the

PWR_ON input must be brought high before entering the

PON state if the part is to remain in the PON state. Buck3

canbeenabledthroughtheEN3inputoncethepushbutton

is in the PUP or PON states.

2

The PGOOD pin is an open-drain output used to indicate

thatBuck1,Buck2andLDO1areenabledandhavereached

their ﬁnal regulation voltage. A 230ms delay is included

from the time Buck1, Buck2 and LDO1 reach 92% of their

regulationvaluetoallowasystemcontrollerampletimeto

reset itself. PGOOD is an open-drain output and requires a

pull-up resistor to an appropriate power source. Optimally

the pull-up resistor is connected to the output of Buck1,

Buck2 or LDO2 so that power is not dissipated while the

regulators are disabled.

PWR_ON going low, or V

dropping to its undervoltage

OUT

lockout(V UVLO)thresholdwillcausethestatemachine

OUT

to leave the PON state and enter the power-down (PDN)

2

state. The PDN state resets the I C registers effectively

shutting down the LED backlight as well as disabling

Buck1, Buck2 and LDO2 together. Buck3 is also disabled

in the PDN and POFF states. The one second delay before

leavingthepower-downstateallowsthesuppliestopower

down completely before they can be re-enabled.

Pushbutton Operation and V

UVLO

OUT

As stated earlier V

dropping to its UVLO threshold will

OUT

causethepushbuttontoleavethepower-onstateandenter

thepower-downstate,thuspoweringdownBuck1,Buck2,

Buck3, LDO2 and the LED backlight. Additionally, LDO1 is

disabled when in UVLO. Thus, all LTC3577-3/LTC3577-4

supplies are disabled and remain disabled as long as the

PUP

PB50ms +

PWR_ON

1SEC

V

OUT

UVLO condition exists. It is not possible to power

POR

POFF

PON

up any of the LTC3577-3/LTC3577-4 generated supplies

while V is below the V UVLO threshold.

OUT

UVLO +

1SEC

PWR_ON

PDN

35773 F13

Figure 13. Pushbutton State Diagram

357734fa

43

LTC3577-3/LTC3577-4

OPERATION

Power-Up via Pushbutton Timing

Power-Up via PWR_ON Timing

The timing diagram, Figure 14, shows the LTC3577-3/

LTC3577-4poweringupthroughapplicationoftheexternal

pushbutton. For this example the pushbutton circuitry

The timing diagram, Figure 15, shows the LTC3577-3/

LTC3577-4 powering up by driving PWR_ON high. For

this example the pushbutton circuitry starts in the POFF

starts in the POFF state with V

not in UVLO and Buck1,

state with V

not in UVLO and Buck1, Buck2 and LDO2

OUT

Buck2 and LDO2 disabled. Pushbutton application (ON

low) for 50ms transitions the pushbutton circuitry into the

PUP state which sequences up LDO2, Buck1 and Buck2

in that order. PWR_ON must be driven high before the 1

secondPUPperiodisovertokeepsuppliesup.IfPWR_ON

is low or goes low after the 1 second PUP period Buck1,

Buck2, and LDO2 will be shut down together. PGOOD is

asserted once Buck1, Buck2 and LDO1 are within 8% of

their regulation voltage for 230ms.

disabled. 50ms after PWR_ON goes high the pushbutton

circuitry transitions into the PUP state which sequences

up LDO2, Buck1 and Buck2 in that order. PWR_ON must

be driven high before the 1 second PUP period is over

to keep supplies up. If PWR_ON is low or goes low after

the 1 second PUP period Buck1, Buck2 and LDO2 will

be shut down together. PGOOD is asserted once Buck1,

Buck2 and LD01 are within 8% of their regulation voltage

for 230ms.

Buck3 and LED backlight can be enabled and disabled at

2

any time via EN3 or I C once in the PUP or PON states.

The PWR_ON input can be driven via a ꢁP/ꢁC or by one of

the sequenced outputs through a high impedance (100kΩ

typ). PBSTAT goes low 50ms after the initial pushbutton

application and will stay low for 50ms minimum. PBSTAT

willgohigh coincidentwithON goinghigh unlessONgoes

high before the 50ms minimum low time.

Powering up via PWR_ON is useful for applications

containing an always on microcontroller. This allows the

microcontroller to power the application up and down

for house keeping and other activities outside the user’s

control.

V

UVLO

OUT

V

UVLO

OUT

ON (PB)

PBSTAT

LDO2

ON (PB)

50ms

PBSTAT

1 SEC

PWR_ON

LDO2

14ms

50ms

14ms

BUCK1

BUCK2

PGOOD

BUCK1

BUCK2

230ms

1 SEC

230ms

PWR_ON

STATE

PGOOD

STATE

35773 F15

POFF

PUP

PON

35773 F14

POFF

PUP

PON

Figure 14. Power-Up via Pushbutton

Figure 15. Power-Up via PWR_ON

357734fa

44

LTC3577-3/LTC3577-4

OPERATION

Power Down via Pushbutton Timing

V

OUT

UVLO Power-Down Timing

The timing diagram, Figure 16, shows the LTC3577-3/

LTC3577-4 powering down by ꢁC/ꢁP control. For this ex-

amplethepushbuttoncircuitrystartsinthePONstatewith

If V

drops below the V

UVLO threshold, the push-

OUT

button circuitry will transition from the PON state to the

PDN state. Buck1, Buck2 and LDO2 are disabled together

upon entering the PDN state. After entering the PDN state,

a 1 second wait time is initiated before entering the POFF

state. During this 1 second time ON and PWR_ON inputs

are ignored to allow all LTC3577-3/LTC3577-4 generated

supplies to go low.

V

not in UVLO and Buck1, Buck2 and LDO2 enabled.

OUT

In this case the pushbutton is applied (ON low) for at least

50ms, which generates a low impedance on the PBSTAT

output. After receiving the PBSTAT the ꢁC/ꢁP will drive

the PWR_ON input low. 50ms after PWR_ON goes low

the pushbutton circuitry will enter the PDN state. Buck1,

Buck2 and LDO2 are disabled together upon entering the

PDN state. After entering the PDN state, a 1 second wait

time is initiated before entering the POFF state. During

this 1 second time ON and PWR_ON inputs are ignored

to allow all LTC3577-3/LTC3577-4 generated supplies to

go low.

Upon entering the PDN state the Buck3 is disabled and

LEDbacklightI Cregistersareclearedeffectivelydisabling

the backlight. LDO1 is also disabled by the V

and stays disabled as long as the V

remains. Note that it is not possible to sequence any of

the supplies up while the V UVLO condition exists.

LDO1 will be re-enabled when the V

2

UVLO

OUT

UVLO condition

OUT

UVLO condition

OUT

Upon entering the PDN state Buck3 is disabled and LED

is removed. The other supplies will remain disabled until

a valid power-up pushbutton event takes place.

2

backlight I C registers are cleared effectively disabling the

2

backlight. The LED backlight can be disabled via I C prior

to entering the PDN state if desired.

V

UVLO

OUT

1 SEC

Holding ON low through the 1 second power-down period

will not cause a power-up event at end of the 1second

period. The ON input must be brought high following the

power-down event and then go low again to establish a

valid power-up event.

ON (PB)

LDO1

PBSTAT

PWR_ON

BUCK1

BUCK2

LDO2

V

UVLO

OUT

1 SEC

ON (PB)

50ms

PBSTAT

PWR_ON

BUCK1

BUCK2

LDO2

μC/μP CONTROL

50ms

PGOOD

STATE

35773 F17

PON

PDN

POFF

Figure 17. V_OUTUVLO Power Down

PGOOD

STATE

PON

PDN

POFF

35773 F16

Figure 16. Power Down via Pushbutton

357734fa

45

LTC3577-3/LTC3577-4

OPERATION

Hard Reset Timing

Power-Up Sequencing

Hard reset provides a way to reset the ꢁC/ꢁP in case of a

software lockup. To initiate a hard reset, the pushbutton

is pressed (ON low) and held for greater than 14 seconds.

Once the hard reset time is exceeded the PGOOD input

will go low for 1.8ms which resets the ꢁC/ꢁP. Operation

of the enabled supplies is not effected by the hard reset

event. All enabled supplies should remain in regulation

and operating correctly assuming speciﬁed operating

conditions are met (i.e., no shorted supplies, etc).

Figure 19 shows the actual power-up sequencing of the

LTC3577-3/LTC3577-4.Buck1,Buck2andLDO2areallini-

tiallydisabled(0V). Oncethepushbuttonhasbeenapplied

(ONlow)for50msPBSTATgoeslowandLDO2isenabled.

Once enabled, LDO2 slews up and enters regulation. The

actual slew rate is controlled by the soft-start function of

LDO2 which ramps the LDO reference up over a 200μs

period typically. After a 14ms delay from LDO2 being

enabled, Buck1 is enabled and slews up into regulation.

When Buck1 is within about 8% of ﬁnal regulation, Buck2

is enabled and slews up into regulation. The bucks also

have a soft-start function to limit inrush current at start-

up. 230ms after Buck2 is within 8% of ﬁnal regulation,

the PGOOD output will go high impedance (not shown in

Figure 19).TheregulatorsinFigure 19areslewingupwith

nominal output capacitors and no load. Adding a load or

increasing output capacitance on any of the outputs will

reduce the slew rate and lengthen the time it takes the

regulator to get into regulation.

ThereareonlytwomethodstopowerdowntheLTC3577-3/

LTC3577-4 supplies: 1) PWR_ON goes low; 2) V

drops

OUT

below the V

UVLO threshold. If the ꢁC/ꢁP controls

OUT

shutdown by bringing PWR_ON low, it is possible that

the application can hang with all supplies enabled if the

ꢁC/ꢁP fails to reset correctly on hard reset. In this case

the battery will continue to be drained until V

drops

OUT

below the V

UVLO threshold, or the user intervenes to

OUT

shut down the application manually. The application can

be shut down manually by removing the battery and any

external supplies, or by providing a suicide button that

will bring PWR_ON low when pressed.

1

PBSTAT

0

V

UVLO

OUT

>14 SEC

LDO2

1V/DIV

ON (PB)

50ms

0V

PBSTAT

PWR_ON

BUCK1

1V/DIV

0V

BUCK2

2V/DIV

BUCK2

LDO1

0V

35773 F19

2ms/DIV

14 SEC

1.8ms

Figure 19. Power-Up Sequencing

35773 F18

PGOOD

STATE PON

Figure 18. Hard Reset Timing

357734fa

46

LTC3577-3/LTC3577-4

OPERATION

LAYOUT AND THERMAL CONSIDERATIONS

where LDOx is the programmed output voltage, VI

NLDOx

is the LDO supply voltage and I

is the LDO output

LDOx

Printed Circuit Board Power Dissipation

load current. Note that if the LDO supply is connected to

one of the buck output, then its supply current must be

added to the buck regulator load current for calculating

the buck power loss.

In order to be able to deliver maximum charge current

under all conditions, it is critical that the exposed ground

pad on the backside of the LTC3577-3/LTC3577-4 pack-

age be soldered to a ground plane on the board. Correctly

The power dissipated by the LED boost regulator can be

estimated as follows:

2

solderedto2500mm groundplaneonadouble-sided1oz

copper board the LTC3577-3/LTC3577-4 have a thermal

2

resistance (θ ) of approximately 45°C/W. Failure to make

⎛

⎜

⎝

⎞

⎟

BOOST

V_OUT– 1

JA

P_DLED= I_LED• 0.3V +R_NSWON• I_LED

•

good thermal contact between the Exposed Pad on the

backside of the package and a adequately sized ground

plane will result in thermal resistances far greater than

45°C/W.

⎠

where BOOST is the output voltage driving the top of

the LED string, R is the on-resistance of the SW

NSWON

N-FET (typically 330mΩ), I

is the LED programmed

LED

The conditions that cause the LTC3577-3/LTC3577-4

to reduce charge current due to the thermal protection

feedback can be approximated by considering the power

dissipated in the part. For high charge currents with a wall

current sink.

Thus the power dissipated by all regulators is:

= P + P + P + P + P

P

+ P

DLED

DREGS

DSW1

DSW2

DSW3

DLDO1

DLDO2

adapterappliedtoV , theLTC3577-3/LTC3577-4power

OUT

It is not necessary to perform any worst-case power dis-

sipationscenariosbecausetheLTC3577-3/LTC3577-4will

automatically reduce the charge current to maintain the

die temperature at approximately 110°C. However, the

approximate ambient temperature at which the thermal

feedback begins to protect the IC is:

dissipation is approximately:

P = (V

– BAT) • I + P

BAT DREGS

D

OUT

where P is the total power dissipated, V

is the supply

D

OUT

BAT

voltage, BAT is the battery voltage and I is the battery

charge current. P

is the sum of power dissipated

DREGS

on-chip by the step-down switching, LDO and LED boost

T = 110°C – P • θ

JA

A

D

regulators.

Example: Consider the LTC3577-3/LTC3577-4 operating

from a wall adapter with 5V (V ) providing 1A (I ) to

The power dissipated by a step-down switching regulator

can be estimated as follows:

OUT

BAT

chargeaLi-Ionbatteryat3.3V(BAT). AlsoassumeP

= 0.3W, so the total power dissipation is:

DREGS

100 –Eff

P

= OUTx •I

(

•

)

D(SWx)

OUTx

100

P = (5V – 3.3V) • 1A + 0.3W = 2W

D

The ambient temperature above which the LTC3577-3/

LTC3577-4 will begin to reduce the 1A charge current, is

approximately

where OUTx is the programmed output voltage, I

OUTx

is the load current and Eff is the % efﬁciency which can

be measured or looked up on an efﬁciency table for the

programmed output voltage.

T = 110°C – 2W • 45°C/W = 20°C

A

The power dissipated on chip by a LDO regulator can be

estimated as follows:

P

= (V

– LDOx) • I

INLDOx LDOx

DLDOx

357734fa

47

LTC3577-3/LTC3577-4

OPERATION

ACcurrenttotheinternalpowerMOSFETsandtheirdriv-

ers. It’s important to minimizing inductance from these

capacitors to the pins of the LTC3577-3/LTC3577-4.

The LTC3577-3/LTC3577-4 can be used above 20°C, but

the charge current will be reduced below 1A. The charge

current at a given ambient temperature can be approxi-

mated by:

Connect V

and V to V

through a short low

IN12

IN3

OUT

impedance trace.

110°C – T_A

P =

= V

–BAT •I_BAT+P

(

)

D

OUT

D(REGS)

3. TheswitchingpowertracesconnectingSW1,SW2,and

SW3 to their respective inductors should be minimized

to reduce radiated EMI and parasitic coupling. Due to

thelargevoltageswingoftheswitchingnodes,sensitive

nodes such as the feedback nodes (FBx, LDOx_FB and

LED_OV) should be kept far away or shielded from the

switching nodes or poor performance could result.

θ_JA

Thus:

110°C – T

(

)

A

θ_JA–P

D(REGS)

I_BAT

=

V_OUT–BAT

4. Connectionsbetweenthestep-downswitchingregulator

inductorsandtheirrespectiveoutputcapacitorsshould

be kept should be kept as short as possible. The GND

side of the output capacitors should connect directly

to the thermal ground plane of the part.

Consider the above example with an ambient temperature

of 55°C. The charge current will be reduced to approxi-

mately:

110°C – 55°C

– 0.3W

45°C/W

5. Keep the buck feedback pin traces (FB1, FB2, and FB3)

asshortaspossible.Minimizeanyparasiticcapacitance

between the feedback traces and any switching node

(i.e. SW1, SW2, SW3, and logic signals). If necessary

shield the feedback nodes with a GND trace.

I_BAT

=

5V – 3.3V

1.22 – 0.3W

= 542mA

1.7V

6. ConnectionsbetweentheLTC3577-3/LTC3577-4power

Printed Circuit Board Layout

path pins (V

and V ) and their respective decou-

BUS

OUT

When laying out the printed circuit board, the following

list should be followed to ensure proper operation of the

LTC3577-3/LTC3577-4:

plingcapacitorsshouldbekeptasshortaspossible.The

GND side of these capacitors should connect directly

to the ground plane of the part.

1. TheExposedPadofthepackage(Pin45)shouldconnect

directlytoalargegroundplanetominimizethermaland

electrical impedance.

7. The boost converter switching power trace connect-

ing SW to the inductor should be minimized to reduce

radiated EMI and parasitic coupling. Due to the large

voltage swing of the SW node, sensitive nodes such

as the feedback nodes (FBx, LDOx_FB and LED_OV)

should be kept far away or shielded from this switching

node or poor performance could result.

2. The step-down switching regulator input supply pins

(V

and V ) and their respective decoupling ca-

IN12

IN3

pacitors should be kept as short as possible. The GND

side of these capacitors should connect directly to the

ground plane of the part. These capacitors provide the

357734fa

48

LTC3577-3/LTC3577-4

TYPICAL APPLICATION

5V WALL

ADAPTER

Si2333DS

4

41

WALL ACPR

V

OUT

13

30

27

39

SYSTEM

LOAD

OVGATE

V

INLDO2

INLDO1

8

10μF

2.2μF

OVSENSE

V

OUT

40

32

6

USB

V

BUS

V

IN12

1k

10μF

2k

LTC3577-3/

LTC3577-4

V

IN3

44

37

CHRG

36

43

Si2333DS

(OPT)

PROG

IDGATE

38

2.1k

BAT

+

100k

CLPROG

34

35

Li-Ion

NTCBIAS

NTC

10

11

12

20μF

100k

NTC

DV

CC

SDA

SCL

CC

10μH

SDA

SCL

ZLLS400

V

BOOST

18,19,20

SW

499k 499k 499k

μC/μP

1μF

50V

10M

9

42

16

14

LED_OV

EXTPWR

PBSTAT

EXTPWR

PBSTAT

22nF

50V

10-LED BACKLIGHT

22

I

LED

PWR_ON

20k

3

LED_FS

KILL

4.7μH

17

1

V

OUT1

33

26

EN3

SW1

FB1

1.8V

I

LIM0

LIM1

LIM0

LIM1

500mA

10pF

806k

10μF

649k

2

RST

PUSHBUTTON

15

ON

4.7μH

3.3μH

V

LDO1

3.3V

OUT2

31

28

LDO1

SW2

3.3V

150mA

500mA

1μF

1.02M

348k

10pF

1.02M

232k

10μF

324k

464k

23

29

25

5

LDO1_FB

LDO2

FB2

V

1.2V

800mA

V

OUT3

LDO2

SW3

1.4V

150mA

10μF

464k

7

24

LDO2_FB

FB3

21

PGOOD

GND

45

100k

35773 TA02

357734fa

49

LTC3577-3/LTC3577-4

TYPICAL APPLICATION

Si2333DS

Si2306BDS

5V WALL

ADAPTER

D3

5.6V

Si2333DS

4

41

R1

WALL ACPR

500k

V

OUT

SYSTEM

LOAD

13

8

30

39

OVGATE

V

INLDO1

6.2k

10μF

2.2μF

OVSENSE

OPTIONAL OVERVOLTAGE/

REVERSE VOLTAGE PROTECTION

V

OUT

40

32

6

USB

V

BUS

V

IN12

1k

LTC3577-3/

LTC3577-4

10μF

V

IN3

44

37

2k

CHRG

36

43

Si2333DS

(OPT)

PROG

IDGATE

38

2.1k

BAT

+

100k

CLPROG

34

35

Li-Ion

NTCBIAS

NTC

10

11

12

20μF

100k

NTC

DV

CC

SDA

SCL

CC

10μH

SDA

SCL

ZLLS400

V

BOOST

18,19,20

SW

499k 499k 499k

μC/μP

1μF

50V

6M

9

42

16

14

LED_OV

EXTPWR

PBSTAT

EXTPWR

PBSTAT

22nF

50V

6-LED BACKLIGHT

22

I

LED

PWR_ON

20k

3

LED_FS

KILL

4.7μH

17

1

V

OUT1

33

26

EN3

SW1

FB1

3.3V

I

LIM0

LIM1

LIM0

LIM1

500mA

10pF

1.02M

10μF

2

324k

RST

PUSHBUTTON

15

30

31

V

ON

INLDO2

4.7μH

3.3μH

V

1.8V

500mA

LDO1

2.5V

150mA

OUT2

28

LDO1

SW2

1μF

1.00M

115k

10pF

806k

402k

10μF

470k

464k

649k

23

29

25

5

LDO1_FB

LDO2

FB2

V

1.3V

800mA

V

OUT3

LDO2

SW3

1.0V

150mA

7

24

LDO2_FB

FB3

21

PGOOD

GND

45

100k

35773 TA03

357734fa

50

LTC3577-3/LTC3577-4

PACKAGE DESCRIPTION

UFF Package

Variation: UFFMA

44-Lead Plastic QFN (4mm × 7mm)

(Reference LTC DWG # 05-08-1762 Rev Ø)

1.48 0.05

0.70 0.05

0.98 0.05

1.70 0.05

2.56 0.05

4.50 0.05

3.10 0.05

2.40 REF

2.02 0.05

2.76 0.05

2.64 0.05

PACKAGE

OUTLINE

0.20 0.05

5.60 REF

0.40 BSC

6.10 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 s 45o

CHAMFER

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 p0.05

2.40 REF

4.00 p0.10

43

44

0.00 – 0.05

0.40 p0.10

1

2

PIN 1

TOP MARK

(SEE NOTE 6)

2.64

0.10

2.56

0.10

7.00 p0.10

5.60 REF

R = 0.10

TYP

1.70

0.10

2.76

0.10

0.74 0.10

R = 0.10 TYP

0.74 0.10

(UFF44MA) QFN REF Ø 1107

R = 0.10 TYP

0.200 REF

0.20 p0.05

0.40 BSC

0.98 0.10

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

3. ALL DIMENSIONS ARE IN MILLIMETERS

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

357734fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

51

LTC3577-3/LTC3577-4

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTC3455

Dual DC/DC Converter with USB Power

Manager and Li-Ion Battery Charger

Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall

Adapter. Two High Efﬁciency DC/DC Converters: Up to 96%. Full Featured Li-Ion Battery

Charger with Accurate USB Current Limiting (500mA/100mA). Pin Selectable Burst Mode

Operation. Hot Swap^TMOutput for SDIO and Memory Cards. 24-Lead 4mm × 4mm QFN

Package

LTC3456

2-Cell, Multi-Output DC/DC Converter

with USB Power Manager

Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power

Sources. Main Output: Fixed 3.3V Output, Core Output: Adjustable from 0.8V to V

.

BATT(MIN)

Hot Swap Output for Memory Cards. Power Supply Sequencing: Main and Hot Swap

Accurate USB Current Limiting. High Frequency Operation: 1MHz. High Efﬁciency: Up to

92%. 24-Lead 4mm × 4mm QFN Package

2

LTC3555

LTC3556

I C Controlled High Efﬁciency USB

Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max

Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, 3.3V/25mA Always-On LDO,

Three Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28

Package

Power Manager Plus Triple Step-Down

DC/DC

High Efﬁciency USB Power Manager Plus Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max

Dual Buck Plus Buck-Boost DC/DC

Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, 3.3V/25mA Always-On LDO, Two

400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28

Package

LTC3557/

LTC3557-1

USB Power Manager with Li-Ion/Polymer Complete Multifunction ASSP: Linear Power Manager and Three Buck Regulaters

Charger and Triple Synchronous Buck

Converter

Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation

Synchronous Buck Efﬁciency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA

Bat-Track Adaptive Output Control, 200m Ideal Diode, 4mm × 4mm QFN28 Package,

“-1” version has 4.1V Float Voltage.

LTC3566

LTC3567

Switching USB Power Manager with

Li-Ion/Polymer Charger, 1A Buck-Boost

Converter Plus LDO

Multifunction PMIC: Switchmode Power Manager and 1A Buck-Boost Regulator + LDO,

Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation

Synchronous Buck-Boost Converters Efﬁciency: >95%, ADJ Output: Down to 0.8V at 1A,

Bat-Track Adaptive Output Control, 180mꢀ Ideal Diode, 4mm × 4mm QFN24 Package

2

Switching USB Power Manager with

Li-Ion/Polymer Charger, 1A Buck-Boost

Multifunction PMIC: Switchmode Power Manager and 1A Buck-Boost + LDO, I C Interface,

Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation

Synchronous Buck-Boost Converters Efﬁciency: >95%, ADJ Output: down to 0.8V at 1A,

Bat-Track Adaptive Output Control, 180mꢀ Ideal Diode, 4mm x 4mm QFN24 Package

2

Converter Plus LDO, I C Interface

LTC3577/

LTC3577-1

Highly Integrated Protable/Navigation

PMIC

Complete Multifunction PMIC: Linear Power Manager and Three Buck Regulators,

Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation,

Synchronous Buck Converters Efﬁciency: >95%, ADJ Outputs: 0.8V to 3.6V at 800mA/

2

500mA/500mA, Pushbutton Control, I C Interface, 2× 150mA LDOs, Overvoltage

Protection Bat-Track Adaptive Output Control, 200mꢀ Ideal Diode, 4mm × 7mm QFN44

Package,

“-1” version has 4.1V Float Voltage.

LTC4085/

LTC4085-1

USB Power Manager with Ideal Diode

Controller and Li-Ion Charger

Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200m Ideal

Diode with <50m option, 4mm × 3mm DFN14 Package, “-1” version has 4.1V Float Voltage.

LTC4088

High Efﬁciency USB Power Manager and Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max

Battery Charger

Charge Current, 180mꢀ Ideal Diode with <50m Option, 3.3V/25mA Always-On LDO,

4mm × 3mm DFN14 Package

LTC4088-1

High Efﬁciency USB Power Manager and Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max

Battery Charger with Regulated Output

Voltage

Charge Current, 180mꢀ Ideal Diode with <50mꢀ option, Automatic Charge Current

Reduction Maintains 3.6V Minimum Vout, Battery charger disabled when all logic inputs

are grounded, 3mm x 4mm DFN14 package

LTC4088-2

LTC4098

High Efﬁciency USB Power Manager and Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max

Battery Charger with Regulated Output

Voltage

Charge Current, 180mꢀ Ideal Diode with <50mꢀ option, Automatic Charge Current

Reduction Maintains 3.6V Minimum Vout, 3mm x 4mm DFN14 package

USB-Compatible Switchmode Power

Manager with OVP

High V : 38V operating, 60V transient; 66V OVP. Maximizes Available Power from USB

IN

Port, Bat-Track, “Instant-On” Operation, 1.5A Max Charge Current from Wall, 600mA

Charge Current from USB, 180mꢀ Ideal Diode with <50mꢀ option; 3mm x 4mm ultra-thin

QFN20 package

Hot Swap is a trademark of Linear Technology Corporation.

357734fa

LT 0709 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

52

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3577-3
厂家：	Linear
描述：	Highly Integrated Portable Product PMIC 高集成度便携式产品PMIC 集成电源管理电路便携式
文件：	总52页 (文件大小：555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3577-3 [Linear]

相关型号：

LTC3577-3_15

LTC3577-4

LTC3577-4

LTC3577-4_15

LTC3577EUFF#PBF

LTC3577EUFF#TRPBF

LTC3577EUFF-1#PBF

LTC3577EUFF-1PBF

LTC3577EUFF-1TRPBF

LTC3577EUFF-3#PBF

LTC3577EUFF-3PBF

LTC3577EUFF-3TRPBF