LTC3589-1 [Linear]
8-Channel Programmable, Parallelable 1A Buck DC/DCs; 8通道可编程，可并联1A降压型DC / DC
| 型号： | LTC3589-1 |
| 厂家： | 
Linear |
| 描述： | 8-Channel Programmable, Parallelable 1A Buck DC/DCs |
| 文件： | 总36页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3375
8-Channel Programmable,
Parallelable 1A Buck DC/DCs
FeaTures
DescripTion
The LTC®3375 is a digitally programmable high efficiency
multioutput power supply IC. The DC/DCs consist of eight
n
8-Channel Independent Step-Down DC/DCs
n
Master-Slave Configurable for Up to 4A Per Output
Channel with a Single Inductor
synchronous buck converters (I
powered from independent 2.25V to 5.5V input supplies.
up to 1A each) all
OUT
n
Independent V Supply for Each DC/DC
IN
(2.25V to 5.5V)
DC/DC enables, output voltages, operating modes, and
phasing may all be independently programmed over I C
or used in standalone mode via simple I/O with power-up
defaults. The DC/DCs may be used independently or in
parallel to achieve higher output currents of up to 4A per
output with a shared inductor. Alarm levels for high die
n
All DC/DCs Have 0.425V to V Output Voltage Range
IN
2
n
Precision Enable Pin Thresholds for Autonomous
2
Sequencing (or I C Control)
n
1MHz to 3MHz Programmable/Synchronizable
Oscillator Frequency (2MHz Default)
2
n
n
I C Selectable Phasing (90° Steps) Per Channel
2
temperaturemayalsobeprogrammedviaI Cwithamask-
able IRQ output for monitoring DC/DC and system faults.
Programmable Power-On Reset/Watch Dog/
Pushbutton Timing
n
n
Pushbutton ON/OFF/RESET control, power-on reset, and
a watchdog timer provide flexible and reliable power-up
sequencing and system monitoring. The LTC3375 is avail-
able in a low profile 48-lead 7mm × 7mm QFN package.
Die Temperature Monitor Output
48-Lead (7mm × 7mm) QFN Package
applicaTions
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
General Purpose Multichannel Power Supplies
Industrial/Automotive/Communications
n
Typical applicaTion
8-Channel 1A Multioutput Buck Regulator
4V TO 40V
V
SW1
IN1
Buck Efficiency vs Load
0.425V TO V
UP TO 1A
IN1
V
V
SHNT
100
90
ALWAYS-ON
LDO
CC
FB1
MASTER
LTC3375
CC
SINGLE BUCK
DUAL BUCK
TRIPLE BUCK
QUAD BUCK
80
70
FBV
ON
V
SW2
IN2
SLAVE
0.425V TO V
UP TO 1A
IN2
KILL
PB
60
50
PB
FB2
40
30
20
10
0
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
RST
TEMP
WDI
WD0
IRQ
Burst Mode OPERATION
MASTER
MASTER
V
V
f
= 3.3V
IN
OUT
•
•
•
= 1.8V
= 2MHz
OSC
V
SLAVE
IN7
L = 2.2µH
0.425V TO V
UP TO 1A
IN7
SW7
1
10
100
1000
LOAD CURRENT (mA)
FB7
3375 TA01b
V
SLAVE
IN8
0.425V TO V
UP TO 1A
IN8
SW8
2
2
I C
SYNC
FB8
CT
RT
3375 TA01a
3375fa
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For more information www.linear.com/3375
LTC3375
Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 3
Order Information.......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics................................. 4
Typical Performance Characteristics ................... 7
Pin Functions..............................................12
Block Diagram.............................................15
Operation...................................................16
Buck Switching Regulators..................................... 16
Buck Regulators with Combined Power Stages...... 16
Pushbutton Interface.............................................. 17
Power-Up and Power-Down Via Pushbutton........... 17
Applications Information ................................26
Buck Switching Regulator Output Voltage and
Feedback Network ..................................................26
Buck Regulators .....................................................26
Combined Buck Regulators.....................................26
V
Shunt Regulator...............................................28
CC
Input and Output Decoupling Capacitor Selection ..29
Choosing the C Capacitor......................................29
T
Programming the Global Register...........................29
Programming the RST and IRQ Mask Registers.....29
Status Byte Read Back ...........................................29
PCB Considerations................................................31
Typical Applications......................................32
Package Description .....................................35
Typical Application .......................................36
Related Parts..............................................36
2
Power-Up and Power-Down Via Enable Pin or I C .. 19
2
2
2
2
2
2
2
2
I C Interface ...........................................................20
I C Bus Speed.........................................................20
I C Start and Stop Conditions.................................20
I C Byte Format ......................................................20
I C Acknowledge ....................................................20
I C Slave Address...................................................21
I C Sub-Addressed Writing.....................................22
I C Bus Write Operation .........................................22
2
I C Bus Read Operation..........................................22
Error Condition Reporting Via RST and IRQ Pins....22
Temperature Monitoring and
Overtemperature Protection ...................................23
RESET_ALL Functionality .......................................24
Programming the Operating Frequency..................24
V
Shunt Regulator...............................................25
CC
Watchdog Timer .....................................................25
3375fa
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For more information www.linear.com/3375
LTC3375
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
, FB1-8, EN1-8, V , V
, FBV , CT,
IN1-8
CC SHNT CC
ON, KILL, IRQ, RST, PB, WDI, WDO, SYNC, RT,
SDA, SCL ..................................................... –0.3V to 6V
TEMP ...................–0.3V to Lesser of (V + 0.3V) or 6V
CC
FB1 1
36 FB8
I
I
, I , I
, I .................................................5mA
V
2
35 V
IN1
IN8
IRQ RST WDO ON
VSHNT
Operating Junction Temperature Range
SW1 3
SW2 4
34 SW8
33 SW7
......................................................................3mA
V
5
32 V
IN2
IN7
FB2 6
FB3 7
31 FB7
30 FB6
GND
49
(Notes 2, 3)............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
V
8
29 V
IN3
IN6
SW3 9
28 SW6
27 SW5
SW4 10
V
11
26 V
IN4
IN5
FB4 12
25 FB5
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
T
= 150°C, θ = 34°C/W
JA
JMAX
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3375EUK#PBF
LTC3375IUK#PBF
LTC3375HUK#PBF
TAPE AND REEL
PART MARKING*
LTC3375UK
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3375EUK#TRPBF
LTC3375IUK#TRPBF
LTC3375HUK#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
LTC3375UK
LTC3375UK
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3375fa
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For more information www.linear.com/3375
LTC3375
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
Voltage Range
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
V
V
2.7
5.5
V
VCC
CC
l
l
Undervoltage Threshold on V
V
V
Voltage Falling
Voltage Rising
2.35
2.45
2.45
2.55
2.55
2.65
V
V
VCC_UVLO
CC
CC
CC
I
V
V
Input Supply Current
Input Supply Current
All Switching Regulators in Shutdown,
11
25
µA
VCC_ALLOFF
VCC
CC
CC
PB = HIGH
I
At Least 1 Buck Active, SYNC = 0V, R = 400k,
50
85
µA
µA
T
V
= 0.85V
FB_BUCK
At Least 1 Buck Active, SYNC = 2MHz
200
325
f
f
Internal Oscillator Frequency
Synchronization Frequency
V
V
= V , SYNC = 0V
1.8
1.75
1.8
2
2
2
2.2
2.25
2.2
MHz
MHz
MHz
OSC
RT
RT
RT
CC
l
l
= V , SYNC = 0V
CC
R
= 400k, SYNC = 0V
t
, t > 40ns
1
3
MHz
SYNC
LOW HIGH
l
l
V
SYNC
SYNC Level High
SYNC Level Low
1.2
V
V
0.4
l
V
RT
RT Servo Voltage
R
RT
= 400k
780
800
820
mV
Temperature Monitor
TEMP Voltage at 25°C
Slope
V
150
6.75
165
10
mV
mV/°C
°C
TEMP(ROOM)
l
∆V
/°C
TEMP
V
TEMP
OT
Overtemperature Shutdown
Overtemperature Hysteresis
Temperature Rising
OT_HYST
DT_WARN
°C
Die Temperature Warning Threshold (Die DT[1], DT[0] = 00
Inactive
140
125
110
Temperature that Causes IRQ = 0)
DT[1], DT[0] = 01
DT[1], DT[0] = 10
DT[1], DT[0] = 11
°C
°C
°C
1A Buck Regulators
l
l
V
V
V
Buck Input Voltage Range
2.25
5.5
V
V
BUCK
V
FB
V
IN
OUT
l
l
Undervoltage Threshold on V
Burst Mode® Operation
Forced Continuous Mode Operation
Shutdown Input Current
Shutdown Input Current
V
V
Voltage Falling
Voltage Rising
1.95
2.05
2.05
2.15
2.15
2.25
V
V
IN_UVLO
IN
IN
IN
I
V
= 0.85V (Note 4)
18
400
0
50
550
1
µA
µA
µA
µA
VIN_BUCK
FB_BUCK
I
= 0µA, V
= 0V
FB_BUCK
SW_BUCK
All Switching Regulators in Shutdown
At Least One Other Buck Active
1
2
I
PMOS Current Limit
(Note 5)
2.0
705
780
405
2.3
725
800
425
25
2.7
745
820
445
A
mV
mV
mV
mV
nA
FWD
l
l
l
V
V
V
V
(Default)
(High)
Feedback Regulation Voltage
Feedback Regulation Voltage
Feedback Regulation Voltage
Forced Continuous Mode Default (1, 1, 0, 0)
Forced Continuous Mode Full Scale (1, 1, 1, 1)
Forced Continuous Mode Zero Scale (0, 0, 0, 0)
FB
FB
FB
(Low)
V
Servo Voltage Step Size
FB
LSB
I
Feedback Leakage Current
Maximum Duty Cycle
PMOS On-Resistance
NMOS On-Resistance
PMOS Leakage Current
NMOS Leakage Current
V
V
= 0.85V
= 0V
–50
100
50
FB
FB_BUCK
FB_BUCK
SW_BUCK
SW_BUCK
l
DMAX
%
R
R
I
I
= 100mA
= –100mA
265
280
mΩ
mΩ
µA
PMOS
NMOS
LEAKP
LEAKN
I
I
EN_BUCK = 0
EN_BUCK = 0
–2
–2
2
2
µA
2
R
Output Pull-Down Resistance in Shutdown EN_BUCK = 0 (I C Bit Set)
Soft-Start Time Default (1, 1, 0, 0) Reference Voltage
1
1
kΩ
SWPD
t
ms
SS
3375fa
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For more information www.linear.com/3375
LTC3375
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
92.5
1
MAX
UNITS
%
V
V
Falling PGOOD Threshold Voltage
PGOOD Hysteresis
Full-Scale (1, 1, 1, 1) Reference Voltage
PGOOD(FALL)
PGOOD(HYS)
%
Buck Regulators Combined
I
I
I
PMOS Current Limit
PMOS Current Limit
PMOS Current Limit
2 Buck Converters Combined (Note 5)
3 Buck Converters Combined (Note 5)
4 Buck Converters Combined (Note 5)
4.6
6.9
9.2
A
A
A
FWD2
FWD3
FWD4
V
Regulator
CC
V
FBV Regulation Voltage
1.17
1.2
1.23
V
FBVCC
CC
R
Pull-Down Resistance for V
(Regulator)
200
Ω
REG
CC
V
V
Clamp Voltage
I
= 2mA, FBV = 0V
6.1
V
VSHNT_MAX
SHNT
SHNT
CC
R
Pull-Down Resistance for V
(Clamp)
200
Ω
CLAMP
SHNT
2
I C Port
2
l
l
l
ADDRESS
I C Address
0110100[R/WB]
V
V
Input High Voltage
SDA/SCL
SDA/SCL
SDA/SCL
SDA/SCL
1.2
V
V
IH
IL
Input Low Voltage
0.4
50
I
IH
I
IL
Input High Current
nA
nA
V
Input Low Current
50
V
SDA Output Low Voltage
Clock Operating Frequency
I
= 3mA
0.4
400
OL_SDA
SCL
SDA
f
t
kHz
µs
Bus Free Time Between Stop and Start
Condition
1.3
0.6
BUF
t
Hold Time After Repeated Start
Condition
µs
HD_SDA
t
t
t
t
t
t
t
t
t
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Output
Data Hold Time Input
0.6
0.6
0
µs
µs
ns
ns
ns
µs
µs
ns
ns
SU_STA
SU_STO
HD_DAT(O)
HD_DAT(I)
SU_DAT
LOW
900
0
Data Set-Up Time
250
1.3
0.6
SCL Clock Low Period
SCL Clock High Period
Clock/Data Fall Time
HIGH
C = Capacitance of One Bus Line (pF)
20+0.1C
20+0.1C
300
300
f
B
B
Clock/Data Rise Time
C = Capacitance of One Bus Line (pF)
B
r
B
Interface Logic Pins (ON, KILL, RST, IRQ, PB, WDI, WDO)
I
Output High Leakage Current
Output Low Voltage
ON, RST, IRQ, WDO 5.5V at Pin
ON, RST, IRQ, WDO 3mA Into Pin
KILL, PB, WDI
-1
1
µA
V
OH
V
V
V
0.1
0.4
OL
l
l
Input High Threshold
1.2
V
IH
Input Low Threshold
KILL, PB, WDI
0.4
2
mV
sec
ms
µs
IL
t
t
t
Time From Last WDI
1.5
WDI
WDO
WDRESET
WDO Low Time Absent a Transition at WDI
200
Time From a WDI Transition Until the
WD Timer Is Reset
3375fa
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For more information www.linear.com/3375
LTC3375
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Interface Logic Pins (EN1, EN2, EN3, EN4, EN5, EN6, EN7, EN8)
l
l
V
V
V
Enable Rising Threshold
Enable Hysteresis
All Regulators Disabled
400
730
60
1200
mV
mV
mV
µA
HI_ALLOFF
EN_HYS
HI
Enable Rising Threshold
Enable Pin Leakage Current
At Least One Regulator Enabled
380
–1
400
420
1
I
EN
EN = V = V = 5.5V
CC IN
Pushbutton Parameters, C = 0.01µF
T
t
t
t
t
PB Low Time to IRQ Low
PB Low Time to ON High
PB Low to ON Forced Low
ON High
28
140
7
50
200
10
1
72
260
13
ms
ms
sec
sec
PB_LO
PB_ON
PB_OFF
HR
Time for Which All Enabled Regulators
Are Disabled After KILL is Asserted High
ON High
ON High
0.7
1.3
t
t
IRQ Minimum Pulse Width
28
7
50
10
72
13
ms
sec
IRQ_PW
Time in Which KILL Must Be Asserted
High
After ON Rising Edge
KILLH
t
t
KILL Low Time to ON Low
RST Assertion Delay
ON High
28
50
72
ms
ms
KILLL
160
230
300
RST
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
(T in °C) is calculated from the ambient temperature (T in °C) and
J A
power dissipation (P in Watts) according to the formula:
D
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
Note 2: The LTC3375 is tested under pulsed load conditions such that
Note 3: The LTC3375 includes overtemperature protection which protects
the device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 4: Static current, switches not switching. Actual current may be
higher due to gate charge losses at the switching frequency.
Note 5: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the maximum specified pin current rating may result in device
degradation over time.
T ≈ T . The LTC3375E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3375I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3375H is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125°C. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
3375fa
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LTC3375
Typical perForMance characTerisTics
VCC Undervoltage Threshold
vs Temperature
Buck VIN Undervoltage Threshold
vs Temperature
VCC Supply Current
vs Temperature
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
60
55
50
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
ALL REGULATORS
IN SHUTDOWN
45
40
35
V
RISING
V
RISING
CC
IN
30
25
20
15
10
5
V
FALLING
V
IN
FALLING
CC
V
= 5.5V
= 3.3V
CC
V
V
CC
CC
= 2.7V
0
50 75
50 75
25
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
50 75
–50 –25
0
100 125 150
–50 –25
0
25
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
3375 G01
3375 G03
3375 G02
VCC Supply Current
vs Temperature
VCC Supply Current
vs Temperature
RT Programmed Oscillator
Frequency vs Temperature
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
125
100
75
50
25
0
400
360
320
280
240
200
160
120
80
AT LEAST ONE BUCK ENABLED
SYNC = 0V
FB = 850mV
AT LEAST ONE BUCK ENABLED
SYNC = 2MHz
R
= 400k
RT
V
V
= 5.5V
= 3.3V
CC
CC
V
V
= 5.5V
= 3.3V
CC
CC
V
= 2.7V
CC
V
= 2.7V
CC
V
CC
V
CC
V
CC
= 5.5V
= 3.3V
= 2.7V
40
0
50 75
–50 –25
0
25
50 75
100 125 150
50 75
–50 –25
–50 –25
0
25
100 125 150
0
25
100 125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3375 G04
3375 G05
3375 G06
Default Oscillator Frequency
vs Temperature
Oscillator Frequency vs RT
Oscillator Frequency vs VCC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
V
= 3.3V
V
= V
CC
CC
RT
V
= V
CC
RT
R
RT
= 400k
V
CC
V
CC
V
CC
= 5.5V
= 3.3V
= 2.7V
450 500
250 300 350 400
550 600 650 700 750 800
50 75
TEMPERATURE (°C)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
–50 –25
0
25
100 125 150
R
RT
(kΩ)
V
CC
3375 G09
3375 G07
3375 G08
3375fa
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For more information www.linear.com/3375
LTC3375
Typical perForMance characTerisTics
Enable Pin Precision Threshold
vs Temperature
VTEMP vs Temperature
Enable Threshold vs Temperature
900
850
800
750
700
650
600
550
500
450
400
1400
1200
1000
800
600
400
200
0
420
415
410
405
400
395
390
385
380
ALL REGULATORS DISABLED
ALL REGULATORS DISABLED
V
= 3.3V
V
= 3.3V
CC
CC
EN RISING
EN RISING
EN FALLING
EN FALLING
ACTUAL V
TEMP
IDEAL V
20
TEMP
–200
0
40
60
80 100 120 140
–50
50
100 125
150
–50 –25
0
25
50 75
TEMPERATURE (°C)
100 125 150
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
3375 G11
3375 G12
3375 G10
Buck VIN Supply Current
vs Temperature
Buck VIN Supply Current
vs Temperature
VOUT vs Temperature
50
40
30
20
10
0
550
500
450
1.88
1.86
1.84
1.82
1.8
Burst Mode OPERATION
FB = 850mV
FORCED CONTINUOUS MODE
FB = 0V
FORCED CONTINUOUS MODE
LOAD = 0mA
V
IN
= 5.5V
400
350
V
V
= 3.3V
IN
= 2.25V
V
IN
= 5.5V
IN
300
250
200
V
IN
= 5.5V
V
IN
= 2.25V
1.78
1.76
1.74
1.72
V = 3.3V
IN
V
IN
= 2.25V
150
100
50
V
IN
= 3.3V
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G14
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G13
3375 G15
PMOS Current Limit
vs Temperature
PMOS RDS(ON) vs Temperature
NMOS RDS(ON) vs Temperature
2.6
2.5
2.4
2.3
2.2
2.1
2
600
550
500
450
400
350
300
250
200
600
550
500
450
400
350
300
250
200
V
IN
= 3.3V
V
IN
= 2.25V
V
IN
= 2.25V
V
IN
= 3.3V
V
IN
= 3.3V
V
IN
= 5.5V
V
IN
= 5.5V
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G16
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G17
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G18
3375fa
8
For more information www.linear.com/3375
LTC3375
Typical perForMance characTerisTics
VSHNT Clamp Voltage
vs Temperature
VCC vs Temperature
1A Buck Efficiency vs ILOAD
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
6.20
6.18
6.16
6.14
6.12
6.10
6.08
6.06
6.04
6.02
6.00
100
90
80
70
60
50
40
30
20
10
0
Burst Mode OPERATION
FOR V FEEDBACK DIVIDER
CC
R
TOP
R
BOT
= 187k
= 107k
V
V
V
V
V
V
= 2.25V
= 3.3V
= 5.5V
= 2.25V
= 3.3V
= 5.5V
IN
IN
IN
IN
IN
IN
FORCED CONTINUOUS MODE
10 100
LOAD CURRENT(mA)
–50
50
100 125
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3375 G20
–25
0
25
75
150
1
1000
TEMPERATURE (°C)
V
f
= 1.8V
OUT
OSC
3375 G19
3375 G21
= 2MHz
L = 2.2µH
1A Buck Efficiency vs ILOAD
2A Buck Efficiency vs ILOAD
2A Buck Efficiency vs ILOAD
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
Burst Mode
OPERATION
Burst Mode
OPERATION
V
V
V
V
V
V
= 2.7V
= 3.3V
= 5.5V
= 2.7V
= 3.3V
= 5.5V
V
V
V
V
V
V
= 2.25V
= 3.3V
= 5.5V
= 2.25V
= 3.3V
= 5.5V
V
= 2.7V
= 3.3V
= 5.5V
= 2.7V
= 3.3V
= 5.5V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
V
V
V
V
V
FORCED CONTINUOUS MODE
FORCED CONTINUOUS MODE
10 100
LOAD CURRENT(mA)
FORCED CONTINUOUS MODE
10 100
LOAD CURRENT(mA)
1
10
100
1000
1
1000
1
1000
LOAD CURRENT(mA)
V
= 2.5V
V
= 1.8V
V
= 2.5V
OUT
OSC
OUT
OSC
OUT
OSC
3375 G22
3375 G23
3375 G24
f
= 2MHz
f
= 2MHz
f
= 2MHz
L = 2.2µH
L = 2.2µH
L = 2.2µH
3A Buck Efficiency vs ILOAD
3A Buck Efficiency vs ILOAD
4A Buck Efficiency vs ILOAD
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
Burst Mode
OPERATION
Burst Mode
OPERATION
V
V
V
V
V
V
= 2.25V
= 3.3V
= 5.5V
= 2.25V
= 3.3V
= 5.5V
V
= 2.7V
= 3.3V
= 5.5V
= 2.7V
= 3.3V
= 5.5V
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.25V
= 3.3V
= 5.5V
= 2.25V
= 3.3V
= 5.5V
IN
IN
IN
IN
IN
IN
IN
V
V
V
V
V
IN
IN
IN
IN
IN
FORCED CONTINUOUS MODE
100
1000
LOAD CURRENT(mA)
FORCED CONTINUOUS MODE
10 100
1000
LOAD CURRENT(mA)
FORCED CONTINUOUS MODE
100
1000
LOAD CURRENT(mA)
1
10
1
1
10
V
= 1.8V
V
= 2.5V
V
= 1.8V
OUT
OSC
OUT
OSC
OUT
OSC
3375 G25
3375 G26
3375 G27
f
= 2MHz
f
= 2MHz
f
= 2MHz
L = 2.2µH
L = 2.2µH
L = 2.2µH
3375fa
9
For more information www.linear.com/3375
LTC3375
Typical perForMance characTerisTics
1A Buck Efficiency vs Frequency
(Forced Continuous Mode)
1A Buck Efficiency vs Frequency
4A Buck Efficiency vs ILOAD
(Forced Continuous Mode)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 2.25V
= 3.3V
IN
I
I
I
= 100mA
= 500mA
= 20mA
L
L
L
V
IN
Burst Mode
OPERATION
V
= 5.5V
IN
V
V
V
V
V
V
= 2.7V
= 3.3V
= 5.5V
= 2.7V
= 3.3V
= 5.5V
IN
IN
IN
IN
IN
IN
V
I
= 1.8V
V
V
= 1.8V
OUT
L
OUT
IN
= 100mA
= 3.3V
L = 3.3µH
L = 3.3µH
FORCED CONTINUOUS MODE
100
1000
LOAD CURRENT(mA)
2.2 2.4
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
1
10
1
1.2 1.4 1.6 1.8
2
2.6 2.8
3
FREQUENCY (MHz)
FREQUENCY (MHz)
V
= 2.5V
OUT
OSC
3375 G28
3375 G29
3375 G30
f
= 2MHz
L = 2.2µH
1A Buck Efficiency vs ILOAD
(Across Operating Frequency)
1A Buck Regulator Load Regulation
(Forced Continuous Mode)
4A Buck Regulator Load Regulation
(Forced Continuous Mode)
100
90
80
70
60
50
40
30
20
10
0
1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
Burst Mode OPERATION
V
V
V
= 5.5V
= 3.3V
= 2.25V
V
V
= 5.5V
= 3.3V
IN
IN
IN
IN
f
f
f
f
f
f
OSC = 1MHz, L = 3.3µH
OSC = 2MHz, L = 2.2µH
OSC = 3MHz, L = 1µH
OSC = 1MHz, L = 3.3µH
OSC = 2MHz, L = 2.2µH
OSC = 3MHz, L = 1µH
1.796
1.792
1.788
1.784
1.78
1.796
1.792
1.788
1.784
1.78
IN
V
= 2.25V
IN
DROPOUT
DROPOUT
f
= 2MHz
f
= 2MHz
OSC
L = 2.2µH
OSC
L = 2.2µH
FORCED CONTINUOUS MODE
10 100
LOAD CURRENT(mA)
1
10
100
1000
1
10
100
1000
1
1000
I
(mA)
I
(mA)
L
L
V
V
= 1.8V
OUT
IN
3375 G31
3375 G32
3375 G33
= 3.3V
4A Buck Regulator No Load
Startup Transient
(Forced Continuous Mode)
1A Buck Regulator Line Regulation
(Forced Continuous Mode)
1A Buck Regulator No Load
Startup Transient (Burst Mode)
1.82
1.815
1.81
V
V
OUT
OUT
1.805
1.8
500mV/DIV
500mV/DIV
I
= 100mA
L
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
I
500mA
L
1.795
1.79
EN
EN
2V/DIV
2V/DIV
3375 G35
3375 G36
200µs/DIV
200µs/DIV
1.785
1.78
f
= 2MHz
OSC
L = 2.2µH
2.25 2.75 3.25 3.75 4.25 4.75 5.25
(V)
V
IN
3375 G34
3375fa
10
For more information www.linear.com/3375
LTC3375
Typical perForMance characTerisTics
1A Buck Regulator,
Transient Response
1A Buck Regulator, Transient
Response (Burst Mode)
(Forced Continuous Mode)
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
INDUCTOR
CURRENT
200mA/DIV
INDUCTOR
CURRENT
200mA/DIV
0mA
0mA
3375 G37
3375 G38
50µs/DIV
50µs/DIV
LOAD STEP = 100mA TO 700mA
LOAD STEP = 100mA TO 700mA
V
= 3.3V, V
= 1.8V
V
= 3.3V, V
= 1.8V
IN
OUT
IN
OUT
4A Buck Regulator,
4A Buck Regulator, Transient
Response (Burst Mode)
Transient Response
(Forced Continuous Mode)
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
0mA
0mA
3375 G39
3375 G40
50µs/DIV
50µs/DIV
LOAD STEP = 100mA TO 2.8A
LOAD STEP = 400mA TO 2.8A
V
= 3.3V, V
= 1.8V
V
= 3.3V, V
= 1.8V
IN
OUT
IN
OUT
3375fa
11
For more information www.linear.com/3375
LTC3375
pin FuncTions
FB1 (Pin 1): Buck Regulator 1 Feedback Pin. Receives
feedbackbyaresistordividerconnectedacrosstheoutput.
V
(Pin 11): Buck Regulator 4 Input Supply. Bypass
IN4
to GND with a 10µF or larger ceramic capacitor. May be
drivenbyanindependentsupplyormustbeshortedtoV
IN3
V
(Pin 2): Buck Regulator 1 Input Supply. Bypass to
IN1
when buck regulator 4 is combined with buck regulator 3
for higher current.
GND with a 10µF or larger ceramic capacitor.
SW1 (Pin 3): Buck Regulator 1 Switch Node. External
inductor connects to this pin.
FB4 (Pin 12): Buck Regulator 4 Feedback Pin. Receives
feedbackbyaresistordividerconnectedacrosstheoutput.
SW2 (Pin 4): Buck Regulator 2 Switch Node. External
inductor connects to this pin.
Connecting FB4 to V combines buck regulator 4 with
IN4
buck regulator 3 for higher current. Up to 4 converters
may be combined in this way.
V
(Pin5):BuckRegulator2InputSupply.BypasstoGND
IN2
with a 10µF or larger ceramic capacitor. May be driven by
EN4 (Pin 13): Buck Regulator 4 Enable Input. Active high.
EN3 (Pin 14): Buck Regulator 3 Enable Input. Active high.
an independent supply or must be shorted to V when
IN1
buck regulator 2 is combined with buck regulator 1 for
higher current.
IRQ(Pin15):InterruptPin(ActiveLow).Open-drainoutput.
Whenanundervoltage,dietemperature,orunmaskederror
condition is detected, this pin is driven LOW.
FB2 (Pin 6): Buck Regulator 2 Feedback Pin. Receives
feedbackbyaresistordividerconnectedacrosstheoutput.
Connecting FB2 to V combines buck regulator 2 with
RST (Pin 16): Reset Pin (Active Low). Open-drain output.
When the regulated output voltage of any unmasked
enabled switching regulator is more than 7.5% below its
programmed level, this pin is driven LOW. Assertion delay
is scaled by the C capacitor. When all buck regulators are
disabled RST is driven LOW.
IN2
buck regulator 1 for higher current. Up to 4 converters
may be combined in this way.
FB3 (Pin 7): Buck Regulator 3 Feedback Pin. Receives
T
feedbackbyaresistordividerconnectedacrosstheoutput.
Connecting FB3 to V combines buck regulator 3 with
IN3
buck regulator 2 for higher current. Up to 4 converters
CT (Pin 17): Timing Capacitor Pin. A capacitor connected
to GND sets a time constant which is scaled for use by
the ON, KILL, PB, RST and IRQ pins.
may be combined in this way.
V
(Pin8):BuckRegulator3InputSupply.BypasstoGND
IN3
with a 10µF or larger ceramic capacitor. May be driven by
SYNC (Pin 18): Oscillator Synchronization Pin. Driving
SYNC with an external clock signal will synchronize all
switcherstotheappliedfrequency.Theslopecompensation
is automatically adapted to the external clock frequency.
The absence of an external clock signal will enable the
frequency programmed by the RT pin. Do not float.
an independent supply or must be shorted to V when
IN2
buck regulator 3 is combined with buck regulator 2 for
higher current.
SW3 (Pin 9): Buck Regulator 3 Switch Node. External
inductor connects to this pin.
RT (Pin 19): Oscillator Frequency Pin. This pin provides
twomodesofsettingtheswitchingfrequency.Connectinga
resistorfromRTtogroundwillsettheswitchingfrequency
SW4 (Pin 10): Buck Regulator 4 Switch Node. External
inductor connects to this pin.
based on the resistor value. If RT is tied to V the default
CC
3375fa
12
For more information www.linear.com/3375
LTC3375
pin FuncTions
internal 2MHz oscillator will be used. Do not float.
SW6 (Pin 28): Buck Regulator 6 Switch Node. External
inductor connects to this pin.
ON (Pin 20): Open-Drain Output. When the PB pin is
pressed and released, the signal is debounced and the
ON signal is held HIGH for a minimum time period that
V
(Pin 29): Buck Regulator 6 Input Supply. Bypass
IN6
to GND with a 10µF or larger ceramic capacitor. May be
is scaled by the C capacitor. ON is forced low if: a) KILL
drivenbyanindependentsupplyormustbeshortedtoV
T
IN5
is not driven high (by µP) within 10 seconds of the initial
valid PB power turn-on event, b) KILL is driven low during
normal operation, c) PB is pressed and held low for 10
when buck regulator 6 is combined with buck regulator 5
for higher current.
FB6 (Pin 30): Buck Regulator 6 Feedback Pin. Receives
2
seconds during normal operation, d) a RESET_ALL I C
feedbackbyaresistordividerconnectedacrosstheoutput.
command is written. This pin can connect directly to a
DC/DC converter enable pin that provides an internal pull-
up. Otherwise a pull-up resistor to an external supply is
Connecting FB6 to V combines buck regulator 6 with
IN6
buck regulator 5 for higher current. Up to 4 converters
may be combined in this way.
required.AllassociatedtimesarescaledbytheC capacitor.
T
FB7 (Pin 31): Buck Regulator 7 Feedback Pin. Receives
PB (Pin 21): Pushbutton Input. Active low. PB is internally
feedbackbyaresistordividerconnectedacrosstheoutput.
pulled to V through a 420k (typical) resistor.
CC
Connecting FB7 to V combines buck regulator 7 with
IN7
KILL (Pin 22): Kill Input Pin. Forcing KILL low releases
the ON output which in turn is forced low. While KILL is
low, the buck converters will be forced to power down and
buck regulator 6 for higher current. Up to 4 converters
may be combined in this way.
V
(Pin 32): Buck Regulator 7 Input Supply. Bypass
IN7
will remain powered down for 1 second (scaled by the C
T
to GND with a 10µF or larger ceramic capacitor. May be
capacitor) after KILL returns high. During system turn-
drivenbyanindependentsupplyormustbeshortedtoV
IN6
on, this pin is blanked by a 10 second (scaled by the C
T
when buck regulator 7 is combined with buck regulator 6
capacitor) (t
) to allow the system to pull KILL high.
KILLH
for higher current.
If unused, connect to V .
CC
SW7 (Pin 33): Buck Regulator 7 Switch Node. External
inductor connects to this pin.
EN6 (Pin 23): Buck Regulator 6 Enable Input. Active high.
EN5 (Pin 24): Buck Regulator 5 Enable Input. Active high.
SW8 (Pin 34): Buck Regulator 8 Switch Node. External
inductor connects to this pin.
FB5 (Pin 25): Buck Regulator 5 Feedback Pin. Receives
feedbackbyaresistordividerconnectedacrosstheoutput.
V
(Pin 35): Buck Regulator 8 Input Supply. Bypass
IN8
Connecting FB5 to V combines buck regulator 5 with
IN5
to GND with a 10µF or larger ceramic capacitor. May be
buck regulator 4 for higher current. Up to 4 converters
drivenbyanindependentsupplyormustbeshortedtoV
IN7
may be combined in this way.
when buck regulator 8 is combined with buck regulator 7
V
(Pin 26): Buck Regulator 5 Input Supply. Bypass
for higher current.
IN5
to GND with a 10µF or larger ceramic capacitor. May be
FB8 (Pin 36): Buck Regulator 8 Feedback Pin. Receives
drivenbyanindependentsupplyormustbeshortedtoV
IN4
feedbackbyaresistordividerconnectedacrosstheoutput.
when buck regulator 5 is combined with buck regulator 4
Connecting FB8 to V combines buck regulator 8 with
IN8
for higher current.
buck regulator 7 for higher current. Up to 4 converters
SW5 (Pin 27): Buck Regulator 5 Switch Node. External
inductor connects to this pin.
may be combined in this way.
3375fa
13
For more information www.linear.com/3375
LTC3375
pin FuncTions
EN8 (Pin 37): Buck Regulator 8 Enable Input. Active high.
V
SHNT
should be connected to the base/gate of an external
highvoltageNPN/NFETtransistorandtoitscollector/drain
through a resistor.
EN7 (Pin 38): Buck Regulator 7 Enable Input. Active high.
WDO (Pin 39): Watchdog Timer Output. Open-drain
output. WDO is pulled low for 200ms during a watchdog
timer failure.
TEMP (Pin 44): Temperature Indication Pin. TEMP out-
puts a voltage of 150mV (typical) at room temperature.
The TEMP voltage will change by 6.75mV/°C (typical)
giving an external indication of the LTC3375 internal die
temperature.
WDI (Pin 40): Watchdog Timer Input. The WDI pin must
be toggled either low to high or high to low every 1.5
seconds. Failure to toggle WDI results in the WDO pin
being pulled low for 200ms.
2
SCL (Pin 45): Serial Clock Line for I C Port.
2
SDA (Pin 46): Serial Data Line for I C Port. Open-drain
V
(Pin 41): Always-On LDO Output Voltage/Internal
CC
output during read back.
Bias Supply. When used as a regulator, V should be
CC
connected to the emitter/source of the external LDO NPN/
EN2 (Pin 47): Buck Regulator 2 Enable Input. Active high.
EN1 (Pin 48): Buck Regulator 1 Enable Input. Active high.
NFET transistor. V serves as a low voltage rail that may
CC
be used to provide power to external circuitry, and is
GND (Exposed Pad Pin 49): Ground. The exposed pad
must be connected to a continuous ground plane on the
printedcircuitboarddirectlyundertheLTC3375forelectri-
cal contact and rated thermal performance.
also used to power the internal top level circuitry of the
LTC3375. Alternatively the V pin may be connected to
CC
a 2.7V to 5.5V external power supply. In this case FBV
CC
and V
should be tied to ground.
SHNT
FBV (Pin 42): Always-On LDO Feedback Pin. Receives
CC
feedback by a resistor divider connected across V .
CC
V
SHNT
(Pin 43): Shunt Regulator Base Control Voltage.
3375fa
14
For more information www.linear.com/3375
LTC3375
block DiagraM
V
CC
41
SCL
45
46
TOP LOGIC,
CT OSCILLATOR
TIMING
2
LDO
I C
SDA
+
–
1.2V
V
SHNT
43
42
RST
IRQ
KILL
ON
FBV
CC
16
15
22
20
17
21
40
39
SYNC
RT
18
19
REF, CLK
CT
PB
BANDGAP,
OSCILLATOR,
UV, OT
TEMP
WDI
WDO
44
TEMP MONITOR
OUTPUT VOLTAGE, SLEW CONTROL
MODE, PHASE, EN, STATUS BITS
V
V
IN1
IN8
2
3
35
34
36
37
SW1
FB1
SW8
FB8
BUCK REGULATOR 1
1A
BUCK REGULATOR 8
1A
1
EN1
EN8
48
MASTER/SLAVE LINES
MASTER/SLAVE LINES
V
V
IN2
IN7
5
4
32
33
31
38
SW2
FB2
SW7
FB7
BUCK REGULATOR 2
1A
BUCK REGULATOR 7
1A
6
EN2
EN7
47
MASTER/SLAVE LINES
MASTER/SLAVE LINES
V
V
IN3
IN6
8
9
29
28
30
23
SW3
FB3
SW6
FB6
BUCK REGULATOR 3
1A
BUCK REGULATOR 6
1A
7
EN3
EN6
14
MASTER/SLAVE LINES
MASTER/SLAVE LINES
V
V
IN4
IN5
11
10
12
13
26
27
25
24
SW4
FB4
SW5
FB5
BUCK REGULATOR 4
1A
BUCK REGULATOR 5
1A
EN4
EN5
MASTER/SLAVE LINES
GND (EXPOSED PAD)
49
3375 BD
3375fa
15
For more information www.linear.com/3375
LTC3375
operaTion
Buck Switching Regulators
additiontosimpleON/OFFcontrol. Eachbuckmayhaveits
2
phase programmed in 90° phase steps via I C. The phase
The LTC3375 contains eight monolithic 1A synchronous
buck switching regulators. All of the switching regulators
areinternallycompensatedandneedonlyexternalfeedback
resistors to set the output voltage. The switching regula-
tors offer two operating modes: Burst Mode operation
(power-up default mode) for higher efficiency at light
loads and forced continuous PWM mode for lower noise
at light loads. In Burst Mode operation at light loads, the
output capacitor is charged to a voltage slightly higher
thanitsregulationpoint.Theregulatorthengoesintosleep
mode,duringwhichtimetheoutputcapacitorprovidesthe
load current. In sleep most of the regulator’s circuitry is
powered down, helping conserve input power. When the
output capacitor droops below its programmed value, the
circuitry is powered on and another burst cycle begins.
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate at constant
frequency PWM mode operation. In forced continuous
step command programs the fixed edge of the switching
sequence, which is when the PMOS turns on. The PMOS
off(NMOSon)phaseissubjecttothedutycycledemanded
by the regulator. Bucks 1 and 2 default to 0°, bucks 3 and 4
default to 90°, bucks 5 and 6 default to 180°, and bucks 7
and 8 default to 270°. Each buck can have its feedback
voltage independently programmed in 25mV increments
from 425mV to 800mV. All regulators’ feedback voltages
defaultto725mVatinitialpower-up.Incaseswherepower
stages are combined, the register content of the master
program the combined buck regulator’s behavior and the
register contents of the slave are ignored.
2
Two additional I C commands act on all the buck switch-
2
ing regulators together. In shutdown, an I C control bit
keeps all the SW nodes in a high impedance state (default)
or forces all the SW nodes to decay to GND through 1k
(typical) resistors. Also, the slew rate of the SW nodes
may be switched from the default value to a lower value
for reduced radiated EMI at the cost of a small drop in
efficiency.
2
mode (selectable via I C command), the oscillator runs
continuously and the buck switch currents are allowed
to reverse under very light load conditions to maintain
regulation. This mode allows the buck to run at a fixed
frequency with minimal output ripple.
Each buck regulator may be enabled via its enable pin or
2
I C. The buck regulator enable pins may be tied to V
OUT
voltages, through a resistor divider, to program power-
Each buck switching regulator has its own V , SW, FB
up sequencing. If a different power-down sequence is
IN
2
and EN pin to maximize flexibility. The enable pins have
two different enable threshold voltages that depend on
the operating state of the LTC3375. With all regulators
disabled,theenablepinthresholdissetto730mV(typical).
Once any regulator is enabled, the enable pin thresholds
of the remaining regulators are set to a bandgap-based
400mV and the EN pins are each monitored by a precision
comparator. This precision EN threshold may be used to
provide event-based sequencing via feedback from other
previously enabled regulators. All buck regulators have
forward and reverse-current limiting, soft-start to limit
inrushcurrentduringstart-up,andshort-circuitprotection.
required, the enables can be redundantly written via I C.
2
The EN pins can then be ignored via an I C command,
and the switching regulators may be powered down via
2
I C while the EN pins remain tied to the output voltages
of other regulators.
In addition to many programming options, there are also
17 bits of data that may be read back to report fault condi-
2
tions on the LTC3375, and all I C commands can be read
back prior to executing.
Buck Regulators with Combined Power Stages
Up to four adjacent buck regulators may be combined
in a master-slave configuration by connecting their SW
Each buck can operate in standalone mode using the EN
pin in its default MODE and FB reference settings, or be
pins together, connecting their V pins together, and
IN
2
2
fully controlled using the I C port. I C commands may
be used to independently program each buck regulators’
operating mode, oscillator phase, and reference voltage in
connecting the higher numbered bucks’ FB pin(s) to the
input supply. The lowest numbered buck is always the
master. In Figure 1, buck regulator 1 is the master. The
3375fa
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LTC3375
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feedback network connected to the FB1 pin programs
the output voltage to 1.2V. The FB2 pin is tied to V
which configures buck regulator 2 as the slave. The SW1
and SW2 pins must be tied together, as must the V and
The LTC3375 is in an off state when it is powered up with
all regulators in shutdown. The ON pin is LOW in the off
state. The ON pin will go HIGH if PB is pulled LOW for
200ms. The ON pin stays in its HIGH state for 10 seconds
and then returns LOW unless KILL is asserted HIGH in
this time in which case ON will remain HIGH. If KILL goes
LOW, for longer than a 50ms debounce time, while ON is
HIGH after the 10 second time has expired, ON will again
go to its LOW state. PB being held low causes the KILL
pin to be ignored.
,
IN1/2
IN1
V
pins. The register contents of the master program,
IN2
the combined buck regulator’s behavior, and the register
contents of the slave are ignored. The slave buck control
circuitry draws no current. The enable of the master buck
(EN1) controls the operation of the combined bucks; the
enableoftheslaveregulator(EN2)mustbetiedtoground.
Once in the “on” state (ON pin is HIGH), the LTC3375 can
be powered down in one of three ways that allow for flex-
ibilitybetweenhardwareandsoftwaresystemresets.First,
if PB is held LOW for at least 10 seconds, then ON will
be driven LOW. This will not force a hard reset on any of
the buck switching regulators. The ON pin, however, may
be used to either drive the EN pin of the first sequenced
buck converter or that of an upstream high voltage buck
switching regulator. In this case the IRQ pin is latched to
its LOW state to indicate a PB induced reset. Second, if
the PB pin is driven LOW for longer than 50ms but less
than 10 seconds, the IRQ pin will be pulled LOW for as
long as the PB pin remains LOW. If a microcontroller sees
a transient IRQ LOW signal, then this should signal that
the user has pressed the PB. A software power-down may
then be initiated if so desired. Finally, if the KILL input is
driven LOW for longer than 50ms, then a hard reset will
be initiated. All enabled buck switching regulators will
be turned off while KILL is low and will remain powered
down for 1 second after KILL returns high. KILL being
low also forces a hard reset while the pushbutton is in the
“off” state. A hard reset may also be generated by using
Any combination of 2, 3, or 4 adjacent buck regulators
may be combined to provide either 2A, 3A, or 4A of aver-
age output load current. For example, buck regulator 1
and buck regulator 2 may run independently, while buck
regulators 3 and 4 may be combined to provide 2A, while
buck regulators 5 through 8 may be combined to provide
4A. Buck regulator 1 is never a slave, and buck regulator 8
is never a master. 15 unique output power stage configu-
rations are possible to maximize application flexibility.
V
IN
L1
V
1.2V
2A
OUT
SW1
V
IN1
C
OUT
BUCK REGULATOR 1
(MASTER)
475k
725k
EN1
FB1
SW2
V
IN2
V
IN
BUCK REGULATOR 2
(SLAVE)
EN2
FB2
2
3375 F01
the RESET_ALL I C command that will last for 1 second.
The pushbutton will return to the “off” state. KILL must be
Figure 1. Buck Regulators Configured as Master-Slave
2
high to power-up using EN pins or I C. In any hard reset
2
event all buck regulator I C bits are set low.
Pushbutton Interface
Power-Up and Power-Down Via Pushbutton
The LTC3375 includes a pushbutton interface which can
be used to provide power-up or power-down control
for either the part or the application. The PB, KILL, and
ON pins provide the user with flexibility to power-up or
The LTC3375 may be turned on and off using the PB,
KILL, and ON pins as shown in Figures 2a and 2b. In
Figures 2a and 2b, pressing PB LOW at time t , causes
1
2
power-down the part in addition to having I C control. All
the ON pin to go HIGH at time t and stay HIGH for at least
2
PB timing parameters are scaled using the CT pin. Times
10 seconds after which ON will go LOW unless KILL has
described below apply to a nominal C capacitor of 0.01µF.
been asserted high. ON can be connected to the EN pin
T
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LTC3375
t
operaTion
PB_ON
PB
ON
t
KILLH
(TIED TO EN1)
KILL = 0
SEQUENCE UP
SEQUENCE DOWN
BUCK1-BUCK8
3375 F02a
HARD RESET
t
t
t
3
KILL NOT ASSERTED
1
2
BEFORE t
3
Figure 2a. Power-Up Using PB (Sequenced Power-Up, Figure 8)
t
PB_ON
t
PB_OFF
PB
ON
t
KILLH
(TIED TO EN1)
KILL
DON’T CARE
BUCK1-BUCK8
SEQUENCE DOWN
SEQUENCE UP
IRQ
HARD RESET
3375 F02b
t
1
t
t
t
t
5
2
3
4
Figure 2b. Power-Up and Power-Down Using PB (Sequenced Power-Up, Figure 8)
t
t
KILL
PB_ON
PB
ON
(TIED TO EN1)
t
KILLH
KILL
BUCK1-BUCK8
IRQ
DON’T CARE
SEQUENCE UP
HARD RESET
3375 F02c
t
1
t
t
t t
4 5
2
3
Figure 2c. Power-Up Using PB and Power-Down Using KILL
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t
PB_ON
<10 SEC
PB
ON
(TIED TO EN1)
t
HR
KILL
BUCK1-BUCK8
IRQ
SEQUENCE
DOWN
SEQUENCE UP
t
PB_LO
t
KILLLO
HARD RESET
t
t
t
t
t
t
t t
7
t
9
1
2
3
4
5
6
8
3375 F02d
Figure 2d. Power-Up Using PB and Power-Down Using a “Soft” Reset
of either an upstream high voltage buck regulator, or any
EN pin causing its associated buck switching regulator
to power-up, which can sequentially power-up the other
buck regulators. The RST pin gets pulled HIGH 230ms
after the last enabled buck is in its PGOOD state. An
applicationshowingsequentialregulatorstart-upisshown
in the Typical Applications section (Figure 8).
brings KILL LOW. 50ms later at time t ON goes LOW. In
8
this case, a hard reset is issued until 1 second after KILL
returns high at t .
9
None of the pushbutton based IRQ signals are reported
2
in an I C register. As such, any IRQ signals that are not
2
revealed by polling the I C read back may be interpreted
as caused by the pushbutton.
In Figure 2b, PB is held LOW at instant t for 10 seconds.
4
2
Power-Up and Power-Down Via Enable Pin or I C
This causes ON to return to a LOW state, which can se-
quenceapower-downbyeithershuttingdownanupstream
high voltage buck, or by shutting down one of the internal
buck switching regulators.
All regulators can be enabled either via its enable pin or
2
I C. IftheuseofthepushbuttoninterfaceisnotdesiredPB
and KILL should be tied to V , and the user may simply
CC
enable any of the buck switching regulators by asserting
In Figure 2c, KILL is pulled LOW while the pushbutton is in
a HIGH signal on any of the EN pins or by writing a buck
the “on” state. This causes a hard reset to be generated at
2
2
switching regulator EN command to the I C. If no I C en-
able has been written, the buck switching regulator may
be powered down by simply returning its EN pin to a LOW
t , all regulators are powered down 50ms later at time t .
4
5
2
An I C signaled reset will have the same effect as pulling
KILL low momentarily.
2
state. If it is wished to power-down the converters via I C,
In Figure 2d, PB is held LOW at instant t for a time
4
an IGNORE_EN command may be written causing the
LTC3375 to treat the state of the EN pin as LOW regard-
less of its input. Then, the buck switching converters can
greater than 50ms but less than 10 seconds. This causes
a transient IRQ signal. This unlatched interrupt can be
used to signal a user pushbutton request. In this case a
software reset may be initiated if so desired. In Figure 2d,
the microprocessor initiates the power-down sequenc-
2
be powered down via I C regardless of their associated
EN pin. Alternatively a RESET_ALL command may be
written that will force all the buck switching regulators to
power-down and remain powered down for a minimum
of one second before they are allowed to be re-enabled.
ing after the user pushbutton signal at time t . At time
6
t , once all the converters are powered down, the micro
7
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DATA BYTE A
DATA BYTE B
ADDRESS
WR
0
0
1
1
0
1
0
0
0
A7
1
A6
2
A5
3
A4
A3
A2
6
A1
7
A0
8
B7
1
B6
2
B5
3
B4
B3
B2
6
B1
7
B0
8
START
STOP
SDA
SCL
0
1
1
0
1
0
0
8
ACK
9
ACK
9
ACK
9
1
2
3
4
5
6
7
4
5
4
5
SDA
t
t
t
BUF
SU, DAT
SU, STA
t
t
t
t
LOW
HD, STA
SU, STO
HD, DAT
3375 F03
SCL
t
t
t
SP
HD, STA
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
Figure 3. I2C Bus Operation
2
commands the LTC3375 to act upon its new command
set. A STOP condition is sent by the master by transition-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
I C Interface
TheLTC3375maycommunicatewithabusmasterusingthe
standardI C2-wireinterface.Thetimingdiagram(Figure3)
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC3375 is both a slave receiver and
2
2
is then free for communication with another I C device.
2
I C Byte Format
Each byte sent to or received from the LTC3375 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3375
most significant bit (MSB) first.
2
slave transmitter. The I C control signals, SDA and SCL
are scaled internally to the V supply.
CC
2
2
The I C port has an undervoltage lockout on the V pin.
I C Acknowledge
CC
2
When V is below 1.8V, the I C serial port is cleared and
theLTC3375registersaresettotheirdefaultconfigurations.
CC
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3375 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC3375 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC3375.
2
I C Bus Speed
2
The I C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure cor-
2
rect operation when addressed from the I C compatible
master device.
An acknowledge (active LOW) generated by the LTC3375
letsthemasterknowthatthelatestbyteofinformationwas
received.Theacknowledgerelatedclockpulseisgenerated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3375 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.
2
I C Start and Stop Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3375,themastermaytransmitaSTOPconditionwhich
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Table 1. Summary of I2C Sub-Addresses and Byte Formats. Bits A7, A6, A5, A4 of Sub-Address Need to be 0 to Access Registers
SUB-ADDRESS
A7A6A5A4A3A2A1A0 OPERATION
DEFAULT
ACTION
BYTE FORMAT D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0 COMMENTS
0000 0000 (00h)
0000 0001 (01h)
0000 0010 (02h)
0000 0011 (03h)
0000 0100 (04h)
0000 0101 (05h)
0000 0110 (06h)
0000 0111 (07h)
0000 1000 (08h)
0000 1001 (09h)
Read/Write Global Logic RESET_ALL, DT[1], DT[0], IGNORE_EN, 0000 0000
1KPD, SLOW, RD_TEMP, Unused
Bits either act at top level or on all
buck switching regulators at once
Read/Write Buck1 Register ENABLE, MODE, PHASE[1], PHASE[0], 0000 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck2 Register ENABLE, MODE, PHASE[1], PHASE[0], 0000 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck3 Register ENABLE, MODE, PHASE[1], PHASE[0], 0001 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck4 Register ENABLE, MODE, PHASE[1], PHASE[0], 0001 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck5 Register ENABLE, MODE, PHASE[1], PHASE[0], 0010 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck6 Register ENABLE, MODE, PHASE[1], PHASE[0], 0010 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck7 Register ENABLE, MODE, PHASE[1], PHASE[0], 0011 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write Buck8 Register ENABLE, MODE, PHASE[1], PHASE[0], 0011 1100
DAC[3], DAC[2]. DAC[1], DAC[0]
Read/Write
RST Mask
PGOOD[8], PGOOD[7], PGOOD[6],
PGOOD[5], PGOOD[4], PGOOD[3],
PGOOD[2], PGOOD[1]
1111 1111
Fault will pull RST low if the
corresponding bit is ‘1’
0000 1010 (0Ah)
Read/Write
IRQ PGOOD PGOOD[8], PGOOD[7], PGOOD[6],
0000 0000
Fault will pull IRQ low if the
corresponding bit is ‘1’
Mask
PGOOD[5], PGOOD[4], PGOOD[3],
PGOOD[2], PGOOD[1]
0000 1011 (0Bh)
0000 1100 (0Ch)
Read/Write
Read
IRQ UVLO
UVLO[8], UVLO[7], UVLO[6], UVLO[5], 0000 0000
UVLO[4], UVLO[3], UVLO[2], UVLO[1]
Fault will pull IRQ low if the
Mask
corresponding bit is ‘1’
PGOOD Status PGOOD[8], PGOOD[7], PGOOD[6],
Read back of PGOOD based
faults. If the corresponding mask
bit is ‘0’, then bit can be used to
read back real time data
Register
PGOOD[5], PGOOD[4], PGOOD[3],
(Latched at PGOOD[2], PGOOD[1]
IRQ fault)
0000 1101 (0Dh)
0000 1110 (0Eh)
0000 1111 (0Fh)
Read
Read
Write
UVLO Status UVLO[8], UVLO[7], UVLO[6], UVLO[5],
Read back of UVLO based faults.
If the corresponding mask bit is
‘0’, then bit can be used to read
back real time data
Register
(Latched at
IRQ fault)
UVLO[4], UVLO[3], UVLO[2], UVLO[1]
Temp Monitor DT_WARN, TEMP[6], TEMP[5],
TEMP[4], TEMP[3], TEMP[2], TEMP[1],
TEMP[0]
TEMP bits read back the TEMP
digital code. DT_WARN bit
latches high if an IRQ fault has
been caused due to a DT Warning
Clear Interrupt
NA
Clears the Interrupt Bit, Status
Latches are Unlatched
2
When the LTC3375 is read from, it releases the SDA line
so that the master may acknowledge receipt of the data.
Since the LTC3375 only transmits one byte of data during
a read cycle, a master not acknowledging the data sent
I C Slave Address
The LTC3375 responds to a 7-bit address which has been
factory programmed to b’0110100[R/WB]’. The LSB of
the address byte, known as the read/write bit, should
be 0 when writing to the LTC3375 and 1 when reading
data from it. Considering the address as an 8-bit word,
2
by the LTC3375 has no I C specific consequence on the
2
operation of the I C port.
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the write address is 68h and the read address is 69h. The
LTC3375willacknowledgebothitsreadandwriteaddress.
signal is issued is the data transferred to the command
latch and acted on.
2
2
I C Sub-Addressed Writing
I C Bus Read Operation
The LTC3375 has 13 command registers for control input.
The LTC3375 has 13 command registers and three status
registers.Thecontentsofanyoftheseregisters,exceptfor
2
They are accessed by the I C port via a sub-addressed
2
writing system.
theClearInterrupt(0Fh)register, maybereadbackviaI C.
AsinglewritecycleoftheLTC3375consistsofexactlythree
bytes except when a clear interrupt command is written.
The first byte is always the LTC3375’s write address. The
second byte represents the LTC3375’s sub-address. The
sub-address is a pointer which directs the subsequent
data byte within the LTC3375. The third byte consists of
the data to be written to the location pointed to by the
sub-address. The LTC3375 contains 12 control registers
which can be written to.
To read the data of a register, that register’s sub-address
must be provided to the LTC3375. The bus master reads
thestatusoftheLTC3375withaSTARTconditionfollowed
by the LTC3375 write address followed by the first data
byte (the sub-address of the register whose data needs
to be read) which is acknowledged by the LTC3375. After
receiving the acknowledge signal from the LTC3375 the
bus master initiates a new START condition followed by
the LTC3375 read address. The LTC3375 acknowledges
the read address and then returns a byte of read back
data from the selected register. A STOP command is not
required for the bus read operation.
2
I C Bus Write Operation
The master initiates communication with the LTC3375
with a START condition and the LTC3375’s write address.
If the address matches that of the LTC3375, the LTC3375
returns an acknowledge. The master should then deliver
the sub-address. Again the LTC3375 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return
of its acknowledge by the LTC3375. This procedure must
be repeated for each sub-address that requires new data.
After one or more cycles of [ADDRESS][SUB-ADDRESS]
[DATA], the master may terminate the communication
with a STOP condition. Multiple sub-addresses may
be written to with a single address command using a
[ADDRESS][SUB-ADDRESS][DATA][SUB-ADDRESS]
[DATA] sequence. Alternatively, a REPEAT-START condi-
tion can be initiated by the master and another chip on
Immediately after writing data to a register, the contents
of that register may be read back if the bus master issues
a START condition followed by the LTC3375 read address.
Error Condition Reporting Via RST and IRQ Pins
Error conditions are reported back via the IRQ and RST
pins. After an error condition is detected, status data can
2
be read back to a microprocessor via I C to determine the
exact nature of the error condition.
Figure 4 is a simplified schematic showing the signal path
for reporting errors via the RST and IRQ pins.
All buck switching regulators have an internal power good
(PGOOD) signal. When the regulated output voltage of an
enabled switcher rises above 93.5% of its programmed
value, the PGOOD signal will transition high. When the
regulated output voltage falls below 92.5% of its pro-
grammed value, the PGOOD signal is pulled low. If any
internal PGOOD signal is not masked and stays low for
greater than 50µs, then the RST and IRQ pins are pulled
low, indicating to a microprocessor that an error condition
has occurred. The 50µs filter time prevents the pins from
being pulled low due to a transient.
2
the I C bus can be addressed. This cycle can continue
indefinitely and the LTC3375 will remember the last input
valid data that it received. Once all chips on the bus have
been addressed and sent valid data, a global STOP can
be sent and the LTC3375 will update its command latches
with the data that it had received.
It is important to understand that until a STOP signal is
transmitted, data written to the LTC3375 command reg-
isters is not acted on by the LTC3375. Only once a STOP
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RST MASK REGISTER
V
CC
EXTERNAL PULL-UP RESISTOR
RST
OTHER UNMASKED
PGOOD OUTPUTS
V
OUT
AND1
REGULATOR
UNMASKED
V
CC
PGOOD OUTPUTS
PGOOD
COMPARATOR
EXTERNAL PULL-UP RESISTOR
–
+
UNMASKED
ERROR
IRQ
AND2
92.5% OF PROGRAMMED V
OUT
SET
CLR
OTHER UNMASKED
ERRORS
CLRINT
IRQ STATUS REGISTER
IRQ MASK REGISTER
3375 F04
Figure 4. Simplified Schematic RST and IRQ Signal Path
BymaskingaPGOODsignal,theRSTorIRQpinwillremain
Hi-Z even though the output voltage of a regulator may be
below its PGOOD threshold. By masking a UVLO signal,
the IRQ pin will remain Hi-Z even though its associated
input voltage may be below its UVLO threshold. However,
when the status registers are read back, the true condi-
tions of PGOOD and UVLO are reported. If a UVLO IRQ is
masked but the associated PGOOD signal is unmasked,
then the IRQ pin may still be pulled low due to a PGOOD
LOW signal that resulted from an input UVLO.
AnerrorconditionthatpullstheRSTpinlowisnotlatched.
Whentheerrorconditiongoesaway,theRSTpinisreleased
and is pulled high if no other error condition exists.
In addition to the PGOOD signals of the regulators the
IRQ pin also indicates the status of the pushbutton, die
temperature, and undervoltage flags. Pushbutton faults
cannot be masked. A fault that causes the IRQ pin to be
pulled low is latched with the exception of a pushbutton
pressthatislessthan10seconds(C =0.01µF)whileONis
T
HIGH. In the case of a transient pushbutton press IRQ will
be held LOW for the duration of the button press latching
after the 10 second power-down time has elapsed. In all
other cases when the fault condition is cleared, the IRQ
pin is still maintained in its low state. The user needs to
clear the interrupt by using a CLRINT command.
Temperature Monitoring and
Overtemperature Protection
To prevent thermal damage to the LTC3375 and its sur-
rounding components, the LTC3375 incorporates an
overtemperature (OT) function. When the LTC3375 die
temperature reaches 165°C (typical) all enabled buck
switching regulators are shut down and remain in shut-
down until the die temperature falls to 155°C (typical).
The LTC3375 also has a die temperature warning function
which warns a user that the die temperature has reached
its programmed alarm threshold which allows the user to
take any corrective action. The die temperature warning
threshold is user programmable as shown in Table 2.
On start-up, all PGOOD status outputs are unmasked with
respecttoRST. WhileallPGOODandUVLOstatusoutputs
are masked with respect to IRQ. A power-on reset will
cause RST to be pulled low. Once all enabled regulators
have their output PGOOD for 230ms typical (C = 0.01µF)
T
the RST output goes Hi-Z.
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LTC3375
operaTion
Table 2. Die Temperature Warning Thresholds
RESET_ALL Functionality
DT[1], DT[0]
DIE TEMPERATURE WARNING THRESHOLD
The RESET_ALL bit shuts down all enabled regulators
2
00 (Default)
Inactive
140°C
125°C
110°C
(enabled either via its enable pin or I C) for one second.
2
01
10
11
The RESET_ALL bit is self clearing, and all other I C bits
(besides the enable bits, which are set low) will remain in
their previous states. The RESET_ALL bit will also reset
the pushbutton to the powered-down state.
Adietemperaturewarningisreportedtotheuserbypulling
the IRQ pin low. This warning can be read back on the LSB
oftheTemp_Monitorregister.Thedietemperaturewarning
flag is disabled when the DT bits are set to 00 (default).
Programming the Operating Frequency
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output voltage ripple.
The temperature may be read back by the user either
digitally through the I C Temp_Monitor Register or by
sampling the TEMP pin analog voltage. The temperature,
T, indicated by the TEMP pin voltage is given by:
2
VTEMP + 19mV
(1)
T =
•1°C
6.75mV
The operating frequency for all of the LTC3375 regulators
is determined by an external resistor that is connected
between the RT pin and ground. The operating frequency
can be calculated by using the following equation:
The analog voltage can be digitally polled using an internal
A/D converter. In order to digitally read the temperature
voltage the user should first issue a RD_TEMP I C com-
mand to tell the A/D converter to poll the TEMP voltage.
At least 2ms after this command has been written the user
may then poll the TEMP bits in the Temp_Monitor register.
The TEMP bits are related to the TEMP voltage as follows:
2
8 •1011 • ΩHz
fOSC
=
(4)
RT
While the LTC3375 is designed to function with operat-
ing frequencies between 1MHz and 3MHz, it has safety
clamps that will prevent the oscillator from running faster
than4MHz(typical)orslowerthan250kHz(typical). Tying
V
TEMP
= 1.3V • (0.08333 + 0.007161 • D)
(2)
where D corresponds to the bit weight of the digital code.
Combining Equation 1 and Equation 2 yields:
the RT pin to V sets the oscillator to the default internal
CC
operating frequency of 2MHz (typical).
T = 18.86°C + 1.379°C • D
(3)
The LTC3375’s internal oscillator can be synchronized,
through an internal PLL circuit, to an external frequency
by applying a square wave clock signal to the SYNC pin.
During synchronization, the top MOSFET turn-on of any
buckswitchingregulatorsoperatingat0°phasearelocked
to the rising edge of the external frequency source. All
other buck switching regulators are locked to the appro-
priate phase of the external frequency source (see Buck
Switching Regulators). The synchronization frequency
range is 1MHz to 3MHz.
If die temperature warning and temperature read back
functionality are not desired, then the user may shut
down the temperature monitor in order to lower quies-
cent current (15µA typical) by tying TEMP to V . In this
CC
case all enabled buck switching regulators are still shut
down when the die temperature reaches 165°C (typical)
and remain in shutdown until the die temperature falls to
155°C (typical). If none of the buck switching regulators
are enabled, then the temperature monitor is also shut
down to further reduce quiescent current.
3375fa
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LTC3375
operaTion
After detecting an external clock on the first rising edge of
the SYNC pin, the PLL starts up at the current frequency
being programmed by the RT pin. The internal PLL then
requires a certain number of periods to gradually settle
until the frequency at SW matches the frequency and
phase of SYNC.
If the use of the V regulator is not desired, then V
CC
CC
should be tied to an external DC voltage source and a
decoupling capacitor. FBV and V
should be tied
CC
SHNT
to ground.
Watchdog Timer
Thewatchdogcircuitmonitorsamicroprocessor’sactivity.
The microprocessor is required to change the logic state
of the WDI pin at least once every 1.5 seconds (typical)
in order to clear the watchdog timer and prevent the WDO
pin from signaling a timeout.
When the external clock is removed the LTC3375 needs
approximately 5µs to detect the absence of the external
clock. During this time, the PLL will continue to provide
clock cycles before it recognizes the lack of a SYNC input.
Once the external clock removal has been identified, the
oscillator will gradually adjust its operating frequency to
match the desired frequency programmed at the RT pin.
The watchdog timer begins running immediately after a
power-on reset. The watchdog timer will continue to run
until a transition is detected on the WDI input. During
this time WDO will be in a Hi-Z state. Once the watchdog
timer times out, WDO will be pulled low and the reset
timer is started. WDO being pulled low may be used to
force a reset on the controlling microprocessor. If no WDI
transition is received when the reset timer times out, after
200ms (typical), WDO will again become Hi-Z and the 1.5
secondswatchdogresettimewillbeginagain.Ifatransition
is received on the WDI input during the watchdog timeout
period, then WDO will become Hi-Z immediately after the
WDI transition and the 1.5 seconds watchdog reset time
will begin at that point.
V
CC
Shunt Regulator
TheLTC3375hasthecontrolcircuitrytoregulatetheoutput
of an N-type device. The circuit should be connected as
showninFigures6aand6b.ThevoltageatFBV willservo
CC
to 1.20V and V can be programmed between 2.7V and
CC
5.5V. The N-type device can be used to regulate a lower
voltage at V while being powered from a high voltage
CC
supply. The N-type device must be chosen so that it can
handlethepowerdissipatedinregulatingV .Theinternal
CC
circuitry of the LTC3375 can only pull-down on the V
SHNT
node. A pull-up resistor is required for positive gate drive.
If V is incorrectly programmed or a current load at V
CC
causes V
CC
will
to go above 6.1V (typical), then V
SHNT
SHNT
be internally clamped and V may lose regulation.
CC
3375fa
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LTC3375
applicaTions inForMaTion
Buck Switching Regulator Output Voltage and
Feedback Network
The input supply needs to be decoupled with a 10µF
capacitor while the output needs to be decoupled with a
22µF capacitor. Refer to Capacitor Selection for details on
selecting a proper capacitor.
The output voltage of the buck switching regulators is
programmed by a resistor divider connected from the
switching regulator’s output to its feedback pin and is
2
EachbuckregulatorcanbeprogrammedviaI C.Toprogram
given by V
= V (1 + R2/R1) as shown in Figure 5.
buck regulator 1 use sub-address 01h, buck regulator 2
sub-address02h, buckregulator3sub-address03h, buck
regulator4subaddress04h,buckregulator5sub-address
05h, buck regulator 6 sub-address 06h, buck regulator 7
sub-address 07h, and buck regulator 8 sub-address 08h.
The bit format is explained in Table 7.
OUT
FB
Typical values for R1 range from 40k to 1M. The buck
regulator transient response may improve with optional
capacitor C that helps cancel the pole created by the
FF
feedback resistors and the input capacitance of the FB
pin. Experimentation with capacitor values between 2pF
and 22pF may improve transient response.
Combined Buck Regulators
A single 2A buck regulator is available by combining two
adjacent 1A buck regulators together. Likewise a 3A or 4A
buck regulator is available by combining any three or four
adjacent buck regulators respectively. Tables 4, 5, and 6
show recommended inductors for these configurations.
V
OUT
+
C
C
R2
FF
OUT
BUCK
SWITCHING
REGULATOR
FB
(OPTIONAL)
R1
Theinputsupplyneedstobedecoupledwitha22µFcapaci-
tor while the output needs to be decoupled with a 47µF
capacitor for a 2A combined buck regulator. Likewise for
3Aand4Aconfigurationstheinputandoutputcapacitance
must be scaled up to account for the increased load. Refer
toCapacitorSelectionintheApplicationsInformationsec-
tion for details on selecting a proper capacitor.
3375 F05
Figure 5. Feedback Components
Buck Regulators
All eight buck regulators are designed to be used with
inductors ranging from 1µH to 3.3µH depending on the
lowest switching frequency that the buck regulator must
operate at. To operate at 1MHz a 3.3µH inductor should
be used, while to operate at 3MHz a 1µH inductor may be
used. Table 3 shows some recommended inductors for
the buck regulators.
In many cases, any extra unused buck converters may be
used to increase the efficiency of the active regulators.
In general the efficiency will improve for any regulators
running close to their rated load currents. If there are
unused regulators, the user should look at their specific
applications and current requirements to decide whether
to add extra stages.
Table 3. Recommended Inductors for 1A Buck Regulators
PART NUMBER
L (µH)
1.0
1
MAX I (A)
MAX DCR (MΩ)
MANUFACTURER
Vishay
SIZE IN mm (L × W × H)
3 × 3.6 × 1.2
DC
IHLP1212ABER1R0M-11
1239AS-H-1R0N
3
38
65
2.5
3.5
2.6
3
Toko
2.5 × 2.0 × 1.2
4 × 4 × 2.1
XFL4020-222ME
2.2
2.2
2.2
3.3
3.3
23.5
84
CoilCraft
Toko
1277AS-H-2R2N
3.2 × 2.5 × 1.2
3 × 3.6 × 1.2
IHLP1212BZER2R2M-11
XFL4020-332ME
46
Vishay
2.8
2.7
38.3
61
CoilCraft
Vishay
4 × 4 × 2.1
IHLP1212BZER3R3M-11
3 × 3.6 × 1.2
3375fa
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For more information www.linear.com/3375
LTC3375
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Table 4. Recommended Inductors for 2A Buck Regulators
PART NUMBER
L (µH)
1.0
1
MAX I (A)
MAX DCR (mΩ)
MANUFACTURER
CoilCraft
SIZE IN mm (L × W × H)
4 × 4 × 2.1
DC
XFL4020-102ME
74437324010
5.1
9
11.9
27
Wurth Elektronik
CoilCraft
4.45 × 4.06 × 1.8
4 × 4 × 2.1
XAL4020-222ME
FDV0530-2R2M
IHLP2020BZER2R2M-11
XAL4030-332ME
FDV0530-3R3M
2.2
2.2
2.2
3.3
3.3
5.6
5.3
5
38.7
15.5
37.7
28.6
34.1
Toko
6.2 × 5.8 × 3
Vishay
5.49 × 5.18 × 2
4 × 4 × 3.1
5.5
4.1
CoilCraft
Toko
6.2 × 5.8 × 3
Table 5. Recommended Inductors for 3A Buck Regulators
PART NUMBER
L (µH)
1.0
1
MAX I (A)
MAX DCR (mΩ)
MANUFACTURER
CoilCraft
Toko
SIZE IN mm (L × W × H)
4 × 4 × 2.1
DC
XAL4020-102ME
FDV0530-1R0M
XAL5030-222ME
IHLP2525CZER2R2M-01
74437346022
8.7
8.4
9.2
8
14.6
11.2
14.5
20
6.2 × 5.8 × 3
2.2
2.2
2.2
3.3
3
CoilCraft
Vishay
5.28 × 5.48 × 3.1
6.86 × 6.47 × 3
7.3 × 6.6 × 2.8
5.28 × 5.48 × 3.1
7.1 × 6.5 × 3
6.5
8.7
7.3
20
Wurth Elektonik
CoilCraft
TDK
XAL5030-332ME
SPM6530T-3R3M
23.3
27
Table 6. Recommended Inductors for 4A Buck Regulators
PART NUMBER
L (µH)
1.2
1
MAX I (A)
MAX DCR (mΩ)
MANUFACTURER
CoilCraft
TDK
SIZE IN mm (L × W × H)
5.28 × 5.48 × 3.1
7.1 × 6.5 × 3
DC
XAL5030-122ME
SPM6530T-1R0M120
XAL5030-222ME
SPM6530T-2R2M
IHLP2525EZER2R2M-01
XAL6030-332ME
FDVE1040-3R3M
12.5
14.1
9.2
8.4
13.6
8
9.4
7.81
14.5
19
2.2
2.2
2.2
3.3
3.3
CoilCraft
TDK
5.28 × 5.48 × 3.1
7.1 × 6.5 × 3
20.9
20.81
10.1
Vishay
6.86 × 6.47 × 5
6.36 × 6.56 × 3.1
11.2 × 10 × 4
CoilCraft
Toko
9.8
Table 7. Global Buck Regulator Program Register Bit Format
Bit7
ENABLE
Default is ‘0’ which disables the part. A buck regulator can also be enabled via its enable pin. When enabled via
2
pin, the contents of the I C register program its functionality.
Bit6
MODE
Default is ‘0’ which is Burst Mode operation. A ‘1’ programs the regulator to operate in forced continuous mode.
Bit5(PHASE1)
Bit4(PHASE0)
Phase Control
Default varies per converter. ‘00’ programs a SW HIGH transition to coincide with the internal clock rising edge.
‘01’ programs a 90° offset, ’10’ programs a 180° offset, and ‘11’ programs a 270° offset.
Bit3(DAC3)
Bit2(DAC2)
Bit1(DAC1)
Bit0(DAC0)
DAC Control
These bits are used to program the feedback regulation voltage. Default is ‘1100’ which programs a voltage of
725mV. Bits ‘0000’ program the lowest feedback regulation of 425mV, and ‘1111’ programs a full-scale voltage of
800mV. An LSB (DAC0) has a bit weight of 25mV.
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LTC3375
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V
Shunt Regulator
For an NPN device the pullup resistor between V
and
SHNT
CC
the supply voltage should be sized such that:
If load steps seen on V are of great concern, then the
CC
compensationcapacitorshouldbetiedfromV toground
CC
VSUPPLY(MINIMUM) − (V + V )
BE
CC
RPULLUP
Where V
<
•β
as shown in Figure 6a. If load steps are not of a concern,
IVCC(MAX)
butinsteadsmallercompensationcomponentsaredesired
is the lowest possible collector
thenthecompensationcapacitorshouldbetiedfromV
SUPPLY(MINIMUM)
SHNT
voltage, V and β are specific to the NPN in the applica-
to ground as shown in Figure 6b.
BE
tion, and I
is the maximum desired load current
VCC(MAX)
from V .
CC
301k
Likewise R
may be sized such to current limit I
VCC
PULLUP
from an NPN device to prevent damage to the circuit
V
V
SHNT
CC
from a short on the V pin, and to prevent the NPN from
exceeding its safe operating current:
1Ω
1.02M
576k
CC
+
–
FBV
CC
22µF
1.2V
VSUPPLY(MAXIMUM) − (V + V )
BE
CC
RPULLUP
>
•β
V
CC
REGULATOR
IVCC(LIMIT)
3375 F06a
Where V = 0V in the case of a grounded output.
CC
Figure 6a. VCC Regulator Compensated from the VCC Pin
Alternatively, the current may be limited by adding a re-
sistor between V and the emitter of the NPN such that:
CC
301k
6.1V − (V + V )
BE
CC
RLIM
=
IVCC(LIMIT)
V
CC
V
SHNT
1.02M
576k
In this case when I
collapse. The NPN should be sized to be able to survive
at least:
exceeds I
V
will start to
VCC
VCC(LIMIT) CC
2.2µF
+
–
FBV
CC
1.2V
6.1V − V
V
REGULATOR
BE
CC
IVCC(MAX)
=
3375 F06b
RLIM
Figure 6b. VCC Regulator Compensated from the VSHNT Pin
for the given supply voltage, where 6.1V is the maximum
V
voltage (typical).
SHNT
The exact components used in the V shunt regulator are
CC
The user should verify that the circuit is stable over the
specific conditions of the desired application. In general
increasingthevalueofthecompensationcapacitorusedor
dependent on the specific conditions used in the applica-
tion. Care should be taken to make sure that the power
dissipation limits of the specific N-type device used are
not exceeded, because damage to the external device can
lead to damage to the LTC3375.
increasing R
can improve stability. The user should
PULLUP
keep in mind that increasing R
also decreases
SUPPLY VCC(MAX)
PULLUP
I
. In general the highest V
at I
VCC(MAX)
yields the worst stability for the circuit in Figure 6a, while
the highest V at no load on V yields the worst
SUPPLY
CC
stability for the circuit in Figure 6b.
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LTC3375
applicaTions inForMaTion
In general the circuit in 6a is recommended if the appli-
Programming the Global Register
cation needs to drive any external circuitry with V or if
CC
The Global Register contains functions that either act on
the LTC3375 top level or act on all buck switching regula-
tors at once. These functions are described in Table 8. The
default structure is ‘0000 0000b’.
the larger compensation capacitor is tolerable. If V is
CC
only needed to drive the LTC3375 and smaller component
sizes are critical, then the circuit in Figure 6b may be used.
Input and Output Decoupling Capacitor Selection
Programming the RST and IRQ Mask Registers
TheLTC3375hasindividualinputsupplypinsforeachbuck
switching regulator. Each of these pins must be decoupled
withlowESRcapacitorstoGND.Thesecapacitorsmustbe
placed as close to the pins as possible. Ceramic dielectric
capacitorsareagoodcompromisebetweenhighdielectric
constant and stability versus temperature and DC bias.
Note that the capacitance of a capacitor deteriorates at
higher DC bias. It is important to consult manufacturer
data sheets and obtain the true capacitance of a capacitor
at the DC bias voltage it will be operated at. For this rea-
son, avoid the use of Y5V dielectric capacitors. The X5R/
X7R dielectric capacitors offer good overall performance.
The RST mask register can be programmed by the user
at sub-address 09h and its format is shown in Table 9.
If a bit is set to ‘1’, then the corresponding regulator’s
PGOOD will pull RST low if a PGOOD fault were to occur.
The default for this register is FFh.
The IRQ mask registers have the same bit format as the
RST mask register. The IRQ mask registers are located at
sub-addresses 0Ah and 0Bh and their default contents
are 00h.
Status Byte Read Back
The input supply voltage Pins 2, 5, 8, 11, 26, 29, 32 and
35 all need to be decoupled with at least 10µF capacitors.
When either the RST or IRQ pin is pulled low, it indicates
to the user that a fault condition has occurred. To find out
the exact nature of the fault, the user can read the status
registers. There are three registers that contain status
information. The register at sub-address 0Ch provides
PGOOD fault condition reporting, while the register at
sub-address0DhprovidesUVLOfaultconditionreporting.
These bits are all latched at interrupt. If any of the bits
are disabled via masking, then their real time, unlatched
status information is still available. Bit7 of the register
at sub-address 0Eh provides latched information on the
status of the DT Warning. Figure 4 shows the operation
of the status registers. The contents of the IRQ status
register are cleared when a CLRINT signal is issued. A
PGOOD bit is a ‘0’ if the regulator’s output voltage is more
than 7.5% below its programmed value. A UVLO bit is a
Choosing the C Capacitor
T
The C capacitor may be used to program the timing
T
parameters associated with the pushbutton. For a given
C capacitor the timing parameters may be calculated as
T
below. C is in units of µF.
T
t
t
t
t
t
t
t
t
= 5000 • C ms
T
PB_LO
PB_ON
PB_OFF
= 20000 • C ms
T
= 1000 • C seconds
T
= 100 • C seconds
HR
T
= 5000 • C ms
IRQ_PW
T
= 1000 • C seconds
KILLH
KILLL
T
‘0’ if the associated V is above its input UVLO threshold.
IN
The format for the status registers is shown in Table 10.
= 5000 • C ms
T
A write operation cannot be performed to any of these
status registers.
= 23000 • C ms
RST
T
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Table 8. Global Control Program Register Bit Format
Bit7
RESET_ALL
Default is ‘0’. When asserted all buck converters will power down for 1 second after which the bit will clear itself.
Bit6(DT1)
Bit5(DT0)
DT WARNING
CONTROL
Default is ‘00’ which deactivates the DT warning. ‘01’ programs –140°, ‘10’ programs –125°,
and ‘11’ programs –110°.
Bit4
Bit3
Bit2
Bit1
Bit0
IGNORE_EN
Default is ‘0’ which allows the EN pins to power on the buck converters. When written to ‘1’ the enable pins will be
2
ignored. This allows power-down sequencing via I C even if the EN pins are tied to a logic HIGH voltage source.
1KPD
Default is ‘0’ in which the SW node remains in a high impedance state when the regulator is in shutdown. A ‘0’ pulls
the SW node to GND through a 10k resistor. This bit acts on all buck converters at once.
SLOW EDGE
RD_TEMP
Unused
This bit controls the slew rate of the switch node. Default is ‘0’ which enables the switch node to slew at a faster
rate, than if the bit were programmed a ‘1’. This bit acts on all buck converters at once.
Default is ‘0’. This bit commands the temperature A/D to sample the voltage present at the TEMP pin. After a read is
complete this bit will clear itself.
This bit is unused and must be written to “0”
Table 9
BIT7
PGOOD[8]
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
PGOOD[7]
PGOOD[6]
PGOOD[5]
PGOOD[4]
PGOOD[3]
PGOOD[2]
PGOOD[1]
Table 10
Sub-
Address
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0Ch
0Dh
0Eh
PGOOD[8] PGOOD[7] PGOOD[6] PGOOD[5] PGOOD[4] PGOOD[3] PGOOD[2]
PGOOD[1]
UVLO[8]
UVLO[7]
UVLO[6]
TEMP[5]
UVLO[5]
TEMP[4]
UVLO[4]
TEMP[3]
UVLO[3]
TEMP[2]
UVLO[2]
TEMP[1]
UVLO[1]
TEMP[0]
DT_WARN TEMP[6]
PCB Considerations
4. The switching power traces connecting SW1, SW2,
SW3, SW4, SW5, SW6, SW7 and SW8 to their respec-
tive inductors should be minimized to reduce radiated
EMI and parasitic coupling. Due to the large voltage
swing of the switching nodes, high input impedance
sensitive nodes, such as the feedback nodes, should
be kept far away or shielded from the switching nodes
or poor performance could result.
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3375:
1. Theexposedpadofthepackage(Pin49)shouldconnect
directlytoalargegroundplanetominimizethermaland
electrical impedance.
2. All the input supply pins should each have a decoupling
capacitor.
5. The GND side of the switching regulator output capaci-
torsshouldconnectdirectlytothethermalgroundplane
of the part. Minimize the trace length from the output
capacitor to the inductor(s)/pin(s).
3. Theconnectionstotheswitchingregulatorinputsupply
pins and their respective decoupling capacitors should
be kept as short as possible. The GND side of these
capacitors should connect directly to the ground plane
of the part. These capacitors provide the AC current
to the internal power MOSFETs and their drivers. It is
importanttominimizeinductancefromthesecapacitors
6. Inacombinedbuckregulatorapplicationthetracelength
of switch nodes to the inductor must be kept equal to
ensure proper operation.
to the V pins of the LTC3375.
IN
3375fa
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For more information www.linear.com/3375
LTC3375
Typical applicaTions
3.3V TO 5.5V
V
V
IN8
2.25V TO 5.5V
IN1
2.2µH
1.02M
287k
2.2µH
2.2µH
2.2µH
2.2µH
10µF
10µF
3.3V
1.8V
1A
SW1
FB1
SW8
FB8
1A
22µF
22µF
22µF
22µF
22µF
649k
432k
3V TO 5.5V
V
IN2
V
IN7
2.25V TO 5.5V
2.25V TO 5.5V
2.25V TO 5.5V
2.2µH
10µF
10µF
10µF
10µF
3V
1.5V
1A
SW2
FB2
SW7
FB7
1A
22µF
1.07M
340k
464k
432k
LTC3375
2.5V TO 5.5V
V
IN3
V
IN6
2.2µH
10µF
2.5V
1.2V
1A
SW3
FB3
SW6
FB6
1A
22µF
1.02M
412k
422k
649k
2.25V TO 5.5V
V
IN4
V
IN5
2.2µH
10µF
2V
1V
1A
SW4
FB4
SW5
FB5
1A
22µF
732k
412k
280k
732k
V
CC
1µF
2
I C
SCL
SDA
CONTROL
HIGH VOLTAGE > 4.0V
2.2µF
WDI
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
KILL
SYNC
RT
301k
V
SHNT
V
CC
MICROPROCESSOR
CONTROL
1.02M
576k
FBV
CC
402k
IRQ
RST
WDO
ON
TEMP
C
T
MICROPROCESSOR
CONTROL
0.01µF
PB
PUSH BUTTON
EXPOSED PAD
3375 F07
Figure 7. Detailed Front Page Application Circuit
3375fa
31
For more information www.linear.com/3375
LTC3375
Typical applicaTions
V
IN
5.5V TO 60V
C
IN
22µF
V
INTV
CC
IN
100k
2.2µF
D1
PGOOD
INTV
CC
PGND
TG
PLLIN/MODE
MTOP
I
LIM
0.1µF
LTC3891
L1
R
SENSE
7mΩ
RUN
BOOST
8µH
5V
6A
SW
FREQ
C
470pF
MBOT
OUT
BG
34.8k
330µF
ITH
+
SENSE
0.1µF
1nF
–
SENSE
EXTV
V
TRACK/SS
SGND
100k
CC
FB
MTOP, MBOT: Si7850DP
SGND
19.1k
L1 COILCRAFT SER1360-802KL
C
: SANYO 10TPE330M
OUT
D1: DFLS1100
V
IN1
V
IN8
10µF
10µF
10µF
10µF
10µF
2.2µH
422k
649k
2.2µH
2.2µH
2.2µH
1.2V
1A
1.2V
1A
SW1
FB1
SW8
FB8
22µF
22µF
22µF
22µF
22µF
422k
649k
V
IN2
V
IN7
10µF
10µF
10µF
2.2µH
2.5V
1A
2.5V
1A
SW2
FB2
SW7
FB7
22µF
22µF
22µF
1.02M
412k
1.02M
412k
LTC3375
V
IN3
V
IN6
2.2µH
1.8V
1A
1.8V
1A
SW3
FB3
SW6
FB6
649k
432k
649k
432k
V
IN4
V
IN5
2.2µH
2.2µH
1.6V
1A
1.6V
1A
SW4
FB4
SW5
FB5
511k
422k
511k
422k
HIGH VOLTAGE
5.5V TO 60V
V
CC
1µF
47k
2
FZT6928
215Ω
V
SHNT
I C
SCL
SDA
CONTROL
KILL
SYNC
WDI
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
RT
MICROPROCESSOR
CONTROL
3.3V
5mA
1Ω
V
CC
CC
1.02M
576k
FBV
22µF
402k
IRQ
RST
WDO
TEMP
ON
C
T
MICROPROCESSOR
CONTROL
0.01µF
PB
PUSH BUTTON
EXPOSED PAD
3375 F08
Figure 8. Buck Regulators with Sequenced Start-Up Driven from a High Voltage Upstream Buck Converter
3375fa
32
For more information www.linear.com/3375
LTC3375
Typical applicaTions
2.7V TO 5.5V
V
IN1
V
IN6
10µF
2.5V
10µF
2.2µH
1.02M
SW1
SW2
SW3
SW4
2.2µH
SW8
SW7
SW6
1.2V
3A
4A
100µF
68µF
422k
649k
FB1
FB6
412k
V
V
IN7
IN2
10µF
10µF
FB2
FB7
LTC3375
V
IN3
V
IN8
10µF
10µF
10µF
10µF
FB3
FB8
V
IN4
V
IN5
2.2µH
1.6V
1A
SW5
22µF
511k
422k
FB4
FB5
1µF
2
I C
SCL
SDA
CONTROL
WDI
EN1
V
SHNT
MICROPROCESSOR
CONTROL
EN5
EN6
KILL
SYNC
V
CC
10µF
FBV
RT
CC
EN2
EN3
EN4
EN7
EN8
IRQ
RST
WDO
ON
TEMP
C
T
MICROPROCESSOR
CONTROL
0.01µF
PB
PUSH BUTTON
EXPOSED PAD
3375 F09
Figure 9. Combined Buck Regulators with Common Input Supply
3375fa
33
For more information www.linear.com/3375
LTC3375
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-ꢀ704 Rev C)
0.70 0.05
5.ꢀ5 0.05
5.50 REF
6.ꢀ0 0.05 7.50 0.05
(4 SIDES)
5.ꢀ5 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
7.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
47 48
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ
CHAMFER
C = 0.35
5.ꢀ5 0.ꢀ0
5.50 REF
(4-SIDES)
5.ꢀ5 0.ꢀ0
(UK48) QFN 0406 REV C
0.200 REF
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3375fa
34
For more information www.linear.com/3375
LTC3375
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
03/13 Clarified V input supply current specification
4
12
CC
Clarified RST pin functionality
Clarified Buck Regulators with Combined Power Stages
Clarified Table 6 Recommended Inductor Ratings
16, 17
27
3375fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3375
Typical applicaTion
Combined Bucks with 3MHz Switch Frequency, Sequenced Power Up, and KILL Based Hardware Override Shut Down
2.25V TO 5.5V
3.3V TO 5.5V
V
V
IN1
IN8
FB8
10µF
10µF
10µF
V
V
IN2
IN7
10µF
10µF
FB2
V
IN3
1µH
3.3V
2A
SW7
SW8
FB7
FB3
47µF
1.02M
287k
1µH
649k
432k
SW1
SW2
SW3
1.8V
3A
68µF
FB1
2.5V TO 5.5V
V
IN6
FB6
10µF
10µF
V
IN5
LTC3375
2.25V TO 5.5V
V
IN4
10µF
1µH
1µH
422k
2.5V
2A
1.2V
1A
SW5
SW6
SW4
FB4
47µF
22µF
1.02M
412k
FB5
649k
1µF
HIGH VOLTAGE >4.0V
V
CC
301k
V
2
SHNT
SDA
SCL
WDI
EN1
EN4
EN5
EN7
EN2
EN3
EN6
EN8
I C
2.2µF
CONTROL
V
CC
1.02M
FBV
CC
576k
IRQ
RST
WDO
TEMP
SYNC
ON
RT
MICROPROCESSOR
CONTROL
267k
C
T
0.01µF
KILL
PB
EXPOSED PAD
PAPER CLIP HOLE
PUSH BUTTON
PUSH BUTTON
3375 TA02
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3675
7-Channel Configurable High Power PMIC
Four Parallelable Buck DC/DCs (1A, 1A, 500mA, 500mA), 1A Boost, 1A
2
Buck-Boost, 25mA LDO, Dual String LED Driver, Pushbutton, I C Control
2
LTC3589/LTC3589-1 8-Output Regulator with Sequencing and I C
Three Buck DC/DCs, Three 250mA LDOs, 25mA LDO, 1.2A Buck-Boost,
2
Pushbutton, I C Control
3375fa
LT 0313 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX:(408)434-0507 www.linear.com/3375
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