LTC3603EMSE [Linear]
2.5A, 15V Monolithic Synchronous Step-Down Regulator; 2.5A ， 15V单片同步降压型稳压器
| 型号： | LTC3603EMSE |
| 厂家： | 
Linear |
| 描述： | 2.5A, 15V Monolithic Synchronous Step-Down Regulator |
| 文件： | 总22页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3603
2.5A, 15V Monolithic
Synchronous Step-Down
Regulator
FEATURES
DESCRIPTION
TheLTC®3603isahighefficiency,monolithicsynchronous
step-downDC/DCconverterutilizingaconstant-frequency,
currentmodearchitecture.Itoperatesfromaninputvoltage
range of 4.5V to 15V and provides an adjustable regulated
output voltage from 0.6V to 14.5V while delivering up to
2.5A of output current. The internal synchronous power
switch with 45mΩ on-resistance increases efficiency
and eliminates the need for an external Schottky diode.
The switching frequency can either be set by an external
resistororsynchronizedtoanexternalclock. OPTI-LOOP®
compensationallowsthetransientresponsetobeoptimized
over a wide range of loads and output capacitors.
n
Wide Input Voltage Range: 4.5V to 15V
n
2.5A Output Current
n
Low R
Internal Switches: 45mΩ and 85mΩ
DS(ON)
n
n
n
Programmable Frequency: 300kHz to 3MHz
Low Quiescent Current: 75μA
0.6V 1ꢀ Reference Allows Precise,
Low Output Voltage
n
n
n
n
n
n
n
99ꢀ Maximum Duty Cycle
Adjustable Burst Mode® Clamp
Synchronizable to External Clock
Power Good Output Voltage Monitor
Overtemperature Protection
Overvoltage Protection
Available in 16-Lead Thermally Enhanced MSOP
and 4mm × 4mm QFN Packages
The LTC3603 can be configured for either Burst Mode op-
erationorforcedcontinuousoperation.Forcedcontinuous
operation reduces noise and RF interference, while Burst
Mode operation provides the highest efficiency at light
loads.InBurstModeoperation,externalcontroloftheburst
clamp level allows the output voltage ripple to be adjusted
according to the requirements of the application.
APPLICATIONS
n
Point-of-Load Supplies
n
Portable Instruments
n
Communications Infrastructure
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered
trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5481178,
6580258, 6498466, 6611131, 6177787, 5705919, 5847554.
TYPICAL APPLICATION
3.3V, 2.5A, 1MHz Step-Down Regulator
Efficiency and Power Loss vs Load Current
V
IN
100
95
90
85
80
75
70
65
60
10000
1000
100
10
4.5V TO 15V
V
= 12V
IN
EFFICIENCY
22μF
1μF
PV
INTV
CC
IN
RUN
RT
BOOST
LTC3603
0.22μF
2.2μH
V
3.3V
2.5A
OUT
105k
PGOOD
SW
100μF
TRACK/SS
POWER LOSS
4.32k
1nF
PGND
ITH
SYNC/MODE
V
FB
475k
10pF
1
10
0.001
0.01
0.1
1
105k
3603 TA01
LOAD CURRENT (A)
3603 TA01b
3603fa
1
LTC3603
ABSOLUTE MAXIMUM RATINGS (Note 1)
PV Supply Voltage (DC) .......................... –0.3V to 16V
Peak SW Sink and Source Current (Note 7).............6.5A
Operating Junction Temperature Range (Notes 2, 5, 6)
LTC3603E ............................................–40°C to 85°C
LTC3603I........................................... –40°C to 125°C
Lead Temperature (Soldering, 10 seconds)
IN
PV Supply Transient Voltage (<1μs) .......................21V
IN
SW..............................................–0.3V to (PV + 0.3V)
IN
BOOST .................................(V –0.3V) to (V + 6V)
SW
SW
RUN ........................................................... –0.3V to 16V
All Other Pins............................................... –0.3V to 6V
MSE Package....................................................300°C
PIN CONFIGURATION
TOP VIEW
20 19 18 17 16
TOP VIEW
1
2
3
4
5
6
7
8
INTV
16 PV
15 PV
CC
IN
IN
PGND
PV
PV
1
2
3
4
5
15
14
13
12
11
IN
IN
SYNC/MODE
PGOOD
RT
PGND
14 BOOST
13 SW
21
SGND
17
SGND
PGND
INTV
CC
ITH
V
SGND
RUN
12 SW
11 PGND
10 PGND
PGND
SYNC/MODE
FB
TRACK/SS
PGOOD
9
TRACK/SS
MSE PACKAGE
16-LEAD PLASTIC MSOP
6
7
8
9 10
T
= 125°C, θ = 45°C/W, θ = 10°C/W
JA JC
JMAX
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
T = 125°C, θ = 37°C/W, θ = 5°C/W
JMAX
JA
JC
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3603EMSE#PBF
LTC3603IMSE #PBF
LTC3603EUF#PBF
LTC3603IUF#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
16-Lead Plastic MSOP
16-Lead Plastic MSOP
20-Lead (4mm × 4mm) Plastic QFN
20-Lead (4mm × 4mm) Plastic QFN
TEMPERATURE RANGE
LTC3603EMSE#TRPBF
LTC3603IMSE#TRPBF
LTC3603EUF#TRPBF
LTC3603IUF#TRPBF
3603
3603
3603
3603
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3603fa
2
LTC3603
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise specified.
SYMBOL
PV
PARAMETER
CONDITIONS
MIN
4.5
TYP
MAX
15
UNITS
V
Operating Voltage Range
Regulated Feedback Voltage
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Power Good Range
IN
l
l
V
FB
ITH = 0.7V (Note 3)
0.594
0.6
0.005
0.02
10
0.606
V
V
IN
= 5V to 15V, I = 0.7V
ꢀ/V
ꢀ
ΔV
ΔV
ΔV
R
TH
FB(LINEREG)
FB(LOADREG)
PGOOD
ITH = 0.36V to 0.84V
0.1
12
80
ꢀ
Power Good Resistance
FB Input Bias Current
55
Ω
nA
mS
PGOOD
I
FB
10
g
Transconductance Amplifier g
1.7
m
m
I
S
Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
500
75
0.2
700
100
1
μA
μA
μA
INTV
V
LDO Output Voltage
CC
4.7
0.4
4.9
95
5.1
115
1
V
ns
CC
t
Minimum Controllable ON-Time
RUN Pin ON Threshold
TRACK/SS Pull-Up Current
Oscillator Frequency
ON, MIN
l
V
RUN
V
Rising
0.7
1.25
1
V
RUN
I
f
f
TRACK/SS = 1V
R = 105k
μA
TRACK/SS
OSC
0.85
0.3
1.15
3
MHz
MHz
T
SYNC Capture Range
SYNC
R
Top Switch On-Resistance
Bottom Switch On-Resistance
85
45
mΩ
mΩ
DS(ON)
I
I
Peak Current Limit
3.8
4.1
4.5
0.1
4.2
700
5.2
1
A
μA
V
LIM
Switch Leakage Current
LSW
l
V
V
INTV Undervoltage Lockout
INTV Ramping Up
4.3
UVLO
CC
CC
INTV Undervoltage Lockout Hysteresis
mV
UVLO, HYS
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T is calculated from the ambient temperature T and the power
J
A
dissipation as follows: T = T + (P )(θ ºC/W).
J
A
D
JA
Note 2: The LTC3603E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3603I is guaranteed
over the –40°C to 125°C operating junction temperature range.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LTC3603 is tested in a feedback loop that adjusts V to
FB
Note 7: This limit indicates the current density limitations of the internal
metallization and it is not tested in production.
achieve a specified error amplifier output voltage (I ).
TH
3603fa
3
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Transient
Forced Continuous
Burst Mode Operation
OUTPUT
OUTPUT
VOLTAGE
100mV/DIV
VOLTAGE
50mV/DIV
LOAD
CURRENT
1A/DIV
INDUCTOR
CURRENT
500mA/DIV
3603 G02
3603 G01
V
V
= 12V
10μs/DIV
V
V
= 12V
10μs/DIV
IN
OUT
IN
OUT
= 3.3V
= 3.3V
LOAD = 50mA
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
VREF vs Temperature
90
85
80
75
70
65
60
55
50
45
40
120
0.6006
0.6004
0.6002
V
– V = INTV
SW CC
V
= 12V
V
= 12V
BOOST
IN
IN
100
80
TOP
TOP
60
0.6000
0.5998
0.5996
0.5994
BOTTOM
40
20
0
BOTTOM
50
TEMPERATURE (°C)
100 125
4
5
6
7
8
11 12 13 14 15
–50
25
50
75
100 125
–50 –25
0
25
75
9
10
–25
0
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3603 G03
3603 G04
3603 G05
PVIN Leakage Current
vs Input Voltage
Frequency vs ROSC
Frequency vs Input Voltage
50
45
40
35
30
25
20
15
10
5
3500
3000
1040
1030
1020
1010
1000
990
V
= 0V
R
= 105kΩ
RUN
OSC
2500
2000
1500
1000
500
980
970
960
0
0
200
300 350
4
5
6
7
8
9
10 11 12 13 14 15
0
50
100 150
250
4
5
6
7
8
9
10 11 12 13 14 15
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
R
OSC
(kΩ)
3603 G07
3603 G06
3603 G08
3603fa
4
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
vs Input Voltage
Quiescent Current
vs Temperature
Frequency vs Temperature
600
500
400
300
200
100
0
600
500
400
300
200
100
0
1020
1015
1010
1005
R
= 105kΩ
OSC
ACTIVE
ACTIVE
1000
995
990
985
980
SLEEP
SLEEP
50
0
TEMPERATURE (°C)
100 125
–50
25
50
75
100 125
–50 –25
25
75
–25
0
4
5
6
7
8
9
10 11 12 13 14 15
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3603 G09
3603 G11
3603 G10
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Maximum Peak Inductor Current
vs Duty Cycle
Efficiency vs Load Current,
Burst Mode Operation
100
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
FIGURE 6 CIRCUIT
V
= 7.2V
IN
V
= 5V
IN
95
90
85
80
75
70
V
= 15V
IN
V
= 12V
IN
2
1
0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.001
0.01
0.1
1
10
0
10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (A)
BURST CLAMP VOLTAGE (V)
DUTY CYCLE (%)
3603 G13
3603 G14
3603 G12
Efficiency vs Load Current,
Forced Continuous
Efficiency vs Input Voltage
Efficiency vs Frequency
100
95
90
85
80
75
70
100
90
80
70
60
50
40
30
100
98
FIGURE 6 CIRCUIT
FIGURE 6 CIRCUIT
FIGURE 6 CIRCUIT
I
= 2A
LOAD
V
= 5V
I
= 1A
IN
LOAD
V
= 15V
IN
96
V
= 12V
I
= 2.5A
IN
LOAD
94
V
= 7.2V
IN
V
= 7.2V
IN
92
90
V
= 12V
IN
88
86
84
4
5
8
9
10 11 12 13 14 15 16
0
1000
2000
3000
6
7
0.01
0.1
1
10
INPUT VOLTAGE (V)
FREQUENCY (kHz)
LOAD CURRENT (A)
3603 G15
3603 G16
3603 G17
3603fa
5
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
5V LDO Output Voltage
vs Temperature
TRACK/SS Current
vs Temperature
Load Regulation
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
1.40
1.35
1.30
1.25
0.10
0
FIGURE 6 CIRCUIT
IN
V
= 12V
1.20
1.15
1.10
–0.10
–0.20
50
TEMPERATURE (°C)
100 125
–50
0
25
50
75 100 125
–50 –25
0
25
75
–25
0
0.5
1
1.5
2
2.5
3
TEMPERATURE (°C)
LOAD CURRENT (A)
3603 G19
3603 G20
3603 G18
PIN FUNCTIONS
MSE/UF Package
INTV (Pin 1/Pin 3): Output of Internal 5V LDO.
TRACK/SS(Pin9/Pin11):TrackingInputfortheController
CC
or Optional External Soft-Start Input. This pin allows the
SYNC/MODE (Pin 2/Pin 4): Mode Select and External
Clock Synchronization Input.
start-up of V
to “track” the external voltage at this pin
OUT
usinganexternalresistordivider.Anexternalsoft-startcan
be programmed by connecting a capacitor between this
pin and ground. Leave this pin floating to use the internal
PGOOD (Pin 3/Pin 5): Power Good Output. Open-drain
logic output that is pulled to ground when the output volt-
age is not within 10ꢀ of regulation point.
1ms soft-start clamp. Do not tie this pin to INTV or to
CC
PV .
IN
RT (Pin 4/Pin 6): Frequency Set Pin.
PGND (Pins 10, 11/Pins 12, 13, 14, 15): Power
ITH (Pin 5/Pin 7): Error Amplifier Compensation Point.
Ground.
V
(Pin 6/Pin 8): Feedback Pin.
FB
SW (Pins 12, 13/Pins 16, 17, 18, 19): Switch Node Con-
nection to the Inductor.
SGND (Pin 7, Exposed Pad Pin 17/Pin 9, Exposed Pad
Pin 21): Signal Ground. Exposed pad is signal ground
and must be soldered to the PCB for rated thermal
performance.
BOOST (Pin 14/Pin 20): Bootstrapped Supply to the Top
Side Floating Gate Driver.
PV (Pins15,16/Pins1,2):PowerInputSupply.Decouple
IN
RUN (Pin 8/Pin 10): Run Control Input. This pin may be
this pin with a capacitor to PGND
tied to PV to enable the chip.
IN
3603fa
6
LTC3603
BLOCK DIAGRAM
ITH
BOOST
INTV
PV
IN
CC
1.2μA
0.6V
VOLTAGE
REFERENCE
SLOPE
COMPENSATION
RECOVERY
TRACK/SS
1ms
SOFT-START
BCLAMP
+
–
ERROR
AMPLIFIER
BURST
COMPARATOR
+
+
+
–
MAIN
I-COMPARATOR
+
V
FB
–
SYNC/MODE
SW
SW
SW
+
–
0.54V
+
–
SLOPE
COMPENSATION
OSCILLATOR
OVER-CURRENT
COMPARATOR
+
–
+
–
LOGIC
PGND
PGND
PGND
0.66V
REVERSE
PGOOD
COMPARATOR
+
–
RT
RUN
SYNC/MODE
3602 BD
3603fa
7
LTC3603
OPERATION
Main Control Loop
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0.42V to 1V enables Burst Mode operation. In Burst
Mode operation, the internal power MOSFETs operate
intermittently at light loads. This increases efficiency by
minimizing switching losses. During Burst Mode opera-
tion, the minimum peak inductor current is externally set
by the voltage on the SYNC/MODE pin and the voltage
on the ITH pin is monitored by the burst comparator to
determine when sleep mode is enabled and disabled.
When the average inductor current is greater than the
load current, the voltage on the ITH pin drops. As the ITH
voltage falls below 330mV, the burst comparator trips and
enables sleep mode. During sleep mode, the top power
MOSFET is held off and the ITH pin is disconnected from
theoutputoftheerroramplifier.Themajorityoftheinternal
circuitry is also turned off to reduce the quiescent current
to 75μA while the load current is solely supplied by the
output capacitor. When the output voltage drops, the ITH
pin is reconnected to the output of the error amplifier and
the top power MOSFET along with all the internal circuitry
is switched back on. This process repeats at a rate that
is dependent on the load demand. Pulse-skipping opera-
tion is implemented by connecting the SYNC/MODE pin
to ground. This forces the burst clamp level to be at 0V.
As the load current decreases, the peak inductor current
will be determined by the voltage on the ITH pin until the
ITH voltage drops below 330mV. At this point, the peak
inductor current is determined by the minimum on-time
of the current comparator. If the load demand is less than
the average of the minimum on-time inductor current,
switching cycles will be skipped to keep the output volt-
age in regulation.
The LTC3603 is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal opera-
tion, theinternaltoppowerswitch(N-channelMOSFET)is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the V pin with an internal 0.6V reference. When the load
FB
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2.5A for forced continuous mode and 0A
for Burst Mode operation.
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
3MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by 10ꢀ. In an overvoltage condition, the top
powerMOSFETisturnedoffandthebottompowerMOSFET
isswitchedonuntileithertheovervoltageconditionclears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Frequency Synchronization
ConnectingtheSYNC/MODEpintoINTV willdisableBurst
CC
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficientthanBurstModeoperation,butmaybedesirablein
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
TheinternaloscillatoroftheLTC3603canbesynchronized
to an external 5V clock connected to the SYNC/MODE pin.
The frequency of the external clock can be in the range of
300kHz to 3MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25ꢀ lower than the synchronization frequency.
When synchronized, the LTC3603 will operate in pulse-
skipping mode.
3603fa
8
LTC3603
OPERATION
Dropout Operation
Overtemperature and PV Overvoltage Protection
IN
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases toward the maximum
on-time. Furtherreductionofthesupplyvoltageforcesthe
top switch to remain on for more than one cycle until it
attempts to stay on continuously. In order to replenish the
voltage on the floating BOOST supply capacitor, however,
the topswitch isforced offand the bottomswitchisforced
onforapproximately85nseverysixteenclockcycles. This
achieves an effective duty cycle that can exceed 99ꢀ. The
output voltage will then be primarily determined by the
input voltage minus the voltage drop across the upper
internal N-channel MOSFET and the inductor.
WhenusingtheLTC3603inanapplicationcircuit,caremust
betakennottoexceedanyoftheratingsspecifiedintheAb-
solute Maximum Ratings section. As an added safeguard,
however,theLTC3603doesincorporateanovertemperature
shutdown feature. If the junction temperature reaches ap-
proximately 150°C, both power switches will be turned off
and the SW node will become high impedance. After the
part has cooled to below 115°C, it will restart. Similarly,
the LTC3603 contains an overvoltage shutdown feature
that monitors the voltage on the PV pin. If this voltage
IN
exceeds approximately 16.5V, both power switches will be
turned off until PV voltage is reduced below 16V.
IN
Slope Compensation and Inductor Peak Current
Voltage Tracking and Soft-Start
Slope compensation provides stability in constant-fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50ꢀ. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 30ꢀ. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3603, however,
slope compensation recovery is implemented to reduce
the variation of the maximum inductor peak current (and
therefore the maximum available output current) over the
range of duty cycles.
Some microprocessors and DSP chips need two power
supplieswithdifferentvoltagelevels. Thesesystemsoften
requirevoltagesequencingbetweenthecorepowersupply
and the I/O power supply. Without proper sequencing,
latch-up failure or excessive current draw may occur that
could result in damage to the processor’s I/O ports or the
I/O ports of a supporting system device such as memory,
an FPGA or a data converter. To ensure that the I/O loads
are not driven until the core voltage is properly biased,
tracking of the core supply and the I/O supply voltage is
necessary.
Voltage tracking is enabled by applying a ramp voltage to
the TRACK/SS pin. When the voltage on the TRACK pin
is below 0.6V, the feedback voltage will regulate to this
tracking voltage. When the tracking voltage exceeds 0.6V,
tracking is disabled and the feedback voltage will regulate
to the internal reference voltage.
Short-Circuit Protection
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases to more than 4.5A, the
top power MOSFET will be held off and switching cycles
will be skipped until the inductor current is reduced.
The TRACK/SS pin is also used to implement an external
soft-start function. A 1.2μA current is sourced from this
pin so that an external capacitor may be added to create
a smooth ramp. If this ramp is slower than the internal
1ms soft-start, then the output voltage will track this ramp
during start-up instead. Leave this pin floating to use the
internal 1ms soft-start ramp. Do not tie the TRACK/SS
pin to INTV or to PV .
CC
IN
3603fa
9
LTC3603
APPLICATIONS INFORMATION
ThebasicLTC3603applicationcircuitisshownonthefront
page of this data sheet. External component selection is
determined by the maximum load current and begins with
theselectionoftheinductorvalueandoperatingfrequency
A reasonable starting point for selecting the ripple current
is ΔI = 0.4(I ), where I is the maximum output
L
MAX
MAX
current. The largest ripple current occurs at the highest
V . To guarantee that the ripple current stays below a
IN
followed by C and C
.
specified maximum, the inductor value should be chosen
IN
OUT
according to the following equation:
Operating Frequency
⎛
⎞ ⎛
⎞
VOUT
fΔI
VOUT
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintainlowoutputripplevoltage.Theoperatingfrequency
oftheLTC3603isdeterminedbyanexternalresistorthatis
connectedbetweentheRTpinandground.Thevalueofthe
resistor sets the ramp current that is used to charge and
dischargeaninternaltimingcapacitorwithintheoscillator
and can be calculated by using the following equation:
L =
• 1–
⎜
⎟ ⎜
⎟
V
⎝
L(MAX)⎠ ⎝
⎠
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
1.15 • 1011
Inductor Core Selection
ROSC
=
– 10k
f(Hz)
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of the more expensive ferrite cores. Actual
core loss is independent of core size for a fixed inductor
value but it is very dependent on the inductance selected.
As the inductance increases, core losses decrease. Un-
fortunately, increased inductance requires more turns of
wire and therefore copper losses will increase.
Although frequencies as high as 3MHz are possible, the
minimum on-time of the LTC3603 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 95ns. Therefore, the minimum duty cycle is
equal to 100 • 95ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
ripplecurrentΔI increaseswithhigherV anddecreases
L
IN
with higher inductance.
⎛
⎞
V
fL
VOUT
⎛
⎞
OUT
ΔIL =
• 1–
⎜
⎝
⎟
⎠
⎜
⎝
⎟
V
⎠
IN
Having a lower ripple current reduces the ESR losses
in the output capacitors and the output voltage ripple.
Highest efficiency operation is achieved at low frequency
with small ripple current. This, however, requires a large
inductor.
Different core materials and shapes will change the
size/current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy ma-
terials are small and do not radiate energy but generally
cost more than powdered iron core inductors with similar
3603fa
10
LTC3603
APPLICATIONS INFORMATION
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long-term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have
ahighvoltagecoefficientandaudiblepiezoelectriceffects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
C and C
Selection
IN
OUT
The input capacitance, C , is needed to filter the trapezoi-
IN
dal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for
the maximum RMS current should be used. RMS current
is given by:
Using Ceramic Input and Output Capacitors
VOUT
V
VOUT
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
IN
IRMS =IOUT(MAX)
•
•
–1
V
IN
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design.
V . At best, this ringing can couple to the output and be
IN
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at V large enough to damage the part.
IN
Output Voltage Programming
The selection of C
is determined by the effective series
OUT
The output voltage is set by an external resistive divider
according to the following equation:
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
R2
R1
⎛
⎝
⎞
VOUT = 0.6V • 1+
⎜
⎟
⎠
The output ripple, ΔV , is determined by:
OUT
The resistive divider allows the V pin to sense a fraction
FB
of the output voltage as shown in Figure 1.
⎛
⎜
⎝
⎞
1
ΔVOUT ≤ ΔIL • ESR+
⎟
8fCOUT
⎠
V
OUT
R2
The output ripple is highest at maximum input voltage
V
since ΔI increases with input voltage. Multiple capacitors
FB
L
LTC3603
R1
placed in parallel may be needed to meet the ESR and
RMScurrenthandlingrequirements.Drytantalum,special
polymer,aluminumelectrolyticandceramiccapacitorsare
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
SGND
3603 F01
Figure 1. Setting the Output Voltage
3603fa
11
LTC3603
APPLICATIONS INFORMATION
Burst Clamp Programming
Pulseskipping,whichisacompromisebetweenlowoutput
voltage ripple and efficiency, can be implemented by con-
If the voltage on the SYNC/MODE pin is in the range of
0.42V to 1V, Burst Mode operation is enabled. During
Burst Mode operation, the voltage on the SYNC/MODE
pin determines the burst clamp level. This level sets the
nectingtheSYNC/MODEpintoground. ThissetsI
to
BURST
0A.Inthiscondition,thepeakinductorcurrentislimitedby
the minimum on-time of the current comparator and the
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
minimumpeakinductorcurrent,I
,foreachswitching
BURST
cycle according to the following equation:
IBURST
VBURST
=
+ 0.42V
6A/V
is the voltage on the SYNC/MODE pin. I
Frequency Synchronization
V
can
BURST
BURST
The LTC3603’s internal oscillator can be synchronized to
an external 5V clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 3MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
be programmed in the range of 0A to 3.5A, which cor-
responds to a V range of 0.42V to 1V. As the output
BURST
load current drops, the peak inductor current decreases
to keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
, the burst clamp will force the peak inductor
BURST
the R resistor. Because slope compensation is generated
T
current to remain equal to I
regardless of further
BURST
by the oscillator’s internal ramp, the external frequency
should be set 25ꢀ higher than the frequency set by the
reductions in the load current. Since the average inductor
current is therefore greater than the output load current,
the voltage on the ITH pin will decrease. When the I
voltage drops to 330mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
againwhentheoutputvoltagedropsoutofregulation. The
R resistor to ensure that adequate slope compensation
T
TH
is present. When synchronized, the LTC3603 will operate
in pulse-skipping mode.
INTV Regulator
CC
TheLTC3603featuresanintegratedP-channellowdropout
value for I
is determined by the desired amount of
linear regulator (LDO) that supplies power to the INTV
BURST
CC
output voltage ripple. As the value of I
increases, the
supply pin from the PV pin. This LDO supply has been
BURST
IN
sleep time between pulses and the output voltage ripple
designed to deliver up to 35mA of load current for the
powering of the internal gate drivers and other internal
circuitry.Asmallexternalloadmayalsobeappliedprovided
increases. The burst clamp voltage, V
, can be set
BURST
by a resistor divider from the INTV pin. Alternatively,
CC
the SYNC/MODE pin may be tied directly to the V pin to
that the total current from the INTV supply does not
FB
CC
set V
= 0.6V (I
= 1A), or through an additional
exceed 35mA. The INTV pin should be bypassed with
BURST
BURST
CC
divider resistor (R3) to set V
Figure 2).
= 0.42V to 0.6V (see
no less than a 0.22μF ceramic capacitor. A 1μF ceramic
capacitor is suitable for most applications.
BURST
R2
Topside MOSFET Driver Supply (BOOST Pin)
V
OUT
INTV
FB
CC
LTC3603
R2
R1
LTC3603
R3 (OPTIONAL)
The LTC3603 uses a bootstrapped supply to power the
gate of the internal topside MOSFET (Figure 3). When the
SYNC/MODE
SGND
SYNC/MODE
topside MOSFET is off and the SW pin is low, diode D
R1
BST
charges capacitor C
to the voltage on the INTV sup-
BST
CC
SGND
ply. In order to turn on the topside MOSFET, the voltage on
3603 F02
the BOOST pin is then applied to its gate. As the topside
V
= 0.42V TO 1V
V
= 0.42V TO 0.6V
BURST
BURST
MOSFET turns on, the SW pin rises to the PV voltage
IN
Figure 2. Programing the Burst Clamp
3603fa
12
LTC3603
APPLICATIONS INFORMATION
and the BOOST pin rises to PV + INTV , thereby keep-
When the LTC3603 detects a fault condition (either
undervoltage lockout or overtemperature), the TRACK/SS
pin is quickly pulled to ground and the internal soft-start
timer is also reset. This ensures an orderly restart when
using an external soft-start capacitor.
IN
CC
ing the MOSFET fully enhanced. For most applications, a
0.22μFceramiccapacitorisappropriateforC . Schottky
BST
diode D should have a reverse breakdown voltage that
BST
is greater than PV
.
IN(MAX)
Toimplementtracking,aresistordividerisplacedbetween
INTV
CC
an external supply (V ) and the TRACK/SS pin as shown
X
D
C
LTC3603
BST
in Figure 5a. This technique can be used to cause V
ratiometrically track the V supply (Figure 5b), according
to
OUT
C
INTVCC
BOOST
X
to the following:
BST
SW
VOUT
VX
RTA RA +RB
•
3603 F03
=
RA RTA +RTB
Figure 3. Topside MOSFET Supply
For coincident tracking, as shown in Figure 5c, (V
X
=
OUT
Run and Soft-Start/Tracking Functions
V during start-up),
The LTC3603 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 0.7V
puts the LTC3603 into a low quiescent current shutdown
R
= R , R = R
A TB B
TA
Note that the 1.2μA current that is sourced from the
TRACK/SS pin will cause a slight offset in the voltage seen
on the TRACK/SS pin and consequently on the V
ageduringtracking. ThisV
current is given by:
mode (I < 1μA). When the RUN pin is greater than 0.7V,
Q
volt-
OUT
thecontrollerisenabled.TheRUNpincanbedrivendirectly
from logic as shown in Figure 4.
offsetduetotheTRACK/SS
OUT
3.3V OR 5V
PV
IN
RTARTA RA +RB
VOS,TRK =(1µA)•
•
LTC3603
RUN
LTC3603
RUN
4.7MΩ
RTA +RTB
RA
3603 F04
For most applications, this offset is small and has minimal
effect on tracking performance. For improved tracking ac-
curacy, reduce the parallel impedance of R and R .
TA
TB
Figure 4. RUN Pin Interfacing
V
OUT
R
Soft-start and tracking are implemented by limiting the
effective reference voltage as seen by the error amplifier.
Ramping up the effective reference into the error amp in
turn causes a smooth and controlled ramp on the output
voltage of the converter. To use the default, internal 1ms
soft-start ramp, leave the TRACK/SS pin floating. Do not
B
V
X
V
FB
R
R
TB
LTC3603
TRACK/SS
R
A
TA
3603 F05a
tietheTRACK/SSpintoINTV ortoPV . Toincreasethe
CC
IN
Figure 5a. Using the TRACK/SS Pin to Track VX
soft-starttimeabove1ms,placeacapontheTRACK/SSpin.
A 1.2μA internal pull-up current will charge this capacitor,
resulting in a soft-start ramp time given by:
0.6V
tSS =CSS •
1.2µA
3603fa
13
LTC3603
APPLICATIONS INFORMATION
supply. Each time the gate is switched from high to
low to high again, a packet of charge, dQ, moves from
V
X
INTV to ground. The resulting dQ/dt is the current
CC
out of INTV that is typically larger than the DC bias
CC
V
OUT
current. In continuous mode, the gate charge current
can be approximated by I
= f(9.5nC). Since the
IN
GATECHG
INTV voltage is generated from V by a linear regula-
CC
tor, the current that is internally drawn from the INTV
CC
TIME
supply can be treated as V current for the purposes
IN
Figure 5b. Ratiometric Tracking
of efficiency considerations.
Transition losses apply only to the internal topside
MOSFET and become more prominent at higher input
voltages. Transition losses can be estimated from:
V
X
2
Transition Loss = (1.7) V • I
• (120pF) • f
V
IN
O(MAX)
OUT
2
2. I R losses are calculated from the resistances of the
internal switches, R and external inductor R . In
SW
L
continuous mode, the average output current flow-
ing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
3603 F05b,c
TIME
Figure 5c. Coincident Tracking
Efficiency Considerations
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100ꢀ. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
R
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
SW
The R
for both the top and bottom MOSFETs can
DS(ON)
beobtainedfromtheTypicalPerformanceCharacteristics
2
curves. Thus, to obtain I R losses, simply add R to
SW
Efficiency = 100ꢀ – (L1 + L2 + L3 + ...)
R and multiply the result by the square of the average
L
output current:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
2
2
I R Loss = I (R + R )
O
SW
L
Although all dissipative elements in the circuit produce
Other losses, including C and C
ESR dissipative
OUT
IN
losses, two main sources usually account for most of the
losses and inductor core losses, generally account for
2
losses: V operating current and I R losses.
IN
less than 2ꢀ of the total power loss.
TheV operatingcurrentlossdominatestheefficiencyloss
IN
2
Thermal Considerations
at very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents.
Inmostapplications,theLTC3603doesnotdissipatemuch
heatduetoitshighefficiency.But,inapplicationswherethe
LTC3603 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both power switches will be turned
1.TheV operatingcurrentcomprisesthreecomponents:
IN
The DC supply current as given in the electrical char-
acteristics, the internal MOSFET gate charge currents
and the internal topside MOSFET transition losses. The
MOSFET gate charge current results from switching the
gatecapacitanceoftheinternalpowerMOSFETswitches.
off and the SW node will become high impedance.
The gates of these switches are driven from the INTV
CC
3603fa
14
LTC3603
APPLICATIONS INFORMATION
To prevent the LTC3603 from exceeding the maximum
junctiontemperature,theuserwillneedtodosomethermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
Design Example
As a design example, consider using the LTC3603 in
an application with the following specifications: V
=
IN
12V, V
= 3.3V, I
= 2.5A, I
= 100mA,
OUT
OUT(MAX)
OUT(MIN)
f = 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
T = (P ) • (θ )
R
D
JA
1.15•1011
where P is the power dissipated by the regulator and θ
D
JA
ROSC
=
–10k =105k
is the thermal resistance from the junction of the die to
1MHz
the ambient temperature.
The junction temperature, T , is given by:
Next, calculate the inductor value for about 40ꢀ ripple
J
current at maximum V :
IN
T = T + T
R
J
A
⎛
⎞
where T is the ambient temperature.
3.3V
3.3V
12V
⎛
⎝
⎞
A
L =
• 1–
⎟ ⎜
= 2.39µH
⎜
⎟
⎠
1MHz 1A
( )
)
(
As an example, consider the LTC3603 in dropout at an
input voltage of 8V, a load current of 2.5A and an ambient
temperatureof70°C. FromtheTypicalPerformancegraph
⎝
⎠
Using a 2.2μH inductor results in a maximum ripple cur-
rent of:
ofSwitchResistance,theR
ofthetopswitchat70°C
DS(ON)
is approximately 85mΩ. Therefore, power dissipated by
⎛
⎞
3.3V
1MHz 2.2µH
3.3V
12V
⎛
⎞
the part is:
ΔI =
• 1–
⎟ ⎜
= 1.1A
⎜
⎟
⎠
L
⎝
(
)
)
(
2
2
⎝
⎠
P = (I
)(R
) = (2.5A) (85mΩ) = 0.53W
DS(ON)
D
LOAD
For the MSOP package, the θ is 45°C/W. Thus, the junc-
C
will be selected based on the ESR that is required
JA
OUT
tion temperature of the regulator is:
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. In this applica-
tion, a tantalum capacitor will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower
the total effective ESR. For this design, a 100μF ceramic
T = 70°C + (0.53W)(45°C/W) = 93.85°C
J
which is below the maximum junction temperature of
125°C.
capacitor will be used. C should be sized for a maximum
current rating of:
IN
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
3.3V
12V
12V
3.3V
IRMS = 2.5A •
•
–1=1.12ARMS
a load step occurs, V
immediately shifts by an amount
OUT
Decoupling the PV pin with a 22μF ceramic capacitor is
IN
equal to ΔI
•(ESR), where ESR is the effective series
LOAD
adequate for most applications.
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
chargeC ,generatingafeedbackerrorsignalusedbythe
The output voltage can now be programmed by choosing
the values of R1 and R2. Choose R1 = 105k and calculate
R2 as:
OUT
regulator to return V
to its steady-state value. During
can be monitored for overshoot
OUT
this recovery time, V
OUT
or ringing that would indicate a stability problem. The I
TH
V
⎛
⎜
⎞
OUT
pinexternalcomponentsandoutputcapacitorshowninthe
frontpageapplicationwillprovideadequatecompensation
for most applications.
R2=R1
–1 = 472.5k
⎟
0.6V
⎝
⎠
3603fa
15
LTC3603
APPLICATIONS INFORMATION
V
IN
12V
C
VCC
C
IN
1μF
22μF
R
PG
SYNC/MODE
PGOOD
INTV
CC
200k
PGOOD
PV
PV
IN
IN
R
105k
OSC
D1
C
RT
BOOST
C
ITH
R
BST
ITH
1nF
0.22μF
4.32k
LTC3603
ITH
SW
SW
V
L1
2.2μH
FB
V
3.3V
2.5A
R1
105k
OUT
RUN
SW
TRACK/SS
PGND
PGND
PGND
R2
475k
C
FB
10pF
C
OUT
100μF
L1: VISHAY IHLP2525CZER2R2MO1
3603 F06
C
C
: TAIYO YUDEN TMK325BJ226MM-T
IN
OUT
: TDK C3225X5ROJ107M
Figure 6. 12V to 3.3V, 2.5A Regulator at 1MHz, Burst Mode Operation
Choose a standard value of R2 = 475k. The voltage on
the MODE pin will be set to 0.6V by tying the MODE pin
to the FB pin. This will set the burst current equal to ap-
proximately 1A. Figure 6 shows a complete schematic for
this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3603. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3603.
How to Reduce SW Ringing
As with any switching regulator, there will be voltage ring-
ing on the SW node, especially for high input voltages.
The ringing amplitude and duration is dependent on the
switchingspeed(gatedrive),layout(parasiticinductance)
and MOSFET output capacitance. This ringing contributes
to the overall EMI, noise and high frequency ripple. One
way to reduce ringing is to optimize layout. A good layout
minimizes parasitic inductance. Adding an RC snubber
from SW to GND is also an effective way to reduce ringing.
Finally, adding a resistor (10Ω to 100Ω) in series with the
BOOST pin will slow down the MOSFET turn-on slew rate
and dampen ringing, but at the cost of reduced efficiency.
Note that since the IC is buffered from high frequency
transients by PCB and bondwire inductances, the ringing
by itself is normally not a concern for reliability.
2.Connectthe(+)terminaloftheinputcapacitor(s),C ,as
IN
closeaspossibletothePV pin.Thiscapacitorprovides
the AC current into the internal power MOSFETs.
IN
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4.Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PV , INTV , V , PGND, SGND, or any other
IN
CC OUT
DC rail in your system).
3603fa
16
LTC3603
TYPICAL APPLICATIONS
1.8V, 2.5A Regulator at 1MHz, Burst Mode Operation
V
IN
12V
C
VCC
C
IN
R3
845k
R
PG
200k
1μF
22μF
SYNC/MODE
PGOOD
INTV
CC
PGOOD
R4
137k
PV
PV
IN
IN
R
OSC
D1
105k
RT
BOOST
C
ITH
C
R
BST
ITH
1nF
0.22μF
4.32k
LTC3603
ITH
SW
SW
V
L1
1μH
FB
V
1.8V
2.5A
R1
105k
OUT
RUN
SW
TRACK/SS
PGND
PGND
PGND
C
R2
210k
FB
10pF
C
OUT
100μF
s 2
L1: VISHAY IHLP2525CZER1R0MO1
3603 TA02
C
C
: TAIYO YUDEN TMK325BJ226MM-T
IN
OUT
: TAIYO YUDEN AMK316BJ107ML
1.2V, 2.5A Regulator at 750kHz, Burst Mode Operation
V
IN
12V
C
VCC
C
IN
22μF
R3
R
PG
1μF
845k 200k
SYNC/MODE
PGOOD
INTV
CC
PGOOD
R4
137k
PV
PV
IN
IN
R
143k
OSC
D1
RT
BOOST
C
ITH
C
BST
R
ITH
1nF
0.22μF
4.32k
LTC3603
ITH
SW
SW
V
L1
1μH
FB
R1
105k
V
1.2V
2.5A
OUT
RUN
SW
TRACK/SS
PGND
PGND
PGND
R2
105k
C
10pF
OUT
100μF
s2
L1: VISHAY IHLP2525CZER1ROMO1
3603 TA03
C
C
: TAIYO YUDEN TMK325BJ226MM-T
IN
OUT
: TAIYO YUDEN AMK316BJ107ML
3603fa
17
LTC3603
TYPICAL APPLICATIONS
Efficiency vs Load Current,
Efficiency vs Load Current,
1.2V Regulator at 750kHz, Burst Mode Operation
1.8V Regulator at 1MHz, Burst Mode Operation
100
95
100
95
V
= 7.2V
= 12V
V
= 7.2V
= 12V
IN
IN
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
V
V
IN
IN
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
3603 TA04a
3603 TA04b
3.3V, 2.5A Regulator, Synchronized to 1.8MHz, Small Size
1.8MHz
V
IN
EXT. CLK
12V
C
VCC
C
IN
1μF
22μF
R
200k
PG
SYNC/MODE
PGOOD
INTV
CC
PGOOD
PV
PV
IN
IN
R
69.8k
OSC
D1
RT
BOOST
C
ITH
C
BST
R
ITH
470pF
0.22μF
2.94k
LTC3603
ITH
SW
SW
V
L1
1μH
FB
V
2.5V
2.5A
R1
105k
OUT
RUN
SW
TRACK/SS
PGND
PGND
PGND
C
R2
332k
FB
10pF
C
OUT
47μF
L1: VISHAY IHLP2525CZER1ROMO1
3603 TA05
C
C
: TAIYO YUDEN TMK325BJ226MM-T
IN
OUT
: MURATA GRM31CR60J476ME19
3603fa
18
LTC3603
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev A)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
2.845 p 0.102
(.112 p .004)
0.889 p 0.127
(.035 p .005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 p 0.102
(.065 p .004)
1.651 p 0.102
(.065 p .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 p 0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 p 0.102
(.159 p .004)
(NOTE 3)
(.0120 p .0015)
TYP
0.280 p 0.076
(.011 p .003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0o – 6o TYP
0.254
(.010)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE16) 0608 REV A
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3603fa
19
LTC3603
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.45 p 0.05
2.00 REF
2.45 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 s 45o
CHAMFER
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
R = 0.05
TYP
R = 0.115
0.75 p 0.05
TYP
4.00 p 0.10
19 20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
2.45 p 0.10
2.00 REF
4.00 p 0.10
2.45 p 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.25 p 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3603fa
20
LTC3603
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/09 Changes to Absolute Maximum Ratings
Changes to Pin Configuration
2
2
Change to Electrical Characteristics
Text Changes to Pin Functions
3
6
Change to Block Diagram
7
Text Changes to Operation Section
Text Changes to Applications Information Section
“How to Reduce SW Ringing” Section Added
Additions to Related Parts
8
10, 12, 15
16
22
3603fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3603
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
95ꢀ Efficiency, V : 4.5V to 15V, V
LTC3601
LTC3605
LTC3609
LTC3612
LTC3412A
LTC3413
LTC3414
LTC3415
LTC3416
LTC3418
LTC3602
LTC3608
LTC3610
LTC3611
15V, 1.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
= 0.6V,
OUT(MIN)
OUT
IN
I = 300μA, I < 14μA, 3mm × 3mm QFN16, MSOP16E
Q
SD
15V, 5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4V to 15V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 2mA, I < 15μA, 4mm × 4mm QFN24
Q
SD
32V, 6A (I ), 1MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4V to 32V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 900μA, I < 15μA, 7mm × 8mm QFN52
Q
SD
6V, 3A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 2.25V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 70μA, I < 1μA, 3mm × 4mm QFN20, TSSOP20E
Q
SD
3A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 2.25V to 5.5V, V
= 0.8V,
OUT
IN
OUT(MIN)
I = 60μA, I < 1μA, TSSOP16E, 4mm × 4mm QFN16
Q
SD
3A (I
Sink/Source), 2MHz, Monolithic Synchronous Regulator for DDR/ 90ꢀ Efficiency, V : 2.25V to 5.5V, V
= V /2,
OUT
IN
OUT(MIN)
REF
QDR Memory Termination
I = 280μA, I < 1μA, TSSOP16E
Q SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 2.25V to 5.5V, V
= 0.8V,
OUT
IN
OUT(MIN)
I = 64μA, I < 1μA, TSSOP20E
Q
SD
7A (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 450μA, I < 1μA, 5mm × 7mm QFN38
Q
SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking 95ꢀ Efficiency, V : 2.25V to 5.5V, V
= 0.8V,
= 0.8V,
OUT
IN
OUT(MIN)
I = 64μA, I < 1μA, TSSOP20E
Q
SD
8A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 2.25V to 5.5V, V
IN
OUT
OUT(MIN)
I = 380μA, I < 1μA, 5mm × 7mm QFN38
Q
SD
10V, 2.5A (I ), 3MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4.5V to 10V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 75μA, I < 1μA, TSSOP16E, 4mm × 4mm QFN20
Q
SD
18V, 8A (I ), 1MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4V to 18V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 900μA, I < 15μA, 5mm × 7mm QFN52
Q
SD
24V, 12A (I ), 1MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4V to 24V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 900μA, I < 15μA, 9mm × 9mm QFN64
Q
SD
32V, 10A (I ), 1MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, V : 4V to 32V, V
= 0.6V,
OUT
IN
OUT(MIN)
I = 900μA, I < 15μA, 9mm × 9mm QFN64
Q
SD
ThinSOT is a trademark of Linear Technology Corporation.
3603fa
LT 1209 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC3603EUF#TRPBF
LTC3603 - 2.5A, 15V Monolithic Synchronous Step-Down Regulator; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
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