LTC3622 [Linear]
17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current;
| 型号： | LTC3622 |
| 厂家： | 
Linear |
| 描述： | 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current |
| 文件： | 总24页 (文件大小：1248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3622/
LTC3622-2/LTC3622-23/5
17V, Dual 1A
Synchronous Step-Down Regulator
with Ultralow Quiescent Current
FEATURES
DESCRIPTION
TheLTC®3622isadual1Aoutput,highefficiencysynchro-
nousmonolithicstep-downregulatorcapableofoperating
from input supplies up to 17V. The switching frequency is
fixed to 1MHz or 2.25MHz with a 50% synchronization
range to an external clock. The regulator features ultralow
quiescent current and high efficiency over a wide output
voltage range.
n
Dual Step-Down Outputs: 1A Per Channel
n
n
n
n
Wide V Range: 2.7V to 17V
IN
Wide V
Range: 0.6V to V
OUT
IN
Up to 95% Efficiency
No-Load I = 5µA with Both Channels Enabled;
Q
I < 4µA with Only One Channel Enabled
Q
n
n
High Efficiency, Low Dropout Operation
(100% Duty Cycle)
The step-down regulators operate from an input voltage
range of 2.7V to 17V and provide an adjustable output
Constant Frequency (1MHz/2.25MHz) with External
Frequency Synchronization
from 0.6V to V while delivering up to 1A of output cur-
IN
n
n
1% Output Voltage Accuracy
Current Mode Operation for Excellent Line and Load
Transient Response
rent. A user-selectable mode input is provided to allow
the user to trade off ripple noise for light load efficiency.
Burst Mode® operation provides the highest efficiency at
lightloads,whilepulse-skippingmodeprovidesthelowest
ripplenoise.Theswitchingregulatorscanbesynchronized
n
n
n
n
Phase Shift Programmable with External Clock
Selectable Current Limit
Internal Compensation and Soft-Start
Compact 14-Pin DFN (3mm × 4mm) and 16-Lead
MSOP Packages
to an external clock. Furthermore, fixed V
available to eliminate the external feedback resistors.
options are
OUT
List of LTC3622 Options
PART NAME
LTC3622
FREQUENCY
1.00MHz
V
OUT
APPLICATIONS
Adjustable
Adjustable
5V/3.3V
n
Battery Powered Systems
Point-of-Load Supplies
LTC3622-2
LTC3622-23/5
2.25MHz
n
2.25MHZ
n
Portable – Handheld Scanners
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 6580258, 6498466, 6611131, 5705919.
TYPICAL APPLICATION
Efficiency vs Load Current
2.5V/5V VOUT Application, fSW = 1MHz
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
V
IN
V
V
INTV
IN1
CC
5.5V TO 17V
IN2 MODE/SYNC
C
C1
IN
RUN1
RUN2
10µF
1µF
PHASE
I
LIM
LTC3622
GND
V
4.7µH
619k
6.8µH
V
OUT2
5V
1A
V
V
= 2.5V
= 5V
OUT1
2.5V
1A
OUT1
OUT2
SW1
FB1
SW2
FB2
V
SW
= 12V
= 1MHz
Burst Mode OPERATION
IN
619k
22pF
22pF
f
C
22µF
C
OUT2
22µF
OUT1
196k
84.5k
0.0001
0.001
0.01
0.1
1
LOAD CURRENT (A)
3622 TA01b
3622 TA01
3622fc
1
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature Range (Note 3)
V
, V
SV (MSOP Only) (Note 2)....... –0.3V to 17V
IN1 IN2, IN
LTC3622E .......................................... –40°C to 125°C
LTC3622I ........................................... –40°C to 125°C
LTC3622H.......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
RUN1, RUN2 ..............................................–0.3V to V
IN1
MODE/SYNC, FB1, FB2 ................................ –0.3V to 6V
PGOOD1, PGOOD2, I , PHASE.................. –0.3V to 6V
LIM
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
14 SW1
13 RUN1
12 FB1
IN1
1
2
3
4
5
6
7
8
V
16 SW1
15 NC
IN1
IN
PGOOD1
MODE/SYNC
PHASE
SV
PGOOD1
MODE/SYNC
PHASE
14 RUN1
13 FB1
15
GND
17
GND
11 INTV
10 FB2
CC
12 INTV
11 FB2
CC
PGOOD2
PGOOD2
I
10 RUN2
LIM
IN2
I
9
8
RUN2
SW2
LIM
V
9
SW2
V
IN2
MSE PACKAGE
16-LEAD PLASTIC MSE
DE PACKAGE
T
= 150°C, θ = 40°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
JMAX
14-LEAD (4mm × 3mm) PLASTIC DFN
T
JMAX
= 150°C, θ = 40°C/W, θ = 4.4°C/W
JA JC
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC3622#orderinfo
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
3622
PACKAGE DESCRIPTION
14-Lead (3mm x 4mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 125°C
LTC3622EDE#PBF
LTC3622EDE#TRPBF
LTC3622IDE#TRPBF
LTC3622IDE#PBF
3622
14-Lead (3mm x 4mm) Plastic DFN
14-Lead (3mm x 4mm) Plastic DFN
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
LTC3622HDE#PBF
LTC3622HDE#TRPBF
LTC3622EMSE#TRPBF
LTC3622IMSE#TRPBF
LTC3622HMSE#TRPBF
LTC3622EDE-2#TRPBF
LTC3622IDE-2#TRPBF
LTC3622HDE-2#TRPBF
LTC3622EMSE-2#TRPBF
LTC3622IMSE-2#TRPBF
LTC3622HMSE-2#TRPBF
LTC3622EDE-23/5#TRPBF
LTC3622IDE-23/5#TRPBF
LTC3622HDE-23/5#TRPBF
3622
LTC3622EMSE#PBF
LTC3622IMSE#PBF
LTC3622HMSE#PBF
LTC3622EDE-2#PBF
LTC3622IDE-2#PBF
LTC3622HDE-2#PBF
LTC3622EMSE-2#PBF
LTC3622IMSE-2#PBF
LTC3622HMSE-2#PBF
LTC3622EDE-23/5#PBF
LTC3622IDE-23/5#PBF
LTC3622HDE-23/5#PBF
3622
3622
16-Lead Plastic MSOP
3622
16-Lead Plastic MSOP
36222
36222
36222
36222
36222
36222
223/5
14-Lead (3mm x 4mm) Plastic DFN
14-Lead (3mm x 4mm) Plastic DFN
14-Lead (3mm x 4mm) Plastic DFN
16-Lead Plastic MSOP
16-Lead Plastic MSOP
16-Lead Plastic MSOP
14-Lead (3mm x 4mm) Plastic DFN
14-Lead (3mm x 4mm) Plastic DFN
14-Lead (3mm x 4mm) Plastic DFN
223/5
223/5
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3622fc
2
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Notes 3, 6)
SYMBOL PARAMETER
, V Operating Voltage
CONDITIONS
MIN
2.7
2.7
0.6
TYP
MAX
17
UNITS
V
V
V
V
IN1 IN2
SV Operating Voltage
IN
MSOP Package
17
V
Operating Voltage
V
IN
OUT
I
Input Quiescent Current
Active Mode, V
= V = 2V (Note 4)
RUN2
3
5
mA
µA
Q
RUN1
Burst Mode Operation, V
= V
= 2V,
10
1
RUN1
RUN2
MODE/SYNC = 3V, No Load
Shutdown Mode; V = V
= 0V
0.1
µA
V
RUN1
RUN2
V
Regulated Feedback Voltage
FB Input Current
LTC3622/LTC3622-2
0.594
0.591
0.6
0.6
0.606
0.609
FB
l
I
LTC3622/LTC3622-2
LTC3622-23/5
10
nA
FB
V
Regulated Fixed Output Voltage
(Channel 1)
4.950
4.925
5.0
5.0
5.050
5.075
V
V
OUT1
l
l
V
Regulated Fixed Output Voltage
(Channel 2)
LTC3622-23/5
3.267
3.250
3.3
3.3
3.333
3.350
V
V
OUT2
I
Feedback Input Leakage Current
Reference Voltage Line Regulation
Output Voltage Load Regulation
LTC3622-23/5
1
5
µA
%/V
%
FB(VOUT)
V
= 2.7V to 17V (Note 5)
0.01
0.1
0.015
IN
(Note 5)
NMOS Switch Leakage
PMOS Switch Leakage
0.1
0.1
1
1
µA
µA
R
NMOS On-Resistance
PMOS On-Resistance
V
= 5V
= 0V
0.15
0.37
Ω
Ω
DS(ON)
IN
l
Maximum Duty Cycle
Minimum On-Time
V
V
100
75
%
FB
FB
t
= 0.7V, V = V = 5
ns
ON(MIN)
IN1
IN2
V
RUN Input High
RUN Input Low
1.0
V
V
RUN
0.35
RUN Input Current
V
= 12V
0.1
20
nA
RUN
V
Pulse-Skipping Mode
Burst Mode Operation
0.15
V
V
MODE
V
–0.4
INTVCC
PHASE Input Threshold
Input Low
Input High
0.4
0.1
V
V
2.0
I
Input Threshold
Input Low
Input High
V
V
LIM
V
–0.1
INTVCC
INTV
CC
t
I
Soft Start Time
0.5
ms
SS
LIM
Peak Current Limit
V
V
V
V
V
> 5V
A
A
A
A
IN
= 0.1V (Both Channels)
1.6
0.8
1.6
0.8
1.8
1.0
1.8
1.0
2.0
1.2
2.0
1.2
ILIM
ILIM
ILIM
ILIM
= INTV – 0.1V (Both Channels)
= Floating, Channel 1
= Floating, Channel 2
CC
V
V
V
V
Undervoltage Lockout
V
Ramping Up
IN
2.3
2.5
160
19
2.65
V
mV
V
INTVCC
INTVCC
Undervoltage Lockout Hysteresis
l
Overvoltage Lockout Rising
18
20
IN
IN
Overvoltage Lockout Hysteresis
300
mV
3622fc
3
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Notes 3, 6)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
f
Oscillator Frequency
LTC3622-2/LTC3622-23/5 –40°C ≤ T ≤ 150°C
1.8
0.82
0.75
2.25
1.00
1.00
2.6
1.16
1.16
MHz
MHz
MHz
OSC
A
LTC3622
LTC3622
–40°C ≤ T ≤ 125°C
A
–40°C ≤ T ≤ 150°C
A
External CLK Amplitude
SYNC Capture Range
0.4
50
V
–0.3
V
%
V
INTVCC
% of Programmed Frequency
150
V
INTV Voltage
3.3
3.6
–7.5
275
3.9
–11
350
INTVCC
CC
Power Good Range
Power Good Resistance
PGOOD Delay
V
> 4V
%
Ω
IN
R
PGOOD
PGOOD R
at 2mA
DS(ON)
t
PGOOD Low to High
PGOOD High to Low
0
32
Cycles
Cycles
PGOOD
Phase Shift Between Channel 1 and Channel
2
V
V
= 0V
0
180
Deg
Deg
PHASE
PHASE
= INTV , V
= 0V
CC MODE/SYNC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. Transient Absolute Maximum Voltages should not be applied for
more than 4% of the switching duty cycle.
range. High junction temperatures degrade operating lifetimes; operating
lifetime is derated for junction temperatures greater than 125°C. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environment
factors.
Note 4. The quiescent current in active mode does not include switching
loss of the power FETs.
Note 3. The LTC3622 is tested under pulsed load conditions such that
T ≈ T . The LTC3622E is guaranteed to meet specified performance from
J
A
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3622I is guaranteed over the
–40°C to 125°C operating junction temperature range and the LTC3622H
is guaranteed over the -40°C to 150°C operating junction temperature
Note 5. The LTC3622 is tested in a proprietary test mode that connects
V
FB
to the output of error amplifier.
Note 6. T is calculated from the ambient T and power dissipation P
D
J
A
according to the following formula: T = T + (P • θ )
J
A
D
JA
3622fc
4
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.
Efficiency vs Load Current at
Dropout Operation
Efficiency vs Load Current
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Burst Mode OPERATION
PULSE SKIP
V
V
= 2.5V
= 3.3V
OUT
OUT
V
V
= 2.5V
= 5V
OUT
OUT
V
f
= 12V
= 2.25MHz
Burst Mode OPERATION
0.001 0.01
LOAD CURRENT (A)
V
= 5V
V
f
= 12V
= 1MHz
IN
SW
IN
IN
SW
100% Duty Cycle
f
= 2.25MHz
Burst Mode OPERATION
0.001 0.01
LOAD CURRENT (A)
SW
0.0001
0.001
0.01
0.1
1
0.0001
0.1
1
0.0001
0.1
1
LOAD CURRENT (A)
3622 G02
3622 G01
3622 G03
VOUT Efficiency vs Input Voltage
Above and Below Dropout
Efficiency vs Load Current
Efficiency vs Input Voltage
95
90
85
80
75
70
90
80
70
60
50
40
30
20
10
0
96
84
72
60
48
36
24
12
0
10mA LOAD
1A LOAD
I
= 10mA
= 1mA
LOAD
I
LOAD
I
= 100µA
LOAD
V
V
f
= 12V
= 1.8V
= 1MHz
IN
OUT
SW
V
f
= 4.25V
V
f
= 2.5V
OUT
SW
OUT
SW
= 1MHz
= 1MHz
Burst Mode OPERATION
Burst Mode OPERATION
10 12 14
INPUT VOLTAGE (V)
Burst Mode OPERATION
2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5
0.001
0.01
0.1
1
0
2
4
6
8
16 18
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3622 G04
3622 G05
3622 G06
IQ vs VIN
Burst Mode Operation
Pulse-Skipping Mode Operation
5
4
3
2
1
0
SW
SW
10V/DIV
10V/DIV
I
I
Burst Mode OPERATION
SHUT DOWN
V
OUT
AC-COUPLED
20mV/DIV
Q
Q
V
OUT
AC-COUPLED
50mV/DIV
I
L
IL
100mA/DIV
200mA/DIV
3622 G08
3622 G09
4µs/DIV
4µs/DIV
V
V
= 12V
V
V
= 12V
IN
OUT
IN
OUT
= 2.5V
= 2.5V
0
2
4
6
8
10 12 14 16 18
Burst Mode OPERATION
= 75mA
PULSE-SKIPPING MODE
= 10mA
INPUT VOLTAGE (V)
I
I
OUT
OUT
3622 G07
3622fc
5
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.
Oscillator Frequency
vs Temperature
Load Step
Start-Up Operation
1500
1400
1300
1200
1100
1000
900
RUN
5V/DIV
V
OUT
I
AC-COUPLED
200mV/DIV
L
200mA/DIV
V
OUT
I
L
1V/DIV
500mA/DIV
PGOOD
2V/DIV
800
700
3622 G11
3622 G10
40µs/DIV
50µs/DIV
V
SW
= 12V
IN
600
V
V
= 12V
f
= 1MHz
IN
OUT
500
= 3.3V
–100 –50
0
50
100
150
200
Burst Mode OPERATION
TEMPERATURE (°C)
LOAD STEP FROM 100mA TO 1A
3622 G12
Oscillator Frequency
vs Supply Voltage
Reference Voltage
vs Temperature
RDS(ON) vs Input Voltage
600.5
600.0
599.5
599.0
598.5
598.0
597.5
597.0
600
500
400
300
200
100
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
PMOS CH1 R
DS(ON)
PMOS CH2 R
NMOS CH1 R
NMOS CH2 R
DS(ON)
DS(ON)
DS(ON)
–50 –30 –10 10 30 50 70 90 110 130 150
0
2
4
6
8
10 12 14 16 18
0
2
4
6
8
10 12 14 16 18
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3622 G14
3622 G13
3622 G15
RDS(ON) vs Temperature
Load Regulation
Line Regulation
0.5
0.4
5
700
600
500
400
300
200
100
PULSE SKIP
Burst Mode OPERATION
PMOS CHANNEL 1
PMOS CHANNEL 2
NMOS CHANNEL 1
NMOS CHANNEL 2
4
3
0.3
0.2
2
0.1
1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
–4
–5
V
I
SW
= 2.5V
V
V
= 12V
OUT
LOAD
IN
OUT
= 500mA
= 3.3V
f
= 1MHz
PULSE SKIPPING OPERATION
PULSE-SKIPPING OPERATION
12
INPUT VOLTAGE (V)
f
= 1MHz
SW
0
3
6
9
15
18
0
0.2
0.4
0.6
0.8
1.0
1.2
–50 –25
0
25 50 75 100 125 150
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3622 G18
3622 G17
3622 G16
3622fc
6
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.
VOUT vs Load Current
IQ vs Temperature
Switch Leakage vs Temperature
16
14
12
10
8
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
SLEEP
SHUTDOWN
NMOS1
NMOS2
PMOS1
PMOS2
5
4
3
2
1
0
6
4
2
I
I
= GND
= INTV
LIM
LIM
0
CC
0
–5000
–100 –50
0
50
100
150
200
0
0.5
1
1.5
2
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
LOAD CURRENT (A)
TEMPERATURE (°C)
3622 G19
3622 G21
3622 G20
Sync Mode Out-Of-Phase
Operation
ILIM vs Input Voltage
Out-Of-Phase Operation
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
EXTERNAL
CLOCK
SW1
10V/DIV
2V/DIV
SW1
10V/DIV
SW2
10V/DIV
SW2
10V/DIV
3622 G22
T
A
A
A
= 150°C
3622 G23
200ns/DIV
200ns/DIV
SYNC MODE OPERATION
EXTERNAL CLOCK PULSE WIDTH
CONTROLS PHASE SHIFT
V
V
= 12V
T
T
= 25°C
IN
OUT
= 2.5V, V
= 3.3V
L1 = 4.7µH, L2 = 3.3µH
= –45°C
OUT
0
3
6
9
12
15
18
OUT-OF-PHASE OPERATION
INPUT VOLTAGE (V)
3622 G24
3622fc
7
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
PIN FUNCTIONS (DFN/MSOP)
VIN1 (Pin 1/Pin 1): Input Voltage of Channel 1 Step-Down
Regulator. This input also powers the INTV LDO.
RUN2(Pin9/Pin10):LogicControlledRUNInputtoChan-
nel 2. Do not leave this pin floating. Logic high activates
the step-down regulator.
CC
PGOOD1 (Pin 2/Pin 3): Open Drain Power Good Indicator
for Channel 1.
FB2 (Pin 10/Pin 11): Feedback Input to the Error Amplifier
ofChannel2Step-DownRegulator.Connectresistordivider
tap to this pin. The output voltage can be adjusted from
MODE/SYNC(Pin3/Pin4):BurstModeSelectandExternal
Clock Synchronization of the Step-Down Regulator. Tie
0.6V to V by: V
= 0.6V • [1 + (R2/R1)]. (Figure 2) For
IN
OUT
MODE/SYNC to INTV for Burst Mode operation with a
CC
fixed V
options, connect the FB pin directly to V
.
OUT
OUT
400mA peak current clamp. Tie MODE/SYNC to GND for
pulse-skippingoperation.Furthermore,connectingthispin
to an external clock will synchronize the switch clock to
theexternalclockandputthepartinpulse-skippingmode.
INTV (Pin 11/Pin 12): Low Dropout Regulator. Bypass
CC
with a low ESR capacitor of at least 1µF to ground.
FB1 (Pin 12/Pin 13): Feedback Input to the Error Amplifier
ofChannel1Step-DownRegulator.Connectresistordivider
tap to this pin. The output voltage can be adjusted from
PHASE (Pin 4/Pin 5): Phase Select Pin. Tie this pin to
ground to run the regulators in phase (0° phase shift)
between SW rising edge of channel 1 and channel 2. Tie
0.6V to V by: V
= 0.6V • [1 + (R2/R1)]. (Figure 2) For
IN
OUT
this pin to INTV to set 180° phase shift between chan-
fixed V
options, connect the FB pin directly to V
.
CC
OUT
OUT
nels. When this pin is high, the phase shift may also be
set by modulating the duty cycle of external clock on the
MODE/SYNC pin (channel 1 edge synced to rising edge
of external clock, channel 2 edge synced to falling edge of
external clock). See Applications Section for more details.
RUN1 (Pin 13/Pin 14): Logic Controlled RUN Input to
Channel 1. Do not leave this pin floating. Logic high acti-
vates the step-down regulator.
SW1 (Pin 14/Pin 16): Switch Node Connection to the
Inductor of Channel 1 Step-Down Regulator.
PGOOD2 (Pin 5/Pin 6): Open Drain Power Good Indicator
for Channel 2.
GND(Pin15/Pin17):GroundforPowerandSignalGround.
The exposed pad must be connected to PCB ground for
rated electrical and rated thermal performance.
ILIM (Pin 6/Pin 7): Current Limit Select Pin. Tying this pin
togroundsetsthefullcurrentlimitforbothchannels.Tying
SV (NA/Pin 2): Signal V Pin. This input powers the
this pin to INTV drops the current limit by a factor of 2
IN
IN
CC
INTV . May be a different voltage than either V or
for both channels. Biasing this pin to 1V sets the current
on channel 1 to be the full amount, and the current on
channel 2 to be dropped by a factor of 2.
CC
IN1
V
. Connect SV to either V or V , whichever one
IN2
IN IN1 IN2
is higher. For applications where it is not known which V
IN
IN1
ishigher,connectexternaldiodebetweenSV tobothV
IN
VIN2 (Pin 7/Pin 8): Input Voltage of Channel 2 Step-Down
and V to ensure that SV is less than a diode drop from
IN2
IN
Regulator. May be a different voltage than V
.
IN1
the higher of V or V
.
IN1
IN2
SW2 (Pin 8/Pin 9): Switch Node Connection to the Induc-
tor of Channel 2 Step-Down Regulator.
3622fc
8
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BLOCK DIAGRAM
V
IN1
0.5ms
SOFT-START
SLOPE
COMPENSATION
ERROR
AMPLIFIER
+
+
–
BURST
COMPARATOR
0.6V
+
–
+
–
FB1
MAIN
I-COMPARATOR
FIXED V
OUT
V
–5V
IN
BUCK
LOGIC
AND
OVERCURRENT
COMPARATOR
SW1
GND
+
–
GATE DRIVE
INTV
CC
RUN1
PGOOD1
+
–
REVERSE
CURRENT
COMPARATOR
CHANNEL 1
CLK1
CLK2
MODE/SYNC
PHASE
I
LIM
CURRENT LIMIT
SELECT
OSCILLATOR
INTV
CC
LDO
SV (MSOP ONLY)
IN
CHANNEL 2
SAME AS CHANNEL 1
FB2
SW2
RUN2
PGOOD2
V
IN2
3622 BD
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OPERATION
The LTC3622 is a dual high efficiency monolithic step-
Low Current Operation
down regulator, which uses a constant frequency, peak
Twodiscontinuousconductionmodes(DCM)areavailable
to control the operation of the LTC3622 at low currents.
Both modes, Burst Mode operation and pulse-skipping
mode, automatically switch from continuous operation to
the selected mode when the load current is low.
current mode architecture. It operates through a wide V
IN
range and regulates with ultralow quiescent current. The
operation frequency is set at either 2.25MHz or 1MHz and
can be synchronized to an external oscillator 50% of the
inherent frequency. To suit a variety of applications, the
selectable MODE/SYNC pin allows the user to trade off
output ripple for efficiency.
To optimize efficiency, Burst Mode operation can be se-
lected by tying the MODE/SYNC pin to INTV . In Burst
Mode operation, the peak inductor current is set to be
at least 400mA, even if the output of the error amplifier
demands less. Thus, when the switcher is on at relatively
light output loads, FB voltage will rise and cause the I
voltagetodrop.OncetheI voltagedropslowenough,the
CC
For each channel, the output voltage is set by an external
dividerreturnedtotheFBpin. Anerroramplifiercompares
the divided output voltage with a reference voltage of
0.6V and adjusts the peak inductor current accordingly.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage is not within 7.5%
of the programmed value. The PGOOD output will go high
immediately after achieving regulation and will go low 32
clock cycles after falling out of regulation.
TH
TH
switchergoesintosleepmodewithbothpowerswitchesoff.
The switchers remain in this sleep state until the external
load pulls the output voltage below its regulation point.
When both channels are in sleep mode, the part draws an
ultralow 5µA of quiescent current from V .
IN
Main Control Loop
To minimize V
ripple, pulse-skipping mode can be
OUT
selected by grounding the MODE/SYNC pin. In LTC3622,
pulse-skipping mode is implemented similarly to Burst
Mode operation with the peak inductor current set to be
at above 66mA. This results in lower ripple than in Burst
Mode operation with the trade-off being slightly lower
efficiency.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
The inductor current is allowed to ramp up to a peak level.
Once the level is reached, the top power switch is turned
off and the bottom switch (N-channel MOSFET) is turned
on until the next clock cycle. The peak current level is con-
trolled by the internally compensated I voltage, which is
TH
High Duty Cycle/Dropout Operation
the output of the error amplifier. This amplifier compares
the FB voltage to the 0.6V internal reference. When the
load current increases, the FB voltage decreases slightly
below the reference, which causes the error amplifier to
Whentheinputsupplyvoltagedecreasestowardstheoutput
voltage, the duty cycle increases and slope compensation
is required to maintain the fixed switching frequency. The
LTC3622 has internal circuitry to accurately maintain the
increase the I voltage until the average inductor current
TH
peak current limit (I ) of 1.8A even at high duty cycles.
matches the new load current.
LIM
As the duty cycle approaches 100%, the LTC3622 enters
dropout operation. During dropout, the part will transition
in and out of sleep mode depending on the output load
current. This significantly reduces the quiescent current,
thus prolonging the use of the input supply.
The main control loop is shut down by pulling the RUN
pin to ground.
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OPERATION
V Overvoltage Protection
IN
Crosstalk can generally be avoided by carefully choosing
the phase shift such that the SW edges do not coincide.
However, there are often situations where this is unavoid-
able, such as when both channels are operating at near
50% duty cycle. In such cases, the optimized phase shift
can be set by modulating the duty cycle of external clock
on the MODE/SYNC pin (channel 1 edge synced to rising
edge of external clock, channel 2 edge synced to falling
edge of external clock), while keeping the PHASE pin volt-
age high. Figure 1 shows a 90° phase shifting between
two channels. Table 1 shows the phase selection by the
PHASE pin.
In order to protect the internal power MOSFET devices
against transient voltage events, the LTC3622 constantly
monitors the V and V pins for an overvoltage condi-
IN1
IN2
tion. When V or V rise above 18.5V, both regulators
IN1
IN2
suspend operation by shutting off both power MOSFETs.
Once V drops below 18.2V, the regulator immediately
IN
resumes normal operation. The regulators execute soft-
start when exiting an overvoltage condition.
Low Supply Operation
The LTC3622 incorporates undervoltage lockout circuits
which shut down the part when the input voltages drop
below 2.5V. As the input voltages rise slightly above the
undervoltage threshold, the switchers will begin basic op-
EXTERNAL
CLOCK
eration.However,theR
ofthetopandbottomswitch
DS(ON)
SW1
SW2
of each channel will be slightly higher than that specified
in the electrical characteristics due to lack of gate drive.
Refer to graph of R
versus V for more details.
IN
DS(ON)
Phase Selection
3622 F01
500ns/DIV
The two channels of LTC3622 can operate in phase, 180°
out-of-phase(anti-phase)dependingonthestateofPHASE
pin- low, or high, respectively. Anti-phase generally re-
duces input voltage and current ripple. Crosstalk between
switch nodes SW1, SW2 and components or sensitive
lines connected to FBx, can sometimes cause unstable
switching waveforms and unexpectedly large input and
output voltage ripple.
Figure 1. 90° Phase Shift Set by External Clock
Table 1. Phase Selection
NO EXTERNAL CLK EXTERNAL CLK
PHASE = 0
0° Phase Shift
0° Phase Shift
PHASE = INTV
180° Phase Shift
Phase Shift Determined by
Clock Edges
CC
The situation improves if rising and falling edges of the
switchnodesaretimedcarefullynottocoincide.Depending
on the duty cycle of the two channels, choose the phase
differencebetweenthechannelstokeepedgesasfaraway
from each other as possible.
Soft-Start
TheLTC3622hasa500µssoft-startrampforeachchannel
when enabled. During soft-start operation, the switchers
operate in pulse-skipping mode.
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APPLICATIONS INFORMATION
Output Voltage Programming
Note that ripple current ratings from capacitor manufac-
turers are often based on only 2000 hours of life which
makesitadvisabletofurtherderatethecapacitor,orchoose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance may be
needed to minimize transient effects during output load
changes.
For non-fixed output voltage parts, the output voltage is
set by external resistive dividers according to the follow-
ing equation:
R2
R1
VOUT = 0.6V • 1+
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 2.
For fixed V
parts, tie FB directly to V , as R2 and R1
OUT
Output Capacitor (C ) Selection
OUT
OUT
are matched internal resistors.
The selection of C
is determined by the effective series
OUT
V
OUT
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
R2
R1
C
FF
FB
LTC3622
the load transient response. The output ripple, ΔV , is
determined by:
OUT
GND
3622 F02
1
ΔVOUT < ΔI
+ESR
L
Figure 2. Setting the Output Voltage
8 • ƒ •C
OUT
Input Capacitor (C ) Selection
IN
Theoutputrippleishighestatmaximuminputvoltagesince
ΔI increaseswithinputvoltage.Multiplecapacitorsplaced
The input capacitance, C , is needed to filter the square
L
IN
inparallelmaybeneededtomeettheESRandRMScurrent
handlingrequirements.Drytantalum,specialpolymerand
hybridconductivepolymercapacitorsareverylowESRbut
havelowercapacitancedensitythanothertypes.Tantalum
capacitors have the highest capacitance density but it is
importance to only use types that have been surge tested
foruseinswitchingpowersupplies.Aluminumelectrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
CeramiccapacitorshaveexcellentlowESRcharacteristics
and small footprints.
wave current at the drain of the top power MOSFET. To
prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The RMS current calculation is different
if the part is used in in-phase or out-of-phase.
For "in phase", when V
= V
OUT2
OUT1
VOUT(V – V
)
IN
OUT
V
IN
This formula has a maximum at V = 2V . This simple
IN
OUT
worstcaseiscommonlyusedtodeterminethehighestI
.
RMS
Using Ceramic Input and Output Capacitors
Forout-of-phasecase, theripplecurrentcanbelowerthan
the "in phase" current. The maximum current typically oc-
Higher capacitance value, lower cost ceramic capacitors
are now becoming available in smaller case sizes. Their
high ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. However,
care must be taken when these capacitors are used at
the input and output. When a ceramic capacitor is used
curs when V
– V /2 = V
or when V
– V /2
OUT1
IN
OUT2
OUT2 IN
= V
. As a good rule of thumb, the amount of worst
OUT1
case ripple is about 75% of the worst case ripple in the
in-phasemode. AlsonotethatwhenV
=V
=V /2
OUT1
OUT2 IN
and I1 = I2, the input current ripple is at its minimum.
3622fc
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APPLICATIONS INFORMATION
at the input and the power is supplied by a wall adapter
Frequency Synchronization Capability
through long wires, a load step at the output can induce
The LTC3622 has the capability to synchronize to a 50%
range of the internal programmed frequency. It takes
several cycles of external clock to engage the sync mode,
and roughly 2μs for the part to detect the absence of the
external clock signal. Once engaged in sync, the LTC3622
immediately runs at the external clock frequency.
ringing at the V input. At best, this ringing can couple to
IN
the output and be mistaken as loop instability. At worst,
a sudden inrush of current through the long wires can
potentially cause a voltage spike at V large enough to
IN
damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
Inductor Selection
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. Typically, five cycles are required to
respond to a load step, but only in the first cycle does the
V
ƒ •L
VOUT
OUT
ΔIL=
1–
IN(MAX)
V
Lower ripple current reduces power losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
output voltage drop linearly. The output droop, V
, is
DROOP
usually about three times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
A reasonable starting point is to choose a ripple current
that is about 50% of I
current does not exceed a specified maximum, the induc-
tance should be chosen according to:
. To guarantee that ripple
OUT(MAX)
ΔIOUT
ƒO • VDROOP
COUT = 3
More capacitance may be required depending on the duty
cycle and load step requirements. In most applications,
the input capacitor is merely required to supply high
frequency bypassing, since the impedance to the supply
is very low. A 10µF ceramic capacitor is usually enough
for these conditions. Place this input capacitor as close
to the V and V pins as possible.
VOUT
ƒ • ΔIL(MAX)
VOUT
L =
1–
IN(MAX)
V
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency in-
creases, core loss decreases. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses increase.
IN1
IN2
Output Power Good
WhentheLTC3622’soutputvoltagesarewithinthe 7.5%
windowoftheregulationpoint,theoutputvoltagesaregood
andthePGOODpinsarepulledhighwithexternalresistors.
Otherwise, internal open-drain pull-down devices (275Ω)
willpullthePGOODpinslow.TopreventunwantedPGOOD
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
glitches during transients or dynamic V
changes, the
OUT
LTC3622’s PGOOD falling edge includes a blanking delay
of approximately 32 switching cycles.
3622fc
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APPLICATIONS INFORMATION
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Würth Elektronik. Refer to
Table 2 for more details.
Different core materials and shapes change the size/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
immediately shifts by an amount
OUT
equaltotheΔI
•ESR, whereESRistheeffectiveseries
LOAD
Table 2. Inductor Selection Table
INDUCTOR
INDUCTANCE
(μH)
DCR
(mΩ)
MAX CURRENT
(A)
DIMENSIONS
(mm)
HEIGHT
(mm)
MANUFACTURER
IHLP-1616BZ-11 Series
1.0
2.2
4.7
24
61
95
4.5
3.25
1.7
4.3 × 4.7
4.3 × 4.7
4.3 × 4.7
2
2
2
Vishay
www.vishay.com
IHLP-2020BZ-01 Series
FDV0620 Series
1
18.9
45.6
79.2
108
113
139
7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
2
2
2
2
2
2
2.2
3.3
4.7
5.6
6.8
4.2
3.3
2.8
2.5
2.4
1
18
37
51
68
5.7
4
3.2
2.8
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
2
2
2
2
Toko
www.toko.com
2.2
3.3
4.7
MPLC0525L Series
HCM0703 Series
1
16
24
40
6.4
5.2
4.1
6.2 × 5.4
6.2 × 5.4
6.2 × 5.4
2.5
2.5
2.5
NEC/Tokin
1.5
2.2
www.nec-tokin.com
1
9
11
9
7 × 7.4
7 × 7.4
7 × 7.4
7 × 7.4
7 × 7.4
3
3
3
3
3
Cooper Bussmann
www.cooperbussmann.com
1.5
2.2
3.3
4.7
14
18
28
37
8
6
5.5
RLF7030 Series
1
8.8
9.6
12
20
31
45
6.4
6.1
5.4
4.1
3.4
2.8
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
3.2
3.2
3.2
3.2
3.2
3.2
TDK
www.tdk.com
1.5
2.2
3.3
4.7
6.8
WE-TPC 4828 Series
1.2
1.8
2.2
2.7
3.3
3.9
4.7
17
20
23
27
30
47
52
3.1
2.7
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
Würth Elektronik
www.we-online.com
2.5
2.35
2.15
1.72
1.55
XFL4020 Series
1.0
1.5
2.2
3.3
4.7
10.8
14.4
21.35
34.8
52.2
8
4 × 4
4 × 4
4 × 4
4 × 4
4 × 4
2
2
2
2
2
Coilcraft
6.7
6.0
3.9
3.6
www.coilcraft.com
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14
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APPLICATIONS INFORMATION
2
resistance of C . ΔI
also begins to charge or dis-
1. I R losses are calculated from the DC resistances of the
internal switches, R , and external inductor, R . In
OUT
LOAD
chargeC generatingafeedbackerrorsignalusedbythe
OUT
SW
L
regulator to return V
to its steady state value. During
can be monitored for overshoot
continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R
cycle (DC) as follows:
OUT
this recovery time, V
OUT
or ringing that indicates a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. In addition, a feedforward capacitor can be added
toimprovethehighfrequencyresponse,showninFigure2.
and the duty
DS(ON)
R
=(R )(DC)+(R )(1 – DC)
DS(ON)TOP DS(ON)BOT
SW
The R
for both the top and bottom MOSFETs
DS(ON)
Capacitor C provides phase lead by creating a high fre-
FF
can be obtained from the Typical Performance Char-
quency zero with R2, which improves the phase margin.
2
acteristics curves. Thus to obtain I R losses:
Theoutputvoltagesettlingbehaviorisrelatedtothestabil-
ity of the closed-loop system and demonstrates the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
2
2
I R Losses = I
(R + R )
SW L
OUT
2. The switching current is the sum of the MOSFET driver
and control currents. The power MOSFET driver cur-
rentresultsfromswitchingthegatecapacitanceofthe
power MOSFETs. Each time a power MOSFET gate is
switched from low to high to low again, a packet of
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1µF) input capacitors.
Thedischargeinputcapacitorsareeffectivelyputinparallel
charge dQ moves from V to ground. The resulting
IN
dQ/dt is a current out of V that is typically much
IN
with C , causing a rapid drop in V . No regulator can
OUT
OUT
larger than the DC control bias current. In continuous
deliverenoughcurrenttopreventthisproblemiftheswitch
connectingtoloadhaslowresistanceandisdrivenquickly.
Thesolutionistolimittheturn-onspeedoftheloadswitch
driver. A Hot Swap controller is designed specifically for
this purpose and usually incorporates current limiting,
short-circuit protection and soft-starting.
mode, I
= f (Q + Q ), where Q and Q are
GATECHG OSC
T B T B
the gate charges of the internal top and bottom power
MOSFETs and f
power loss is thus:
is the switching frequency. The
OSC
Switching Loss = I
• V
GATECHG
IN
The gate charge loss is proportional to V and f
and thus their effects will be more pronounced at
higher supply voltages and higher frequencies.
IN
OSC
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account
for additional efficiency degradations in the overall
power system. It is very important to include these
“system”levellossesinthedesignofasystem.Transi-
tion loss arises from the brief amount of time the top
power MOSFET spends in the saturated region during
switch node transitions. The LTC3622 internal power
devicesswitchquicklyenoughthattheselosesarenot
significant compared to other sources. These losses
plus other losses, including diode conduction losses
during dead time and inductor core losses, generally
% Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2 etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
the circuit produce losses, three main sources usually
account for most of the losses in LTC3622 circuit: 1) I R
losses, 2) switching and biasing losses, 3) other losses.
2
account for less than 2% total additional loss.
3622fc
15
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
APPLICATIONS INFORMATION
Thermal Conditions
The active current through V at 2.25MHz without load
IN
is about 10mA, which includes switching and internal
biasing current loss, and transition loss. Therefore, the
total power dissipated by the part is:
In a majority of applications, the LTC3622 does not dis-
sipate much heat due to its high efficiency. However, in
applications where the LTC3622 is running at high ambi-
2
ent temperature, high V , high switching frequency, and
P = 2 • I
D
• R + V • I
IN IN(Q)
IN
OUT
SW
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
all power switches will be turned off until the temperature
drops about 15°C cooler.
2
= 2 • 1A • 183mΩ + 12V • 10mA
= 486mW
For the DFN package, the θ is 40°C/W. Therefore, the
JA
junction temperature of the regulator operating at 25°C
ambient temperature is approximately:
To prevent the LTC3622 from exceeding the maximum
junction temperature, the user needs to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T = 486mW • 40°C/W + 25°C = 44.4°C
J
Remembering that the above junction temperature is
obtained from an R
the junction temperature based on a higher R
it increases with temperature. Redoing the calculation
assuming that R increased 5% at 44.4°C yields a new
at 25°C, we might recalculate
DS(ON)
since
DS(ON)
T
RISE
= P • θ
D JA
SW
junction temperature of 45.4°C. If the application calls
for a higher ambient temperature and/or higher switching
frequency, care should be takentoreducethe temperature
rise of the part by using a heat sink or air flow.
As an example, consider the case when the LTC3622 is
used in applications where V = 12V, I = I = I
IN
= V
OUT OUT1 OUT2
= 1A, ƒ = 2.25MHz, V
= V
= 1.8V. The
OUT
OUT1
OUT2
equivalent power MOSFET resistance R is:
SW
VOUT
V
IN
VOUT
V
IN
RSW =RDS(ON)TOP
•
+RDS(ON)BOT • 1–
1.8V
1.8V
= 370mΩ •
+150mΩ • 1–
= 183mΩ
3622fc
16
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
APPLICATIONS INFORMATION
Board Layout Considerations
4. Solder the exposed pad (Pin 15 for DFN, Pin 17 for
MSOP) on the bottom of the package to the GND
plane. Connect this GND plane to other layers with
thermal vias to help dissipate heat from the LTC3622.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3622 (refer to Figure 3). Check the following in
the layout:
5. Keep sensitive components away from the SW pin. The
input capacitor, C , feedback resistors, and INTV
IN
CC
1. Do the capacitors C connect to the V and GND as
IN
IN
bypass capacitors should be routed away from the
close as possible? These capacitors provide the AC
SW trace and the inductor.
currenttotheinternalpowerMOSFETsandtheirdrivers.
Does C
connect to INTV as close as possible?
6. A ground plane is highly recommended.
VCC
CC
2. Are C
and L closely connected? The (–) plate of
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
OUT
C
returns current to GND and the (–) plate of C .
OUT
IN
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
and a ground line ter-
OUT
minated near GND. The feedback signal V should
FB
be routed away from noisy components and traces,
suchastheSWline,anditstraceshouldbeminimized.
Keep R1 and R2 close to the IC.
GND
V
VIAS TO
GROUND
PLANE
IN
C
OUT1
L1
C
IN
SW1
VIAS TO
GROUND
PLANE
SW2
C
IN
L2
C
OUT2
VIAS TO
GROUND
PLANE
V
IN
GND
36222 F03
Figure 3. Layout Diagram
3622fc
17
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
APPLICATIONS INFORMATION
Design Example
Using standard value of 3.3µH and 2.7µH for inductors
results in maximum ripple currents of:
As a design example, consider using the LTC3622 in an
application with the following specifications:
5V
5V
13.2V
ΔIL1 =
ΔIL2 =
1–
= 0.42A
= 0.41A
2.25MHz • 3.3µH
V
V
V
= V = 10.8V to 13.2V
IN1
IN1
= 5V
OUT1
OUT2
3.3V
3.3V
13.2V
= 3.3V
1–
2.25MHz • 2.7µH
I
I
I
f
= 1A
= 1A
= 0
OUT1(MAX)
OUT2(MAX)
OUT(MIN)
SW
C
will be selected based on the ESR that is required to
OUT
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22µF ceramic capacitor will be used.
= 2.25MHz
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
C should be sized for a maximum current rating of:
IN
Given the internal oscillator of 2.25MHz, we can calculate
the inductors value for about 40% ripple current at maxi-
5
13.2
13.2
5
IRMS1= 1A
– 1= 0.49A
– 1= 0.43A
mum V :
IN
5V
5V
13.2V
3.3
13.2
3.3
L1=
L2 =
1–
= 3.4µH
IRMS2 = 1A
2.25MHz • 0.4A
13.2
3.3V
3.3V
2.25MHz • 0.4A
Decoupling the V
and V
pins with 10µF ceramic
IN1
IN2
1–
= 2.75µH
13.2V
capacitors is adequate for most applications.
V
IN
V
V
INTV
CC
MODE/SYNC
IN1
IN2
17V MAX
C1
1µF
C
IN
RUN1
RUN2
10µF
PHASE
I
LIM
LTC3622-2
PGOOD1 PGOOD2
V
3.3µH
619k
2.7µH
V
3.3V
1A
OUT1
5V
1A
OUT2
SW2
FB2
SW2
FB2
22pF
619k
137k
22pF
C
C
OUT2
22µF
OUT1
22µF
GND
84.5k
3622 F04
Figure 4. 5V/3.3V VOUT Burst Mode Operation Application
3622fc
18
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL APPLICATIONS
5V/3.3V VOUT, Burst Mode Operation, In-Phase Switching
V
IN
V
V
INTV
CC
MODE/SYNC
IN1
IN2
17V MAX
C1
1µF
C
IN
RUN1
RUN2
10µF
PHASE
I
LIM
LTC3622-2
PGOOD1 PGOOD2
V
6.8µH
619k
3.3µH
V
3.3V
1A
OUT1
5V
1A
OUT2
SW1
FB1
SW2
FB2
22pF
619k
137k
22pF
C
C
OUT2
22µF
OUT1
22µF
GND
84.5k
3622 TA02
Efficiency vs Load
Load Step Waveform
100
90
80
70
60
50
40
30
20
10
0
I
L
500mA/DIV
V
OUT
AC-COUPLED
200mV/DIV
V
V
= 5V
OUT
OUT
= 3.3V
3622 TA02b
V
f
= 12V
= 2.25MHz
Burst Mode OPERATION
0.001 0.01
LOAD CURRENT (A)
IN
SW
40µs/DIV
V
V
= 12V
OUT1
LOAD
IN
= 5V
I
= 5mA → 500mA
Burst Mode OPERATION
0.0001
0.1
1
f
= 2.25MHz
SW
3622 TA02a
3622fc
19
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL APPLICATIONS
Dual Output Regulators from Multiple Input Sources
1µF
SV
IN
V
IN2
V
IN1
V
V
IN2
RUN2
IN1
5V
12V
RUN1
C
C
IN2
10µF
IN1
10µF
LTC3622
INTV
CC
MODE/SYNC
C1
1µF
PHASE
I
LIM
PGOOD1
SW1
PGOOD2
SW2
V
3.3µH
1µH
V
3.3V
1A
OUT1
5V
1A
OUT2
22pF
604k
604k
22pF
C
C
OUT2
22µF
OUT1
FB1
FB2
GND
22µF
134k
82.5k
3622 TA06
3622fc
20
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3622#packaging for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ±0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ±0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3622fc
21
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3622#packaging for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3622fc
22
For more information www.linear.com/LTC3622
LTC3622/
LTC3622-2/LTC3622-23/5
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
03/15 Added LTC3622-23/5 Options in Header.
Added LTC3622-23/5 to Options Table.
Added LTC3622-23/5 to Electrical Characteristics.
Added MSOP-16E Package Options.
Added H-Grade Options.
All
1
3
1, 2, 3, 22
2, 3, 4
Clarified Pin Functions.
8
14
17
2
Clarified Table 2.
Added MSOP-16E in #4.
B
C
8/15
6/16
Clarified package description to MSE.
Clarified Package Description to MSE, 16-Lead MSOP, exposed die pad.
Changed ABS Max Rating of RUN1 and RUN2 pins.
22
2
3622fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC3622/
LTC3622-2/LTC3622-23/5
TYPICAL APPLICATION
5V/3.3V Series Output, Burst Mode Operation
V
IN
V
INTV
CC
MODE/SYNC
5V TO 17V
IN1
C
IN
C1
1µF
RUN1
RUN2
10µF
PHASE
I
V
IN2
LIM
LTC3622-2
10k
INTV
PGOOD1 PGOOD2
CC
V
3.3µH
1µH
V
3.3V
1A
OUT1
5V
1A
OUT2
SW1
FB1
SW2
FB2
22pF
604k
604k
134k
22pF
C
C
OUT2
22µF
OUT1
22µF
GND
82.5k
3622 TA03
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3621/
LTC3621-2
1A, 17V, 1/2.25MHz, Synchronous Step-Down Regulator 95% Efficiency, V : 2.7V to 17V, V
= 0.6V, I = 3.5µA, I < 1µA,
OUT(MIN) Q SD
IN
2mm × 3mm DFN-6, MSOP-8E
LTC3600
LTC3601
LTC3603
LTC3633A
LTC3605A
LTC3604
1.5A, 15V, 4MHz Synchronous Rail-to-Rail Single
Resistor Step-Down Regulator
95% Efficiency, V : 4V to 15V, V
= 0V, I = 700µA, I < 1µA,
OUT(MIN) Q SD
IN
3mm × 3mm DFN-12, MSOP-12E Packages
15V, 1.5A (I ) 4MHz Synchronous Step-Down
95% Efficiency, V : 4.5V to 15V, V
= 0.6V, I = 300µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converter
4mm × 4mm QFN-20, MSOP-16E Packages
15V, 2.5A (I ) 3MHz Synchronous Step-Down
95% Efficiency, V : 4.5V to 15V, V
= 0.6V, I = 75µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converter
4mm × 4mm QFN-20, MSOP-16E Packages
20V, Dual 3A (I ) 4MHz Synchronous Step-Down
95% Efficiency, V : 3.6V to 20V, V
= 0.6V, I = 500µA, I < 15µA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converter
4mm × 5mm QFN-28, TSSOP-28E Packages. A Version Up to 20V
IN
20V, 5A (I ) 4MHz Synchronous Step-Down
95% Efficiency, V : 4V to 20V, V
= 0.6V, I = 2mA, I < 15µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
4mm × 4mm QFN-24 Package. A Version Up to 20V
IN
15V, 2.5A (I ) 4MHz Synchronous Step-Down
95% Efficiency, V : 3.6V to 15V, V
= 0.6V, I = 300µA, I < 14µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
3mm × 3mm QFN-16, MSOP-16E Packages
LTC3624/
LTC3624-2
2A, 17V, 1MHz/2.25MHz Synchronous Step-Down
Regulator
95% Efficiency, V : 2.7V to 17V, V
= 0.6V, I = 3.5µA, I < 1µA,
OUT(MIN) Q SD
IN
3mm × 3mm DFN-8 Package
3622fc
LT 0616 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 2014
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3622
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