LTC3703-5 [Linear]
60V Synchronous Switching Regulator Controller; 60V同步开关稳压控制器
| 型号： | LTC3703-5 |
| 厂家： | 
Linear |
| 描述： | 60V Synchronous Switching Regulator Controller |
| 文件： | 总32页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3703-5
60V Synchronous
Switching Regulator Controller
U
FEATURES
DESCRIPTIO
The LTC®3703-5 is a synchronous step-down switching
regulator controller that can directly step-down voltages
fromupto60V,makingitidealfortelecomandautomotive
applications. The LTC3703-5 drives external logic level
N-channel MOSFETs using a constant frequency (up to
■
High Voltage Operation: Up to 60V
■
Large 1
Ω Gate Drivers (with 5V Supply)
■
■
■
■
■
No Current Sense Resistor Required
Step-Up or Step-Down DC/DC Converter
Dual N-Channel MOSFET Synchronous Drive
Excellent Transient Response and DC Line Regulation
Programmable Constant Frequency: 100kHz to
600kHz
600kHz), voltage mode architecture.
A precise internal reference provides 1% DC accuracy. A
high bandwidth error amplifier and patented* line feed
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703-5 to drive multiple MOSFETs for higher current
applications. The operating frequency is user program-
mable from 100kHz to 600kHz and can also be synchro-
nized to an external clock for noise-sensitive applications.
Current limit is programmable with an external resistor
and utilizes the voltage drop across the synchronous
MOSFET to eliminate the need for a current sense resistor.
For applications requiring up to 100V operation, refer to
the LTC3703 data sheet.
■
■
■
■
■
■
■
■
±1% Reference Accuracy
Synchronizable up to 600kHz
Selectable Pulse Skip Mode Operation
Low Shutdown Current: 25µA Typ
Programmable Current Limit
Undervoltage Lockout
Programmable Soft-Start
16-Pin Narrow SUSOP and 28-Pin SSOP Packages
APPLICATIO S
■
48V Telecom and Base Station Power Supplies
Networking Equipment, Servers
Automotive and Industrial Control
■
PARAMETER
LTC3703-5
LTC3703
■
Maximum V
60V
100V
IN
, LTC and LT are registered trademarks of Linear Technology Corporation.
*U.S. Patent Numbers: 5408150, 5055767, 6677210, 5847554, 5481178, 6304066, 6580258;
Others Pending.
MOSFET Gate Drive
4.5V to 15V
3.7V
9.3V to 15V
8.7V
+
V
V
UV
CC
CC
–
UV
3.1V
6.2V
U
TYPICAL APPLICATIO
High Efficiency High Voltage Step-Down Converter
V
CC
5V
Efficiency vs Load Current
+
V
IN
100
95
90
85
80
22µF
6V TO 60V
MMDL770T1
MODE/SYNC
V
IN
V
IN
= 12V
+
V
IN
= 24V
22µF
×2
30k
FSET
BOOST
TG
Si7850DP
10k
COMP
V
IN
= 42V
0.1µF
1000pF
LTC3703-5
470pF
12k
8µH
FB
I
SW
V
5V
5A
OUT
21.5k
1%
V
MAX
CC
10Ω
+
270µF
16V
INV
DRV
CC
Si7850DP
0.1µF
RUN/SS
GND
BG
D1
MBR1100
10µF
0
1
2
3
4
5
100Ω
113k
1%
BGRTN
LOAD CURRENT (A)
1µF
37053 TA04b
2200pF
37035 TA04
37035f
1
LTC3703-5
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltages
MODE/SYNC, INV Voltages....................... –0.3V to 15V
VCC, DRVCC .......................................... –0.3V to 15V
(DRVCC – BGRTN), (BOOST – SW) ...... –0.3V to 15V
BOOST (Continuous) ............................ –0.3V to 85V
BOOST (400ms) ................................... –0.3V to 95V
BGRTN ...................................................... –5V to 0V
VIN Voltage (Continuous).......................... –0.3V to 70V
VIN Voltage (400ms) ................................. –0.3V to 80V
SW Voltage (Continuous) ............................ –1V to 70V
SW Voltage (400ms) ................................... –1V to 80V
Run/SS Voltage .......................................... –0.3V to 5V
fSET, FB, IMAX, COMP Voltages ................... –0.3V to 3V
Driver Outputs
TG ................................ SW – 0.3V to BOOST + 0.3V
BG ........................... BGRTN – 0.3V to DRVCC + 0.3V
Peak Output Current <10µs BG,TG ............................ 5A
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Notes 3, 7) ....................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
V
1
2
28 BOOST
27 TG
IN
NC
TOP VIEW
NC
NC
3
26 SW
25 NC
24 NC
23 NC
22 NC
LTC3703EGN-5
LTC3703EG-5
MODE/SYNC
1
2
3
4
5
6
7
8
16
V
IN
4
f
15 B00ST
SET
NC
5
COMP
FB
14
13
12
11
10
9
TG
MODE/SYNC
6
f
7
SW
SET
COMP
FB
8
21
V
CC
I
V
CC
MAX
9
20 DRV
19 BG
18 NC
17 NC
16 NC
CC
INV
RUN/SS
GND
DRV
BG
CC
GN PART
MARKING
I
10
11
12
13
14
MAX
INV
NC
BGRTN
37035
RUN/SS
GND
GN PACKAGE
15 BGRTN
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 5V, VMODE/SYNC = VINV = VSW
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
15
60
2.5
40
5
UNITS
V
V
V
, DRV
CC
IN
V
V
V
, DRV Supply Voltage
●
●
●
4.1
CC
CC
IN
CC
Pin Voltage
V
I
I
I
Supply Current
V = 0V
FB
1.7
25
0
mA
µA
CC
CC
RUN/SS = 0V
(Note 5)
DRV Supply Current
µA
DRVCC
BOOST
CC
RUN/SS = 0V
0
5
µA
BOOST Supply Current
(Note 5)
RUN/SS = 0V
●
360
0
500
5
µA
µA
37035f
2
LTC3703-5
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 5V, VMODE/SYNC = VINV = VSW
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
Feedback Voltage
(Note 4)
0.792
0.788
0.800
0.808
0.812
V
V
FB
●
●
●
∆V
∆V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
MODE/SYNC Threshold
MODE/SYNC Hysteresis
MODE/SYNC Current
5V < V < 15V (Note 4)
0.007
0.01
0.8
20
0.05
0.1
%/V
%
FB, LINE
CC
1V < V
< 2V (Note 4)
FB, LOAD
COMP
VMODE/SYNC
∆VMODE/SYNC
IMODE/SYNC
MODE/SYNC Rising
0.75
1
0.87
V
mV
µA
V
0 ≤ V ≤ 15V
0
1
2
1
MODE/SYNC
V
Invert Threshold
1.5
0
INV
INV
VIN
I
I
Invert Current
0 ≤ V ≤ 15V
µA
INV
V
Sense Input Current
V
= 60V
IN
80
0
130
1
µA
µA
IN
RUN/SS = 0V, V = 10V
IN
I
I
Source Current
V = 0V
IMAX
10.5
–25
0.7
2.3
9
12
10
13.5
55
µA
mV
V
MAX
MAX
V
V
V
Offset Voltage
|V | – V
at I
= 0µA
RUN/SS
OS, IMAX
RUN/SS
IMAX
SW
IMAX
Shutdown Threshold
0.9
3.8
17
1.2
5.3
25
I
RUN/SS Source Current
Maximum RUN/SS Sink Current
Undervoltage Lockout
RUN/SS = 0V
|V | – V
µA
µA
RUN/SS
> 100mV
IMAX
SW
V
V
V
Rising
●
●
●
3.4
2.8
0.45
3.7
3.1
0.65
4.1
3.4
0.85
V
V
V
UV
CC
CC
Falling
Hysteresis
Oscillator
f
f
t
Oscillator Frequency
R
= 25kΩ
270
100
300
330
600
kHz
kHz
ns
OSC
SET
External Sync Frequency Range
Minimum On-Time
SYNC
ON, MIN
200
93
DC
Maximum Duty Cycle
f < 200kHz
89
96
%
MAX
Driver
I
BG Driver Peak Source Current
0.75
0.75
1
A
Ω
A
BG, PEAK
R
BG Driver Pull-Down R
(Note 8)
(Note 8)
(Note 4)
1.2
1
1.8
1.8
BG, SINK
TG, PEAK
DS, ON
I
TG Driver Peak Source Current
TG Driver Pull-Down R
R
1.2
Ω
TG, SINK
DS, ON
Feedback Amplifier
A
Op Amp DC Open Loop Gain
74
85
25
0
dB
MHz
µA
VOL
f
I
I
Op Amp Unity Gain Crossover Frequency (Note 6)
U
FB Input Current
0 ≤ V ≤ 3V
1
FB
FB
COMP Sink/Source Current
±5
±10
mA
COMP
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(Q • f ).
G
OSC
Note 2: The LTC3703-5 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
LTC3703-5: T = T + (P • 100 °C/W) G Package
J
A
D
Note 8: R
guaranteed by correlation to wafer level measurement.
DS(ON)
Note 4: The LTC3703-5 is tested in a feedback loop that servos V to the
FB
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
37035f
3
LTC3703-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C (unless otherwise noted).
Load Transient Response
Efficiency vs Input Voltage
Efficiency vs Load Current
100
95
90
85
80
100
95
V
= 24V
= 42V
IN
V
OUT
50mV/DIV
V
IN
I
= 1A
OUT
I
= 5A
OUT
90
I
OUT
2A/DIV
85
V
OUT
= 5V
V
OUT
= 12V
50µs/DIV
V
V
= 50V
IN
OUT
f = 250kHz
FORCED CONTINUOUS
f = 250kHz
PULSE SKIP ENABLED
= 12V
1A TO 5A LOAD STEP
37035 G03
80
0
10
20
30
40
50
60
0
1
2
3
4
5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
37035 G01
37035 G02
VCC Shutdown Current vs VCC
Voltage
V
CC Current vs VCC Voltage
VCC Current vs Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
120
100
80
60
40
20
0
V
RISING
CC
COMP = 1.5V
COMP = 1.5V
3
2
1
0
V
FB
= 0V
V
FB
= 0V
20 40
TEMPERATURE (°C)
80
10 12
VOLTAGE (V)
–60 –40 –20
0
100
0
2
4
6
8
14 16
2.5
5
10
7.5
VOLTAGE (V)
12.5
15
60
0
V
V
CC
CC
37035 G05
37035 G06
37035 G04
Normalized Frequency
vs Temperature
VCC Shutdown Current
vs Temperature
Reference Voltage
vs Temperature
0.803
0.802
0.801
0.800
0.799
0.798
35
30
25
20
15
10
5
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
V
CC
= 5V
0
20 40
TEMPERATURE (°C)
80
20 40
–60 –40 –20
TEMPERATURE (°C)
80
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
100
0
100
60
60
TEMPERATURE (°C)
37035 G08
37035 G07
37035 G09
37035f
4
LTC3703-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Driver Pull-Down RDS(ON)
vs Temperature
Driver Peak Source Current
vs Temperature
Driver Peak Source Current
vs Supply Voltage
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.1
1.0
0.9
0.8
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
V
= 5V
CC
CC
0
2.5
5
7.5
10
12.5
15
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
20 40 60 80 100
DRV /BOOST VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
37035 G10
37035 G12
37035 G11
Rise/Fall Time
vs Gate Capacitance
RUN/SS Pull-Up Current
vs Temperature
Driver Pull-Down RDS(ON)
vs Supply Voltage
200
150
100
50
1.3
1.2
5
4
3
2
1
0
V
= 5V
V
= 5V
CC
CC
1.1
1.0
0.9
0.8
0.7
0.6
RISE TIME
FALL TIME
0
5
7.5
10
15
0
10
15
20
–60
20
TEMPERATURE (°C)
60 80
2.5
12.5
–40 –20
0
40
100
5
DRV /BOOST VOLTAGE (V)
GATE CAPACITANCE (nF)
CC
15735 G15
37035 G13
37035 G14
RUN/SS Pull-Up Current
vs VCC Voltage
RUN/SS Sink Current
vs SW Voltage
Max % DC vs RUN/SS Voltage
5
4
3
2
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
I
= 0.3V
MAX
0
1
0
–5
–10
–10
0.4
0.2 0.3
|SW| VOLTAGE (V)
0.6 0.7
0
5
7.5
10
12.5
15
0
0.1
0.5
2.5
0.5
1.0
1.5
2.0
2.5
3.0
V
CC
VOLTAGE (V)
RUN VOLTAGE (V)
37035 G16
37035 G17
37035 G18
37035f
5
LTC3703-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Max % DC vs Frequency and
Temperature
IMAX Current vs Temperature
% Duty Cycle vs COMP Voltage
100
80
60
40
20
0
13
12
11
100
95
90
85
80
75
70
V
= 10V
IN
V
= 50V
IN
–45°C
V
= 25V
IN
25°C
90°C
0.5
1.00 1.25 1.50
COMP (V)
1.75 2.00
0
100 200 300 400 500 600 700
FREQUENCY (kHz)
0.75
–60 –40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
37035 G20
37035 G21
37035 G19
Shutdown Threshold vs
Temperature
tON(MIN) vs Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
160
140
120
100
80
60
40
20
0
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
37035 G22
37035 G23
37035f
6
LTC3703-5
U
U
U
PI FU CTIO S
(GN16/G28)
MODE/SYNC(Pin 1/Pin 6): Pulse Skip Mode Enable/Sync
Pin. This multifunction pin provides Pulse Skip Mode en-
able/disablecontrolandanexternalclockinputforsynchro-
nizationoftheinternaloscillator.Pullingthispinbelow0.8V
ortoanexternallogic-levelsynchronizationsignaldisables
Pulse Skip Mode operation and forces continuous opera-
tion. Pulling the pin above 0.8V enables Pulse Skip Mode
operation. This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
GND (Pin 8/Pin 14): Ground Pin.
BGRTN (Pin 9/Pin 15): Bottom Gate Return. This pin con-
nects to the source of the pull-down MOSFET in the BG
driver and is normally connected to ground. Connecting a
negative supply to this pin allows the synchronous
MOSFET’s gate to be pulled below ground to help prevent
falseturn-onduringhighdV/dttransitionsontheSWnode.
See the Applications Information section for more details.
BG (Pin 10/Pin 19): Bottom Gate Drive. The BG pin drives
the gate of the bottom N-channel synchronous switch
MOSFET. This pin swings from BGRTN to DRVCC.
f
SET (Pin 2/Pin 7): Frequency Set. A resistor connected to
this pin sets the free running frequency of the internal os-
cillator. See applications section for resistor value selec-
tion details.
DRVCC (Pin 11/Pin 20): Driver Power Supply Pin. DRVCC
provides power to the BG output driver. This pin should be
connected to a voltage high enough to fully turn on the
external MOSFETs, normally 4.5V to 15V for logic level
thresholdMOSFETs.DRVCC shouldbebypassedtoBGRTN
with a 10µF, low ESR (X5R or better) ceramic capacitor.
COMP (Pin 3/Pin 8): Loop Compensation. This pin is con-
nected directly to the output of the internal error amplifier.
An RC network is used at the COMP pin to compensate the
feedback loop for optimal transient response.
V
CC (Pin 12/Pin 21) :Main Supply Pin. All internal circuits
FB (Pin 4/Pin 9): Feedback Input. Connect FB through a
resistor divider network to VOUT to set the output voltage.
Also connect the loop compensation network from COMP
to FB.
except the output drivers are powered from this pin. VCC
should be connected to a low noise power supply voltage
between 4.5V and 15V and should be bypassed to GND
(Pin 8) with at least a 0.1µF capacitor in close proximity to
the LTC3703-5.
IMAX (Pin 5/Pin 10): Current Limit Set. The IMAX pin sets
the current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
voltage at IMAX, the controller goes into current limit. The
IMAX pin has an internal 12µA current source, allowing the
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section for
SW (Pin 13/Pin 26): Switch Node Connection to Inductor
and Bootstrap Capacitor. Voltage swing at this pin is from
a Schottky diode (external) voltage drop below ground to
VIN.
TG (Pin 14/Pin 27): Top Gate Drive. The TG pin drives the
gateofthetopN-channelsynchronousswitchMOSFET.The
TG driver draws power from the BOOST pin and returns to
theSWpin,providingtruefloatingdrivetothetopMOSFET.
more information on choosing RIMAX
.
INV(Pin6/Pin11):Top/BottomGateInvert.Pullingthispin
above 2V sets the controller to operate in step-up (boost)
modewiththeTGoutputdrivingthesynchronousMOSFET
and the BG output driving the main switch. Below 1V, the
controller will operate in step-down (buck) mode.
BOOST(Pin15/Pin28):TopGateDriverSupply.TheBOOST
pinsuppliespowertothefloatingTGdriver.TheBOOSTpin
should be bypassed to SW with a low ESR (X5R or better)
0.1µFceramiccapacitor.AnadditionalfastrecoverySchot-
tkydiodefromDRVCCtoBOOSTwillcreateacompletefloat-
ing charge-pumped supply at BOOST.
RUN/SS(Pin7/Pin13):Run/Soft-Start.PullingRUN/SSbe-
low0.9VwillshutdowntheLTC3703-5,turnoffbothofthe
external MOSFET switches and reduce the quiescent sup-
ply current to 25µA. A capacitor from RUN/SS to ground
will control the turn-on time and rate of rise of the output
voltage at power-up. An internal 4µA current source pull-
upattheRUN/SSpinsetstheturn-ontimeatapproximately
750ms/µF.
VIN (Pin16/Pin1):InputVoltageSensePin.Thispiniscon-
nectedtothehighvoltageinputoftheregulatorandisused
by the internal feedforward compensation circuitry to im-
prove line regulation. This is not a supply pin.
37035f
7
LTC3703-5
U
U
W
FU CTIO AL DIAGRA
RSET
FSET
2
OVERCURRENT
12µA
4µA
I
MAX
–
+
5
R
MAX
50mV
–
+
±
RUN/SS
–
+
5
1
±
INV
CHIP
SD
C
SS
1V
3.2V
UVSD OTSD
V
CC
EXT SYNC
+
SYNC
DETECT
OSC
MODE/SYNC
COMP
–
D
B
BOOST
TG
V
IN
REVERSE
CURRENT
FORCED CONTINUOUS
INV
15
14
13
C
B
M1
3
4
SW
–
DRIVE
LOGIC
PWM
+
+
–
0.8V
% DC
LIMIT
+
FB
DRV
CC
÷
FB
11
10
BG
V
IN
16
M2
R1
R2
MIN
MAX
–
–
+
+
BGRTN
9
6
INV
0.84V
0.76V
V
CC
(<15V)
12
L1
OVER
TEMP
V
OUT
GND
8
BANDGAP
V
CC
UVLO
C
OUT
OT SD
0.8V
REFERENCE
INTERNAL
3.2V V
UV SD
CC
GN16
V
CC
C
VCC
37035 FD
U
(Refer to Functional Diagram)
OPERATIO
The LTC3703-5 is a constant frequency, voltage mode
controller for DC/DC step-down converters. It is designed
to be used in a synchronous switching architecture with
two external N-channel MOSFETs. Its high operating volt-
agecapabilityallowsittodirectlystepdowninputvoltages
up to 60V without the need for a step-down transformer.
For circuit operation, please refer to the Functional
Diagram of the IC and the circuit on the first page of this
data sheet. The LTC3703-5 uses voltage mode control in
which the duty ratio is controlled directly by the error
amplifier output and thus requires no current sense resis-
tor. The VFB pin receives the output voltage feedback and
is compared to the internal 0.8V reference by the error
amplifier, which outputs an error signal at the COMP pin.
37035f
8
LTC3703-5
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OPERATIO
(Refer to Functional Diagram)
When the load current increases, it causes a drop in the
feedback voltage relative to the reference. The COMP volt-
age then rises, increasing the duty ratio until the output
feedback voltage again matches the reference voltage. In
normal operation, the top MOSFET is turned on when the
RS latch is set by the on-chip oscillator and is turned off
when the PWM comparator trips and resets the latch. The
PWMcomparatortripsattheproperdutyratiobycompar-
ing the error amplifier output (after being “compensated”
bythelinefeedforwardmultiplier)toasawtoothwaveform
generatedbytheoscillator.WhenthetopMOSFETisturned
off, the bottom MOSFET is turned on until the next cycle
begins or, if Pulse Skip Mode operation is enabled, until
theinductorcurrentreversesasdeterminedbythereverse
current comparator. MAX and MIN comparators ensure
that the output never exceed ±5% of nominal value by
monitoringVFB andforcingtheoutputbackintoregulation
quickly by either keeping the top MOSFET off or forcing
maximumdutycycle.Theoperationofitsotherfeatures—
fasttransientresponse,outstandinglineregulation,strong
gate drivers, short-circuit protection, and shutdown/
soft-start—are described below.
V
OUT
50mV/DIV
V
IN
20V/DIV
I
L
2A/DIV
37035 F01
V
LOAD
25V TO 60V V STEP
= 12V
= 1A
20µs/DIV
OUT
I
IN
Figure 1. Line Transient Performance
Strong Gate Drivers
The LTC3703-5 contains very low impedance drivers
capableofsupplyingampsofcurrenttoslewlargeMOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
60V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET (see
Figure 2). They can be powered from either a separate DC
supply or a voltage derived from the input or output
voltage (see MOSFET Driver Supplies section). The bot-
tom side driver is supplied directly from the DRVCC pin.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which normally is recharged during
eachoffcyclethroughanexternaldiodefromDRVCC when
the top MOSFET turns off. In Pulse Skip Mode operation,
where it is possible that the bottom MOSFET will be off for
anextendedperiodoftime, aninternalcounterguarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703-5
shut down unless this voltage is above 4.1V.
Fast Transient Response
The LTC3703-5 uses a fast 25MHz op amp as an error am-
plifier. This allows the compensation network to be opti-
mized for better load transient response. The high
bandwidth of the amplifier, along with high switching fre-
quencies and low value inductors, allow very high loop
crossoverfrequencies.The800mVinternalreferenceallows
regulated output voltages as low as 800mV without exter-
nal level shifting amplifiers.
Line Feedforward Compensation
The LTC3703-5 achieves outstanding line transient re-
sponse using a patented feedforward correction scheme.
With this circuit the duty cycle is adjusted instantaneously
to changes in input voltage, thereby avoiding unaccept-
able overshoot or undershoot. It has the added advantage
of making the DC loop gain independent of input voltage.
Figure 1 shows how large transient steps at the input have
little effect on the output voltage.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Millercapacitance, evenwhenthebottomdriverisholding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-thru between the top side and bottom side
37035f
9
LTC3703-5
U
OPERATIO
(Refer to Functional Diagram)
cycle control set to 0%. As CSS continues to charge, the
duty cycle is gradually increased, allowing the output
voltagetorise.Thissoft-startschemesmoothlyrampsthe
output voltage to its regulated value, with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
isenabledandtheLTC3703-5isinfulloperation.Whenthe
RUN/SS is low, the supply current is reduced to 25µA.
MOSFETs can occur. To prevent this from occuring, the
bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
theeffectoftheMillerpull-up.Forexample,ifa–2Vsupply
is used on BGRTN, the switch node dV/dt could pull the
gateup2VbeforetheVGS ofthebottomMOSFEThasmore
than 0V across it.
V
DRV
IN
CC
D
+
B
DRV
CC
LTC3703-5
V
OUT
BOOST
TG
C
IN
C
B
M1
0V
NORMAL OPERATION
SW
SHUTDOWN START-UP
CURRENT
LIMIT
L
V
OUT
MIN COMPARATOR ENABLED
4V
3V
BG
+
OUTPUT VOLTAGE
IN REGULATION
M2
C
OUT
BGRTN
0V TO –5V
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
V
RUN/SS
37035 F02
1.4V
1V
Figure 2. Floating TG Driver Supply and Negative BG Return
MINIMUM
DUTY CYCLE
0V
LTC3703-5 POWER
ENABLE DOWN MODE
Constant Frequency
37035 F03
The internal oscillator can be programmed with an exter-
nalresistorconnectedfromfSET togroundtorun between
100kHz and 600kHz, thereby optimizing component size,
efficiency, and noise for the specific application. The
internal oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin and can lock to a
frequency in the 100kHz to 600kHz range. When locked to
an external clock, Pulse Skip Mode operation is automati-
callydisabled. Constantfrequencyoperationbringswithit
anumberofbenefits:Inductorandcapacitorvaluescanbe
chosenforapreciseoperatingfrequencyandthefeedback
loop can be similarly tightly specified. Noise generated by
the circuit will always be at known frequencies.
Subharmonic oscillation and slope compensation, com-
mon headaches with constant frequency current mode
switchers, are absent in voltage mode designs like the
LTC3703-5.
Figure 3. Soft-Start Operation in Start Up and Current Limit
Current Limit
The LTC3703-5 includes an onboard current limit circuit
that limits the maximum output current to a user-pro-
grammedlevel.Itworksbysensingthevoltagedropacross
the bottom MOSFET and comparing that voltage to a user-
programmed voltage at the IMAX pin. Since the bottom
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowinginit. Inabuckconverter, theaveragecurrentinthe
inductor is equal to the output current. This current also
flows through the bottom MOSFET during its on-time.
Thus by watching the drain-to-source voltage when the
bottom MOSFET is on, the LTC3703-5 can monitor the
output current. The LTC3703-5 senses this voltage and
inverts it to allow it to compare the sensed voltage (which
becomes more negative as peak current increases) with a
positive voltage at the IMAX pin. The IMAX pin includes a
12µA pull-up, enabling the user to set the voltage at IMAX
with a single resistor (RIMAX) to ground. See the Current
Shutdown/Soft-Start
The main control loop is shut down by pulling RUN/SS pin
low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor CSS. When CSS
reaches 1V, the main control loop is enabled with the duty
Limit Programming section for RIMAX selection.
37035f
10
LTC3703-5
U
OPERATIO
(Refer to Functional Diagram)
For maximum protection, the LTC3703-5 current limit
consists of a steady-state limit circuit and an instanta-
neous limit circuit. The steady-state limit circuit is a gm
amplifier that pulls a current from the RUN/SS pin propor-
tional to the difference between the SW and IMAX voltages.
This current begins to discharge the capacitor at RUN/SS,
reducing the duty cycle and controlling the output voltage
until the current regulates at the limit. Depending on the
size of the capacitor, it may take many cycles to discharge
the RUN/SS voltage enough to properly regulate the
output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
until the gm amplifier gains control.
skip cycles to maintain regulation. The frequency drops
but this further improves efficiency by minimizing gate
charge losses. In forced continuous mode, the bottom
MOSFET is always on when the top MOSFET is off,
allowing the inductor current to reverse at low currents.
This mode is less efficient due to resistive losses, but has
theadvantageofbettertransientresponseatlowcurrents,
constant frequency operation, and the ability to maintain
regulation when sinking current. See Figure 4 for a com-
parison of the effect on efficiency at light loads for each
mode. The MODE/SYNC threshold is 0.8V ±7.5%, allow-
ing the MODE/SYNC to act as a feedback pin for regulating
a second winding. If the feedback voltage drops below
0.8V, the LTC3703-5 reverts to continuous operation to
maintain regulation in the secondary supply.
100
V
IN
= 12V
90
80
70
60
50
40
30
20
10
0
V
= 42V
IN
Pulse Skip Mode
The LTC3703-5 can operate in one of two modes select-
able with the MODE/SYNC pin—Pulse Skip Mode or
forced continuous mode. Pulse Skip Mode is selected
when increased efficiency at light loads is desired. In this
mode, the bottom MOSFET is turned off when inductor
current reverses to minimize the efficiency loss due to
reverse current flow. As the load is decreased (see Fig-
ure 5), the duty cycle is reduced to maintain regulation
until its minimum on-time (~200ns) is reached. When the
load decreases below this point, the LTC3703-5 begins to
V
= 12V
IN
V
IN
= 42V
V
OUT
= 5V
FORCED CONTINUOUS
PULSE SKIP MODE
10
100
1000
LOAD (mA)
10000
37035 F04
Figure 4. Efficiency in Pulse Skip/Forced Continuous Modes
PULSE SKIP MODE
FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
37035 F05
Figure 5. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation
37035f
11
LTC3703-5
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OPERATIO
(Refer to Functional Diagram)
Buck or Boost Mode Operation
of the operating mode with the following exceptions: In
boost mode, Pulse Skip Mode operation is always dis-
abled regardless of the level of the MODE/SYNC pin and
the line feedforward compensation is also disabled. The
overcurrentcircuitrycontinuestomonitortheloadcurrent
by looking at the drain voltage of the main (bottom side)
MOSFET. In boost mode, however, the peak MOSFET
current does not equal the load current but instead
ID = ILOAD/(1 – D). This factor needs to be taken into
account when programming the IMAX voltage.
The LTC3703-5 has the capability of operating both as a
step-down(buck)andstep-up(boost)controller. Inboost
mode, output voltages as high as 60V can be tightly
regulated. With the INV pin grounded, the LTC3703-5
operates in buck mode with TG driving the main (top side)
switch and BG driving the synchronous (bottom side)
switch. If the INV pin is pulled above 2V, the LTC3703-5
operates in boost mode with BG driving the main (bottom
side) switch and TG driving the synchronous (top side)
switch. Internalcircuitoperationisverysimilarregardless
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APPLICATIO S I FOR ATIO
ThebasicLTC3703-5applicationcircuitisshownonthefirst
pageofthisdatasheet.Externalcomponentselectionisde-
termined by the input voltage and load requirements as
explained in the following sections. After the operating
frequency is selected, RSET and L can be chosen. The
operating frequency and the inductor are chosen for a
desired amount of ripple current and also to optimize ef-
ficiencyandcomponentsize.Next,thepowerMOSFETsand
D1 are selected based on voltage, load and efficiency re-
quirements.CIN isselectedforitsabilitytohandlethelarge
RMScurrentsintheconverterandCOUT ischosenwithlow
enoughESRtomeettheoutputvoltagerippleandtransient
specifications.Finally,theloopcompensationcomponents
are chosen to meet the desired transient specifications.
noise-sensitive communications systems, it is often de-
sirable to keep the switching noise out of a sensitive
frequency band.
The LTC3703-5 uses a constant frequency architecture
that can be programmed over a 100kHz to 600kHz range
withasingleresistorfromthefSET pintoground,asshown
in the circuit on the first page of this data sheet. The
nominalvoltageonthefSET pinis1.2V,andthecurrentthat
flows from this pin is used to charge and discharge an
internal oscillator capacitor. The value of RSET for a given
operating frequency can be chosen from Figure 6 or from
the following equation:
7100
RSET (kΩ) =
f(kHz)– 25
Operating Frequency
1000
100
The choice of operating frequency and inductor value is a
trade off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses and gate charge losses. How-
ever, lower frequency operation requires more induc-
tance for a given amount of ripple current, resulting in a
larger inductor size and higher cost. If the ripple current
is allowed to increase, larger output capacitors may be
required to maintain the same output ripple. For convert-
ers with high step-down VIN to VOUT ratios, another
consideration is the minimum on-time of the LTC3703-5
(see the Minimum On-time Considerations section). A
final consideration for operating frequency is that in
10
1
200
400
600
800
1000
0
FREQUENCY (kHz)
37035 F06
Figure 6. Timing Resistor (RSET) Value
37035f
12
LTC3703-5
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U
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
Pulse Skip Mode operation is disabled. The clock high
level must exceed 2V for at least 25ns. As shown in
Figure 7, the top MOSFET turn-on will follow the rising
edgeoftheexternalclockbyaconstantdelayequaltoone-
tenth of the cycle period.
ripple current occurs at the highest VIN. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
VOUT
f ∆IL(MAX)
VOUT
V
IN(MAX)
L ≥
1–
The inductor also has an affect on low current operation
when Pulse Skip Mode operation is enabled. The fre-
quency begins to decrease when the output current drops
belowtheaverageinductorcurrentatwhichtheLTC3703-5
is operating at its tON(MIN) in discontinuous mode (see
Figure 5). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
2V TO 10V
MODE/
SYNC
t
= 25ns
MIN
0.8T
T
T = 1/f
O
TG
D = 40%
0.1T
Power MOSFET Selection
The LTC3703-5 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capaci-
tance MOSFET should be used for the top MOSFET in
applications that have an output voltage that is less than
I
L
37035 F07
Figure 7. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703-5 circuit is chosen for
a specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
1/3oftheinputvoltage. InapplicationswhereVIN >>VOUT
,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
inputcapacitanceforthemainswitchapplicationinswitch-
ing regulators.
VOUT
(f)(L)
VOUT
V
IN
∆IL =
1–
Selection criteria for the power MOSFETs include the “on”
resistance RDS(ON), input capacitance, breakdown voltage
and maximum output current.
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this how-
ever, requires a large inductor.
The most important parameter in high voltage applica-
tions is breakdown voltage BVDSS. Both the top and
bottom MOSFETs will see full input voltage plus any
additional ringing on the switch node across its drain-to-
source during its off-time and must be chosen with the
37035f
A reasonable starting point is to choose a ripple current
between 20% and 40% of IO(MAX). Note that the largest
13
LTC3703-5
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APPLICATIO S I FOR ATIO
appropriatebreakdownspecification.SincemostMOSFETs
in the 30V to 60V range have logic level thresholds
(VGS(MIN) ≥ 4.5V), the LTC3703-5 is designed to be used
with a 4.5V to 15V gate drive supply (DRVCC pin).
VOUT
V
IN
MainSwitchDutyCycle =
V – VOUT
IN
SynchronousSwitchDutyCycle =
V
IN
For maximum efficiency, on-resistance RDS(ON) and input
capacitanceshouldbeminimized. LowRDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 8).
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
V
IN
PMAIN
=
I
(
2(1+ δ)RDR(ON)
+
MAX
)
2 I
V
IN
MAX (RDR)(CMILLER)•
V
IN
2
1
1
MILLER EFFECT
V
V
+
(f)
GS
VCC – VTH(IL) VTH(IL)
a
b
+
–
V
DS
V – V
+
IN
Q
PSYNC
=
OUT (IMAX)2(1+ δ)RDS(0N)
V
IN
= (Q – Q )/V
DS
GS
V
–
C
IN
MILLER
B
A
37035 F08
Figure 8. Gate Charge Characteristic
where δ is the temperature dependency of RDS(ON), RDR is
the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
indrainpotentialintheparticularapplication. VTH(IL) isthe
data sheet specified typical gate threshold voltage speci-
fied in the power MOSFET data sheet at the specified drain
current. CMILLER is the calculated capacitance using the
gate charge curve from the MOSFET data sheet and the
technique described above.
BothMOSFETshaveI2RlosseswhilethetopsideN-channel
equationincludesanadditionaltermfortransitionlosses,
which peak at the highest input voltage. For VIN < 25V, the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 25V, the transition losses
rapidly increase to the point that the use of a higher
RDS(ON)devicewithlowerCMILLERactuallyprovideshigher
efficiency. The synchronous MOSFET losses are greatest
athighinputvoltagewhenthetopswitchdutyfactorislow
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initialslopeistheeffectofthegate-to-sourceandthegate-
to-drain capacitance. The flat portion of the curve is the
resultoftheMillermultiplicationeffectofthedrain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombsonthehorizontalaxisfromatobwhilethecurve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified VDS
values. A way to estimate the CMILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated VDS voltage
specified. CMILLER is the most important selection criteria
fordeterminingthetransitionlossterminthetopMOSFET
but is not directly specified on MOSFET data sheets. CRSS
and COS are specified sometimes but definitions of these
parameters are not included.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
37035f
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LTC3703-5
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U
MultipleMOSFETscanbeusedinparalleltolowerRDS(ON) plies above 30V, choice of input capacitor type is limited
and meet the current and thermal requirements if desired. toceramicsoraluminumelectrolytics.Ceramiccapacitors
The LTC3703-5 contains large low impedance drivers have the advantage of very low ESR and can handle high
capable of driving large gate capacitances without signifi- RMS current, however ceramics with high voltage ratings
cantly slowing transition times. In fact, when driving (>50V) are not available with more than a few microfarads
MOSFETs with very low gate charge, it is sometimes of capacitance. Furthermore, ceramics have high voltage
helpful to slow down the drivers by adding small gate coefficients which means that the capacitance values de-
resistors (10Ω or less) to reduce noise and EMI caused by crease even more when used at the rated voltage. X5R and
the fast transitions.
X7R type ceramics are recommended for their lower volt-
age and temperature coefficients. Another consideration
when using ceramics is their high Q which if not properly
damped, may result in excessive voltage stress on the
powerMOSFETs.Aluminumelectrolyticshavemuchhigher
bulkcapacitance,however,theyhavehigherESRandlower
RMS current ratings.
Schottky Diode Selection
The Schottky diode D1 shown in the circuit on the first
page of this data sheet. conducts during the dead time
between the conduction of the power MOSFETs. This
prevents the body diode of the bottom MOSFET from
turning on and storing charge during the dead time and
requiring a reverse recovery period that could cost as
much as 1% to 2% in efficiency. A 1A Schottky diode is
generally a good size for 3A to 5A regulators. Larger
diodes result in additional losses due to their larger
junction capacitance. The diode can be omitted if the
efficiency loss can be tolerated.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low
ESR and RMS current. If the RMS current cannot be
handled by the aluminum capacitors alone, when used
together, the percentage of RMS current that will be
supplied by the aluminum capacitor is reduced to
approximately:
Input Capacitor Selection
1
%IRMS,ALUM
≈
•100%
2
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
1+ (8fCRESR
)
where RESR is the ESR of the aluminum capacitor and C is
theoverallcapacitanceoftheceramiccapacitors.Usingan
aluminum electrolytic with a ceramic also helps damp the
high Q of the ceramic, minimizing ringing.
1/2
VOUT
V
IN
V
IN
VOUT
ICIN(RMS) IO(MAX)
– 1
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(∆VOUT) is approximately equal to:
This formula has a maximum at VIN = 2VOUT, where IRMS
=IO(MAX)/2.Thissimpleworst-caseconditioniscommonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that the ripple current ratings from
capacitormanufacturersareoftenbasedononly2000hours
of life. This makes it advisable to further derate the capaci-
tor or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be placed in
parallel to meet size or height requirements in the design.
1
∆VOUT ≤ ∆IL ESR +
8fCOUT
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. ESR also has a signifi-
cant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
Because tantalum and OS-CON capacitors are not avail-
able in voltages above 30V, for regulators with input sup-
ESR of COUT until the feedback loop in the LTC3703-5 can
37035f
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LTC3703-5
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APPLICATIO S I FOR ATIO
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
MOSFET Driver Supplies (DRVCC and BOOST)
The LTC3703-5 drivers are supplied from the DRVCC and
BOOST pins (see Figure 2), which have an absolute
maximum voltage of 15V. If the main supply voltage, VIN,
is higher than 15V a separate supply with a voltage
between 5V and 15V must be used to power the drivers. If
a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure 9. If the output voltage is between 5V and
15V, the output can be used to directly power the drivers
as shown in Figure 9a. If the output is below 5V, Figure 9b
shows an easy way to boost the supply voltage to a
sufficient level. This boost circuit uses the LT1613 in a
ThinSOTTM package and a chip inductor for minimal extra
area (<0.2 in2). Two other possible schemes are an extra
winding on the inductor (Figure 9c) or a capacitive charge
pump (Figure 9d). All the circuits shown in Figure 9
require a start-up circuit (Q1, D1 and R1) to provide driver
power at initial start-up or following a short-circuit. The
resistorR1mustbesizedsothatitsuppliessufficientbase
currentandzenerbiascurrentatthelowestexpectedvalue
of VIN. When using an existing supply, the supply must be
capable of supplying the required gate driver current
which can be estimated from:
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon-
ductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electro-
lytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recom-
mended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, spe-
cial polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminumelectrolyticcapacitorshavesignificantlyhigher
ESR,butcanbeusedincost-drivenapplicationsproviding
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include Pana-
sonic SP and Sanyo POSCAPs.
IDRVCC = (f)(QG(TOP) + QG(BOTTOM)
)
This equation for IDRVCC is also useful for properly sizing
the circuit components shown in Figure 9.
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs. Capacitor CB is charged through external
diode, DB, from the DRVCC supply when SW is low. When
the top side MOSFET is turned on, the driver places the CB
voltage across the gate-source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. With the topside MOSFET on, the boost voltage
is above the input supply: VBOOST = VIN + VDRVCC. The
value of the boost capacitor CB needs to be 100 times that
of the total input capacitance of the top side MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
Output Voltage
The LTC3703-5 output voltage is set by a resistor divider
according to the following formula:
R1
VOUT = 0.8V 1+
R2
The external resistor divider is connected to the output as
shownintheFunctionalDiagram, allowingremotevoltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of ±1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
ThinSOT is a tradmark of Linear Technology Corporation.
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D2
ZHCS400
L2
4.7µH
V
V
IN
IN
+
C10
1µF
10V
C9
4.7µF
6.3V
1µF
R17
37.4k
V
SW
IN
1%
+
LT1613
SHDN
C
V
IN
FB
5.1V
+
R17
12.1k
1%
C
IN
GND
V
IN
IN
LTC3703-5
5.1V
LTC3703-5
TG
SW
BG
TG
SW
V
OUT
5V TO
15V
V
OUT
L1
L1
<5V
V
V
CC
CC
+
+
C
C
DRV
OUT
DRV
BG
OUT
CC
CC
BGRTN
BGRTN
37035 F09a
3703 F09b
Figure 9a. VCC Generated from 5V < VOUT < 15V
Figure 9b. VCC Generated from VOUT < 5V
V
(<40V)
IN
V
IN
+
1µF
+
C
IN
OPTIONAL V
+
CC
CONNECTION
5V < V < 15V
C
IN
SEC
5.1V
BAT85
5.1V
BAT85
V
IN
V
IN
V
SEC
+
+
LTC3703-5
CC
0.22µF
VN2222LL
LTC3703-5
BAT85
1µF
N
1
V
TG1
SW
CC
TG
SW
BG
T1
V
OUT
V
OUT
DRV
FCB
L1
V
CC
R1
R2
+
C
BG1
OUT
C
DRV
OUT
CC
GND
BGRTN
BGRTN
3703 F09c
3703 F09d
Figure 9c. Secondary Output Loop and VCC Connection
Figure 9d. Capacitive Charge Pump for VCC (VIN < 40V)
current to flow at full reverse voltage. If the reverse
current times reverse voltage exceeds the maximum
allowable power dissipation, the diode may be damaged.
For best results, use an ultrafast recovery diode such as
the MMDL770T1.
below the UVLO threshold, the LTC3703-5 shuts down
and the gate drive outputs remain low.
Bottom MOSFET Source Supply (BGRTN)
Thebottomgatedriver,BG,switchesfromDRVCCtoBGRTN
where BGRTN can be a voltage between ground and –5V.
Why not just keep it simple and always connect BGRTN to
ground? In high voltage switching converters, the switch
An internal undervoltage lockout (UVLO) monitors the
voltage on DRVCC to ensure that the LTC3703-5 has
sufficient gate drive voltage. If the DRVCC voltage falls
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node dV/dt can be many volts/ns, which will pull up on the
gateofthebottomMOSFETthroughitsMillercapacitance.
If this Miller current, times the internal gate resistance of
theMOSFETplusthedriverresistance,exceedsthethresh-
old of the FET, shoot-through will occur. By using a nega-
tive supply on BGRTN, the BG can be pulled below ground
when turning the bottom MOSFET off. This provides a few
extra volts of margin before the gate reaches the turn-on
threshold of the MOSFET. Be aware that the maximum
voltage difference between DRVCC and BGRTN is 15V. If,
for example, VBGRTN = –2V, the maximum voltage on
DRVCC pin is now 13V instead of 15V.
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
For best results, use a VPROG voltage between 100mV and
500mV. Values outside of this range may give less accu-
rate current limit. The current limit can also be disabled by
floating the IMAX pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
Current Limit Programming
Programming current limit on the LTC3703-5 is straight
forward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703-5 current
limitcircuitinvertsthenegativevoltageacrosstheMOSFET
before comparing it to the voltage at IMAX, allowing the
current limit to be set with a positive voltage.
In a typical LTC3703-5 circuit, the feedback loop consists
of the modulator, the external inductor, the output capaci-
tor and the feedback amplifier with its compensation
network. Allofthesecomponentsaffectloopbehaviorand
must be accounted for in the loop compensation. The
modulator consists of the internal PWM generator, the
output MOSFET drivers and the external MOSFETs them-
selves. From a feedback loop point of view, it looks like a
linear voltage transfer function from COMP to SW and has
a gain roughly equal to the input voltage. It has fairly
benign AC behavior at typical loop compensation frequen-
cies with significant phase shift appearing at half the
switching frequency.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
VPROG = (ILIMIT)(RDS(ON))(1 + δ
)
Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
componentscauseasecondorderLCrolloffattheoutput,
withtheattendant180°phaseshift.Thisrolloffiswhatfilters
the PWM waveform, resulting in the desired DC output
voltage, but the phase shift complicates the loop compen-
sation if the gain is still higher than unity at the pole fre-
quency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will ap-
proachitsESRandtherolloffduetothecapacitorwillstop,
leaving 6dB/octave and 90° of phase shift (Figure 10).
where
δ
is explained in the MOSFET Selection section.
VPROG is then programmed at the IMAX pin using the
internal 12µA pull-up and an external resistor:
RIMAX = VPROG/12µA
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
So far, the AC response of the loop is pretty well out of the
user’scontrol.Themodulatorisafundamentalpieceofthe
LTC3703-5 design and the external L and C are usually
chosen based on the regulation and load current require-
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
ments without considering the AC loop response. The
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C2
C1
IN
R2
–
–6dB/OCT
GAIN
R1
FB
GAIN
A
V
–6dB/OCT
–12dB/OCT
0
FREQ
–90
R
OUT
0
FREQ
–90
B
PHASE
V
REF
+
–180
–270
–360
–180
–270
–360
–6dB/OCT
PHASE
37035 F10
37035 F12
Figure 12. Type 2 Schematic and Transfer Function
Figure 10. Transfer Function of Buck Modulator
for an extended frequency range. LTC3703-5 circuits
using conventional switching grade electrolytic output
capacitors can often get acceptable phase margin with
Type 2 compensation.
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and some-
thing less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 11). This “Type
1” configuration is stable but transient response is less
than exceptional if the LC pole is at a low frequency.
“Type 3” loops (Figure 13) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703-5
circuitsusinglowESRtantalumorOS-CONoutputcapaci-
torsneedType3compensationtoobtainacceptablephase
margin with a high bandwidth feedback loop.
C1
IN
GAIN
R1
FB
–
–6dB/OCT
R
OUT
0
FREQ
–90
B
V
+
REF
–180
–270
–360
PHASE
IN
C2
C1
C3
R3
R2
37035 F11
R1
–6dB/OCT
GAIN
FB
Figure 11. Type 1 Schematic and Transfer Function
–
+6dB/OCT
–6dB/OCT
R
OUT
0
FREQ
–90
B
Figure 12 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
V
+
REF
–180
–270
–360
PHASE
37035 F13
Figure 13. Type 3 Schematic and Transfer Function
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable perfor-
mance with similar power components, but can be way off
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nodes don’t corrupt the measurements or damage the
analyzer.
if even one major power component is changed signifi-
cantly. Applications that require optimized transient re-
sponse will require recalculation of the compensation
values specifically for the circuit in question. The underly-
ing mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(VOUT )/V(COMP) in dB and phase of
VOUT in degrees. Refer to your SPICE manual for details of
how to generate this plot.
Modulator gain and phase can be measured directly from
a breadboard or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurateresults,butsimulationcanoftengetcloseenough
to give a working system. To measure the modulator gain
andphasedirectly,wireupabreadboardwithanLTC3703-5
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC3703-5, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
VOUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
a network analyzer (Figure 14) to inject a test signal into
the loop. Measure the gain and phase from the COMP pin
to the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and VOUT
*3703-5 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02
;MOSFET rdson
*inductor
lext sw out1 10u
;inductor value
rl out1 out 0.015 ;inductor series R
*output cap
cout out out2 540u ;capacitor value
resr out2 0 0.01
;capacitor ESR
*3703-5 internals
emod mod 0 value = {43*v(comp)}
;3703-5multiplier
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
5V
V
IN
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 10. Choose the crossover frequency in the
rising or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain at 0dB at this
frequency.Nowcalculatetheneededphaseboost,assum-
ing 60° as a target phase margin:
+
+
10µF
C
IN
V
BOOST
V
CC
DRV
CC
IN
f
TG
SW
BG
M1
L
SET
EXT
V
V
COMP
TO
OUT
TO
COMP
0.1µF
ANALYZER
ANALYZER
LTC3703-5
+
FB
M2
C
OUT
NC
RUN/SS
INV
R
10k
B
MODE/SYNC
GND
AC
SOURCE
FROM
BGRTN
BOOST = –(PHASE + 30°)
ANALYZER
37035 F14
If the required BOOST is less than 60°, a Type 2 loop can
Figure 14. Modulator Gain/Phase Measurement Set-Up
be used successfully, saving two external components.
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BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
Boost Converter Design
The following sections discuss the use of the LTC3703-5
as a step-up (boost) converter. In boost mode, the
LTC3703-5 can step-up output voltages as high as 60V.
These sections discuss only the design steps specific to a
boost converter. For the design steps common to both a
buck and a boost, see the applicable section in the buck
mode section. An example of a boost converter circuit is
shown in the Typical Applications section. To operate the
LTC3703-5 in boost mode, the INV pin should be tied to
the VCC voltage (or a voltage above 2V). Note that in boost
mode, pulse-skipoperationandthelinefeedforwardcom-
pensation are disabled.
Finally, choose a convenient resistor value for R1 (10k is
usuallyagoodvalue). Nowcalculatetheremainingvalues:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
BOOST
K = tan
C2 =
+ 45°
For a boost converter, the duty cycle of the main switch is:
2
1
VOUT – V
IN
D =
VOUT
2π • f •G •K •R1
C1= C2 K2 −1
For high VOUT to VIN ratios, the maximum VOUT is limited
bytheLTC3703-5’smaximumdutycyclewhichistypically
93%. The maximum output voltage is therefore:
(
)
K
R2 =
RB =
2π • f •C1
VREF(R1)
VOUT − VREF
V
IN(MIN)
VOUT(MAX)
=
14V
IN(MIN)
1– DMAX
Boost Converter: Inductor Selection
TYPE 3 Loop:
BOOST
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
K = tan2
+ 45°
4
IO(MAX)
1− DMAX
VO
IL(MAX)
=
= IO(MAX) •
1
V
IN(MIN)
C2 =
2π • f •G •R1
Similartoabuckconverter, choosetheripplecurrenttobe
20% to 40% of IL(MAX). The ripple current amplitude then
determines the inductor value as follows:
C1= C2 K −1
(
)
K
R2 =
R3 =
C3 =
2π • f •C1
R1
V
IN(MIN)
L =
•DMAX
∆IL • f
K − 1
The minimum required saturation current for the inductor
is:
1
2πf K • R3
VREF(R1)
VOUT − VREF
IL(SAT) > IL(MAX) + ∆IL/2
RB =
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∆V
Boost Converter: Power MOSFET Selection
COUT
V
OUT
For information about choosing power MOSFETs for a
boost converter, see the Power MOSFET Selection sec-
tion for the buck converter, since MOSFET selection is
similar. However, note that the power dissipation equa-
tions for the MOSFETs at maximum output current in a
boost converter are:
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆V
ESR
Figure 15. Output Voltage Ripple
Waveform for a Boost Converter
a single capacitor type. However, at output voltages above
30V where capacitors with both low ESR and high bulk
capacitance are hard to find, the best approach is to use a
combination of aluminum and ceramic capacitors (see
discussion in Input Capacitor section for the buck con-
verter). With this combination, the ripple voltage can be
improved significantly. The low ESR ceremic capacitor
will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
2
IMAX
1–DMAX
P
MAIN = DMAX
1+ δ R
+
(
)
DS(ON)
1
2
IMAX
2
VOUT
R
C
•
(
DR)(
)
MILLER
1–DMAX
1
1
+
f
( )
VCC – VTH(IL) VTH(IL)
Boost Converter: Input Capacitor Selection
1
2
PSYNC = –
I
1+ δ R
(
MAX) (
)
DS(ON)
1–DMAX
Theinputcapacitorofaboostconverterislesscriticalthan
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is
recommended though not as critical as for the output
capacitor.
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
moredemandingduetothefactthatthecurrentwaveform
ispulsedinsteadofcontinuousasinabuckconverter. The
choice of component(s) is driven by the acceptable ripple
voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:
The RMS input capacitor ripple current for a boost con-
verter is:
V
IN(MIN)
1
ESR
IRMS(CIN) = 0.3 •
•DMAX
∆VOUT = IO(MAX)
+
L• f
f •COUT 1– DMAX
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
where the first term is due to the bulk capacitance and
second term due to the ESR.
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
Boost Converter: Current Limit Programming
VO – V
IN(MIN)
IRMS(COUT) ≈ IO(MAX)
•
TheLTC3703-5providescurrentlimitinginboostmodeby
monitoring the VDS of the main switch during its on-time
and comparing it to the voltage at IMAX. To set the current
limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
V
IN(MIN)
At lower output voltages (less than 30V), it may be
possible to satisfy both the output ripple voltage and RMS
ripplecurrentrequirementswithoneormorecapacitorsof
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GAIN
(dB)
PHASE
(DEG)
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum load
current,sothelimitmustbesetforthemaximumexpected
duty cycle (minimum VIN) in order to ensure that the
GAIN
A
V
0
–12dB/OCT
current limit does not kick in at loads < IO(MAX)
:
0
IO(MAX)
1– DMAX
VOUT
–90
–180
PHASE
VPROG
=
=
RDS(ON)(1+ δ)
IO(MAX) •RDS(ON)(1+ δ)
V
IN(MIN)
37035 F16
Once VPROG is determined, RIMAX is chosen as follows:
Figure 16. Transfer Function of Boost Modulator
RIMAX = VPROG/12µA
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN.
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
quency so that the overall loop gain is 0dB here. The
compensation component to achieve this, using a Type 1
amplifier (see Figure 11), is:
G = 10–GAIN/20
C1 = 1/(2π • f • G • R1)
Run/Soft-Start Function
Boost Converter: Feedback Loop/Compensation
The RUN/SS pin is a multipurpose pin that provide a soft-
start function and a means to shut down the LTC3703-5.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Compensating a voltage mode boost converter is unfortu-
nately more difficult than for a buck converter. This is due
to an additional right-half plane (RHP) zero that is present
intheboostconverterbutnotinabuck.Theadditionalphase
lagresultingfromtheRHPzeroisdifficultifnotimpossible
tocompensateevenwithaType3loop,sothebestapproach
is usually to roll off the loop gain at a lower frequency than
what could be achievable in buck converter.
Pulling RUN/SS below 1V puts the LTC3703-5 into a low
quiescent current shutdown (IQ 25µA). This pin can be
drivendirectlyfromlogicasshowninFigure17. Releasing
A typical gain/phase plot of a voltage-mode boost con-
verter is shown in Figure 16. The modulator gain and
phase can be measured as described for a buck converter
or can be estimated as follows:
RUN/SS
2V/DIV
GAIN (COMP-to-VOUT DC gain) = 20Log(VOUT2/VIN)
V
OUT
5V/DIV
V
VOUT
1
IN
I
L
Dominant Pole: fP =
•
2A/DIV
2π LC
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of the
compensation network should equal –GAIN at this fre-
37035 F17
V
= 50V
2ms/DIV
IN
I
= 2A
LOAD
C
= 0.01µF
SS
Figure 17. LTC3703-5 Startup Operation
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the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
the RUN/SS pin allows an internal 4µA current source to
charge up the soft-start capacitor CSS. When the voltage
on RUN/SS reaches 1V, the LTC3703-5 begins operating
at its minimum on-time. As the RUN/SS voltage increases
from 1V to 3V, the duty cycle is allowed to increase from
0% to 100%. The duty cycle control minimizes input
supply inrush current and elimates output voltage over-
shootatstart-upandensurescurrentlimitprotectioneven
withahardshort.TheRUN/SSvoltageisinternallyclamped
at 4V.
V
SEC ≈ (N + 1)VOUT
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output is
running in continuous mode. As the load on the primary
output drops and the LTC3703-5 switches to Pulse Skip
Mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precise control of the auxiliary voltage and is set as
follows:
If RUN/SS starts at 0V, the delay before starting is
approximately:
1V
4µA
tDELAY,START
=
CSS = (0.25s /µF)CSS
plus an additional delay, before the output will reach its
regulated value, of:
3V – 1V
4µA
R1
VSEC(MIN) ≈ 0.8V 1+
R2
tDELAY,REG
≥
CSS = (0.5s /µF)CSS
The start delay can be reduced by using diode D1 in
Figure 18.
where R1 and R2 are shown in Figure 9c.
If the LTC3703-5 is operating in Pulse Skip Mode and the
auxiliaryoutputvoltagedropsbelowVSEC(MIN),theMODE/
SYNCpinwilltripandtheLTC3703-5willresumecontinu-
ous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
3.3V
OR 5V
RUN/SS
RUN/SS
D1
C
SS
C
SS
37035 F18
Figure 18. RUN/SS Pin Interfacing
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
TheMODE/SYNCpinisadualfunctionpinthatcanbeused
for enabling or disabling Pulse Skip Mode operation and
alsoasanexternalclockinputforsynchronizingtheinter-
naloscillator(seenextsection).PulseSkipModeisenabled
when the MODE/SYNC pin is above 0.8V and is disabled,
i.e. forced continuous, when the pin is below 0.8V.
The following table summarizes the possible states avail-
able on the MODE/SYNC pin:
Table 1.
MODE/SYNC Pin
Condition
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 9c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
DC Voltage: ≥ 0.87V
Pulse Skip Mode Operation
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V
Forced Continuous
No Current Reversal
37035f
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APPLICATIO S I FOR ATIO
MODE/SYNC Pin (External Synchronization)
PC board trace clearance between high and low voltage
pins in higher voltage applications. Where clearance is an
issue, the G28 package should be used. The G28 package
has 4 unconnected pins between the all adjacent high
voltage and low voltage pins, providing 5(0.0106”) =
0.053” clearance which will be sufficient for most applica-
tions up to 60V. For more information, refer to the printed
circuit board design standards described in IPC-2221
(www.ipc.org).
The internal LTC3703-5 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNCpinwithasignalabove2VP-P.Theinternaloscillator
locks to the external clock after the second clock transi-
tion is received. When external synchronization is de-
tected, LTC3703-5 will operate in forced continuous
mode. If an external clock transition is not detected for
threesuccessiveperiods, theinternaloscillatorwillrevert
to the frequency programmed by the RSET resistor. The
internal oscillator can synchronize to frequencies be-
tween 100kHz and 600kHz, independent of the frequency
programmed by the RSET resistor. However, it is recom-
mended that an RSET resistor be chosen such that the
frequencyprogrammedbytheRSET resistorisclosetothe
expected frequency of the external clock. In this way, the
best converter operation (ripple, component stress, etc)
is achieved if the external clock signal is lost.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703-5 circuits: 1) LTC3703-5 VCC current,
2)MOSFETgatecurrent,3)I2Rlosses,4)TopsideMOSFET
transition losses.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC3703-5 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimumon-timelimitandcareshouldbetakentoensure
1. VCC Supply current. The VCC current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703-5.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to VCC.
that:
VOUT
V • f
IN
tON
=
> tON(MIN)
where tON(MIN) is typically 200ns.
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3703-5 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
tON(MIN) for the same step-down ratio.
2. DRVCC current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge QG moves from DRVCC to
ground. The resulting dQ/dt is a current out of the DRVCC
supply.Incontinuousmode,IDRVCC =f(QG(TOP)+QG(BOT)),
where QG(TOP) and QG(BOT) are the gate charges of the top
and bottom MOSFETs.
Pin Clearance/Creepage Considerations
3. I2R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
The LTC3703-5 is available in two packages (GN16 and
G28) both with identical functionality. The GN16 package
gives the smallest size solution, however the 0.013”
(minimum)spacebetweenpinsmaynotprovidesufficient
37035f
25
LTC3703-5
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APPLICATIO S I FOR ATIO
towards a new duty cycle. If the unity gain crossover fre-
quencyissetto50kHz, theCOMPpinwillgetto60%ofthe
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
theinductorvalueis10µH, thepeakdi/dtwillbe43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor cur-
rent will rise somewhat above the level of the output cur-
rent to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
DCR resistance of L to obtain I2R losses. For example, if
each RDS(ON) = 25mΩ and RL = 25mΩ, then total resis-
tance is 50mΩ. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buckmodeandtheybecomesignificantwhenoperatingat
higher input voltages (typically 20V or greater). Transition
lossescanbeestimatedfromthesecondtermofthePMAIN
equation found in the Power MOSFET Selection section.
The transition losses can become very significant at the
high end of the LTC3703-5 operating voltage range. To
improve efficiency, one may consider lowering the fre-
quency and/or using MOSFETs with lower CRSS at the
Most loads care only about the maximum deviation from
ideal, whichoccurssomewhereinthefirsttwocyclesafter
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirelycontrolledbytheESRofthecapacitorandamounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple ca-
pacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an excep-
tion; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
expense of higher RDS(ON)
.
Other losses including CIN and COUT ESR dissipative
losses, Schottkyconductionlossesduringdead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensationoftheLTC3703-5, theoutputaccuracydue
to DC variations in input voltage and output load current
will be almost negligible. For the few cycles following a
load transient, however, the output deviation may be
larger while the feedback loop is responding. Consider a
typical 48V input to 5V output application circuit,
subjected to a 1A to 5A load transient. Initially, the loop is
in regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A (= 5A-1A) flows out of the
output capacitor while the inductor is still supplying only
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC3703-5 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section de-
scribes in detail the techniques used to design an opti-
mized Type 3 feedback loop, appropriate for most
LTC3703-5 systems.
1A. This sudden change will generate a (4A) • (RESR
)
voltage step at the output; with a typical 0.015Ω output
capacitor ESR, this is a 60mV step at the output.
The feedback loop will respond and will move at the band-
width allowed by the external compensation network
37035f
26
LTC3703-5
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APPLICATIO S I FOR ATIO
Measurement Techniques
togetthedesiredvalue.Thisgivesanoninductiveresistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC3703-5
circuits. SoldertheMOSFETandtheresistor(s)ascloseto
the output of the LTC3703-5 circuit as possible and set up
thesignalgeneratortopulseata100Hzratewitha5%duty
cycle. This pulses the LTC3703-5 with 500µs
transients10ms apart, adequate for viewing the entire
transient recovery time for both positive and negative
transitions while keeping the load resistor cool.
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to test the circuit. Output mea-
surements should be taken with a scope probe directly
across the output capacitor. Proper high frequency prob-
ing techniques should be used. In particular, don’t use the
6" ground lead that comes with the probe! Use an adapter
that fits on the tip of the probe and has a short ground clip
toensurethatinductanceinthegroundpathdoesn’tcause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Design Example
As a design example, take a supply with the following
specifications: VIN = 20V to 60V (48V nominal), VOUT
=
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703-5 and the transient generator
must be minimized.
12V±5%, IOUT(MAX) = 10A, f=250kHz. First, calculate RSET
to give the 250kHz operating frequency:
RSET = 7100/(250-25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum VIN:
12V
12
60
L =
1–
= 10µH
(250kHz)(0.4)(10A)
Figure 19 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
With 10µH inductor, ripple current will vary from 1.9A to
3.8A (19% to 38%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum VIN:
VOUT
12
tON(MIN)
=
=
= 800ns
LTC3703-5
V
OUT
V
IN(MIN)(f) 60(250kHz)
R
LOAD
whichisabovetheLTC3703-5’s200nsminimumon-time.
IRFZ44 OR
PULSE
EQUIVALENT
GENERATOR
50Ω
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
60V(max) plus any ringing, choose a 60V MOSFET.
Si7850DP has a 60V BVDSS, RDS(ON) = 22mΩ(max), δ =
0.007/°C,CMILLER =(9nC–3nC)/30V=200pF,VGS(MILLER)
= 3.8V, θJA = 20°C/W. The power dissipation can be
0V TO 10V
100Hz, 5%
DUTY CYCLE
37035 F19
LOCATE CLOSE TO THE OUTPUT
Figure 19. Transient Load Generator
37035f
27
LTC3703-5
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APPLICATIO S I FOR ATIO
estimated at maximum input voltage, assuming a junction
temperature of 100°C (30°C above an ambient of 70°C):
However, a 0A to 10A load step will cause an output
voltage change of up to:
∆VOUT(STEP) = ∆ILOAD(ESR) = (10A)(0.009Ω)
12
PMAIN
=
(10)2 1+ 0.007(100 – 25) (0.022)
[
]
= 90mV
60
+(60)2
10
2
1
1
PC Board Layout Checklist
(2)(200pF)•
+
(250k)
10 – 3.8 3.8
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703-5. These items are also illustrated graphically in
thelayoutdiagramofFigure20.ForlayoutofaBoostMode
Converter, layout is similar with VIN and VOUT swapped.
Check the following in your layout:
= 0.67W + 0.76W = 1.43W
And double check the assumed TJ in the MOSFET:
TJ = 70°C + (1.43W)(20°C/W) = 99°C
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7850DP
MOSFETs on the bottom:
1. Keepthesignalandpowergroundsseparate. Thesignal
ground consists of the LTC3703-5 GND pin, the ground
return of CVCC, and the (–) terminal of VOUT. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRVCC capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRVCC capacitor and away from
the Schottky loop described in (2).
60 − 12
PSYNC
=
(10)2 1+ 0.007(100 – 25) •
[
]
60
0.022
2
= 1.34W
TJ = 70°C + (1.34W)(20°C/W) = 97°C
Next, set the current limit resistor. Since IMAX = 10A, the
limit should be set such that the minimum current limit is
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the CIN capacitor
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
>10A.MinimumcurrentlimitoccursatmaximumRDS(ON)
.
Using the above calculation for bottom MOSFET TJ, the
max RDS(ON) = (22mΩ/2) [1 + 0.007 (97-25)] = 16.5mΩ
Therefore,IMAX pinvoltageshouldbesetto(10A)(0.0165)
= 0.165V. The RSET resistor can now be chosen to be
0.165V/12µA = 14kΩ.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom side
MOSFET directly to the (–) terminal of CIN. This capacitor
provides the AC current to the MOSFETs.
CIN is chosen for an RMS current rating of about 5A
(IMAX/2) at 85°C. For the output capacitor, two low ESR
OSCON capacitors (18mΩ each) are used to minimize
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
4. Place the ceramic CDRVCC decoupling capacitor imme-
diately next to the IC, between DRVCC and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the CB capacitor should also be next to the IC
between BOOST and SW.
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4A)(0.018Ω/2)
= 36mV
37035f
28
LTC3703-5
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APPLICATIO S I FOR ATIO
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). In
the layout shown in Figure 20, all the small signal compo-
nents have been placed on one side of the IC and all of the
power components have been placed on the other. This
also helps keep the signal ground and power ground
isolated.
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703-5 in order to
keep the high impedance FB node short.
8. Forapplicationswithmultipleswitchingpowerconvert-
ersconnectedtothesameinputsupply,makesurethatthe
input filter capacitor for the LTC3703-5 is not shared with
other converters. AC input current from another converter
couldcausesubstantialinputvoltageripple,andthiscould
interfere with the operation of the LTC3703-5. A few
inches of PC trace or wire (L 100nH) between CIN of the
LTC3703-5 and the actual source VIN should be sufficient
to prevent input noise interference problems.
6. A separate decoupling capacitor for the supply, VCC, is
useful with an RC filter between the DRVCC supply and VCC
pin to filter any noise injected by the drivers. Connect this
capacitor close to the IC, between the VCC and GND pins
and keep the ground side of the VCC capacitor (signal
ground) isolated from the ground side of the DRVCC
capacitor (power ground).
V
CC
V
IN
D
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
R
SET
M1
FSET
COMP
FB
BOOST
TG
+
R
C1
C
IN
C
B
C
C2
C
C1
SW
LTC3703-5
L1
R
MAX
+
I
V
R2
MAX
CC
R
F
+
INV
DRV
CC
V
OUT
C
OUT
C
SS
D1
C
RUN/SS
GND
BG
DRVCC
M2
X5R
R
C2
BGRTN
–
R1
C
VCC
C
C3
X5R
37035 F18
Figure 20. LTC3703-5 Buck Converter Suggested Layout
37035f
29
LTC3703-5
U
TYPICAL APPLICATIO S
15V-60V Input Voltage to 12V/10A Step-Down Converter with Pulse Skip Mode Enabled
V
CC
5V TO 15V
+
V
22µF
25V
IN
D
B
15V TO 60V
MMDL770T1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
MODE/SYNC
V
IN
C
IN
R
SET
+
22µF
100V
×2
25k
FSET
COMP
FB
BOOST
TG
R
C1
M1
Si7850DP
10k
C
B
C
C
C1
C2
0.1µF
L1
8µH
470pF
1000pF
SW
V
12V
10A
OUT
R
15k
LTC3703-5
MAX
I
V
C
MAX
CC
OUT
+
220µF
25V
×2
R
F
R2
8.06k
1%
INV
DRV
CC
10Ω
C
M2
Si7460DP
SS
0.1µF
10
9
RUN/SS
GND
BG
D1
MBR1100
C
DRVCC
10µF
R
C2
100Ω
R1
113k
1%
BGRTN
C
C
C3
2200pF
VCC
1µF
37035 TA01
Single Input Supply 5V/5A Output Step-Down Converter
100Ω
*
10k
V
IN
FZT600
6V TO 60V
5.1V
+
22µF
25V
D
B1
MMDL770T1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
+
C
IN
CMDSH-3
R
25k
15k
SET
4.7Ω
22µF
FSET
COMP
FB
BOOST
TG
R
100V
C1
M1
Si7850DP
10k
D
B2
C
B
C
C
C2
C1
470pF
MMDL770T1
0.1µF
1000pF
SW
L1 4.7µH
V
OUT
R
LTC3703-5
5V
5A
MAX
I
V
MAX
CC
CC
+
C
OUT
220µF
R
F
R2
21.5k
1%
INV
DRV
25V
10Ω
M2
Si7850DP
C
SS
0.1µF
RUN/SS
GND
BG
D1
MBR1100
C
DRVCC
R
C2
100Ω
R1
113k
1%
10µF
BGRTN
C
C
C3
VCC
1µF
2200pF
3703 TA02
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, V
UVLO
5 + V
Z
37035f
30
LTC3703-5
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
NOTE:
G28 SSOP 0204
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
37035f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC3703-5
U
TYPICAL APPLICATIO
5V to 24V/5A Synchronous Boost Converter
+
D
22µF
25V
B
V
24V
5A
OUT
CMDSH-3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
+
OUT
MODE/SYNC
V
IN
220µF
30V
×3
R
25k
SET
FSET
COMP
FB
BOOST
TG
M1
10k
Si7390DP
MBRS140T3
C
B
C
C1
0.1µF
0.1µF
L1
3.3µH
100pF
SW
V
IN
LTC3703-5
R
MAX
15k
4.5V TO 15V
I
V
MAX
CC
CC
+
C
IN
100µF
R
F
R1
113k
1%
R2
3.92k
1%
INV
DRV
20V
10Ω
M2
Si7892DP
C
SS
0.1µF
RUN/SS
GND
BG
C
DRVCC
10µF
BGRTN
C
VCC
1µF
37035 TA03
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37035f
LT/TP 0404 1K • PRINTED IN USA
32 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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