LTC3707EGN-SYNC [Linear]
High Effi ciency, 2-Phase Synchronous Step-Down Switching Regulator; 高艾菲效率,两相同步降压型开关稳压器型号: | LTC3707EGN-SYNC |
厂家: | Linear |
描述: | High Effi ciency, 2-Phase Synchronous Step-Down Switching Regulator |
文件: | 总32页 (文件大小:399K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3707-SYNC
High Efficiency, 2-Phase
Synchronous Step-Down Switching Regulator
FEATURES
DESCRIPTION
TheLTC®3707-SYNCisahighperformancedualstep-down
switching regulator controller that drives all N-channel
synchronouspowerMOSFETstages.Aconstantfrequency
currentmodearchitectureallowsphase-lockablefrequency
of up to 300kHz. Power loss and noise due to the ESR of
the input capacitors are minimized by operating the two
controller output stages out of phase.
n
180° Phased Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes C
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n
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n
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OUT
Dual N-Channel MOSFET Synchronous Drive
1.5% Output Voltage Accuracy
Power Good Output Voltage Monitor
Phase-Lockable Fixed Frequency 150kHz to 300kHz
Wide V Range: 4.5V to 28V Operation
IN
OPTI-LOOPcompensationallowsthetransientresponseto
be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
outputindicatorarecompatiblewithfuturemicroprocessor
generations,andawide4.5Vto28V(30Vmaximum)input
supply range encompasses all battery chemistries.
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
Latched Short-Circuit Shutdown with Defeat Option
Output Overvoltage Protection
Remote Output Voltage Sense
A RUN/SS pin for each controller provides both soft-
start and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
Low Shutdown I : 20μA
Q
5V and 3.3V Standby Regulators
Small 28-Lead Narrow SSOP Package (0.150˝ Wide)
Selectable Constant Frequency, Burst Mode® or
PWM Operation
MOSFET until V
returns to normal. The FCB mode
OUT
APPLICATIONS
pin can select among Burst Mode operation, constant
frequency mode and continuous inductor current mode
or regulate a secondary winding. The IC includes a power
goodoutputpinthatindicateswhenbothoutputsarewithin
7.5% of their designed set point.
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Notebook and Palmtop Computers, PDAs
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Telecom Systems
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Portable Instruments
Battery-Operated Digital Devices
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L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode
and OPTI-LOOP are registered trademarks of Linear Technology Corporation. Protected by U.S.
Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6304066, 6580258.
n
DC Power Distribution Systems
V
IN
5.2V TO 28V
C
22μF
50V
IN
+
TYPICAL APPLICATION
1μF
4.7μF
D3
CERAMIC
D4
V
PGOOD INTV
IN
CC
CERAMIC
M1
M3
M4
TG1
TG2
L1
6.3μH
L2
6.3μH
C
, 0.1μF
B2
BOOST1
SW1
BOOST2
SW2
LTC3707-SYNC
C
, 0.1μF
B1
M2
BG1
BG2
D1
D2
f
PLLIN
SENSE1
PGND
IN
+
–
+
SENSE2
R
R
SENSE1
SENSE2
0.01Ω
1000pF
1000pF
0.01Ω
–
SENSE1
V
SENSE2
V
V
3.3V
5A
OUT1
5V
5A
OUT2
V
OSENSE1
TH1
OSENSE2
R2
105k
1%
R4
63.4k
1%
I
I
TH2
C
C
C2
C
C1
220pF
C
OUT1
OUT
RUN/SS1
SGND
RUN/SS2
+
+
R1
20k
1%
R3
20k
1%
220pF
R
C2
47μF
6V
56mμF
6V
R
C1
C
C
SS2
0.1μF
SS1
0.1μF
15k
15k
SP
SP
M1, M2, M3, M4: FDS6680A
3707 F01
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter
3707sfa
1
LTC3707-SYNC
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (V )......................... 30V to –0.3V
IN
1
2
PGOOD
TG1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN/SS1
Top Side Driver Voltages
+
SENSE1
(BOOST1, BOOST2) ................................... 36V to –0.3V
Switch Voltage (SW1, SW2) ......................... 30V to –5V
–
3
SW1
SENSE1
4
BOOST1
V
OSENSE1
INTV , EXTV , RUN/SS1, RUN/SS2, (BOOST1-SW1),
CC
CC
5
V
PLLFLTR
PLLIN
FCB
IN
(BOOST2-SW2), PGOOD.............................. 7V to –0.3V
6
BG1
+
–
+
–
SENSE1 , SENSE2 , SENSE1 ,
7
EXTV
CC
SENSE2 Voltages .........................(1.1)INTV to –0.3V
8
INTV
CC
CC
CC
I
TH1
PLLIN, PLLFLTR, FCB, Voltage ............. INTV to –0.3V
9
PGND
BG2
SGND
I
, I , V
, V
Voltages ... 2.7V to –0.3V
10
11
12
13
14
3.3V
OUT
TH1 TH2 OSENSE1 OSENSE2
BOOST2
SW2
I
Peak Output Current <10μs (TG1, TG2, BG1, BG2).....3A
TH2
V
INTV Peak Output Current ................................. 40mA
OSENSE2
–
CC
TG2
SENSE2
SENSE2
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
+
RUN/SS2
GN PACKAGE
28-LEAD PLASTIC SSOP
T
= 125°C, θ = 80°C/W
JA
JMAX
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
28-Lead Plastic SSOP
28-Lead Plastic SSOP
PACKAGE DESCRIPTION
28-Lead Plastic SSOP
28-Lead Plastic SSOP
TEMPERATURE RANGE
LTC3707EGN-SYNC#PBF
LTC3707IGN-SYNC#PBF
LEAD BASED FINISH
LTC3707EGN-SYNC
LTC3707IGN-SYNC
LTC3707EGN-SYNC#TRPBF LTC3707EGN-SYNC
LTC3707IGN-SYNC#TRPBF LTC3707IGN-SYNC
–40°C to 85°C
–40°C to 85°C
TAPE AND REEL
PART MARKING
TEMPERATURE RANGE
–40°C to 85°C
LTC3707EGN-SYNC#TR
LTC3707IGN-SYNC#TR
LTC3707EGN-SYNC
LTC3707IGN-SYNC
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
l
V
Regulated Feedback Voltage
Feedback Current
(Note 4); I
Voltage = 1.2V
TH1, 2
0.788
0.800
–5
0.812
–50
V
nA
OSENSE1, 2
I
(Note 4)
VOSENSE1, 2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 3.6V to 30V (Note 4)
0.002
0.02
%/V
REFLNREG
LOADREG
IN
(Note 4)
l
l
Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔITH Voltage = 1.2V to 2.0V
0.1
–0.1
0.5
–0.5
%
%
g
Transconductance Amplifier g
I = 1.2V; Sink/Source 5μA; (Note 4)
TH1, 2
1.3
mmho
m1, 2
m
3707sfa
2
LTC3707-SYNC
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 1.2V; (Note 4)
MIN
TYP
MAX
UNITS
g
Transconductance Amplifier GBW
I
3
MHz
mGBW1, 2
TH1, 2
I
Q
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
IN
RUN/SS1, 2
V
V
= 15V; EXTV Tied to V ; V = 5V
OUT1 OUT1
350
20
μA
μA
CC
= 0V, V
= Open
STBYMD
35
l
V
Forced Continuous Threshold
Forced Continuous Pin Current
0.76
0.800
–0.18
4.3
0.84
–0.1
4.8
V
μA
V
FCB
I
V
= 0.85V
–0.30
FCB
FCB
V
Burst Inhibit (Constant Frequency)
Threshold
Measured at FCB pin
BINHIBIT
l
l
UVLO
Undervoltage Lockout
Feedback Overvoltage Lockout
Sense Pins Total Source Current
Maximum Duty Factor
V
Ramping Down
3.5
0.86
–60
99.4
1.2
1.5
4.1
2
4
V
V
IN
V
OVL
Measured at V
0.84
–90
98
0.88
OSENSE1, 2
–
–
+ +
= 0V
SENSE1 , 2
I
(Each Channel); V
In Dropout
= V
μA
%
μA
V
SENSE
SENSE1 , 2
DF
MAX
I
Soft-Start Charge Current
V
V
V
= 1.9V
0.5
1.0
RUN/SS1, 2
RUN/SS1, 2
V
V
ON RUN/SS Pin ON Threshold
LT RUN/SS Pin Latchoff Arming Threshold
RUN/SS Discharge Current
, V Rising
RUN/SS1 RUN/SS2
2.0
4.75
4
RUN/SS1, 2
RUN/SS1, 2
SCL1, 2
, V
Rising from 3V
V
RUN/SS1 RUN/SS2
I
I
Soft Short Condition V
V
= 0.5V;
0.5
μA
OSENSE1, 2
= 4.5V
RUN/SS1, 2
Shutdown Latch Disable Current
Maximum Current Sense Threshold
V
= 0.5V
1.6
5
μA
SDLHO
OSENSE1, 2
–
–
–
–
V
V
V
= 0.7V,V
= 0.7V,V
= 5V
= 5V
65
62
75
75
85
88
mV
mV
SENSE(MAX)
OSENSE1, 2
OSENSE1, 2
SENSE1 , 2
SENSE1 , 2
l
TG Transition Time:
Rise Time
Fall Time
(Note 6)
TG1, 2 t
TG1, 2 t
C
C
= 3300pF
60
60
110
110
ns
ns
r
f
LOAD
LOAD
= 3300pF
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG1, 2 t
BG1, 2 t
C
C
= 3300pF
= 3300pF
50
50
110
100
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
1D
C
= 3300pF Each Driver
= 3300pF Each Driver
80
ns
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
2D
C
LOAD
80
ns
ns
t
Minimum On-Time
Tested with a Square Wave (Note 7)
180
ON(MIN)
INTV Linear Regulator
CC
V
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
4.8
4.5
5.0
0.2
100
4.7
0.2
5.2
2.0
200
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I
CC
I
CC
I
CC
= 0 to 20mA, V
= 4V
EXTVCC
LDO
LDO
CC
EXT
EXTV Voltage Drop
= 20mA, V
= 5V
EXTVCC
mV
V
CC
l
EXTV Switchover Voltage
= 20mA, EXTV Ramping Positive
CC
EXTVCC
LDOHYS
CC
EXTV Hysteresis
V
CC
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Resistance
V
V
V
= 1.2V
= 0V
190
120
280
220
140
310
50
250
160
360
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
PLLFLTR
PLLFLTR
PLLFLTR
≥ 2.4V
R
PLLIN
3707sfa
3
LTC3707-SYNC
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLLFLTR
f
f
< f
> f
–15
15
μA
μA
PLLIN
PLLIN
OSC
OSC
3.3V Linear Regulator
l
V
V
V
3.3V Regulator Output Voltage
3.3V Regulator Load Regulation
3.3V Regulator Line Regulation
No Load
= 0 to 10mA
3.20
3.35
0.5
3.45
2
V
%
%
3.3OUT
3.3IL
I
3.3
6V < V < 30V
0.05
0.2
3.3VL
IN
PGOOD Output
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
1
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Trip Level, Either Controller
V
V
μA
PGOOD
PGOOD
V
with Respect to Set Output Voltage
Ramping Negative
Ramping Positive
PG
OSENSE
V
V
–6
6
–7.5
7.5
–9.5
9.5
%
%
OSENSE
OSENSE
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The IC is tested in a feedback loop that servos V
to a
ITH1, 2
.
specified voltage and measures the resultant V
OSENSE1, 2
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 2: The LTC3707E-SYNC is guaranteed to meet performance
specification from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC3707I-SYNC
is guaranteed to meet performance specifications over the full –40°C
to 85°C operating temperature range.
Note 6: Rise and fall times are measured using 10% and 90% levels.
Delay times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of I
(see minimum on-time
MAX
considerations in the Applications Information section).
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LTC3707-SYNC: T = T + (P • 95 °C/W)
J
A
D
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
and Mode (Figure 13)
Efficiency vs Output Current
(Figure 13)
Efficiency vs Input Voltage
(Figure 13)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
100
90
80
70
60
50
Burst Mode
OPERATION
V
= 7V
IN
V
= 10V
IN
FORCED
CONTINUOUS
MODE
V
IN
= 15V
V
= 20V
IN
CONSTANT
FREQUENCY
(BURST DISABLE)
V
I
= 5V
= 3A
V
V
= 15V
= 5V
OUT
OUT
IN
OUT
V
= 5V
OUT
0.1
1
0.01
0.1
1
5
15
25
35
0.001
0.01
10
0.001
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
3707 G02
3707 G03
3707 G01
3707sfa
4
LTC3707-SYNC
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Input Voltage
and Mode (Figure 13)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
1000
800
600
400
200
0
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
INTV VOLTAGE
CC
BOTH
CONTROLLERS ON
EXTV SWITCHOVER THRESHOLD
CC
SHUTDOWN
10
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
5
15
20
25
30
30
6
0
10
20
30
40
INPUT VOLTAGE (V)
CURRENT (mA)
3707 G06
3707 G04
3707 G05
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs Duty Factor
Internal 5V LDO Line Regulation
5.1
5.0
75
50
25
0
80
70
60
50
40
30
20
10
0
I
= 1mA
LOAD
4.9
4.8
4.7
4.6
4.5
4.4
20
INPUT VOLTAGE (V)
0
5
10
15
25
0
20
40
60
80
100
50
0
25
75
100
DUTY FACTOR (%)
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3707 G07
3707 G08
3707 G09
Maximum Current Sense
Threshold vs VRUN/SS (Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Current Sense Threshold
vs ITH Voltage
90
80
80
76
72
68
64
60
80
60
40
20
V
= 1.6V
SENSE(CM)
70
60
50
40
30
20
10
0
–10
–20
–30
0
0
1
2
3
4
5
0
1
2
3
4
5
0
0.5
1
1.5
(V)
2
2.5
V
(V)
COMMON MODE VOLTAGE (V)
V
ITH
RUN/SS
3707 G10
3707 G11
3707 G12
3707sfa
5
LTC3707-SYNC
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation
VITH vs VRUN/SS
SENSE Pins Total Source Current
0.0
–0.1
–0.2
–0.3
–0.4
100
50
2.5
2.0
1.5
1.0
V
= 0.7V
OSENSE
0
–50
–100
0.5
0
FCB = 0V
V
= 15V
IN
FIGURE 1
2
4
0
6
0
1
2
3
4
5
0
2
3
4
5
6
1
V
(V)
V
COMMON MODE VOLTAGE (V)
SENSE
LOAD CURRENT (A)
RUN/SS
3707 G15
3707 G13
3707 G14
Maximum Current Sense
Threshold vs Temperature
Dropout Voltage vs Output Current
(Figure 13)
RUN/SS Current vs Temperature
80
78
76
74
72
70
4
3
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
= 5V
OUT
R
= 0.015Ω
SENSE
R
= 0.010Ω
SENSE
0
0
–50 –25
0
25
50
75 100 125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT CURRENT (A)
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3707 G17
3707 G18
3707 G25
Soft-Start Up (Figure 13)
Load Step (Figure 13)
Load Step (Figure 13)
V
V
OUT
200mV/DIV
V
OUT
OUT
200mV/DIV
5V/DIV
V
RUN/SS
5V/DIV
I
I
OUT
2A/DIV
OUT
2A/DIV
I
OUT
2A/DIV
3707 G20
3707 G21
3707 G19
20μs/DIV
20μs/DIV
V
V
= 15V
= 5V
V
V
= 15V
= 5V
OUT
5ms/DIV
V
V
= 15V
= 5V
IN
OUT
IN
IN
OUT
LOAD STEP = 0A TO 3A
Burst Mode OPERATION
LOAD STEP = 0A TO 3A
CONTINUOUS MODE
3707sfa
6
LTC3707-SYNC
TYPICAL PERFORMANCE CHARACTERISTICS
Input Source/Capacitor
Instantaneous Current (Figure 13)
Constant Frequency (Burst Inhibit)
Operation (Figure 13)
Burst Mode Operation (Figure 13)
I
IN
V
OUT
2A/DIV
V
OUT
20mV/DIV
20mV/DIV
V
IN
200mV/DIV
V
SW1
10V/DIV
I
V
I
OUT
SW2
OUT
0.5A/DIV
10V/DIV
0.5A/DIV
3707 G24
3707 G23
3707 G22
2μs/DIV
10μs/DIV
1μs/DIV
V
V
V
I
= 15V
= 5V
V
V
V
I
= 15V
= 5V
V
V
I
= 15V
= 5V
OUT5 OUT3.3
IN
OUT
FCB
IN
OUT
FCB
IN
OUT
= 5V
= OPEN
= 20mA
= I
= 2A
= 20mA
OUT
OUT
Current Sense Pin Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
35
33
31
29
27
25
10
8
350
300
V
= 5V
V
= 2.4V
OUT
PLLFLTR
250
200
150
100
50
V
= 1.2V
= 0V
PLLFLTR
6
V
PLLFLTR
4
2
0
0
50
100 125
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
75
–50 –25
0
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3707 G28
3707 G26
3707 G27
Undervoltage Lockout
vs Temperature
Shutdown Latch Thresholds
vs Temperature
3.50
3.45
3.40
3.35
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LATCH ARMING
LATCHOFF
THRESHOLD
3.30
3.25
3.20
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
3707 G29
3707 G30
3707sfa
7
LTC3707-SYNC
PIN FUNCTIONS
RUN/SS1, RUN/SS2 (Pins 1, 15): Combination of
soft-start, run control inputs and short-circuit detection
timers. Acapacitortogroundateachofthesepinssetsthe
ramptimetofulloutputcurrent.Forcingeitherofthesepins
back below 1.0V causes the IC to shut down the circuitry
requiredforthatparticularcontroller. Latchoffovercurrent
protection is also invoked via this pin as described in the
Applications Information section.
3.3V
(Pin 10): Output of a linear regulator capable of
OUT
supplying 10mA DC with peak currents as high as 50mA.
PGND (Pin 20): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifiers and the (–) terminal(s)
of C .
IN
INTV (Pin 21): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTV Switch. The driver
and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of
4.7μF tantalum or other low ESR capacitor.
CC
CC
+
+
SENSE1 , SENSE2 (Pins 2, 14): The (+) Input to the
Differential Current Comparators. The I pin voltage and
TH
–
+
controlledoffsetsbetweentheSENSE andSENSE pinsin
conjunction with R
set the current trip threshold.
SENSE
EXTV (Pin22):ExternalPowerInputtoanInternalSwitch
CC
–
–
SENSE1 , SENSE2 (Pins 3, 13): The (–) Input to the
Connected to INTV . This switch closes and supplies V
CC
CC
Differential Current Comparators.
power,bypassingtheinternallowdropoutregulator,when-
V
, V
(Pins 4, 12): Receives the remotely-
ever EXTV is higher than 4.7V. See EXTV connection
OSENSE1 OSENSE2
sensedfeedbackvoltageforeachcontrollerfromanexternal
CC CC
in Applications section. Do not exceed 7V on this pin.
resistive divider across the output.
BG1, BG2 (Pins 23, 19): High Current Gate Drives for
PLLFLTR(Pin5):ThePhase-LockedLoop’sLowpassFilter
is Tied to This Pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTV .
CC
V (Pin 24): Main Supply Pin. A bypass capacitor should
IN
be tied between this pin and the signal ground pin.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
betweentheboostandswitchpinsandSchottkydiodesare
tied between the boost and INTV pins. Voltage swing at
CC
the boost pins is from INTV to (V + INTV ).
CC
IN
CC
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding. Pulling this pin below 0.8V will
force continuous synchronous operation. Do not leave
this pin floating.
SW1, SW2 (Pins 26, 17): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V .
IN
TG1, TG2 (Pins 27, 16): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
I
,I (Pins8,11):ErrorAmplifierOutputandSwitching
TH1 TH2
drivers with a voltage swing equal to INTV – 0.5V
CC
RegulatorCompensationPoint.Eachassociatedchannels’
current comparator trip point increases with this control
voltage.
superimposed on the switch node voltage SW.
PGOOD (Pin 28): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on either V
is not within 7.5% of its set point.
pin
OSENSE
SGND (Pin 9): Small Signal Ground common to both
controllers, must be routed separately from high current
grounds to the common (–) terminals of the C
capacitors.
OUT
3707sfa
8
LTC3707-SYNC
FUCTIONAL DIAGRAM
PLLIN
INTV
CC
V
IN
F
IN
PHASE DET
D
C
B
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
50k
BOOST
TG
PLLFLTR
B
DROP
OUT
+
CLK1
CLK2
–
TOP
BOT
R
LP
C
IN
D
OSCILLATOR
1
DET
BOT
FCB
C
LP
SW
TOP ON
0.86V
S
Q
Q
+
SWITCH
LOGIC
INTV
CC
R
V
OSENSE1
PGOOD
BG
–
+
0.74V
0.86V
C
OUT
PGND
B
+
–
0.55V
–
+
V
OUT
SHDN
R
SENSE
V
OSENSE2
–
+
INTV
CC
0.74V
BINH
I1
I2
V
SEC
3V
+
–
+
–
+
4.5V
0.8V
–
+ +
–
+
0.18μA
FCB
–
SENSE
SENSE
D
SEC
C
SEC
30k
30k
R6
3mV
0.86V
4(V
–
)
FB
+
–
FCB
R5
SLOPE
COMP
45k
45k
2.4V
3.3V
V
OSENSE
R2
OUT
V
FB
+
–
V
REF
–
EA
+
0.80V
0.86V
R1
OV
V
IN
+
–
V
IN
C
C
+
–
4.8V
I
TH
5V
1.2μA
EXTV
INTV
LDO
REG
CC
SHDN
RST
RUN
SOFT
START
R
C
C
C2
6V
4(V
)
FB
CC
5V
+
RUN/SS
INTERNAL
SUPPLY
SGND
C
SS
3707 FD/F02
Figure 2
OPERATION
(Refer to Functional Diagram)
Main Control Loop
by the EA. When the load current increases, it causes a
slight decrease in V
relative to the 0.8V reference,
OSENSE
TheICusesaconstantfrequency,currentmodestep-down
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
which in turn causes the I voltage to increase until the
TH
average inductor current matches the new load current.
After the top MOSFET has turned off, the bottom MOSFET
is turned on until either the inductor current starts to
reverse, as indicated by current comparator I2, or the
beginning of the next cycle.
voltage on the I pin, which is the output of each error
ThetopMOSFETdriversarebiasedfromfloatingbootstrap
TH
amplifierEA.TheV
pinreceivesthevoltagefeedback
capacitor C , which normally is recharged during each off
OSENSE
B
signal, whichiscomparedtotheinternalreferencevoltage
cycle through an external diode when the top MOSFET
3707sfa
9
LTC3707-SYNC
OPERATION
(Refer to Functional Diagram)
turns off. As V decreases to a voltage close to V
,
avariable“sleep”intervaldependingupontheloadcurrent.
The resultant output voltage ripple is held to a very small
value by having the hysteretic comparator after the error
amplifier gain block.
IN
OUT
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 400ns every
tenth cycle to allow C to recharge.
B
Frequency Synchronization
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.2μA
current source to charge soft-start capacitor C . When
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 140kHz to 310kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
minimum frequency.
SS
C
reaches 1.5V, the main control loop is enabled with
TH
SS
the I voltage clamped at approximately 30% of its
maximum value. As C continues to charge, the I pin
SS
TH
voltage is gradually released allowing normal, full-current
operation. When both RUN/SS1 and RUN/SS2 are low, all
controller functions are shut down, including the 5V and
3.3V regulators.
Low Current Operation
Continuous Current (PWM) Operation
TheFCBpinisamultifunctionpinprovidingtwofunctions:
1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on both
controllers;and2)selectbetweentwomodesoflowcurrent
operation. When the FCB pin voltage is below 0.8V, the
controllerforcescontinuousPWMcurrentmodeoperation.
In this mode, the top and bottom MOSFETs are alternately
turned on to maintain the output voltage independent
of direction of inductor current. When the FCB pin is
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
whileinforcedcontinuousoperation,currentwillbeforced
back into the main power supply potentially boosting the
input supply to dangerous voltage levels—BEWARE!
INTV /EXTV Power
CC
CC
below V
– 2V but greater than 0.8V, the controller
INTVCC
enters Burst Mode operation. Burst Mode operation sets
a minimum output current level before inhibiting the top
switch and turns off the synchronous MOSFET(s) when
the inductor current goes negative. This combination of
Power for the top and bottom MOSFET drivers and most
otherinternalcircuitryisderivedfromtheINTV pin.When
CC
the EXTV pin is left open, an internal 5V low dropout
CC
linear regulator supplies INTV power. If EXTV is taken
CC
CC
requirements will, at low currents, force the I pin below
above 4.7V, the 5V regulator is turned off and an internal
TH
a voltage threshold that will temporarily inhibit turn-on of
bothoutputMOSFETsuntiltheoutputvoltagedrops.There
is 60mV of hysteresis in the burst comparator B tied to
switch is turned on connecting EXTV to INTV . This al-
CC
CC
lowstheINTV powertobederivedfromahighefficiency
CC
external source such as the output of the regulator itself
or a secondary winding, as described in the Applications
Information section.
the I pin. This hysteresis produces output signals to the
TH
MOSFETs that turn them on for several cycles, followed by
3707sfa
10
LTC3707-SYNC
OPERATION
Output Overvoltage Protection
(Refer to Functional Diagram)
Theory and Benefits of 2-Phase Operation
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
The LTC1628 and the LTC3707-SYNC dual high efficiency
DC/DC controllers bring the considerable benefits of
2-phase operation to portable applications for the first
time. Notebook computers, PDAs, handheld terminals
and automotive electronics will all benefit from the lower
input filtering requirement, reduced electromagnetic
interference (EMI) and increased efficiency associated
with 2-phase operation.
Power Good (PGOOD) Pin
ThePGOODpinisconnectedtoanopendrainofaninternal
MOSFET. TheMOSFETturnsonandpullsthepinlowwhen
either output is not within 7.5% of the nominal output
levelasdeterminedbytheresistivefeedbackdivider.When
both outputs meet the 7.5% requirement, the MOSFET is
turned off within 10μs and the pin is allowed to be pulled
up by an external resistor to a source of up to 7V.
Whytheneedfor2-phaseoperation?UpuntiltheLTC1628
familyofparts, constant-frequencydualswitchingregula-
tors operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and battery.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
TheRUN/SScapacitorsareusedinitiallytolimittheinrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SScapacitorisusedinashort-circuittime-outcircuit.
If the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin(s) voltage(s) are recycled. This built-in
latchoff can be overridden by providing a >5μA pull-up
at a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft start period but also prevents net dis-
charge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting
is also activated when the output voltage falls below
70% of its nominal level whether or not the short-circuit
latchoff circuit is enabled. Even if a short is present and
the short-circuit latchoff is not enabled, a safe, low output
current is provided due to internal current foldback and
actual power wasted is low due to the efficient nature of
the current mode switching regulator.
With 2-phase operation, the two channels of the
dual-switching regulator are operated 180 degrees out of
phase.Thiseffectivelyinterleavesthecurrentpulsesdrawn
by the switches, greatly reducing the overlap time where
they add together. The result is a significant reduction in
totalRMSinputcurrent,whichinturnallowslessexpensive
inputcapacitorstobeused,reducesshieldingrequirements
for EMI and improves real world operating efficiency.
Figure3comparestheinputwaveformsforarepresentative
single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement
oftheRMSinputcurrentundertheseconditionsshowsthat
2-phaseoperationdroppedtheinputcurrentfrom2.53A
RMS
to1.55A
. Whilethisisanimpressivereductioninitself,
RMS
2
remember that the power losses are proportional to I
,
RMS
meaningthattheactualpowerwastedisreducedbyafactor
of 2.66. The reduced input ripple voltage also means less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances and
protection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage.
3707sfa
11
LTC3707-SYNC
OPERATION
(Refer to Functional Diagram)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
3707 F03a
3707 F03b
I
= 2.53A
I
= 1.55A
RMS
IN(MEAS)
RMS
IN(MEAS)
(a)
(b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for
Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input
Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive Input Capacitors,
Reduces Shielding Requirements for EMI and Improves Efficiency
Of course, the improvement afforded by 2-phase opera-
2-phase operation. In addition, isolation between the two
channels becomes more critical with 2-phase operation
becauseswitchtransitionsinonechannelcouldpotentially
disrupt the operation of the other channel.
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage V (Duty Cycle = V /V ). Figure 4 shows how
IN
OUT IN
theRMSinputcurrentvariesforsingle-phaseand2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
TheLTC1628familyofpartsisproofthatthesehurdleshave
beensurmounted.Thenewdeviceoffersuniqueadvantages
for the ever-expanding number of high efficiency power
supplies required in portable electronics.
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
theinputcapacitorrequirementtothatforjustonechannel
operating at maximum current and 50% duty cycle.
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
2.0
1.5
1.0
0.5
0
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer
is that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation”
signal to allow stable operation of each regulator at over
50% duty cycle. This signal is relatively easy to derive in
single-phase dual switching regulators, but required the
development of a new and proprietary technique to allow
2-PHASE
DUAL CONTROLLER
V
V
= 5V/3A
O1
O2
= 3.3V/3A
0
10
20
30
40
INPUT VOLTAGE (V)
3707 F04
Figure 4. RMS Input Current Comparison
3707sfa
12
LTC3707-SYNC
APPLICATIONS INFORMATION
2.5
2.0
1.5
1.0
0.5
0
Figure 1 on the first page is a basic IC application circuit.
External component selection is driven by the load re-
quirement, and begins with the selection of R
and
SENSE
the inductor value. Next, the power MOSFETs and D1 are
selected. Finally, C and C are selected. The circuit
IN
OUT
shown in Figure 1 can be configured for operation up to an
input voltage of 28V (limited by the external MOSFETs).
R
SENSE
Selection For Output Current
R
is chosen based on the required output current.
120
170
220
270
320
SENSE
OPERATING FREQUENCY (kHz)
The current comparator has a maximum threshold of
3707 F05
75mV/R
and an input common mode range of SGND
SENSE
to1.1(INTV ). Thecurrentcomparatorthresholdsetsthe
CC
Figure 5. PLLFLTR Pin Voltage vs Frequency
peak of the inductor current, yielding a maximum average
output current I
peak-to-peak ripple current, ΔI .
equal to the peak value less half the
MAX
Inductor Value Calculation
L
The operating frequency and inductor selection are
interrelated in that higher operating frequencies allow the
useofsmallerinductorandcapacitorvalues.Sowhywould
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
Allowing a margin for variations in the IC and external
component values yields:
50mV
IMAX
RSENSE
=
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due
to the internal compensation required to meet stability
criterionforbuckregulatorsoperatingatgreaterthan50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
L
inductance or frequency and increases with higher V :
IN
⎛
⎞
VOUT
1
Operating Frequency
ΔIL =
VOUT 1–
⎜
⎝
⎟
(f)(L)
V
⎠
IN
The IC uses a constant frequency phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current
plus an additional current which is proportional to the
voltageappliedtothePLLFLTRpin.RefertoPhase-Locked
Loop and Frequency Synchronization in the Applications
Information section for additional information.
Accepting larger values of ΔI allows the use of low in-
L
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔI =0.3(I
at the maximum input voltage.
). The maximum ΔI occurs
L
L
MAX
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
isincreasedthegatechargelosseswillbehigher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
25% of the current limit determined by R
. Lower
SENSE
inductor values (higher ΔI ) will cause this to occur at
L
lower load currents, which can cause a dip in efficiency in
3707sfa
13
LTC3707-SYNC
APPLICATIONS INFORMATION
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
exception is if low input voltage is expected (V < 5V);
IN
then, sub-logic level threshold MOSFETs (V
< 3V)
speci-
GS(TH)
should be used. Pay close attention to the BV
DSS
fication for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mμ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance R
, reverse transfer capacitance C
,
DS(ON)
RSS
input voltage and maximum output current. When the IC
is operating in continuous mode the duty cycles for the
top and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
VIN
V – VOUT
IN
Synchronous SwitchDuty Cycle=
V
IN
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
2
PMAIN
=
I
(
1+δ R
+
(
)
)
MAX
DS(ON)
V
IN
1
2
2
V
I
R
C
MILLER
(
IN) ( MAX)( DR )(
)
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ. Toroids are very space efficient,
especiallywhenyoucanuseseverallayersofwire.Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.
⎡
⎢
⎣
⎤
⎥
⎦
1
1
+
f
( )
V
INTVCC – VTH VTH
V – VOUT
2
IN
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
MAX
V
IN
where δ is the temperature dependency of R
, R is
DS(ON) DR
theeffectivetopdriverresistanceoverthe(ofapproximately
4Ω at V = V ), V is the drain potential and the
GS
MILLER
IN
Power MOSFET and D1 Selection
change in drain potential in the particular application. V
TH
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet. C is the
Two external power MOSFETs must be selected for each
controller in the IC: One N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
MILLER
calculated capacitance using the gate charge curve from
the MOSFET data sheet. C is determined by dividing
MILLER
the increase in charge indicated on the x axis during the
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
CC
flat, Miller portion of the curve by the stated V transition
DS
This voltage is typically 5V during start-up (see EXTV
CC
voltage specified on the curve.
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. The only
3707sfa
14
LTC3707-SYNC
APPLICATIONS INFORMATION
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20μF to 40μF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coefficients are very high and may have audible
piezoelectric effects; tantalums need to be surge-rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22μF or two to three
10μF ceramic capacitors are an ideal choice in a 20W to
35W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest efficiency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
The term (1+δ) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the
dead-time and requiring a reverse recovery period that
could cost as much as 3% in efficiency at high V . A 1A
IN
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current.Largerdiodesresultinadditionaltransitionlosses
due to their larger junction capacitance.
C and C
IN
Selection
OUT
The selection of C is simplified by the multiphase ar-
IN
Incontinuousmode,thesourcecurrentofthetopN-channel
chitecture and its impact on the worst-case RMS current
drawnthroughtheinputnetwork(battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
MOSFETisasquarewaveofdutycycleV /V .Toprevent
OUT IN
largevoltagetransients,alowESRinputcapacitorsizedfor
the maximum RMS current of one channel must be used.
The maximum RMS capacitor current is given by:
the highest (V )(I ) product needs to be used in the
OUT OUT
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
theotherout-of-phasecontroller,willactuallydecreasethe
input RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
30% to 70% when compared to a single phase power
supply solution.
1/2
⎡
⎤
OUT
VOUT V − V
(
)
IN
⎣
⎦
CIN RequiredIRMS ≈IMAX
V
IN
This formula has a maximum at V = 2V , where I
RMS
= I /2. This simple worst case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturer’sripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
IN
OUT
OUT
3707sfa
15
LTC3707-SYNC
APPLICATIONS INFORMATION
to choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The I pin
TH
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
The benefit of the LTC3707-SYNC multiphase can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switch on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the interleaving of current
pulses through the input capacitor’s ESR. This is why the
input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Remember that input protection fuse resistance,
battery resistance and PC board trace resistance losses
are also reduced due to the reduced peak currents in a
multiphase system. The overall benefit of a multiphase
designwillonlybefullyrealizedwhenthesourceimpedance
of the power supply/battery is included in the efficiency
testing. The drains of the two top MOSFETS should be
Manufacturers such as Nichicon, United Chemicon
and Sanyo can be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo has the lowest
(ESR)(size) product of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON capacitors is recommended to
reduce the inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages.
Special polymer surface mount capacitors offer very low
ESR but have lower storage capacity per unit volume
than other capacitor types. These capacitors offer a very
cost-effective output capacitor solution and are an ideal
choice when combined with a controller having high
loop bandwidth. Tantalum capacitors offer the highest
capacitancedensityandareoftenusedasoutputcapacitors
for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm
to 4mm. Aluminum electrolytic capacitors can be used
in cost-driven applications providing that consideration
is given to ripple current ratings, temperature and long
term reliability. A typical application will require several
to many aluminum electrolytic capacitors in parallel.
A combination of the above mentioned capacitors will
often result in maximizing performance and minimizing
overall cost. Other capacitor types include Nichicon PL
series, NEC Neocap, Cornell Dubilier ESRE and Sprague
595D series. Consult manufacturers for other specific
recommendations.
placedwithin1cmofeachotherandshareacommonC (s).
IN
Separating the drains and C may produce undesirable
IN
voltage and current resonances at V .
IN
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (ΔV ) is determined by:
OUT
⎛
⎞
1
ΔVOUT ≈ ΔIL ESR+
⎜
⎝
⎟
8fCOUT
⎠
Wheref=operatingfrequency, C
=outputcapacitance,
OUT
and ΔI = ripple current in the inductor. The output ripple is
L
highestatmaximuminputvoltagesinceΔI increaseswith
L
inputvoltage.WithΔI =0.3I
theoutputripplewill
IN
L
OUT(MAX)
typically be less than 50mV at max V assuming:
C
OUT
Recommended ESR < 2 R
SENSE
and C
> 1/(8fR
)
OUT
SENSE
ThefirstconditionrelatestotheripplecurrentintotheESR
oftheoutputcapacitancewhilethesecondtermguarantees
thattheoutputcapacitancedoesnotsignificantlydischarge
duringtheoperatingfrequencyperiodduetoripplecurrent.
3707sfa
16
LTC3707-SYNC
APPLICATIONS INFORMATION
INTV Regulator
EXTV Connection
CC
CC
An internal P-channel low dropout regulator produces 5V
The IC contains an internal P-channel MOSFET switch
at the INTV pin from the V supply pin. INTV powers
connected between the EXTV and INTV pins. When
CC
IN
CC
CC CC
thedriversandinternalcircuitrywithintheLTC3707-SYNC.
thevoltageappliedtoEXTV risesabove4.7V,theinternal
CC
The INTV pin regulator can supply a peak current of
regulator is turned off and the switch closes, connecting
CC
50mA and must be bypassed to ground with a minimum
of 4.7μF tantalum, 10μF special polymer, or low ESR type
electrolytic capacitor. A 1μF ceramic capacitor placed di-
theEXTV pintotheINTV pintherebysupplyinginternal
CC CC
power. The switch remains closed as long as the voltage
applied to EXTV remains above 4.5V. This allows the
CC
rectly adjacent to the INTV and PGND IC pins is highly
MOSFET driver and control power to be derived from the
CC
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
output during normal operation (4.7V < V
< 7V) and
OUT
from the internal regulator when the output is out of regu-
lation (start-up, short-circuit). If more current is required
through the EXTV switch than is specified, an external
CC
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the IC to be
exceeded.Thesystemsupplycurrentisnormallydominated
by the gate charge current. Additional external loading of
Schottky diode can be added between the EXTV and
CC
INTV pins. Do not apply greater than 7V to the EXTV
CC
CC
pin and ensure that EXTV ≤ V .
CC
IN
Significant efficiency gains can be realized by powering
INTV from the output, since the V current resulting
the INTV and 3.3V linear regulators also needs to be
CC
CC
IN
taken into account for the power dissipation calculations.
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
The total INTV current can be supplied by either the
CC
5V internal linear regulator or by the EXTV input pin.
supply means connecting the EXTV pin directly to V
.
CC
CC
OUT
When the voltage applied to the EXTV pin is less than
However, for 3.3V and other lower voltage regulators,
CC
4.7V, all of the INTV current is supplied by the internal
additional circuitry is required to derive INTV power
CC
CC
5V linear regulator. Power dissipation for the IC in this
from the output.
case is highest: (V )(I
), and overall efficiency is
IN INTVCC
The following list summarizes the four possible connec-
lowered.Thegatechargecurrentisdependentonoperating
frequency as discussed in the Efficiency Considerations
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
tions for EXTV :
CC
1. EXTV LeftOpen(orGrounded).ThiswillcauseINTV
CC
CC
tobepoweredfromtheinternal5Vregulatorresultinginan
efficiency penalty of up to 10% at high input voltages.
Characteristics. For example, the IC V current is limited
IN
to less than 24mA from a 24V supply when not using the
2. EXTV Connected directly to V . This is the normal
CC
OUT
EXTV pin as follows:
CC
connection for a 5V regulator and provides the highest
efficiency.
T = 70°C + (24mA)(24V)(95°C/W) = 125°C
J
3. EXTV Connected to an External supply. If an external
Use of the EXTV input pin reduces the junction
CC
CC
supply is available in the 5V to 7V range, it may be used to
temperature to:
powerEXTV providing itis compatible with the MOSFET
CC
T = 70°C + (24mA)(5V)(95°C/W) = 81°C
J
gate drive requirements.
Dissipationshouldbecalculatedtoalsoincludeanyadded
current drawn from the internal 3.3V linear regulator.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked
4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.
CC
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV to an
CC
output-derived voltage that has been boosted to greater
operating in continuous mode at maximum V .
IN
3707sfa
17
LTC3707-SYNC
APPLICATIONS INFORMATION
Output Voltage
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.
TheICoutputvoltagesareeachsetbyanexternalfeedback
resistivedividercarefullyplacedacrosstheoutputcapacitor.
Theresultantfeedbacksignaliscomparedwiththeinternal
precision 0.800V voltage reference by the error amplifier.
The output voltage is given by the equation:
Topside MOSFET Driver Supply (C , D )
B
B
External bootstrap capacitors C connected to the BOOST
B
⎛
⎞
R2
R1
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
VOUT = 0.8V 1+
⎜
⎟
Capacitor C in the functional diagram is charged though
⎝
⎠
B
external diode D from INTV when the SW pin is low.
B
CC
where R1 and R2 are defined in Figure 2.
When one of the topside MOSFETs is to be turned on,
the driver places the C voltage across the gate-source
B
+
–
SENSE /SENSE Pins
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
The common mode input range of the current comparator
rises to V and the BOOST pin follows. With the topside
sense pins is from 0V to (1.1)INTV . Continuous linear
IN
CC
MOSFET on, the boost voltage is above the input supply:
operation is guaranteed throughout this range allowing
V
= V + V
. The value of the boost capacitor
output voltage setting from 0.8V to 7.7V, depending upon
BOOST
IN
INTVCC
C needstobe100timesthatofthetotalinputcapacitance
B
the voltage applied to EXTV . A differential NPN input
CC
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than V
stageisbiasedwithinternalresistorsfromaninternal2.4V
source as shown in the Functional Diagram. This requires
that current either be sourced or sunk from the SENSE
pinsdependingontheoutputvoltage. Iftheoutputvoltage
is below 2.4V current will flow out of both SENSE pins to
the main output. The output can be easily preloaded by
.
IN(MAX)
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
+
V
IN
V
IN
1μF
OPTIONAL EXTV
CONNECTION
CC
+
+
5V < V
< 7V
SEC
C
C
IN
IN
0.22μF
BAT85
BAT85
BAT85
V
V
SEC
V
IN
IN
+
N-CH
N-CH
LTC3707-SYNC
LTC3707-SYNC
1μF
V
VN2222LL
TG1
TG1
SW
R
R
SENSE
SENSE
V
OUT
OUT
T1
1:N
L1
EXTV
FCB
SW
EXTV
CC
CC
R6
R5
+
+
C
OUT
C
BG1
BG1
OUT
N-CH
N-CH
SGND
PGND
PGND
3707 F06a
3707 F06b
Figure 6a. Secondary Output Loop and EXTVCC Connection
Figure 6b. Capacitive Charge Pump for EXTVCC
3707sfa
18
LTC3707-SYNC
APPLICATIONS INFORMATION
V
IN
INTV
CC
the V
resistive divider to compensate for the current
OUT
3.3V OR 5V
RUN/SS
*
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
R
R *
SS
SS
D1
RUN/SS
+
–
C
SS
I
+ I
= (2.4V – V )/24k
SENSE
SENSE OUT
C
SS
Since V
is servoed to the 0.8V reference voltage,
OSENSE
we can choose R1 in Figure 2 to have a maximum value
to absorb this current.
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
(a)
3707 F07
(b)
⎛
⎞
0.8V
Figure 7. RUN/SS Pin Interfacing
R1
= 24k
(MAX)
⎜
⎟
2.4V – V
⎝
⎠
OUT
By pulling both RUN/SS pins below 1V, the IC is put into
low current shutdown (I = 20μA). The RUN/SS pins
for V
< 2.4V
Q
OUT
can be driven directly from logic as shown in Figure 7.
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb
the sense currents; however, R1 is still bounded by the
Diode D1 in Figure 7 reduces the start delay but allows
C
SS
to ramp up slowly providing the soft-start function.
Each RUN/SS pin has an internal 6V zener clamp (See
Functional Diagram).
V
feedback current.
OSENSE
Fault Conditions: Overcurrent Latchoff
Soft-Start/Run Function
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
thatprovideasoft-startfunctionandameanstoshutdown
the IC. Soft-start reduces the input power source’s surge
currents by gradually increasing the controller’s current
The RUN/SS capacitor, C , is used initially to turn on
SS
and limit the inrush current. After the controller has been
started and been given adequate time to charge up the
outputcapacitorandprovidefullloadcurrent, theRUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
limit (proportional to V ). This pin can also be used for
ITH
power supply sequencing.
An internal 1.2μA current source charges up the C
SS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to
start operating. As the voltage on RUN/SS increases from
1.5V to 3.0V, the internal current limit is increased from
after C reaches 4.1V, C begins discharging on the as-
SS
SS
sumption that the output is in an overcurrent condition. If
theconditionlastsforalongenoughperiodasdetermined
by the size of the C and the specified discharge current,
SS
25mV/R
to 75mV/R
. The output current limit
the controller will be shut down until the RUN/SS pin volt-
age is recycled. If the overload occurs during start-up, the
time can be approximated by:
SENSE
SENSE
rampsupslowly,takinganadditional1.25s/μFtoreachfull
current.Theoutputcurrentthusrampsupslowly,reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
t
≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)
LO1
SS
6
= 2.7 • 10 (C )
SS
If the overload occurs after start-up the voltage on C will
1.5V
1.2µA
SS
tDELAY
=
=
C = 1.25s /µF C
SS SS
(
)
begin discharging from the zener clamp voltage:
6
t
≈ [C (6 – 3.5)]/(1.2μA) = 2.1 • 10 (C )
LO2
SS
SS
3V −1.5V
1.2µA
tIRAMP
C = 1.25s /µF C
SS SS
(
)
3707sfa
19
LTC3707-SYNC
APPLICATIONS INFORMATION
This built-in overcurrent latchoff can be overridden by
providinga pull-up resistorto the RUN/SS pinas shownin
Figure7.Thisresistanceshortensthesoft-startperiodand
prevents the discharge of the RUN/SS capacitor during an
the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time t
of the
ON(MIN)
over current condition. Tying this pull-up resistor to V as
LTC3707-SYNC (less than 200ns), the input voltage and
inductor value:
IN
inFigure7a,defeatsovercurrentlatchoff.Diode-connecting
this pull-up resistor to INTV , as in Figure 7b, eliminates
CC
ΔI
= t (V /L)
ON(MIN) IN
L(SC)
any extra supply current during controller shutdown while
The resulting short-circuit current is:
eliminating the INTV loading from preventing controller
CC
start-up.
25mV
RSENSE
1
2
ISC =
+ ΔIL(SC)
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
muchhigherthannominallevels.Thecrowbarcauseshuge
currents to flow, that blow the fuse to protect against a
shortedtopMOSFETiftheshortoccurswhilethecontroller
is operating.
The value of the soft-start capacitor C may need to
SS
A comparator monitors the output for overvoltage con-
ditions. The comparator (OV) detects overvoltage faults
greaterthan7.5%abovethenominaloutputvoltage.When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
thereforeallowaswitchingregulatorsystemhavingapoor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
be scaled with output voltage, output capacitance and
load current characteristics. The minimum soft-start
capacitance is given by:
–4
C
> (C
)(V ) (10 ) (R
)
SENSE
SS
OUT
OUT
The minimum recommended soft-start capacitor of C
0.1μF will be sufficient for most applications.
=
SS
Fault Conditions: Current Limit and Current Foldback
The current comparators have a maximum sense voltage
of 75mV resulting in a maximum MOSFET current of
as the OV condition persists; if V
returns to a safe level,
OUT
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
openthesystemfuse.Theswitchingregulatorwillregulate
properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
75mV/R
. The maximum value of current limit
SENSE
generallyoccurswiththelargestV atthehighestambient
IN
temperature, conditions that cause the highest power
dissipation in the top MOSFET.
The IC includes current foldback to help further limit load
currentwhentheoutputisshortedtoground.Thefoldback
circuit is active even when the overload shutdown latch
described above is overridden. If the output falls below
70% of its nominal output level, then the maximum sense
voltage is progressively lowered from 75mV to 25mV.
Under short-circuit conditions with very low duty cycles,
the controller will begin cycle skipping in order to limit
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is 50% around the center
frequency f . A voltage applied to the PLLFLTR pin of 1.2V
O
3707sfa
20
LTC3707-SYNC
APPLICATIONS INFORMATION
corresponds to a frequency of approximately 220kHz. The
nominal operating frequency range of the PLL is 140kHz
to 310kHz.
Minimum On-Time Considerations
Minimum on-time t is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
ON(MIN)
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal oscillators. This type of phase detector
willnotlockuponinputfrequenciesclosetotheharmonics
of the VCO center frequency. The PLL hold-in range, Δf ,
H
VOUT
VIN(f)
is equal to the capture range, Δf :
tON(MIN)
<
C
Δf = Δf = 0.5 f (150kHz-300kHz)
H
C
O
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
Theoutputofthephasedetectorisacomplementarypairof
current sources charging or discharging the external filter
network on the PLLFLTR pin. A simplified block diagram
is shown in Figure 7.
The minimum on-time for the controller is generally less
than200ns. However, asthepeaksensevoltagedecreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Iftheexternalfrequency(f
)isgreaterthantheoscillator
PLLIN
frequency f , current is sourced continuously, pulling
OSC
up the PLLFLTR pin. When the external frequency is less
than f , current is sunk continuously, pulling down the
OSC
PLLFLTR pin. If the external and internal frequencies are
thesamebutexhibitaphasedifference,thecurrentsources
turn on for an amount of time corresponding to the phase
difference.ThusthevoltageonthePLLFLTRpinisadjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
C
holds the voltage. The IC PLLIN pin must be driven
LP
from a low impedance source such as a logic gate located
close to the pin. When using multiple LTC3707-SYNC’s
(or LTC1629’s, as shown in Figure 14) for a phase-locked
system,thePLLFLTRpinofthemasteroscillatorshouldbe
biasedatavoltagethatwillguaranteetheslaveoscillator(s)
ability to lock onto the master’s frequency. A DC voltage
of 0.7V to 1.7V applied to the master oscillator’s PLLFLTR
pin is recommended in order to meet this requirement.
The resultant operating frequency can range from 170kHz
to 270kHz.
When primary load currents are low and/or the V /V
IN OUT
ratio is low, the synchronous switch may not be on for
a sufficient amount of time to transfer power from the
outputcapacitortothesecondaryload.Forcedcontinuous
operationwillsupportsecondarywindingsprovidingthere
issufficientsynchronousswitchdutyfactor.Thus,theFCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
The loop filter components (C , R ) smooth out the
LP LP
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C and R determine how fast the loop
LP
LP
acquires lock. Typically R =10kΩ and C is 0.01μF to
LP
LP
0.1μF.
3707sfa
21
LTC3707-SYNC
APPLICATIONS INFORMATION
ThesecondaryoutputvoltageV isnormallysetasshown
midpoint operating voltage range of the error amplifier, or
1.2V (see Figure 8).
SEC
in Figure 6a by the turns ratio N of the transformer:
V
≅ (N + 1) V
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier.
The maximum output voltage deviation can theoretically
be reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application.
A complete explanation is included in Design Solutions
10. (See www.linear-tech.com)
SEC
OUT
However, if the controller goes into Burst Mode operation
andhaltsswitchingduetoalightprimaryloadcurrent,then
SEC
V
will droop. An external resistive divider from V to
SEC
the FCB pin sets a minimum voltage V
:
SEC(MIN)
R6
R5
⎛
⎞
VSEC(MIN) ≈0.8V 1+
⎜
⎟
⎠
⎝
INTV
CC
where R5 and R6 are shown in Figure 2.
If V drops below this level, the FCB voltage forces
R
T2
T1
I
TH
SEC
LTC3707-SYNC
R
R
C
temporary continuous switching operation until V
is
SEC
C
C
again above its minimum.
3707 F08
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18μA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
Figure 8. Active Voltage Positioning Applied
to the LTC3707-SYNC
Efficiency Considerations
The following table summarizes the possible states
available on the FCB pin:
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
Table 1
FCB PIN
CONDITION
0V to 0.75V
Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
0.85V < V < 4.3V
Minimum Peak Current Induces
Burst Mode Operation
%Efficiency = 100% – (L1 + L2 + L3 + ...)
FCB
No Current Reversal Allowed
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Feedback Resistors
>4.8V
Regulating a Secondary Winding
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in application circuits: 1) IC V current (including
IN
loadingonthe3.3Vinternalregulator),2)INTV regulator
CC
2
Voltage Positioning
current, 3) I R losses, 4) Topside MOSFET transition
losses.
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the controller by loading the I pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
1. The V current has two components: the first is the DC
IN
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V current typically results in a small (<0.1%)
TH
IN
loss.
3707sfa
22
LTC3707-SYNC
APPLICATIONS INFORMATION
2. INTV current is the sum of the MOSFET driver and
voltages (typically 15V or greater). Transition losses can
be estimated from:
CC
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from INTV
to ground. The resulting dQ/dt is a current out of INTV
thatistypicallymuchlargerthanthecontrolcircuitcurrent.
1
2
2
TransitionLoss= VIN IO(MAX)RDRCMILLER
CC
CC
⎡
⎢
⎣
⎤
⎥
⎦
1
1
+
f
( )
V
INTVCC – VTH VTH
In continuous mode, I
B
MOSFETs.
=f(Q +Q ), where Q and
GATECHG
T B T
Q are the gate charges of the topside and bottom side
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
Supplying INTV power through the EXTV switch
CC
CC
input from an output-derived source will scale the V
IN
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Efficiency). For example, in a
C has adequate charge storage and very low ESR at the
IN
20V to 5V application, 10mA of INTV current results
CC
switching frequency. A 25W supply will typically require
a minimum of 20μF to 40μF of capacitance having a
maximum of 20mΩ to 50mΩ of ESR. The LTC3707-SYNC
2-phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
in approximately 2.5mA of V current. This reduces the
IN
mid-current loss from 10% or more (if the driver was
powered directly from V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
, but is “chopped” between the topside MOSFET
SENSE
and the synchronous MOSFET. If the two MOSFETs have
Checking Transient Response
approximately the same R
, then the resistance of
DS(ON)
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
one MOSFET can simply be summed with the resistances
2
of L, R
and ESR to obtain I R losses. For example, if
SENSE
each R
= 30mΩ, RL = 50mΩ, R
= 40mΩ (sum of both input and output capacitance
= 10mΩ and
DS(ON)
SENSE
load current. When a load step occurs, V
shifts by
OUT
R
ESR
an amount equal to ΔI
(ESR), where ESR is the
LOAD
losses), then the total resistance is 130mΩ. This results
in losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
effective series resistance of C . ΔI
also begins to
OUT
LOAD
charge or discharge C
generating the feedback error
OUT
signal that forces the regulator to adapt to the current
change and return V
this recovery time V
to its steady-state value. During
can be monitored for excessive
OUT
OUT
square of V
for the same external components and
OUT
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I pin
TH
not only allows optimization of control loop behavior but
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
3707sfa
23
LTC3707-SYNC
APPLICATIONS INFORMATION
resistance is low and it is driven quickly. If the ratio of
to C is greater than1:50, the switch rise time
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
C
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
pin. The I external components shown in the Figure 1
TH
circuit will provide an adequate starting point for most
applications.
Automotive Considerations:
Plugging into the Cigarette Lighter
The I series R -C filter sets the dominant pole-zero
TH
C
C
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserveorevenrechargebatterypacksduringoperation.
But before you connect, be advised: you are plugging
into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery, and
double-battery.
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I pin waveforms that will
TH
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
ThenetworkshowninFigure9isthemoststraightforward
approachtoprotectaDC/DCconverterfromtheravagesof
anautomotivepowerline.Theseriesdiodepreventscurrent
from flowing during reverse-battery, while the transient
suppressor clamps the input voltage during load-dump.
Note that the transient suppressor should not conduct
during double-battery operation, but must still clamp the
input voltage below breakdown of the converter.
why it is better to look at the I pin signal which is in the
TH
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing R and the bandwidth of the loop will be
C
increased by decreasing C . If R is increased by the same
C
C
factor that C is decreased, the zero frequency will be kept
C
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
50A I RATING
PK
V
IN
12V
LTC3707-SYNC
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
3707 F09
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
Figure 9. Automotive Application Protection
3707sfa
24
LTC3707-SYNC
APPLICATIONS INFORMATION
Design Example
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Fairchild FOS6982S results
As a design example for one channel, assume V
=
IN
= 5A,
in; R
= 0.035Ω/0.022Ω, calculated C
is
DS(ON)
MILLER
12V(nominal), V = 22V(max), V
= 1.8V, I
IN
OUT
MAX
3nC/15V = 200pF. At maximum input voltage with
T(estimated) = 50°C:
and f = 300kHz.
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
1.8V
22V
1
2
PMAIN
=
5
( )
1+(0.005)(50°C–25°C) 0.035Ω
(
]
)
[
1
1
⎛
⎞
2
pin to the INTV pin for 300kHz operation. The minimum
CC
+
22V 5A 4Ω 200pF
+
300kHz
(
) ( )( )(
)
(
)
⎜
⎝
⎟
⎠
2
5–2 2
inductance for 30% ripple current is:
= 323mW
⎛
⎞
VOUT
(f)(L)
VOUT
VIN
ΔIL =
1–
⎜
⎟
A short-circuit to ground will result in a folded back
current of:
⎝
⎠
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3μH value. Increasing the ripple current
will also help ensure that the minimum on-time of 200ns
is not violated. The minimum on-time occurs at maximum
25mV 1⎛ 200ns(22V)⎞
ISC =
+
= 3.2A
⎜
⎟
⎝
⎠
0.01Ω 2
3.3µH
with a typical value of R
and δ = (0.005/°C)(20) = 0.1.
DS(ON)
The resulting power dissipated in the bottom MOSFET is:
V :
IN
22V –1.8V
22V
2
PSYNC
=
3.2A 1.1 0.022Ω
(
) ( )(
)
VOUT
VIN(MAX)f 22V(300kHz)
1.8V
tON(MIN)
=
=
= 273ns
= 227mW
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
The R
resistor value can be calculated by using the
SENSE
IN
maximum current sense voltage specification with some
accommodation for tolerances:
temperature assuming only this channel is on. C
is
OUT
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
60mV
5.84A
RSENSE
≤
≈ 0.01Ω
Since the output voltage is below 2.4V the output resis-
tive divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
V
= R
(ΔI ) = 0.02Ω(1.67A) = 33mV
ESR L P–P
ORIPPLE
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phasesynchronousregulatorsoperatinginthecontinu-
ous mode. Check the following in your layout:
⎛
⎞
0.8V
R1
= 24k
(MAX)
⎜
⎟
2.4V – V
⎝
⎠
OUT
⎛
⎞
0.8V
2.4V – 1.8V
= 24K
= 32k
⎜
⎟
⎝
⎠
Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
3707sfa
25
LTC3707-SYNC
APPLICATIONS INFORMATION
1. Are the top N-channel MOSFETs M1 and M3 located
connected between the (+) terminal of C
ground. The R2 and R4 connections should not be along
the high current input feeds from the input capacitor(s).
and signal
OUT
within 1cm of each other with a common drain connection
at C ? Do not attempt to split the input decoupling for
IN
the two channels as it can cause a large resonant loop.
–
+
4. Are the SENSE and SENSE leads routed together with
minimum PC trace spacing? The filter capacitor between
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
+
–
SENSE and SENSE should be as close as possible to the
IC.EnsureaccuratecurrentsensingwithKelvinconnections
at the SENSE resistor.
ofC
mustreturntothecombinedC (–)terminals.
INTVCC
OUT
The path formed by the top N-channel MOSFET, Schottky
diodeandtheC capacitorshouldhaveshortleadsandPC
IN
5. Is the INTV decoupling capacitor connected close to
CC
tracelengths.Theoutputcapacitor(–)terminalsshouldbe
connected as close as possible to the (–) terminals of the
inputcapacitorbyplacingthecapacitorsnexttoeachother
and away from the Schottky loop described above.
the IC, between the INTV and the power ground pins?
CC
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV and PGND pins can help improve noise
CC
3. Do the IC V
pins resistive dividers connect to
OUT
performance substantially.
OSENSE
the (+) terminals of C ? The resistive divider must be
R
PU
V
PULL-UP
(<7V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGOOD
RUN/SS1
PGOOD
TG1
L1
R
SENSE
+
V
SENSE1
OUT1
3
–
SENSE1
SW1
R2
M1
M2
C
B1
R1
4
D1
V
BOOST1
OSENSE1
5
PLLFLTR
PLLIN
FCB
V
IN
f
IN
6
C
C
OUT1
BG1
R
IN
7
C
IN
INTV
EXTV
CC
CC
CC
C
VIN
GND
LTC3707-SYNC
INTV
8
I
TH1
V
IN
C
INTVCC
9
SGND
PGND
BG2
OUT2
D2
10
11
12
13
14
3.3V
3.3V
OUT
I
BOOST2
SW2
TH2
C
B2
M3
M4
L2
V
OSENSE2
–
R
R3
R4
SENSE
V
OUT2
SENSE2
SENSE2
TG2
+
RUN/SS2
3707 F10
Figure 10. LTC3707-SYNC Recommended Printed Circuit Layout Diagram
3707sfa
26
LTC3707-SYNC
APPLICATIONS INFORMATION
SW1
D1
L1
R
SENSE1
V
OUT1
+
C
R
L1
OUT1
V
IN
R
IN
+
C
IN
SW2
L2
R
SENSE2
V
OUT2
+
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
3707 F11
Figure 11. Branch Current Waveforms
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the IC and occupy minimum PC trace area.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
dropsbelowthelowcurrentoperationthreshold—typically
10% to 20% of the maximum designed current level in
Burst Mode operation.
7. Useamodified“starground”technique:alowimpedance,
largecopperareacentralgroundingpointonthesameside
of the PC board as the input and output capacitors with
tie-ins for the bottom of the INTV decoupling capacitor,
CC
the bottom of the voltage feedback resistive divider and
the SGND pin of the IC.
3707sfa
27
LTC3707-SYNC
APPLICATIONS INFORMATION
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for their individual performance
should both controllers be turned on at the same time.
A particularly difficult region of operation is when one
controller channel is nearing its current comparator trip
pointwhentheotherchannelisturningonitstopMOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Short-circuit testing can be performed to verify proper
overcurrentlatchoff,or5μAcanbeprovidedtotheRUN/SS
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
pin(s) by resistors from V to prevent the short-circuit
IN
latchoff from occurring.
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
3707sfa
28
LTC3707-SYNC
TYPICAL APPLICATIONS
59k
1M
100k
MBRS1100T3
T1, 1:1.8
V
+
PULL-UP
33μF
25V
(<7V)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10μH
PGOOD
TG1
PGOOD
RUN/SS1
0.015Ω
V
0.1μF
OUT1
2
+
5V
SENSE1
3A; 4A PEAK
180pF
1000pF
INTV
3
4
8
–
SW1
SENSE1
105k, 1%
5
M1
M2
0.1μF
D1
MBRM
140T3
LT1121
ON/OFF
BOOST1
V
OSENSE1
3
2
1
20k
1%
220k
V
5
OUT2
V
IN
PLLFLTR
PLLIN
FCB
CC
12V
120mA
6
150μF, 6.3V
PANASONIC SP
BG1
2×
10μF
35V
+
33pF
1μF
25V
10Ω
100k
7
CMDSH-3TR
EXTV
CC
0.1μF
GND
LTC3707-SYNC
INTV
8
I
CC
TH1
1μF
10V
15k
4.7μF
1000pF
1000pF
9
180μF, 4V
PGND
BG2
SGND
PANASONIC SP
V
33pF
IN
CMDSH-3TR
7V TO
28V
10
11
12
13
14
3.3V
3.3V
OUT
D2
MBRM
140T3
BOOST2
SW2
I
TH2
15k
0.1μF
M3
M4
V
OSENSE2
20k
1%
V
OUT2
3.3V
5A; 6A PEAK
–
TG2
SENSE2
SENSE2
63.4k
1%
0.01Ω
1000pF
L1
6.3μH
+
RUN/SS2
180pF
0.1μF
3707 F12
V
V
: 7V TO 28V
IN
: 5V, 3A/3.3V, 6A, 12V, 150mA
OUT
SWITCHING FREQUENCY = 300kHz
MI, M2, M3, M4: NDS8410A
L1: SUMIDA CEP123-6R3MC
T1: 10mH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
Figure 12. LTC3707-SYNC High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator
3707sfa
29
LTC3707-SYNC
TYPICAL APPLICATIONS
V
PULL-UP
(<7V)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
L1
PGOOD
RUN/SS1
PGOOD
TG1
4.3μH
0.007Ω
0.1μF
68pF
2
3
V
OUT1
+
SENSE1
SENSE1
5V/5A
1000pF
105k
1%
–
SW1
20k
1%
M1A
M1B
0.1μF
4
V
BOOST1
OSENSE1
5
PLLFLTR
PLLIN
FCB
V
0.01μF
IN
10k
1000pF
150μF
6.3V
6
f
2s
10μF
35V
SYNC
BG1
68pF
10Ω
7
CMDSH-3TR
EXTV
INTV
CC
CC
0.1μF
GND
LTC3707-SYNC
8
I
TH1
1μF
10V
6.34k
68pF
4.7μF
1000pF
1000pF
9
SGND
PGND
BG2
180μF, 4V
V
IN
CMDSH-3TR
7V TO
24V
10
11
12
13
14
3.3V
3.3V
OUT
I
BOOST2
SW2
TH2
5.1k
0.1μF
M2A
M2B
V
OSENSE2
–
20k
1%
V
OUT2
SENSE2
SENSE2
TG2
3.3V/5A
0.007Ω
63.4k
1%
1000pF
L2
4.3μH
+
68pF
RUN/SS2
0.1μF
: 7V TO 24V
3707 F13
V
V
SWITCHING FREQUENCY = 300kHz
MI, M2: FAIRCHILD FDS6982S
(INTERNAL SCHOTTKY)
L1, L2: 8mH SUMIDA CDEP105-4R3MC-88
OUTPUT CAPACITORS: PANASONIC SP SERIES
IN
: 5V/5A, 3.3V/5A
OUT
Figure 13. LTC3707-SYNC 5V/5A, 3.3V/5A Regulator with External Frequency Synchronization
3707sfa
30
LTC3707-SYNC
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 p.005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 p.0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
.015 p .004
(0.38 p 0.10)
.0532 – .0688
(1.35 – 1.75)
s 45o
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN28 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3707sfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3707-SYNC
TYPICAL APPLICATION
I
IN
12V
IN
C
IN
I
I
*
1
IN
0°
BUCK: 2.5V/15A
BUCK: 2.5V/15A
OPEN
PHASMD TG1
180°
I
1
2
3
4
2.5V /30A
O
TG2
U1
LTC1629
I
I
90°
2
3
I
CLKOUT
I
I
1.5V /15A
O
90°
BUCK: 1.5V/15A
BUCK: 1.8V/15A
TG1
270°
1.8V /15A
O
TG2
LTC3707-SYNC
U2
*INPUT RIPPLE CURRENT CANCELLATION
INCREASES THE RIPPLE FREQUENCY AND
REDUCES THE RMS INPUT RIPPLE CURRENT
THUS, SAVING INPUT CAPACITORS
I
90°
4
PLLIN
3707 F14
Figure 14. Multioutput Multiphase Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1438-ADJ
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LTC1539
Dual Synchronous Controller with Auxiliary Regulator
POR, External Feedback Divider
Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Auxiliary Regulator, 5V Standby
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LTC1530
High Power Step-Down Synchronous DC/DC Controller in SO-8
TM Current Mode Synchronous Step-Down Controllers
High Efficiency 5V to 3.3V Conversion at Up to 15A
97% Efficiency, No Sense Resistor, 16-Pin SSOP
LTC1625/LTC1775 No R
SENSE
LTC1628-SYNC
Higher Voltage and Higher Accuracy Specified LTC3707-SYNC
20A to 200A PolyPhaseTM Synchronous Controllers
V
up to 36V, 1% V
Accuracy
IN
OUT
LTC1629/
LTC1629-PG
Expandable from 2-Phase to 12-Phase, Uses All
Surface Mount Components, No Heat Sink
LTC1702
LTC1703
No R
No R
2-Phase Dual Synchronous Step-Down Controller
2-Phase Dual Synchronous Step-Down Controller
550kHz, No Sense Resistor
SENSE
SENSE
Mobile Pentium® III Processors, 550kHz,
with 5-Bit Mobile VID Control
V ≤ 7V
IN
LTC1708-PG
2-Phase, Dual Synchronous Controller with Mobile VID
3.5V ≤ V ≤ 36V, VID Sets V
, PGOOD
OUT1
IN
LT1709/
LT1709-8
High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
with 5-Bit VID
1.3V ≤ V
≤ 3.5V, Current Mode Ensures
OUT
Accurate Current Sharing, 3.5V ≤ V ≤ 36V
IN
LTC1735
LTC1736
High Efficiency Synchronous Step-Down Switching Regulator
Output Fault Protection, 16-Pin SSOP
High Efficiency Synchronous Controller with 5-Bit Mobile VID Control
Output Fault Protection, 24-Pin SSOP,
3.5V ≤ V ≤ 36V
IN
LTC1929/
LTC1929-PG
2-Phase Synchronous Controllers
Up to 42A, Uses All Surface Mount Components,
No Heat Sinks, 3.5V ≤ V ≤ 36V
IN
LTC3707
Includes Standby Mode Function
V up to 36V, PGOOD
IN
Adaptive Power, No R
and PolyPhase are trademarks of Linear Technology Corporation.
SENSE
3707sfa
LT 0508 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2002
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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